mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_rcc_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief Extension RCC HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities RCC extension peripheral:
bogdanm	0:9b334a45a8ff	10	* + Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	******************************************************************************
bogdanm	0:9b334a45a8ff	13	* @attention
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	16	*
bogdanm	0:9b334a45a8ff	17	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	18	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	19	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	20	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	22	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	23	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	25	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	26	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	27	*
bogdanm	0:9b334a45a8ff	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	38	*
bogdanm	0:9b334a45a8ff	39	******************************************************************************
bogdanm	0:9b334a45a8ff	40	*/
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	43	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	46	* @{
bogdanm	0:9b334a45a8ff	47	*/
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @defgroup RCCEx RCCEx
bogdanm	0:9b334a45a8ff	50	* @brief RCCEx HAL module driver
bogdanm	0:9b334a45a8ff	51	* @{
bogdanm	0:9b334a45a8ff	52	*/
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	#ifdef HAL_RCC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	57	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @addtogroup RCCEx_Private_Constants
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	/**
bogdanm	0:9b334a45a8ff	62	* @}
bogdanm	0:9b334a45a8ff	63	*/
bogdanm	0:9b334a45a8ff	64	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	65	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	66	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	67	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	68	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm	0:9b334a45a8ff	69	* @{
bogdanm	0:9b334a45a8ff	70	*/
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	73	* @brief Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	74	*
bogdanm	0:9b334a45a8ff	75	@verbatim
bogdanm	0:9b334a45a8ff	76	===============================================================================
bogdanm	0:9b334a45a8ff	77	##### Extended Peripheral Control functions #####
mbed_official	19:112740acecfa	78	===============================================================================
bogdanm	0:9b334a45a8ff	79	[..]
bogdanm	0:9b334a45a8ff	80	This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm	0:9b334a45a8ff	81	frequencies.
bogdanm	0:9b334a45a8ff	82	[..]
bogdanm	0:9b334a45a8ff	83	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm	0:9b334a45a8ff	84	select the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	85	order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	86	the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	@endverbatim
bogdanm	0:9b334a45a8ff	89	* @{
bogdanm	0:9b334a45a8ff	90	*/
mbed_official	19:112740acecfa	91	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
mbed_official	19:112740acecfa	92	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
mbed_official	19:112740acecfa	93	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
mbed_official	19:112740acecfa	94	defined(STM32F469xx) \|\| defined(STM32F479xx)
mbed_official	19:112740acecfa	95	/**
mbed_official	19:112740acecfa	96	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	19:112740acecfa	97	* @note The default reset state of the clock configuration is given below:
mbed_official	19:112740acecfa	98	* - HSI ON and used as system clock source
mbed_official	19:112740acecfa	99	* - HSE, PLL and PLLI2S OFF
mbed_official	19:112740acecfa	100	* - AHB, APB1 and APB2 prescaler set to 1.
mbed_official	19:112740acecfa	101	* - CSS, MCO1 and MCO2 OFF
mbed_official	19:112740acecfa	102	* - All interrupts disabled
mbed_official	19:112740acecfa	103	* @note This function doesn't modify the configuration of the
mbed_official	19:112740acecfa	104	* - Peripheral clocks
mbed_official	19:112740acecfa	105	* - LSI, LSE and RTC clocks
mbed_official	19:112740acecfa	106	* @retval None
mbed_official	19:112740acecfa	107	*/
mbed_official	19:112740acecfa	108	void HAL_RCC_DeInit(void)
mbed_official	19:112740acecfa	109	{
mbed_official	19:112740acecfa	110	/* Set HSION bit */
mbed_official	19:112740acecfa	111	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
mbed_official	19:112740acecfa	112
mbed_official	19:112740acecfa	113	/* Reset CFGR register */
mbed_official	19:112740acecfa	114	CLEAR_REG(RCC->CFGR);
mbed_official	19:112740acecfa	115
mbed_official	19:112740acecfa	116	/* Reset HSEON, CSSON, PLLON, PLLI2S */
mbed_official	19:112740acecfa	117	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON\| RCC_CR_PLLI2SON);
mbed_official	19:112740acecfa	118
mbed_official	19:112740acecfa	119	/* Reset PLLCFGR register */
mbed_official	19:112740acecfa	120	CLEAR_REG(RCC->PLLCFGR);
mbed_official	19:112740acecfa	121	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
mbed_official	19:112740acecfa	122
mbed_official	19:112740acecfa	123	/* Reset PLLI2SCFGR register */
mbed_official	19:112740acecfa	124	CLEAR_REG(RCC->PLLI2SCFGR);
mbed_official	19:112740acecfa	125	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
mbed_official	19:112740acecfa	126
mbed_official	19:112740acecfa	127	/* Reset HSEBYP bit */
mbed_official	19:112740acecfa	128	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official	19:112740acecfa	129
mbed_official	19:112740acecfa	130	/* Disable all interrupts */
mbed_official	19:112740acecfa	131	CLEAR_REG(RCC->CIR);
mbed_official	19:112740acecfa	132	}
mbed_official	19:112740acecfa	133	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
mbed_official	19:112740acecfa	134	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
mbed_official	19:112740acecfa	135
mbed_official	19:112740acecfa	136	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
mbed_official	19:112740acecfa	137	/**
mbed_official	19:112740acecfa	138	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	19:112740acecfa	139	* @note The default reset state of the clock configuration is given below:
mbed_official	19:112740acecfa	140	* - HSI ON and used as system clock source
mbed_official	19:112740acecfa	141	* - HSE and PLL OFF
mbed_official	19:112740acecfa	142	* - AHB, APB1 and APB2 prescaler set to 1.
mbed_official	19:112740acecfa	143	* - CSS, MCO1 and MCO2 OFF
mbed_official	19:112740acecfa	144	* - All interrupts disabled
mbed_official	19:112740acecfa	145	* @note This function doesn't modify the configuration of the
mbed_official	19:112740acecfa	146	* - Peripheral clocks
mbed_official	19:112740acecfa	147	* - LSI, LSE and RTC clocks
mbed_official	19:112740acecfa	148	* @retval None
mbed_official	19:112740acecfa	149	*/
mbed_official	19:112740acecfa	150	void HAL_RCC_DeInit(void)
mbed_official	19:112740acecfa	151	{
mbed_official	19:112740acecfa	152	/* Set HSION bit */
mbed_official	19:112740acecfa	153	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
mbed_official	19:112740acecfa	154
mbed_official	19:112740acecfa	155	/* Reset CFGR register */
mbed_official	19:112740acecfa	156	CLEAR_REG(RCC->CFGR);
mbed_official	19:112740acecfa	157
mbed_official	19:112740acecfa	158	/* Reset HSEON, CSSON, PLLON */
mbed_official	19:112740acecfa	159	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON);
mbed_official	19:112740acecfa	160
mbed_official	19:112740acecfa	161	/* Reset PLLCFGR register */
mbed_official	19:112740acecfa	162	CLEAR_REG(RCC->PLLCFGR);
mbed_official	19:112740acecfa	163	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
mbed_official	19:112740acecfa	164
mbed_official	19:112740acecfa	165	/* Reset HSEBYP bit */
mbed_official	19:112740acecfa	166	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official	19:112740acecfa	167
mbed_official	19:112740acecfa	168	/* Disable all interrupts */
mbed_official	19:112740acecfa	169	CLEAR_REG(RCC->CIR);
mbed_official	19:112740acecfa	170	}
mbed_official	19:112740acecfa	171	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
mbed_official	19:112740acecfa	172
bogdanm	0:9b334a45a8ff	173	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	174	/**
bogdanm	0:9b334a45a8ff	175	* @brief Initializes the RCC extended peripherals clocks according to the specified
bogdanm	0:9b334a45a8ff	176	* parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	177	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	178	* contains the configuration information for the Extended Peripherals
bogdanm	0:9b334a45a8ff	179	* clocks(I2S, SAI, LTDC RTC and TIM).
bogdanm	0:9b334a45a8ff	180	*
bogdanm	0:9b334a45a8ff	181	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm	0:9b334a45a8ff	182	* the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	183	* order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	184	* the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	185	*
bogdanm	0:9b334a45a8ff	186	* @retval HAL status
bogdanm	0:9b334a45a8ff	187	*/
bogdanm	0:9b334a45a8ff	188	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	189	{
bogdanm	0:9b334a45a8ff	190	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	191	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	192	uint32_t plli2sp = 0;
bogdanm	0:9b334a45a8ff	193	uint32_t plli2sq = 0;
bogdanm	0:9b334a45a8ff	194	uint32_t plli2sr = 0;
bogdanm	0:9b334a45a8ff	195	uint32_t pllsaip = 0;
bogdanm	0:9b334a45a8ff	196	uint32_t pllsaiq = 0;
bogdanm	0:9b334a45a8ff	197	uint32_t plli2sused = 0;
bogdanm	0:9b334a45a8ff	198	uint32_t pllsaiused = 0;
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200	/* Check the peripheral clock selection parameters */
bogdanm	0:9b334a45a8ff	201	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official	19:112740acecfa	202
mbed_official	19:112740acecfa	203	/------------------------ I2S APB1 configuration --------------------------/
bogdanm	0:9b334a45a8ff	204	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
bogdanm	0:9b334a45a8ff	205	{
bogdanm	0:9b334a45a8ff	206	/* Check the parameters */
bogdanm	0:9b334a45a8ff	207	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	/* Configure I2S Clock source */
bogdanm	0:9b334a45a8ff	210	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
bogdanm	0:9b334a45a8ff	211	/* Enable the PLLI2S when it's used as clock source for I2S */
bogdanm	0:9b334a45a8ff	212	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	213	{
bogdanm	0:9b334a45a8ff	214	plli2sused = 1;
bogdanm	0:9b334a45a8ff	215	}
bogdanm	0:9b334a45a8ff	216	}
mbed_official	19:112740acecfa	217	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	218
mbed_official	19:112740acecfa	219	/---------------------------- I2S APB2 configuration ----------------------/
bogdanm	0:9b334a45a8ff	220	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
bogdanm	0:9b334a45a8ff	221	{
bogdanm	0:9b334a45a8ff	222	/* Check the parameters */
bogdanm	0:9b334a45a8ff	223	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/* Configure I2S Clock source */
bogdanm	0:9b334a45a8ff	226	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
bogdanm	0:9b334a45a8ff	227	/* Enable the PLLI2S when it's used as clock source for I2S */
bogdanm	0:9b334a45a8ff	228	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	229	{
bogdanm	0:9b334a45a8ff	230	plli2sused = 1;
bogdanm	0:9b334a45a8ff	231	}
bogdanm	0:9b334a45a8ff	232	}
mbed_official	19:112740acecfa	233	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	234
mbed_official	19:112740acecfa	235	/--------------------------- SAI1 configuration ---------------------------/
bogdanm	0:9b334a45a8ff	236	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
bogdanm	0:9b334a45a8ff	237	{
bogdanm	0:9b334a45a8ff	238	/* Check the parameters */
bogdanm	0:9b334a45a8ff	239	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	/* Configure SAI1 Clock source */
bogdanm	0:9b334a45a8ff	242	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
bogdanm	0:9b334a45a8ff	243	/* Enable the PLLI2S when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	244	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	245	{
bogdanm	0:9b334a45a8ff	246	plli2sused = 1;
bogdanm	0:9b334a45a8ff	247	}
bogdanm	0:9b334a45a8ff	248	/* Enable the PLLSAI when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	249	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	pllsaiused = 1;
bogdanm	0:9b334a45a8ff	252	}
bogdanm	0:9b334a45a8ff	253	}
mbed_official	19:112740acecfa	254	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	255
mbed_official	19:112740acecfa	256	/-------------------------- SAI2 configuration ----------------------------/
bogdanm	0:9b334a45a8ff	257	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
bogdanm	0:9b334a45a8ff	258	{
bogdanm	0:9b334a45a8ff	259	/* Check the parameters */
bogdanm	0:9b334a45a8ff	260	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262	/* Configure SAI2 Clock source */
bogdanm	0:9b334a45a8ff	263	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	/* Enable the PLLI2S when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	266	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	267	{
bogdanm	0:9b334a45a8ff	268	plli2sused = 1;
bogdanm	0:9b334a45a8ff	269	}
bogdanm	0:9b334a45a8ff	270	/* Enable the PLLSAI when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	271	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
bogdanm	0:9b334a45a8ff	272	{
bogdanm	0:9b334a45a8ff	273	pllsaiused = 1;
bogdanm	0:9b334a45a8ff	274	}
bogdanm	0:9b334a45a8ff	275	}
mbed_official	19:112740acecfa	276	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	277
mbed_official	19:112740acecfa	278	/----------------------------- RTC configuration --------------------------/
bogdanm	0:9b334a45a8ff	279	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	19:112740acecfa	280	{
bogdanm	0:9b334a45a8ff	281	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	282	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	285	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/* Get tick */
bogdanm	0:9b334a45a8ff	288	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	291	{
bogdanm	0:9b334a45a8ff	292	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	293	{
bogdanm	0:9b334a45a8ff	294	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	295	}
bogdanm	0:9b334a45a8ff	296	}
bogdanm	0:9b334a45a8ff	297	/* Reset the Backup domain only if the RTC Clock source selction is modified */
bogdanm	0:9b334a45a8ff	298	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	19:112740acecfa	299	{
bogdanm	0:9b334a45a8ff	300	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	301	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	302	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	303	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	304	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	305	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	306	RCC->BDCR = tmpreg1;
mbed_official	19:112740acecfa	307
bogdanm	0:9b334a45a8ff	308	/* Wait for LSERDY if LSE was enabled */
bogdanm	0:9b334a45a8ff	309	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	310	{
bogdanm	0:9b334a45a8ff	311	/* Get tick */
bogdanm	0:9b334a45a8ff	312	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	315	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	316	{
bogdanm	0:9b334a45a8ff	317	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	318	{
bogdanm	0:9b334a45a8ff	319	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	320	}
bogdanm	0:9b334a45a8ff	321	}
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	324	}
bogdanm	0:9b334a45a8ff	325	}
mbed_official	19:112740acecfa	326	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	327
mbed_official	19:112740acecfa	328	/---------------------------- TIM configuration ---------------------------/
bogdanm	0:9b334a45a8ff	329	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
bogdanm	0:9b334a45a8ff	330	{
bogdanm	0:9b334a45a8ff	331	/* Configure Timer Prescaler */
bogdanm	0:9b334a45a8ff	332	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
bogdanm	0:9b334a45a8ff	333	}
mbed_official	19:112740acecfa	334	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	335
mbed_official	19:112740acecfa	336	/---------------------------- FMPI2C1 Configuration -----------------------/
bogdanm	0:9b334a45a8ff	337	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
bogdanm	0:9b334a45a8ff	338	{
bogdanm	0:9b334a45a8ff	339	/* Check the parameters */
bogdanm	0:9b334a45a8ff	340	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/* Configure the FMPI2C1 clock source */
bogdanm	0:9b334a45a8ff	343	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
bogdanm	0:9b334a45a8ff	344	}
mbed_official	19:112740acecfa	345	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	346
mbed_official	19:112740acecfa	347	/------------------------------ CEC Configuration -------------------------/
bogdanm	0:9b334a45a8ff	348	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
bogdanm	0:9b334a45a8ff	349	{
bogdanm	0:9b334a45a8ff	350	/* Check the parameters */
bogdanm	0:9b334a45a8ff	351	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
bogdanm	0:9b334a45a8ff	352
bogdanm	0:9b334a45a8ff	353	/* Configure the CEC clock source */
bogdanm	0:9b334a45a8ff	354	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
bogdanm	0:9b334a45a8ff	355	}
mbed_official	19:112740acecfa	356	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	357
mbed_official	19:112740acecfa	358	/------------------------------ CK48 Configuration ------------------------/
bogdanm	0:9b334a45a8ff	359	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
bogdanm	0:9b334a45a8ff	360	{
bogdanm	0:9b334a45a8ff	361	/* Check the parameters */
bogdanm	0:9b334a45a8ff	362	assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
bogdanm	0:9b334a45a8ff	363
mbed_official	19:112740acecfa	364	/* Configure the CK48 clock source */
bogdanm	0:9b334a45a8ff	365	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	/* Enable the PLLSAI when it's used as clock source for CK48 */
bogdanm	0:9b334a45a8ff	368	if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
bogdanm	0:9b334a45a8ff	369	{
bogdanm	0:9b334a45a8ff	370	pllsaiused = 1;
bogdanm	0:9b334a45a8ff	371	}
bogdanm	0:9b334a45a8ff	372	}
mbed_official	19:112740acecfa	373	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	374
mbed_official	19:112740acecfa	375	/----------------------------- SDIO Configuration -------------------------/
bogdanm	0:9b334a45a8ff	376	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
bogdanm	0:9b334a45a8ff	377	{
bogdanm	0:9b334a45a8ff	378	/* Check the parameters */
bogdanm	0:9b334a45a8ff	379	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	/* Configure the SDIO clock source */
bogdanm	0:9b334a45a8ff	382	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
bogdanm	0:9b334a45a8ff	383	}
mbed_official	19:112740acecfa	384	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	385
mbed_official	19:112740acecfa	386	/------------------------------ SPDIFRX Configuration ---------------------/
bogdanm	0:9b334a45a8ff	387	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
bogdanm	0:9b334a45a8ff	388	{
bogdanm	0:9b334a45a8ff	389	/* Check the parameters */
bogdanm	0:9b334a45a8ff	390	assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* Configure the SPDIFRX clock source */
bogdanm	0:9b334a45a8ff	393	__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
bogdanm	0:9b334a45a8ff	394	/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
bogdanm	0:9b334a45a8ff	395	if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
bogdanm	0:9b334a45a8ff	396	{
bogdanm	0:9b334a45a8ff	397	plli2sused = 1;
bogdanm	0:9b334a45a8ff	398	}
bogdanm	0:9b334a45a8ff	399	}
mbed_official	19:112740acecfa	400	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	401
mbed_official	19:112740acecfa	402	/---------------------------- PLLI2S Configuration ------------------------/
bogdanm	0:9b334a45a8ff	403	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
bogdanm	0:9b334a45a8ff	404	I2S on APB2 or SPDIFRX */
bogdanm	0:9b334a45a8ff	405	if((plli2sused == 1) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
bogdanm	0:9b334a45a8ff	406	{
bogdanm	0:9b334a45a8ff	407	/* Disable the PLLI2S */
bogdanm	0:9b334a45a8ff	408	__HAL_RCC_PLLI2S_DISABLE();
bogdanm	0:9b334a45a8ff	409	/* Get tick */
bogdanm	0:9b334a45a8ff	410	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	411	/* Wait till PLLI2S is disabled */
bogdanm	0:9b334a45a8ff	412	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm	0:9b334a45a8ff	413	{
bogdanm	0:9b334a45a8ff	414	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	415	{
bogdanm	0:9b334a45a8ff	416	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	417	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	418	}
bogdanm	0:9b334a45a8ff	419	}
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/* check for common PLLI2S Parameters */
bogdanm	0:9b334a45a8ff	422	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
bogdanm	0:9b334a45a8ff	423	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
bogdanm	0:9b334a45a8ff	424
mbed_official	19:112740acecfa	425	/------ In Case of PLLI2S is selected as source clock for I2S -----------/
bogdanm	0:9b334a45a8ff	426	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
bogdanm	0:9b334a45a8ff	427	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
bogdanm	0:9b334a45a8ff	428	{
bogdanm	0:9b334a45a8ff	429	/* check for Parameters */
bogdanm	0:9b334a45a8ff	430	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
bogdanm	0:9b334a45a8ff	433	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	434	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
bogdanm	0:9b334a45a8ff	435	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	436	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	437	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	438	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	439	}
mbed_official	19:112740acecfa	440
mbed_official	19:112740acecfa	441	/------- In Case of PLLI2S is selected as source clock for SAI ----------/
bogdanm	0:9b334a45a8ff	442	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
bogdanm	0:9b334a45a8ff	443	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
bogdanm	0:9b334a45a8ff	444	{
bogdanm	0:9b334a45a8ff	445	/* Check for PLLI2S Parameters */
bogdanm	0:9b334a45a8ff	446	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
bogdanm	0:9b334a45a8ff	447	/* Check for PLLI2S/DIVQ parameters */
bogdanm	0:9b334a45a8ff	448	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
bogdanm	0:9b334a45a8ff	451	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	452	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	453	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	454	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm	0:9b334a45a8ff	455	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	456	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
bogdanm	0:9b334a45a8ff	457	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
bogdanm	0:9b334a45a8ff	460	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
bogdanm	0:9b334a45a8ff	461	}
bogdanm	0:9b334a45a8ff	462
mbed_official	19:112740acecfa	463	/------ In Case of PLLI2S is selected as source clock for SPDIFRX -------/
bogdanm	0:9b334a45a8ff	464	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
bogdanm	0:9b334a45a8ff	465	{
bogdanm	0:9b334a45a8ff	466	/* check for Parameters */
bogdanm	0:9b334a45a8ff	467	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
bogdanm	0:9b334a45a8ff	468	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	469	plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	470	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	471	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	472	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	473	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
bogdanm	0:9b334a45a8ff	474	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
bogdanm	0:9b334a45a8ff	475	}
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/----------------- In Case of PLLI2S is just selected -----------------/
bogdanm	0:9b334a45a8ff	478	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	/* Check for Parameters */
bogdanm	0:9b334a45a8ff	481	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
bogdanm	0:9b334a45a8ff	482	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	483	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	486	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	487	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	488	}
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	/* Enable the PLLI2S */
bogdanm	0:9b334a45a8ff	491	__HAL_RCC_PLLI2S_ENABLE();
bogdanm	0:9b334a45a8ff	492	/* Get tick */
bogdanm	0:9b334a45a8ff	493	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	494	/* Wait till PLLI2S is ready */
bogdanm	0:9b334a45a8ff	495	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm	0:9b334a45a8ff	496	{
bogdanm	0:9b334a45a8ff	497	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	498	{
bogdanm	0:9b334a45a8ff	499	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	500	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503	}
mbed_official	19:112740acecfa	504	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	505
mbed_official	19:112740acecfa	506	/----------------------------- PLLSAI Configuration -----------------------/
bogdanm	0:9b334a45a8ff	507	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
bogdanm	0:9b334a45a8ff	508	if(pllsaiused == 1)
bogdanm	0:9b334a45a8ff	509	{
bogdanm	0:9b334a45a8ff	510	/* Disable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	511	__HAL_RCC_PLLSAI_DISABLE();
bogdanm	0:9b334a45a8ff	512	/* Get tick */
bogdanm	0:9b334a45a8ff	513	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	514	/* Wait till PLLSAI is disabled */
bogdanm	0:9b334a45a8ff	515	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
bogdanm	0:9b334a45a8ff	516	{
bogdanm	0:9b334a45a8ff	517	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	518	{
bogdanm	0:9b334a45a8ff	519	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	520	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	521	}
bogdanm	0:9b334a45a8ff	522	}
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Check the PLLSAI division factors */
bogdanm	0:9b334a45a8ff	525	assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
bogdanm	0:9b334a45a8ff	526	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
bogdanm	0:9b334a45a8ff	527
mbed_official	19:112740acecfa	528	/------ In Case of PLLSAI is selected as source clock for SAI -----------/
bogdanm	0:9b334a45a8ff	529	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|
bogdanm	0:9b334a45a8ff	530	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	/* check for PLLSAIQ Parameter */
bogdanm	0:9b334a45a8ff	533	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
bogdanm	0:9b334a45a8ff	534	/* check for PLLSAI/DIVQ Parameter */
bogdanm	0:9b334a45a8ff	535	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
bogdanm	0:9b334a45a8ff	538	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	539	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	540	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	541	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
bogdanm	0:9b334a45a8ff	542	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0);
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
bogdanm	0:9b334a45a8ff	545	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
bogdanm	0:9b334a45a8ff	546	}
bogdanm	0:9b334a45a8ff	547
mbed_official	19:112740acecfa	548	/------ In Case of PLLSAI is selected as source clock for CK48 ----------/
bogdanm	0:9b334a45a8ff	549	/* In Case of PLLI2S is selected as source clock for CK48 */
bogdanm	0:9b334a45a8ff	550	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
bogdanm	0:9b334a45a8ff	551	{
bogdanm	0:9b334a45a8ff	552	/* check for Parameters */
bogdanm	0:9b334a45a8ff	553	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
bogdanm	0:9b334a45a8ff	554	/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	555	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	556	/* Configure the PLLSAI division factors */
mbed_official	19:112740acecfa	557	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
bogdanm	0:9b334a45a8ff	558	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
bogdanm	0:9b334a45a8ff	559	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0);
bogdanm	0:9b334a45a8ff	560	}
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	/* Enable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	563	__HAL_RCC_PLLSAI_ENABLE();
bogdanm	0:9b334a45a8ff	564	/* Get tick */
bogdanm	0:9b334a45a8ff	565	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	566	/* Wait till PLLSAI is ready */
bogdanm	0:9b334a45a8ff	567	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
bogdanm	0:9b334a45a8ff	568	{
bogdanm	0:9b334a45a8ff	569	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	570	{
bogdanm	0:9b334a45a8ff	571	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	572	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	573	}
bogdanm	0:9b334a45a8ff	574	}
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576	return HAL_OK;
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	/**
bogdanm	0:9b334a45a8ff	580	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
bogdanm	0:9b334a45a8ff	581	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	582	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	583	* will be configured.
bogdanm	0:9b334a45a8ff	584	* @retval None
bogdanm	0:9b334a45a8ff	585	*/
bogdanm	0:9b334a45a8ff	586	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	587	{
bogdanm	0:9b334a45a8ff	588	uint32_t tempreg;
bogdanm	0:9b334a45a8ff	589
bogdanm	0:9b334a45a8ff	590	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	591	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
bogdanm	0:9b334a45a8ff	592	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
bogdanm	0:9b334a45a8ff	593	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
bogdanm	0:9b334a45a8ff	594	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_FMPI2C1 \|\
bogdanm	0:9b334a45a8ff	595	RCC_PERIPHCLK_CK48 \| RCC_PERIPHCLK_SDIO \|\
bogdanm	0:9b334a45a8ff	596	RCC_PERIPHCLK_SPDIFRX;
bogdanm	0:9b334a45a8ff	597
mbed_official	19:112740acecfa	598	/* Get the PLLI2S Clock configuration --------------------------------------*/
bogdanm	0:9b334a45a8ff	599	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
bogdanm	0:9b334a45a8ff	600	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
bogdanm	0:9b334a45a8ff	601	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	602	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
bogdanm	0:9b334a45a8ff	603	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	19:112740acecfa	604	/* Get the PLLSAI Clock configuration --------------------------------------*/
bogdanm	0:9b334a45a8ff	605	PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
bogdanm	0:9b334a45a8ff	606	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
bogdanm	0:9b334a45a8ff	607	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	608	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	19:112740acecfa	609	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
bogdanm	0:9b334a45a8ff	610	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
bogdanm	0:9b334a45a8ff	611	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
bogdanm	0:9b334a45a8ff	612
mbed_official	19:112740acecfa	613	/* Get the SAI1 clock configuration ----------------------------------------*/
bogdanm	0:9b334a45a8ff	614	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
bogdanm	0:9b334a45a8ff	615
mbed_official	19:112740acecfa	616	/* Get the SAI2 clock configuration ----------------------------------------*/
bogdanm	0:9b334a45a8ff	617	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
bogdanm	0:9b334a45a8ff	618
mbed_official	19:112740acecfa	619	/* Get the I2S APB1 clock configuration ------------------------------------*/
bogdanm	0:9b334a45a8ff	620	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
bogdanm	0:9b334a45a8ff	621
mbed_official	19:112740acecfa	622	/* Get the I2S APB2 clock configuration ------------------------------------*/
bogdanm	0:9b334a45a8ff	623	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
bogdanm	0:9b334a45a8ff	624
mbed_official	19:112740acecfa	625	/* Get the RTC Clock configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	626	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
bogdanm	0:9b334a45a8ff	627	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	628
mbed_official	19:112740acecfa	629	/* Get the CEC clock configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	630	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
bogdanm	0:9b334a45a8ff	631
mbed_official	19:112740acecfa	632	/* Get the FMPI2C1 clock configuration -------------------------------------*/
bogdanm	0:9b334a45a8ff	633	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
bogdanm	0:9b334a45a8ff	634
mbed_official	19:112740acecfa	635	/* Get the CK48 clock configuration ----------------------------------------*/
bogdanm	0:9b334a45a8ff	636	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
bogdanm	0:9b334a45a8ff	637
mbed_official	19:112740acecfa	638	/* Get the SDIO clock configuration ----------------------------------------*/
bogdanm	0:9b334a45a8ff	639	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
bogdanm	0:9b334a45a8ff	640
mbed_official	19:112740acecfa	641	/* Get the SPDIFRX clock configuration -------------------------------------*/
bogdanm	0:9b334a45a8ff	642	PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
bogdanm	0:9b334a45a8ff	643
mbed_official	19:112740acecfa	644	/* Get the TIM Prescaler configuration -------------------------------------*/
bogdanm	0:9b334a45a8ff	645	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649	else
bogdanm	0:9b334a45a8ff	650	{
bogdanm	0:9b334a45a8ff	651	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
bogdanm	0:9b334a45a8ff	652	}
bogdanm	0:9b334a45a8ff	653	}
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	/**
bogdanm	0:9b334a45a8ff	656	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
bogdanm	0:9b334a45a8ff	657	* @note Return 0 if peripheral clock identifier not managed by this API
bogdanm	0:9b334a45a8ff	658	* @param PeriphClk: Peripheral clock identifier
bogdanm	0:9b334a45a8ff	659	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	660	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
bogdanm	0:9b334a45a8ff	661	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
bogdanm	0:9b334a45a8ff	662	* @retval Frequency in KHz
bogdanm	0:9b334a45a8ff	663	*/
bogdanm	0:9b334a45a8ff	664	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
bogdanm	0:9b334a45a8ff	665	{
bogdanm	0:9b334a45a8ff	666	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	667	/* This variable used to store the SAI clock frequency (value in Hz) */
bogdanm	0:9b334a45a8ff	668	uint32_t frequency = 0;
bogdanm	0:9b334a45a8ff	669	/* This variable used to store the VCO Input (value in Hz) */
bogdanm	0:9b334a45a8ff	670	uint32_t vcoinput = 0;
bogdanm	0:9b334a45a8ff	671	/* This variable used to store the SAI clock source */
bogdanm	0:9b334a45a8ff	672	uint32_t saiclocksource = 0;
bogdanm	0:9b334a45a8ff	673	if ((PeriphClk == RCC_PERIPHCLK_SAI1) \|\| (PeriphClk == RCC_PERIPHCLK_SAI2))
bogdanm	0:9b334a45a8ff	674	{
bogdanm	0:9b334a45a8ff	675	saiclocksource = RCC->DCKCFGR;
bogdanm	0:9b334a45a8ff	676	saiclocksource &= (RCC_DCKCFGR_SAI1SRC \| RCC_DCKCFGR_SAI2SRC);
bogdanm	0:9b334a45a8ff	677	switch (saiclocksource)
bogdanm	0:9b334a45a8ff	678	{
bogdanm	0:9b334a45a8ff	679	case 0: /* PLLSAI is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	/* Configure the PLLSAI division factor */
bogdanm	0:9b334a45a8ff	682	/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
bogdanm	0:9b334a45a8ff	683	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	684	{
bogdanm	0:9b334a45a8ff	685	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	686	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
bogdanm	0:9b334a45a8ff	687	}
bogdanm	0:9b334a45a8ff	688	else
bogdanm	0:9b334a45a8ff	689	{
bogdanm	0:9b334a45a8ff	690	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	691	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	694	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
bogdanm	0:9b334a45a8ff	695	tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
bogdanm	0:9b334a45a8ff	696	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg1);
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
bogdanm	0:9b334a45a8ff	699	tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
bogdanm	0:9b334a45a8ff	700	frequency = frequency/(tmpreg1);
bogdanm	0:9b334a45a8ff	701	break;
bogdanm	0:9b334a45a8ff	702	}
bogdanm	0:9b334a45a8ff	703	case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	704	case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	/* Configure the PLLI2S division factor */
bogdanm	0:9b334a45a8ff	707	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm	0:9b334a45a8ff	708	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	709	{
bogdanm	0:9b334a45a8ff	710	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	711	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
bogdanm	0:9b334a45a8ff	712	}
bogdanm	0:9b334a45a8ff	713	else
bogdanm	0:9b334a45a8ff	714	{
bogdanm	0:9b334a45a8ff	715	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	716	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
bogdanm	0:9b334a45a8ff	717	}
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	720	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
bogdanm	0:9b334a45a8ff	721	tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
bogdanm	0:9b334a45a8ff	722	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg1);
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
bogdanm	0:9b334a45a8ff	725	tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
bogdanm	0:9b334a45a8ff	726	frequency = frequency/(tmpreg1);
bogdanm	0:9b334a45a8ff	727	break;
bogdanm	0:9b334a45a8ff	728	}
bogdanm	0:9b334a45a8ff	729	case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	730	case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	731	{
bogdanm	0:9b334a45a8ff	732	/* Configure the PLLI2S division factor */
bogdanm	0:9b334a45a8ff	733	/* PLL_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	734	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	735	{
bogdanm	0:9b334a45a8ff	736	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	737	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm	0:9b334a45a8ff	738	}
bogdanm	0:9b334a45a8ff	739	else
bogdanm	0:9b334a45a8ff	740	{
bogdanm	0:9b334a45a8ff	741	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	742	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
bogdanm	0:9b334a45a8ff	743	}
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	/* PLL_VCO Output = PLL_VCO Input * PLLN */
bogdanm	0:9b334a45a8ff	746	/* SAI_CLK_x = PLL_VCO Output/PLLR */
bogdanm	0:9b334a45a8ff	747	tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28;
bogdanm	0:9b334a45a8ff	748	frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6))/(tmpreg1);
bogdanm	0:9b334a45a8ff	749	break;
bogdanm	0:9b334a45a8ff	750	}
bogdanm	0:9b334a45a8ff	751	case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	752	{
bogdanm	0:9b334a45a8ff	753	frequency = EXTERNAL_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	754	break;
bogdanm	0:9b334a45a8ff	755	}
bogdanm	0:9b334a45a8ff	756	case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	757	{
bogdanm	0:9b334a45a8ff	758	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	761	frequency = (uint32_t)(HSI_VALUE);
bogdanm	0:9b334a45a8ff	762	}
bogdanm	0:9b334a45a8ff	763	else
bogdanm	0:9b334a45a8ff	764	{
bogdanm	0:9b334a45a8ff	765	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	766	frequency = (uint32_t)(HSE_VALUE);
bogdanm	0:9b334a45a8ff	767	}
bogdanm	0:9b334a45a8ff	768	break;
bogdanm	0:9b334a45a8ff	769	}
bogdanm	0:9b334a45a8ff	770	default :
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	break;
bogdanm	0:9b334a45a8ff	773	}
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775	}
bogdanm	0:9b334a45a8ff	776	return frequency;
bogdanm	0:9b334a45a8ff	777	}
bogdanm	0:9b334a45a8ff	778
bogdanm	0:9b334a45a8ff	779	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	780
mbed_official	19:112740acecfa	781	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
mbed_official	19:112740acecfa	782	/**
mbed_official	19:112740acecfa	783	* @brief Initializes the RCC extended peripherals clocks according to the specified
mbed_official	19:112740acecfa	784	* parameters in the RCC_PeriphCLKInitTypeDef.
mbed_official	19:112740acecfa	785	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	19:112740acecfa	786	* contains the configuration information for the Extended Peripherals
mbed_official	19:112740acecfa	787	* clocks(I2S, SAI, LTDC, RTC and TIM).
mbed_official	19:112740acecfa	788	*
mbed_official	19:112740acecfa	789	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
mbed_official	19:112740acecfa	790	* the RTC clock source; in this case the Backup domain will be reset in
mbed_official	19:112740acecfa	791	* order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official	19:112740acecfa	792	* the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official	19:112740acecfa	793	*
mbed_official	19:112740acecfa	794	* @retval HAL status
mbed_official	19:112740acecfa	795	*/
mbed_official	19:112740acecfa	796	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	19:112740acecfa	797	{
mbed_official	19:112740acecfa	798	uint32_t tickstart = 0;
mbed_official	19:112740acecfa	799	uint32_t tmpreg1 = 0;
mbed_official	19:112740acecfa	800	uint32_t pllsaip = 0;
mbed_official	19:112740acecfa	801	uint32_t pllsaiq = 0;
mbed_official	19:112740acecfa	802	uint32_t pllsair = 0;
mbed_official	19:112740acecfa	803
mbed_official	19:112740acecfa	804	/* Check the parameters */
mbed_official	19:112740acecfa	805	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official	19:112740acecfa	806
mbed_official	19:112740acecfa	807	/--------------------------- CLK48 Configuration --------------------------/
mbed_official	19:112740acecfa	808	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
mbed_official	19:112740acecfa	809	{
mbed_official	19:112740acecfa	810	/* Check the parameters */
mbed_official	19:112740acecfa	811	assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
mbed_official	19:112740acecfa	812
mbed_official	19:112740acecfa	813	/* Configure the CLK48 clock source */
mbed_official	19:112740acecfa	814	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
mbed_official	19:112740acecfa	815	}
mbed_official	19:112740acecfa	816	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	817
mbed_official	19:112740acecfa	818	/------------------------------ SDIO Configuration ------------------------/
mbed_official	19:112740acecfa	819	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
mbed_official	19:112740acecfa	820	{
mbed_official	19:112740acecfa	821	/* Check the parameters */
mbed_official	19:112740acecfa	822	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
mbed_official	19:112740acecfa	823
mbed_official	19:112740acecfa	824	/* Configure the SDIO clock source */
mbed_official	19:112740acecfa	825	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
mbed_official	19:112740acecfa	826	}
mbed_official	19:112740acecfa	827	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	828
mbed_official	19:112740acecfa	829	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
mbed_official	19:112740acecfa	830	/------------------- Common configuration SAI/I2S -------------------------/
mbed_official	19:112740acecfa	831	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
mbed_official	19:112740acecfa	832	factor is common parameters for both peripherals */
mbed_official	19:112740acecfa	833	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
mbed_official	19:112740acecfa	834	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) \|\|
mbed_official	19:112740acecfa	835	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
mbed_official	19:112740acecfa	836	{
mbed_official	19:112740acecfa	837	/* check for Parameters */
mbed_official	19:112740acecfa	838	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official	19:112740acecfa	839
mbed_official	19:112740acecfa	840	/* Disable the PLLI2S */
mbed_official	19:112740acecfa	841	__HAL_RCC_PLLI2S_DISABLE();
mbed_official	19:112740acecfa	842	/* Get tick */
mbed_official	19:112740acecfa	843	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	844	/* Wait till PLLI2S is disabled */
mbed_official	19:112740acecfa	845	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official	19:112740acecfa	846	{
mbed_official	19:112740acecfa	847	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	848	{
mbed_official	19:112740acecfa	849	/* return in case of Timeout detected */
mbed_official	19:112740acecfa	850	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	851	}
mbed_official	19:112740acecfa	852	}
mbed_official	19:112740acecfa	853
mbed_official	19:112740acecfa	854	/---------------------- I2S configuration -------------------------------/
mbed_official	19:112740acecfa	855	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
mbed_official	19:112740acecfa	856	only for I2S configuration */
mbed_official	19:112740acecfa	857	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official	19:112740acecfa	858	{
mbed_official	19:112740acecfa	859	/* check for Parameters */
mbed_official	19:112740acecfa	860	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official	19:112740acecfa	861	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	862	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official	19:112740acecfa	863	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official	19:112740acecfa	864	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	19:112740acecfa	865	}
mbed_official	19:112740acecfa	866
mbed_official	19:112740acecfa	867	/---------------------------- SAI configuration -------------------------/
mbed_official	19:112740acecfa	868	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
mbed_official	19:112740acecfa	869	be added only for SAI configuration */
mbed_official	19:112740acecfa	870	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official	19:112740acecfa	871	{
mbed_official	19:112740acecfa	872	/* Check the PLLI2S division factors */
mbed_official	19:112740acecfa	873	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official	19:112740acecfa	874	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
mbed_official	19:112740acecfa	875
mbed_official	19:112740acecfa	876	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
mbed_official	19:112740acecfa	877	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	19:112740acecfa	878	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	879	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
mbed_official	19:112740acecfa	880	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
mbed_official	19:112740acecfa	881	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
mbed_official	19:112740acecfa	882	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
mbed_official	19:112740acecfa	883	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
mbed_official	19:112740acecfa	884	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
mbed_official	19:112740acecfa	885	}
mbed_official	19:112740acecfa	886
mbed_official	19:112740acecfa	887	/----------------- In Case of PLLI2S is just selected -----------------/
mbed_official	19:112740acecfa	888	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
mbed_official	19:112740acecfa	889	{
mbed_official	19:112740acecfa	890	/* Check for Parameters */
mbed_official	19:112740acecfa	891	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official	19:112740acecfa	892	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official	19:112740acecfa	893
mbed_official	19:112740acecfa	894	/* Configure the PLLI2S multiplication and division factors */
mbed_official	19:112740acecfa	895	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	19:112740acecfa	896	}
mbed_official	19:112740acecfa	897
mbed_official	19:112740acecfa	898	/* Enable the PLLI2S */
mbed_official	19:112740acecfa	899	__HAL_RCC_PLLI2S_ENABLE();
mbed_official	19:112740acecfa	900	/* Get tick */
mbed_official	19:112740acecfa	901	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	902	/* Wait till PLLI2S is ready */
mbed_official	19:112740acecfa	903	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official	19:112740acecfa	904	{
mbed_official	19:112740acecfa	905	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	906	{
mbed_official	19:112740acecfa	907	/* return in case of Timeout detected */
mbed_official	19:112740acecfa	908	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	909	}
mbed_official	19:112740acecfa	910	}
mbed_official	19:112740acecfa	911	}
mbed_official	19:112740acecfa	912	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	913
mbed_official	19:112740acecfa	914	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
mbed_official	19:112740acecfa	915	/----------------------- Common configuration SAI/LTDC --------------------/
mbed_official	19:112740acecfa	916	/* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
mbed_official	19:112740acecfa	917	factor is common parameters for these peripherals */
mbed_official	19:112740acecfa	918	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
mbed_official	19:112740acecfa	919	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\|
mbed_official	19:112740acecfa	920	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) &&
mbed_official	19:112740acecfa	921	(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)))
mbed_official	19:112740acecfa	922	{
mbed_official	19:112740acecfa	923	/* Check the PLLSAI division factors */
mbed_official	19:112740acecfa	924	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
mbed_official	19:112740acecfa	925
mbed_official	19:112740acecfa	926	/* Disable PLLSAI Clock */
mbed_official	19:112740acecfa	927	__HAL_RCC_PLLSAI_DISABLE();
mbed_official	19:112740acecfa	928	/* Get tick */
mbed_official	19:112740acecfa	929	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	930	/* Wait till PLLSAI is disabled */
mbed_official	19:112740acecfa	931	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
mbed_official	19:112740acecfa	932	{
mbed_official	19:112740acecfa	933	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	934	{
mbed_official	19:112740acecfa	935	/* return in case of Timeout detected */
mbed_official	19:112740acecfa	936	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	937	}
mbed_official	19:112740acecfa	938	}
mbed_official	19:112740acecfa	939
mbed_official	19:112740acecfa	940	/---------------------------- SAI configuration -------------------------/
mbed_official	19:112740acecfa	941	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
mbed_official	19:112740acecfa	942	be added only for SAI configuration */
mbed_official	19:112740acecfa	943	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
mbed_official	19:112740acecfa	944	{
mbed_official	19:112740acecfa	945	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
mbed_official	19:112740acecfa	946	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
mbed_official	19:112740acecfa	947
mbed_official	19:112740acecfa	948	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
mbed_official	19:112740acecfa	949	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
mbed_official	19:112740acecfa	950	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official	19:112740acecfa	951	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official	19:112740acecfa	952	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official	19:112740acecfa	953	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	19:112740acecfa	954	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
mbed_official	19:112740acecfa	955	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
mbed_official	19:112740acecfa	956	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
mbed_official	19:112740acecfa	957	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
mbed_official	19:112740acecfa	958	}
mbed_official	19:112740acecfa	959
mbed_official	19:112740acecfa	960	/---------------------------- LTDC configuration ------------------------/
mbed_official	19:112740acecfa	961	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
mbed_official	19:112740acecfa	962	{
mbed_official	19:112740acecfa	963	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
mbed_official	19:112740acecfa	964	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
mbed_official	19:112740acecfa	965
mbed_official	19:112740acecfa	966	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
mbed_official	19:112740acecfa	967	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
mbed_official	19:112740acecfa	968	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official	19:112740acecfa	969	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	19:112740acecfa	970	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official	19:112740acecfa	971	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	19:112740acecfa	972	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
mbed_official	19:112740acecfa	973	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
mbed_official	19:112740acecfa	974	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
mbed_official	19:112740acecfa	975	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
mbed_official	19:112740acecfa	976	}
mbed_official	19:112740acecfa	977
mbed_official	19:112740acecfa	978	/---------------------------- CLK48 configuration ------------------------/
mbed_official	19:112740acecfa	979	/* Configure the PLLSAI when it is used as clock source for CLK48 */
mbed_official	19:112740acecfa	980	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == (RCC_PERIPHCLK_CK48)) &&
mbed_official	19:112740acecfa	981	(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
mbed_official	19:112740acecfa	982	{
mbed_official	19:112740acecfa	983	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
mbed_official	19:112740acecfa	984
mbed_official	19:112740acecfa	985	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official	19:112740acecfa	986	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	19:112740acecfa	987	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official	19:112740acecfa	988	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official	19:112740acecfa	989	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official	19:112740acecfa	990	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	19:112740acecfa	991	/* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
mbed_official	19:112740acecfa	992	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
mbed_official	19:112740acecfa	993	}
mbed_official	19:112740acecfa	994
mbed_official	19:112740acecfa	995	/* Enable PLLSAI Clock */
mbed_official	19:112740acecfa	996	__HAL_RCC_PLLSAI_ENABLE();
mbed_official	19:112740acecfa	997	/* Get tick */
mbed_official	19:112740acecfa	998	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	999	/* Wait till PLLSAI is ready */
mbed_official	19:112740acecfa	1000	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
mbed_official	19:112740acecfa	1001	{
mbed_official	19:112740acecfa	1002	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1003	{
mbed_official	19:112740acecfa	1004	/* return in case of Timeout detected */
mbed_official	19:112740acecfa	1005	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1006	}
mbed_official	19:112740acecfa	1007	}
mbed_official	19:112740acecfa	1008	}
mbed_official	19:112740acecfa	1009
mbed_official	19:112740acecfa	1010	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1011
mbed_official	19:112740acecfa	1012	/---------------------------- RTC configuration ---------------------------/
mbed_official	19:112740acecfa	1013	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	19:112740acecfa	1014	{
mbed_official	19:112740acecfa	1015	/* Enable Power Clock*/
mbed_official	19:112740acecfa	1016	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	19:112740acecfa	1017
mbed_official	19:112740acecfa	1018	/* Enable write access to Backup domain */
mbed_official	19:112740acecfa	1019	PWR->CR \|= PWR_CR_DBP;
mbed_official	19:112740acecfa	1020
mbed_official	19:112740acecfa	1021	/* Get tick */
mbed_official	19:112740acecfa	1022	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	1023
mbed_official	19:112740acecfa	1024	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	19:112740acecfa	1025	{
mbed_official	19:112740acecfa	1026	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1027	{
mbed_official	19:112740acecfa	1028	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1029	}
mbed_official	19:112740acecfa	1030	}
mbed_official	19:112740acecfa	1031	/* Reset the Backup domain only if the RTC Clock source selection is modified */
mbed_official	19:112740acecfa	1032	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	19:112740acecfa	1033	{
mbed_official	19:112740acecfa	1034	/* Store the content of BDCR register before the reset of Backup Domain */
mbed_official	19:112740acecfa	1035	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official	19:112740acecfa	1036	/* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official	19:112740acecfa	1037	__HAL_RCC_BACKUPRESET_FORCE();
mbed_official	19:112740acecfa	1038	__HAL_RCC_BACKUPRESET_RELEASE();
mbed_official	19:112740acecfa	1039	/* Restore the Content of BDCR register */
mbed_official	19:112740acecfa	1040	RCC->BDCR = tmpreg1;
mbed_official	19:112740acecfa	1041
mbed_official	19:112740acecfa	1042	/* Wait for LSERDY if LSE was enabled */
mbed_official	19:112740acecfa	1043	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
mbed_official	19:112740acecfa	1044	{
mbed_official	19:112740acecfa	1045	/* Get tick */
mbed_official	19:112740acecfa	1046	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	1047
mbed_official	19:112740acecfa	1048	/* Wait till LSE is ready */
mbed_official	19:112740acecfa	1049	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	19:112740acecfa	1050	{
mbed_official	19:112740acecfa	1051	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1052	{
mbed_official	19:112740acecfa	1053	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1054	}
mbed_official	19:112740acecfa	1055	}
mbed_official	19:112740acecfa	1056	}
mbed_official	19:112740acecfa	1057	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official	19:112740acecfa	1058	}
mbed_official	19:112740acecfa	1059	}
mbed_official	19:112740acecfa	1060	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1061
mbed_official	19:112740acecfa	1062	/---------------------------- TIM configuration ---------------------------/
mbed_official	19:112740acecfa	1063	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
mbed_official	19:112740acecfa	1064	{
mbed_official	19:112740acecfa	1065	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
mbed_official	19:112740acecfa	1066	}
mbed_official	19:112740acecfa	1067	return HAL_OK;
mbed_official	19:112740acecfa	1068	}
mbed_official	19:112740acecfa	1069
mbed_official	19:112740acecfa	1070	/**
mbed_official	19:112740acecfa	1071	* @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
mbed_official	19:112740acecfa	1072	* RCC configuration registers.
mbed_official	19:112740acecfa	1073	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	19:112740acecfa	1074	* will be configured.
mbed_official	19:112740acecfa	1075	* @retval None
mbed_official	19:112740acecfa	1076	*/
mbed_official	19:112740acecfa	1077	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	19:112740acecfa	1078	{
mbed_official	19:112740acecfa	1079	uint32_t tempreg;
mbed_official	19:112740acecfa	1080
mbed_official	19:112740acecfa	1081	/* Set all possible values for the extended clock type parameter------------*/
mbed_official	19:112740acecfa	1082	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \|\
mbed_official	19:112740acecfa	1083	RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \|\
mbed_official	19:112740acecfa	1084	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
mbed_official	19:112740acecfa	1085	RCC_PERIPHCLK_CK48 \| RCC_PERIPHCLK_SDIO;
mbed_official	19:112740acecfa	1086
mbed_official	19:112740acecfa	1087	/* Get the PLLI2S Clock configuration --------------------------------------*/
mbed_official	19:112740acecfa	1088	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official	19:112740acecfa	1089	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	19:112740acecfa	1090	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
mbed_official	19:112740acecfa	1091	/* Get the PLLSAI Clock configuration --------------------------------------*/
mbed_official	19:112740acecfa	1092	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
mbed_official	19:112740acecfa	1093	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official	19:112740acecfa	1094	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	19:112740acecfa	1095	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
mbed_official	19:112740acecfa	1096	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
mbed_official	19:112740acecfa	1097	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
mbed_official	19:112740acecfa	1098	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
mbed_official	19:112740acecfa	1099	/* Get the RTC Clock configuration -----------------------------------------*/
mbed_official	19:112740acecfa	1100	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official	19:112740acecfa	1101	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official	19:112740acecfa	1102
mbed_official	19:112740acecfa	1103	/* Get the CK48 clock configuration --------------------------------------*/
mbed_official	19:112740acecfa	1104	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
mbed_official	19:112740acecfa	1105
mbed_official	19:112740acecfa	1106	/* Get the SDIO clock configuration ----------------------------------------*/
mbed_official	19:112740acecfa	1107	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
mbed_official	19:112740acecfa	1108
mbed_official	19:112740acecfa	1109	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
mbed_official	19:112740acecfa	1110	{
mbed_official	19:112740acecfa	1111	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
mbed_official	19:112740acecfa	1112	}
mbed_official	19:112740acecfa	1113	else
mbed_official	19:112740acecfa	1114	{
mbed_official	19:112740acecfa	1115	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
mbed_official	19:112740acecfa	1116	}
mbed_official	19:112740acecfa	1117	}
mbed_official	19:112740acecfa	1118	#endif /* STM32F469xx \|\| STM32F479xx */
mbed_official	19:112740acecfa	1119
mbed_official	19:112740acecfa	1120	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
mbed_official	19:112740acecfa	1121	/**
mbed_official	19:112740acecfa	1122	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official	19:112740acecfa	1123	* RCC_PeriphCLKInitTypeDef.
mbed_official	19:112740acecfa	1124	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	19:112740acecfa	1125	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
mbed_official	19:112740acecfa	1126	*
mbed_official	19:112740acecfa	1127	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
mbed_official	19:112740acecfa	1128	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
mbed_official	19:112740acecfa	1129	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
mbed_official	19:112740acecfa	1130	*
mbed_official	19:112740acecfa	1131	* @retval HAL status
mbed_official	19:112740acecfa	1132	*/
mbed_official	19:112740acecfa	1133	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	19:112740acecfa	1134	{
mbed_official	19:112740acecfa	1135	uint32_t tickstart = 0;
mbed_official	19:112740acecfa	1136	uint32_t tmpreg1 = 0;
mbed_official	19:112740acecfa	1137
mbed_official	19:112740acecfa	1138	/* Check the parameters */
mbed_official	19:112740acecfa	1139	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official	19:112740acecfa	1140
mbed_official	19:112740acecfa	1141	/---------------------------- RTC configuration ---------------------------/
mbed_official	19:112740acecfa	1142	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	19:112740acecfa	1143	{
mbed_official	19:112740acecfa	1144	/* Enable Power Clock*/
mbed_official	19:112740acecfa	1145	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	19:112740acecfa	1146
mbed_official	19:112740acecfa	1147	/* Enable write access to Backup domain */
mbed_official	19:112740acecfa	1148	PWR->CR \|= PWR_CR_DBP;
mbed_official	19:112740acecfa	1149
mbed_official	19:112740acecfa	1150	/* Get tick */
mbed_official	19:112740acecfa	1151	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	1152
mbed_official	19:112740acecfa	1153	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	19:112740acecfa	1154	{
mbed_official	19:112740acecfa	1155	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1156	{
mbed_official	19:112740acecfa	1157	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1158	}
mbed_official	19:112740acecfa	1159	}
mbed_official	19:112740acecfa	1160	/* Reset the Backup domain only if the RTC Clock source selection is modified */
mbed_official	19:112740acecfa	1161	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	19:112740acecfa	1162	{
mbed_official	19:112740acecfa	1163	/* Store the content of BDCR register before the reset of Backup Domain */
mbed_official	19:112740acecfa	1164	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official	19:112740acecfa	1165	/* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official	19:112740acecfa	1166	__HAL_RCC_BACKUPRESET_FORCE();
mbed_official	19:112740acecfa	1167	__HAL_RCC_BACKUPRESET_RELEASE();
mbed_official	19:112740acecfa	1168	/* Restore the Content of BDCR register */
mbed_official	19:112740acecfa	1169	RCC->BDCR = tmpreg1;
mbed_official	19:112740acecfa	1170
mbed_official	19:112740acecfa	1171	/* Wait for LSERDY if LSE was enabled */
mbed_official	19:112740acecfa	1172	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
mbed_official	19:112740acecfa	1173	{
mbed_official	19:112740acecfa	1174	/* Get tick */
mbed_official	19:112740acecfa	1175	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	1176
mbed_official	19:112740acecfa	1177	/* Wait till LSE is ready */
mbed_official	19:112740acecfa	1178	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	19:112740acecfa	1179	{
mbed_official	19:112740acecfa	1180	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1181	{
mbed_official	19:112740acecfa	1182	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1183	}
mbed_official	19:112740acecfa	1184	}
mbed_official	19:112740acecfa	1185	}
mbed_official	19:112740acecfa	1186	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official	19:112740acecfa	1187	}
mbed_official	19:112740acecfa	1188	}
mbed_official	19:112740acecfa	1189	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1190
mbed_official	19:112740acecfa	1191	/---------------------------- TIM configuration ---------------------------/
mbed_official	19:112740acecfa	1192	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
mbed_official	19:112740acecfa	1193	{
mbed_official	19:112740acecfa	1194	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
mbed_official	19:112740acecfa	1195	}
mbed_official	19:112740acecfa	1196	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1197
mbed_official	19:112740acecfa	1198	/---------------------------- FMPI2C1 Configuration -----------------------/
mbed_official	19:112740acecfa	1199	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
mbed_official	19:112740acecfa	1200	{
mbed_official	19:112740acecfa	1201	/* Check the parameters */
mbed_official	19:112740acecfa	1202	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
mbed_official	19:112740acecfa	1203
mbed_official	19:112740acecfa	1204	/* Configure the FMPI2C1 clock source */
mbed_official	19:112740acecfa	1205	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
mbed_official	19:112740acecfa	1206	}
mbed_official	19:112740acecfa	1207	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1208
mbed_official	19:112740acecfa	1209	/---------------------------- LPTIM1 Configuration ------------------------/
mbed_official	19:112740acecfa	1210	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
mbed_official	19:112740acecfa	1211	{
mbed_official	19:112740acecfa	1212	/* Check the parameters */
mbed_official	19:112740acecfa	1213	assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
mbed_official	19:112740acecfa	1214
mbed_official	19:112740acecfa	1215	/* Configure the LPTIM1 clock source */
mbed_official	19:112740acecfa	1216	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
mbed_official	19:112740acecfa	1217	}
mbed_official	19:112740acecfa	1218
mbed_official	19:112740acecfa	1219	/---------------------------- I2S Configuration ------------------------/
mbed_official	19:112740acecfa	1220	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
mbed_official	19:112740acecfa	1221	{
mbed_official	19:112740acecfa	1222	/* Check the parameters */
mbed_official	19:112740acecfa	1223	assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
mbed_official	19:112740acecfa	1224
mbed_official	19:112740acecfa	1225	/* Configure the I2S clock source */
mbed_official	19:112740acecfa	1226	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
mbed_official	19:112740acecfa	1227	}
mbed_official	19:112740acecfa	1228
mbed_official	19:112740acecfa	1229	return HAL_OK;
mbed_official	19:112740acecfa	1230	}
mbed_official	19:112740acecfa	1231
mbed_official	19:112740acecfa	1232	/**
mbed_official	19:112740acecfa	1233	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	19:112740acecfa	1234	* RCC configuration registers.
mbed_official	19:112740acecfa	1235	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	19:112740acecfa	1236	* will be configured.
mbed_official	19:112740acecfa	1237	* @retval None
mbed_official	19:112740acecfa	1238	*/
mbed_official	19:112740acecfa	1239	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	19:112740acecfa	1240	{
mbed_official	19:112740acecfa	1241	uint32_t tempreg;
mbed_official	19:112740acecfa	1242
mbed_official	19:112740acecfa	1243	/* Set all possible values for the extended clock type parameter------------*/
mbed_official	19:112740acecfa	1244	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
mbed_official	19:112740acecfa	1245
mbed_official	19:112740acecfa	1246	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official	19:112740acecfa	1247	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official	19:112740acecfa	1248
mbed_official	19:112740acecfa	1249	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
mbed_official	19:112740acecfa	1250	{
mbed_official	19:112740acecfa	1251	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
mbed_official	19:112740acecfa	1252	}
mbed_official	19:112740acecfa	1253	else
mbed_official	19:112740acecfa	1254	{
mbed_official	19:112740acecfa	1255	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
mbed_official	19:112740acecfa	1256	}
mbed_official	19:112740acecfa	1257	/* Get the FMPI2C1 clock configuration -------------------------------------*/
mbed_official	19:112740acecfa	1258	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
mbed_official	19:112740acecfa	1259
mbed_official	19:112740acecfa	1260	/* Get the I2S clock configuration -----------------------------------------*/
mbed_official	19:112740acecfa	1261	PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
mbed_official	19:112740acecfa	1262
mbed_official	19:112740acecfa	1263
mbed_official	19:112740acecfa	1264	}
mbed_official	19:112740acecfa	1265	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
mbed_official	19:112740acecfa	1266
bogdanm	0:9b334a45a8ff	1267	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1268	/**
bogdanm	0:9b334a45a8ff	1269	* @brief Initializes the RCC extended peripherals clocks according to the specified
bogdanm	0:9b334a45a8ff	1270	* parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	1271	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1272	* contains the configuration information for the Extended Peripherals
bogdanm	0:9b334a45a8ff	1273	* clocks(I2S, SAI, LTDC RTC and TIM).
bogdanm	0:9b334a45a8ff	1274	*
bogdanm	0:9b334a45a8ff	1275	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm	0:9b334a45a8ff	1276	* the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	1277	* order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	1278	* the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	1279	*
bogdanm	0:9b334a45a8ff	1280	* @retval HAL status
bogdanm	0:9b334a45a8ff	1281	*/
bogdanm	0:9b334a45a8ff	1282	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	1283	{
bogdanm	0:9b334a45a8ff	1284	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1285	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1288	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm	0:9b334a45a8ff	1289
mbed_official	19:112740acecfa	1290	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
mbed_official	19:112740acecfa	1291	/----------------------- Common configuration SAI/I2S ----------------------/
bogdanm	0:9b334a45a8ff	1292	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
bogdanm	0:9b334a45a8ff	1293	factor is common parameters for both peripherals */
bogdanm	0:9b334a45a8ff	1294	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
bogdanm	0:9b334a45a8ff	1295	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
bogdanm	0:9b334a45a8ff	1296	{
bogdanm	0:9b334a45a8ff	1297	/* check for Parameters */
bogdanm	0:9b334a45a8ff	1298	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/* Disable the PLLI2S */
bogdanm	0:9b334a45a8ff	1301	__HAL_RCC_PLLI2S_DISABLE();
bogdanm	0:9b334a45a8ff	1302	/* Get tick */
bogdanm	0:9b334a45a8ff	1303	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1304	/* Wait till PLLI2S is disabled */
bogdanm	0:9b334a45a8ff	1305	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm	0:9b334a45a8ff	1306	{
bogdanm	0:9b334a45a8ff	1307	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1308	{
bogdanm	0:9b334a45a8ff	1309	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1310	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1311	}
bogdanm	0:9b334a45a8ff	1312	}
bogdanm	0:9b334a45a8ff	1313
bogdanm	0:9b334a45a8ff	1314	/---------------------------- I2S configuration -------------------------------/
bogdanm	0:9b334a45a8ff	1315	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
bogdanm	0:9b334a45a8ff	1316	only for I2S configuration */
bogdanm	0:9b334a45a8ff	1317	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
bogdanm	0:9b334a45a8ff	1318	{
bogdanm	0:9b334a45a8ff	1319	/* check for Parameters */
bogdanm	0:9b334a45a8ff	1320	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	1321	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	1322	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
bogdanm	0:9b334a45a8ff	1323	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	1324	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	1325	}
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	/---------------------------- SAI configuration -------------------------------/
bogdanm	0:9b334a45a8ff	1328	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
bogdanm	0:9b334a45a8ff	1329	be added only for SAI configuration */
bogdanm	0:9b334a45a8ff	1330	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
bogdanm	0:9b334a45a8ff	1331	{
bogdanm	0:9b334a45a8ff	1332	/* Check the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	1333	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
bogdanm	0:9b334a45a8ff	1334	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
bogdanm	0:9b334a45a8ff	1335
bogdanm	0:9b334a45a8ff	1336	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	1337	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	1338	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	1339	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	1340	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	1341	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
bogdanm	0:9b334a45a8ff	1342	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
bogdanm	0:9b334a45a8ff	1343	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
bogdanm	0:9b334a45a8ff	1344	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
bogdanm	0:9b334a45a8ff	1345	}
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* Enable the PLLI2S */
bogdanm	0:9b334a45a8ff	1348	__HAL_RCC_PLLI2S_ENABLE();
bogdanm	0:9b334a45a8ff	1349	/* Get tick */
bogdanm	0:9b334a45a8ff	1350	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1351	/* Wait till PLLI2S is ready */
bogdanm	0:9b334a45a8ff	1352	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm	0:9b334a45a8ff	1353	{
bogdanm	0:9b334a45a8ff	1354	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1355	{
bogdanm	0:9b334a45a8ff	1356	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1357	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1358	}
bogdanm	0:9b334a45a8ff	1359	}
bogdanm	0:9b334a45a8ff	1360	}
mbed_official	19:112740acecfa	1361	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1362
bogdanm	0:9b334a45a8ff	1363	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
bogdanm	0:9b334a45a8ff	1364	/----------------------- Common configuration SAI/LTDC --------------------/
bogdanm	0:9b334a45a8ff	1365	/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
bogdanm	0:9b334a45a8ff	1366	factor is common parameters for both peripherals */
bogdanm	0:9b334a45a8ff	1367	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
bogdanm	0:9b334a45a8ff	1368	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
bogdanm	0:9b334a45a8ff	1369	{
bogdanm	0:9b334a45a8ff	1370	/* Check the PLLSAI division factors */
bogdanm	0:9b334a45a8ff	1371	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	/* Disable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	1374	__HAL_RCC_PLLSAI_DISABLE();
bogdanm	0:9b334a45a8ff	1375	/* Get tick */
bogdanm	0:9b334a45a8ff	1376	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1377	/* Wait till PLLSAI is disabled */
bogdanm	0:9b334a45a8ff	1378	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
bogdanm	0:9b334a45a8ff	1379	{
bogdanm	0:9b334a45a8ff	1380	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1381	{
bogdanm	0:9b334a45a8ff	1382	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1383	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1384	}
bogdanm	0:9b334a45a8ff	1385	}
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	/---------------------------- SAI configuration -------------------------/
bogdanm	0:9b334a45a8ff	1388	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
bogdanm	0:9b334a45a8ff	1389	be added only for SAI configuration */
bogdanm	0:9b334a45a8ff	1390	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
bogdanm	0:9b334a45a8ff	1391	{
bogdanm	0:9b334a45a8ff	1392	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
bogdanm	0:9b334a45a8ff	1393	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	1396	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
bogdanm	0:9b334a45a8ff	1397	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	1398	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	1399	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
bogdanm	0:9b334a45a8ff	1400	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
bogdanm	0:9b334a45a8ff	1401	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
bogdanm	0:9b334a45a8ff	1402	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
bogdanm	0:9b334a45a8ff	1403	}
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	/---------------------------- LTDC configuration ------------------------/
bogdanm	0:9b334a45a8ff	1406	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
bogdanm	0:9b334a45a8ff	1407	{
bogdanm	0:9b334a45a8ff	1408	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
bogdanm	0:9b334a45a8ff	1409	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	1412	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	1413	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	1414	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	1415	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
bogdanm	0:9b334a45a8ff	1416	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
bogdanm	0:9b334a45a8ff	1417	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
bogdanm	0:9b334a45a8ff	1418	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
bogdanm	0:9b334a45a8ff	1419	}
bogdanm	0:9b334a45a8ff	1420	/* Enable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	1421	__HAL_RCC_PLLSAI_ENABLE();
bogdanm	0:9b334a45a8ff	1422	/* Get tick */
bogdanm	0:9b334a45a8ff	1423	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1424	/* Wait till PLLSAI is ready */
bogdanm	0:9b334a45a8ff	1425	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
bogdanm	0:9b334a45a8ff	1426	{
bogdanm	0:9b334a45a8ff	1427	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1428	{
bogdanm	0:9b334a45a8ff	1429	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1430	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1431	}
bogdanm	0:9b334a45a8ff	1432	}
bogdanm	0:9b334a45a8ff	1433	}
mbed_official	19:112740acecfa	1434	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1435
bogdanm	0:9b334a45a8ff	1436	/---------------------------- RTC configuration ---------------------------/
bogdanm	0:9b334a45a8ff	1437	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	19:112740acecfa	1438	{
mbed_official	19:112740acecfa	1439	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	1440	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	19:112740acecfa	1441
bogdanm	0:9b334a45a8ff	1442	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	1443	PWR->CR \|= PWR_CR_DBP;
mbed_official	19:112740acecfa	1444
bogdanm	0:9b334a45a8ff	1445	/* Get tick */
bogdanm	0:9b334a45a8ff	1446	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	1447
bogdanm	0:9b334a45a8ff	1448	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	1449	{
mbed_official	19:112740acecfa	1450	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1451	{
mbed_official	19:112740acecfa	1452	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1453	}
mbed_official	19:112740acecfa	1454	}
mbed_official	19:112740acecfa	1455
bogdanm	0:9b334a45a8ff	1456	/* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm	0:9b334a45a8ff	1457	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	19:112740acecfa	1458	{
bogdanm	0:9b334a45a8ff	1459	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	1460	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	1461	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	1462	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	1463	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	1464	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	1465	RCC->BDCR = tmpreg1;
mbed_official	19:112740acecfa	1466
bogdanm	0:9b334a45a8ff	1467	/* Wait for LSERDY if LSE was enabled */
bogdanm	0:9b334a45a8ff	1468	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	1469	{
bogdanm	0:9b334a45a8ff	1470	/* Get tick */
bogdanm	0:9b334a45a8ff	1471	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1474	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1475	{
bogdanm	0:9b334a45a8ff	1476	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1477	{
bogdanm	0:9b334a45a8ff	1478	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1479	}
bogdanm	0:9b334a45a8ff	1480	}
bogdanm	0:9b334a45a8ff	1481	}
bogdanm	0:9b334a45a8ff	1482	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	1483	}
bogdanm	0:9b334a45a8ff	1484	}
mbed_official	19:112740acecfa	1485	/--------------------------------------------------------------------------/
mbed_official	19:112740acecfa	1486
bogdanm	0:9b334a45a8ff	1487	/---------------------------- TIM configuration ---------------------------/
bogdanm	0:9b334a45a8ff	1488	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
bogdanm	0:9b334a45a8ff	1489	{
bogdanm	0:9b334a45a8ff	1490	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
bogdanm	0:9b334a45a8ff	1491	}
bogdanm	0:9b334a45a8ff	1492	return HAL_OK;
bogdanm	0:9b334a45a8ff	1493	}
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/**
mbed_official	19:112740acecfa	1496	* @brief Configures the PeriphClkInit according to the internal
bogdanm	0:9b334a45a8ff	1497	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	1498	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1499	* will be configured.
bogdanm	0:9b334a45a8ff	1500	* @retval None
bogdanm	0:9b334a45a8ff	1501	*/
bogdanm	0:9b334a45a8ff	1502	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	1503	{
bogdanm	0:9b334a45a8ff	1504	uint32_t tempreg;
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	1507	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \| RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1510	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
bogdanm	0:9b334a45a8ff	1511	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	1512	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
bogdanm	0:9b334a45a8ff	1513	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1514	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
bogdanm	0:9b334a45a8ff	1515	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
bogdanm	0:9b334a45a8ff	1516	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	1517	/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1518	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
bogdanm	0:9b334a45a8ff	1519	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
bogdanm	0:9b334a45a8ff	1520	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
bogdanm	0:9b334a45a8ff	1521	/* Get the RTC Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1522	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
bogdanm	0:9b334a45a8ff	1523	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
bogdanm	0:9b334a45a8ff	1526	{
bogdanm	0:9b334a45a8ff	1527	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529	else
bogdanm	0:9b334a45a8ff	1530	{
bogdanm	0:9b334a45a8ff	1531	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
bogdanm	0:9b334a45a8ff	1532	}
bogdanm	0:9b334a45a8ff	1533	}
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	0:9b334a45a8ff	1538	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1539	/**
bogdanm	0:9b334a45a8ff	1540	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
bogdanm	0:9b334a45a8ff	1541	* RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	1542	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1543	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
bogdanm	0:9b334a45a8ff	1544	*
bogdanm	0:9b334a45a8ff	1545	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
bogdanm	0:9b334a45a8ff	1546	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
bogdanm	0:9b334a45a8ff	1547	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
bogdanm	0:9b334a45a8ff	1548	*
bogdanm	0:9b334a45a8ff	1549	* @retval HAL status
bogdanm	0:9b334a45a8ff	1550	*/
bogdanm	0:9b334a45a8ff	1551	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	1552	{
bogdanm	0:9b334a45a8ff	1553	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1554	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1557	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	/---------------------------- I2S configuration ---------------------------/
bogdanm	0:9b334a45a8ff	1560	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
bogdanm	0:9b334a45a8ff	1561	{
bogdanm	0:9b334a45a8ff	1562	/* check for Parameters */
bogdanm	0:9b334a45a8ff	1563	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	1564	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
bogdanm	0:9b334a45a8ff	1565	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1566	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
bogdanm	0:9b334a45a8ff	1567	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	1568	/* Disable the PLLI2S */
bogdanm	0:9b334a45a8ff	1569	__HAL_RCC_PLLI2S_DISABLE();
bogdanm	0:9b334a45a8ff	1570	/* Get tick */
bogdanm	0:9b334a45a8ff	1571	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1572	/* Wait till PLLI2S is disabled */
bogdanm	0:9b334a45a8ff	1573	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm	0:9b334a45a8ff	1574	{
bogdanm	0:9b334a45a8ff	1575	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1576	{
bogdanm	0:9b334a45a8ff	1577	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1578	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1579	}
bogdanm	0:9b334a45a8ff	1580	}
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1583	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	1584	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	1585	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	1586	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	1587	#else
bogdanm	0:9b334a45a8ff	1588	/* Configure the PLLI2S division factors */
mbed_official	19:112740acecfa	1589	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
bogdanm	0:9b334a45a8ff	1590	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	1591	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	1592	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	1593
bogdanm	0:9b334a45a8ff	1594	/* Enable the PLLI2S */
bogdanm	0:9b334a45a8ff	1595	__HAL_RCC_PLLI2S_ENABLE();
bogdanm	0:9b334a45a8ff	1596	/* Get tick */
bogdanm	0:9b334a45a8ff	1597	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1598	/* Wait till PLLI2S is ready */
bogdanm	0:9b334a45a8ff	1599	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1602	{
bogdanm	0:9b334a45a8ff	1603	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1604	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1605	}
bogdanm	0:9b334a45a8ff	1606	}
bogdanm	0:9b334a45a8ff	1607	}
bogdanm	0:9b334a45a8ff	1608
bogdanm	0:9b334a45a8ff	1609	/---------------------------- RTC configuration ---------------------------/
bogdanm	0:9b334a45a8ff	1610	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	19:112740acecfa	1611	{
mbed_official	19:112740acecfa	1612	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	1613	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	19:112740acecfa	1614
bogdanm	0:9b334a45a8ff	1615	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	1616	PWR->CR \|= PWR_CR_DBP;
mbed_official	19:112740acecfa	1617
bogdanm	0:9b334a45a8ff	1618	/* Get tick */
bogdanm	0:9b334a45a8ff	1619	tickstart = HAL_GetTick();
mbed_official	19:112740acecfa	1620
bogdanm	0:9b334a45a8ff	1621	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	1622	{
mbed_official	19:112740acecfa	1623	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	19:112740acecfa	1624	{
mbed_official	19:112740acecfa	1625	return HAL_TIMEOUT;
mbed_official	19:112740acecfa	1626	}
mbed_official	19:112740acecfa	1627	}
mbed_official	19:112740acecfa	1628
bogdanm	0:9b334a45a8ff	1629	/* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm	0:9b334a45a8ff	1630	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
bogdanm	0:9b334a45a8ff	1631	{
bogdanm	0:9b334a45a8ff	1632	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	1633	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	1634	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	1635	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	1636	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	1637	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	1638	RCC->BDCR = tmpreg1;
mbed_official	19:112740acecfa	1639
bogdanm	0:9b334a45a8ff	1640	/* Wait for LSERDY if LSE was enabled */
bogdanm	0:9b334a45a8ff	1641	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	1642	{
bogdanm	0:9b334a45a8ff	1643	/* Get tick */
bogdanm	0:9b334a45a8ff	1644	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1645
bogdanm	0:9b334a45a8ff	1646	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1647	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1648	{
bogdanm	0:9b334a45a8ff	1649	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1650	{
bogdanm	0:9b334a45a8ff	1651	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1652	}
bogdanm	0:9b334a45a8ff	1653	}
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	1656	}
bogdanm	0:9b334a45a8ff	1657	}
mbed_official	19:112740acecfa	1658
bogdanm	0:9b334a45a8ff	1659	return HAL_OK;
bogdanm	0:9b334a45a8ff	1660	}
bogdanm	0:9b334a45a8ff	1661
bogdanm	0:9b334a45a8ff	1662	/**
bogdanm	0:9b334a45a8ff	1663	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1664	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	1665	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1666	* will be configured.
bogdanm	0:9b334a45a8ff	1667	* @retval None
bogdanm	0:9b334a45a8ff	1668	*/
bogdanm	0:9b334a45a8ff	1669	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	1670	{
bogdanm	0:9b334a45a8ff	1671	uint32_t tempreg;
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	1674	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_RTC;
bogdanm	0:9b334a45a8ff	1675
mbed_official	19:112740acecfa	1676	/* Get the PLLI2S Clock configuration --------------------------------------*/
bogdanm	0:9b334a45a8ff	1677	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
bogdanm	0:9b334a45a8ff	1678	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	1679	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1680	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
mbed_official	19:112740acecfa	1681	#endif /* STM32F411xE */
mbed_official	19:112740acecfa	1682	/* Get the RTC Clock configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	1683	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
bogdanm	0:9b334a45a8ff	1684	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	1685
bogdanm	0:9b334a45a8ff	1686	}
mbed_official	19:112740acecfa	1687	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	0:9b334a45a8ff	1688
mbed_official	19:112740acecfa	1689	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	1690	/**
bogdanm	0:9b334a45a8ff	1691	* @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm	0:9b334a45a8ff	1692	* RCC_OscInitTypeDef.
bogdanm	0:9b334a45a8ff	1693	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1694	* contains the configuration information for the RCC Oscillators.
bogdanm	0:9b334a45a8ff	1695	* @note The PLL is not disabled when used as system clock.
mbed_official	19:112740acecfa	1696	* @note This function add the PLL/PLLR factor management during PLL configuration this feature
mbed_official	19:112740acecfa	1697	* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices
bogdanm	0:9b334a45a8ff	1698	* @retval HAL status
bogdanm	0:9b334a45a8ff	1699	*/
bogdanm	0:9b334a45a8ff	1700	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	1701	{
bogdanm	0:9b334a45a8ff	1702	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1705	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm	0:9b334a45a8ff	1706	/------------------------------- HSE Configuration ------------------------/
bogdanm	0:9b334a45a8ff	1707	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm	0:9b334a45a8ff	1708	{
bogdanm	0:9b334a45a8ff	1709	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1710	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm	0:9b334a45a8ff	1711	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
mbed_official	19:112740acecfa	1712	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	1713	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
bogdanm	0:9b334a45a8ff	1714	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) \|\|\
bogdanm	0:9b334a45a8ff	1715	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official	19:112740acecfa	1716	#else
mbed_official	19:112740acecfa	1717	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
mbed_official	19:112740acecfa	1718	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official	19:112740acecfa	1719	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	1720	{
bogdanm	0:9b334a45a8ff	1721	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
bogdanm	0:9b334a45a8ff	1722	{
bogdanm	0:9b334a45a8ff	1723	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1724	}
bogdanm	0:9b334a45a8ff	1725	}
bogdanm	0:9b334a45a8ff	1726	else
bogdanm	0:9b334a45a8ff	1727	{
bogdanm	0:9b334a45a8ff	1728	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm	0:9b334a45a8ff	1729	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1732	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	/* Wait till HSE is disabled */
bogdanm	0:9b334a45a8ff	1735	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1736	{
bogdanm	0:9b334a45a8ff	1737	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1738	{
bogdanm	0:9b334a45a8ff	1739	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1740	}
bogdanm	0:9b334a45a8ff	1741	}
bogdanm	0:9b334a45a8ff	1742
bogdanm	0:9b334a45a8ff	1743	/* Set the new HSE configuration ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1744	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm	0:9b334a45a8ff	1745
bogdanm	0:9b334a45a8ff	1746	/* Check the HSE State */
bogdanm	0:9b334a45a8ff	1747	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
bogdanm	0:9b334a45a8ff	1748	{
bogdanm	0:9b334a45a8ff	1749	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1750	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1751
bogdanm	0:9b334a45a8ff	1752	/* Wait till HSE is ready */
bogdanm	0:9b334a45a8ff	1753	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1754	{
bogdanm	0:9b334a45a8ff	1755	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1756	{
bogdanm	0:9b334a45a8ff	1757	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1758	}
bogdanm	0:9b334a45a8ff	1759	}
bogdanm	0:9b334a45a8ff	1760	}
bogdanm	0:9b334a45a8ff	1761	else
bogdanm	0:9b334a45a8ff	1762	{
bogdanm	0:9b334a45a8ff	1763	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1764	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1765
bogdanm	0:9b334a45a8ff	1766	/* Wait till HSE is bypassed or disabled */
bogdanm	0:9b334a45a8ff	1767	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1768	{
bogdanm	0:9b334a45a8ff	1769	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1770	{
bogdanm	0:9b334a45a8ff	1771	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1772	}
bogdanm	0:9b334a45a8ff	1773	}
bogdanm	0:9b334a45a8ff	1774	}
bogdanm	0:9b334a45a8ff	1775	}
bogdanm	0:9b334a45a8ff	1776	}
bogdanm	0:9b334a45a8ff	1777	/----------------------------- HSI Configuration --------------------------/
bogdanm	0:9b334a45a8ff	1778	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm	0:9b334a45a8ff	1779	{
bogdanm	0:9b334a45a8ff	1780	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1781	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm	0:9b334a45a8ff	1782	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm	0:9b334a45a8ff	1783
bogdanm	0:9b334a45a8ff	1784	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
mbed_official	19:112740acecfa	1785	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	1786	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
bogdanm	0:9b334a45a8ff	1787	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) \|\|\
bogdanm	0:9b334a45a8ff	1788	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official	19:112740acecfa	1789	#else
mbed_official	19:112740acecfa	1790	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
mbed_official	19:112740acecfa	1791	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official	19:112740acecfa	1792	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	1793	{
bogdanm	0:9b334a45a8ff	1794	/* When HSI is used as system clock it will not disabled */
bogdanm	0:9b334a45a8ff	1795	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	1796	{
bogdanm	0:9b334a45a8ff	1797	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1798	}
bogdanm	0:9b334a45a8ff	1799	/* Otherwise, just the calibration is allowed */
bogdanm	0:9b334a45a8ff	1800	else
bogdanm	0:9b334a45a8ff	1801	{
bogdanm	0:9b334a45a8ff	1802	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	1803	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	1804	}
bogdanm	0:9b334a45a8ff	1805	}
bogdanm	0:9b334a45a8ff	1806	else
bogdanm	0:9b334a45a8ff	1807	{
bogdanm	0:9b334a45a8ff	1808	/* Check the HSI State */
bogdanm	0:9b334a45a8ff	1809	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
bogdanm	0:9b334a45a8ff	1810	{
bogdanm	0:9b334a45a8ff	1811	/* Enable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	1812	__HAL_RCC_HSI_ENABLE();
bogdanm	0:9b334a45a8ff	1813
bogdanm	0:9b334a45a8ff	1814	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1815	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1816
bogdanm	0:9b334a45a8ff	1817	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	1818	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	1819	{
bogdanm	0:9b334a45a8ff	1820	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1821	{
bogdanm	0:9b334a45a8ff	1822	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1823	}
bogdanm	0:9b334a45a8ff	1824	}
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	1827	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	1828	}
bogdanm	0:9b334a45a8ff	1829	else
bogdanm	0:9b334a45a8ff	1830	{
bogdanm	0:9b334a45a8ff	1831	/* Disable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	1832	__HAL_RCC_HSI_DISABLE();
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1835	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1836
bogdanm	0:9b334a45a8ff	1837	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	1838	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	1839	{
bogdanm	0:9b334a45a8ff	1840	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1841	{
bogdanm	0:9b334a45a8ff	1842	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1843	}
bogdanm	0:9b334a45a8ff	1844	}
bogdanm	0:9b334a45a8ff	1845	}
bogdanm	0:9b334a45a8ff	1846	}
bogdanm	0:9b334a45a8ff	1847	}
bogdanm	0:9b334a45a8ff	1848	/------------------------------ LSI Configuration -------------------------/
bogdanm	0:9b334a45a8ff	1849	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm	0:9b334a45a8ff	1850	{
bogdanm	0:9b334a45a8ff	1851	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1852	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm	0:9b334a45a8ff	1853
bogdanm	0:9b334a45a8ff	1854	/* Check the LSI State */
bogdanm	0:9b334a45a8ff	1855	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
bogdanm	0:9b334a45a8ff	1856	{
bogdanm	0:9b334a45a8ff	1857	/* Enable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	1858	__HAL_RCC_LSI_ENABLE();
bogdanm	0:9b334a45a8ff	1859
bogdanm	0:9b334a45a8ff	1860	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1861	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	1864	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	1865	{
bogdanm	0:9b334a45a8ff	1866	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1867	{
bogdanm	0:9b334a45a8ff	1868	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1869	}
bogdanm	0:9b334a45a8ff	1870	}
bogdanm	0:9b334a45a8ff	1871	}
bogdanm	0:9b334a45a8ff	1872	else
bogdanm	0:9b334a45a8ff	1873	{
bogdanm	0:9b334a45a8ff	1874	/* Disable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	1875	__HAL_RCC_LSI_DISABLE();
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1878	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1879
bogdanm	0:9b334a45a8ff	1880	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	1881	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	1882	{
bogdanm	0:9b334a45a8ff	1883	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1884	{
bogdanm	0:9b334a45a8ff	1885	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1886	}
bogdanm	0:9b334a45a8ff	1887	}
bogdanm	0:9b334a45a8ff	1888	}
bogdanm	0:9b334a45a8ff	1889	}
mbed_official	19:112740acecfa	1890	/------------------------------ LSE Configuration -------------------------/
bogdanm	0:9b334a45a8ff	1891	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm	0:9b334a45a8ff	1892	{
bogdanm	0:9b334a45a8ff	1893	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1894	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm	0:9b334a45a8ff	1895
bogdanm	0:9b334a45a8ff	1896	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	1897	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	1898
bogdanm	0:9b334a45a8ff	1899	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	1900	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	1901
bogdanm	0:9b334a45a8ff	1902	/* Wait for Backup domain Write protection disable */
bogdanm	0:9b334a45a8ff	1903	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1904
bogdanm	0:9b334a45a8ff	1905	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	1906	{
bogdanm	0:9b334a45a8ff	1907	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1908	{
bogdanm	0:9b334a45a8ff	1909	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1910	}
bogdanm	0:9b334a45a8ff	1911	}
bogdanm	0:9b334a45a8ff	1912
bogdanm	0:9b334a45a8ff	1913	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm	0:9b334a45a8ff	1914	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm	0:9b334a45a8ff	1915
bogdanm	0:9b334a45a8ff	1916	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1917	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1918
bogdanm	0:9b334a45a8ff	1919	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1920	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1921	{
bogdanm	0:9b334a45a8ff	1922	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1923	{
bogdanm	0:9b334a45a8ff	1924	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926	}
bogdanm	0:9b334a45a8ff	1927
bogdanm	0:9b334a45a8ff	1928	/* Set the new LSE configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	1929	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm	0:9b334a45a8ff	1930	/* Check the LSE State */
bogdanm	0:9b334a45a8ff	1931	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
bogdanm	0:9b334a45a8ff	1932	{
bogdanm	0:9b334a45a8ff	1933	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1934	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1937	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1938	{
bogdanm	0:9b334a45a8ff	1939	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1940	{
bogdanm	0:9b334a45a8ff	1941	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1942	}
bogdanm	0:9b334a45a8ff	1943	}
bogdanm	0:9b334a45a8ff	1944	}
bogdanm	0:9b334a45a8ff	1945	else
bogdanm	0:9b334a45a8ff	1946	{
bogdanm	0:9b334a45a8ff	1947	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1948	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1949
bogdanm	0:9b334a45a8ff	1950	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1951	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1952	{
bogdanm	0:9b334a45a8ff	1953	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1954	{
bogdanm	0:9b334a45a8ff	1955	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1956	}
bogdanm	0:9b334a45a8ff	1957	}
bogdanm	0:9b334a45a8ff	1958	}
bogdanm	0:9b334a45a8ff	1959	}
bogdanm	0:9b334a45a8ff	1960	/-------------------------------- PLL Configuration -----------------------/
bogdanm	0:9b334a45a8ff	1961	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1962	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm	0:9b334a45a8ff	1963	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm	0:9b334a45a8ff	1964	{
bogdanm	0:9b334a45a8ff	1965	/* Check if the PLL is used as system clock or not */
bogdanm	0:9b334a45a8ff	1966	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
bogdanm	0:9b334a45a8ff	1967	{
bogdanm	0:9b334a45a8ff	1968	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm	0:9b334a45a8ff	1969	{
bogdanm	0:9b334a45a8ff	1970	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1971	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm	0:9b334a45a8ff	1972	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
bogdanm	0:9b334a45a8ff	1973	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
bogdanm	0:9b334a45a8ff	1974	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
bogdanm	0:9b334a45a8ff	1975	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
bogdanm	0:9b334a45a8ff	1976	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
bogdanm	0:9b334a45a8ff	1977
bogdanm	0:9b334a45a8ff	1978	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	1979	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1982	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	1985	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	1986	{
bogdanm	0:9b334a45a8ff	1987	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1988	{
bogdanm	0:9b334a45a8ff	1989	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1990	}
bogdanm	0:9b334a45a8ff	1991	}
bogdanm	0:9b334a45a8ff	1992
bogdanm	0:9b334a45a8ff	1993	/* Configure the main PLL clock source, multiplication and division factors. */
bogdanm	0:9b334a45a8ff	1994	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm	0:9b334a45a8ff	1995	RCC_OscInitStruct->PLL.PLLM,
bogdanm	0:9b334a45a8ff	1996	RCC_OscInitStruct->PLL.PLLN,
bogdanm	0:9b334a45a8ff	1997	RCC_OscInitStruct->PLL.PLLP,
bogdanm	0:9b334a45a8ff	1998	RCC_OscInitStruct->PLL.PLLQ,
bogdanm	0:9b334a45a8ff	1999	RCC_OscInitStruct->PLL.PLLR);
bogdanm	0:9b334a45a8ff	2000
bogdanm	0:9b334a45a8ff	2001	/* Enable the main PLL. */
bogdanm	0:9b334a45a8ff	2002	__HAL_RCC_PLL_ENABLE();
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	2005	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2006
bogdanm	0:9b334a45a8ff	2007	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	2008	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	2009	{
bogdanm	0:9b334a45a8ff	2010	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	2011	{
bogdanm	0:9b334a45a8ff	2012	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2013	}
bogdanm	0:9b334a45a8ff	2014	}
bogdanm	0:9b334a45a8ff	2015	}
bogdanm	0:9b334a45a8ff	2016	else
bogdanm	0:9b334a45a8ff	2017	{
bogdanm	0:9b334a45a8ff	2018	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	2019	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	2020
bogdanm	0:9b334a45a8ff	2021	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	2022	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	2025	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	2026	{
bogdanm	0:9b334a45a8ff	2027	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	2028	{
bogdanm	0:9b334a45a8ff	2029	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2030	}
bogdanm	0:9b334a45a8ff	2031	}
bogdanm	0:9b334a45a8ff	2032	}
bogdanm	0:9b334a45a8ff	2033	}
bogdanm	0:9b334a45a8ff	2034	else
bogdanm	0:9b334a45a8ff	2035	{
bogdanm	0:9b334a45a8ff	2036	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	2037	}
bogdanm	0:9b334a45a8ff	2038	}
bogdanm	0:9b334a45a8ff	2039	return HAL_OK;
bogdanm	0:9b334a45a8ff	2040	}
bogdanm	0:9b334a45a8ff	2041
bogdanm	0:9b334a45a8ff	2042	/**
bogdanm	0:9b334a45a8ff	2043	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	2044	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	2045	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
bogdanm	0:9b334a45a8ff	2046	*
mbed_official	19:112740acecfa	2047	* @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
bogdanm	0:9b334a45a8ff	2048	* @note This function add the PLL/PLLR factor management
bogdanm	0:9b334a45a8ff	2049	* @retval None
bogdanm	0:9b334a45a8ff	2050	*/
bogdanm	0:9b334a45a8ff	2051	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	2052	{
bogdanm	0:9b334a45a8ff	2053	/* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm	0:9b334a45a8ff	2054	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
bogdanm	0:9b334a45a8ff	2055
bogdanm	0:9b334a45a8ff	2056	/* Get the HSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	2057	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm	0:9b334a45a8ff	2058	{
bogdanm	0:9b334a45a8ff	2059	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm	0:9b334a45a8ff	2060	}
bogdanm	0:9b334a45a8ff	2061	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm	0:9b334a45a8ff	2062	{
bogdanm	0:9b334a45a8ff	2063	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm	0:9b334a45a8ff	2064	}
bogdanm	0:9b334a45a8ff	2065	else
bogdanm	0:9b334a45a8ff	2066	{
bogdanm	0:9b334a45a8ff	2067	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm	0:9b334a45a8ff	2068	}
bogdanm	0:9b334a45a8ff	2069
bogdanm	0:9b334a45a8ff	2070	/* Get the HSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	2071	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	2072	{
bogdanm	0:9b334a45a8ff	2073	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm	0:9b334a45a8ff	2074	}
bogdanm	0:9b334a45a8ff	2075	else
bogdanm	0:9b334a45a8ff	2076	{
bogdanm	0:9b334a45a8ff	2077	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm	0:9b334a45a8ff	2078	}
bogdanm	0:9b334a45a8ff	2079
bogdanm	0:9b334a45a8ff	2080	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm	0:9b334a45a8ff	2081
bogdanm	0:9b334a45a8ff	2082	/* Get the LSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	2083	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm	0:9b334a45a8ff	2084	{
bogdanm	0:9b334a45a8ff	2085	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm	0:9b334a45a8ff	2086	}
bogdanm	0:9b334a45a8ff	2087	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm	0:9b334a45a8ff	2088	{
bogdanm	0:9b334a45a8ff	2089	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm	0:9b334a45a8ff	2090	}
bogdanm	0:9b334a45a8ff	2091	else
bogdanm	0:9b334a45a8ff	2092	{
bogdanm	0:9b334a45a8ff	2093	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm	0:9b334a45a8ff	2094	}
bogdanm	0:9b334a45a8ff	2095
bogdanm	0:9b334a45a8ff	2096	/* Get the LSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	2097	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	2098	{
bogdanm	0:9b334a45a8ff	2099	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm	0:9b334a45a8ff	2100	}
bogdanm	0:9b334a45a8ff	2101	else
bogdanm	0:9b334a45a8ff	2102	{
bogdanm	0:9b334a45a8ff	2103	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm	0:9b334a45a8ff	2104	}
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	/* Get the PLL configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	2107	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	2108	{
bogdanm	0:9b334a45a8ff	2109	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm	0:9b334a45a8ff	2110	}
bogdanm	0:9b334a45a8ff	2111	else
bogdanm	0:9b334a45a8ff	2112	{
bogdanm	0:9b334a45a8ff	2113	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm	0:9b334a45a8ff	2114	}
bogdanm	0:9b334a45a8ff	2115	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
bogdanm	0:9b334a45a8ff	2116	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
bogdanm	0:9b334a45a8ff	2117	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
bogdanm	0:9b334a45a8ff	2118	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
bogdanm	0:9b334a45a8ff	2119	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
bogdanm	0:9b334a45a8ff	2120	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
bogdanm	0:9b334a45a8ff	2121	}
mbed_official	19:112740acecfa	2122	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	2123
mbed_official	19:112740acecfa	2124	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
mbed_official	19:112740acecfa	2125	/**
mbed_official	19:112740acecfa	2126	* @brief Select LSE mode
mbed_official	19:112740acecfa	2127	*
mbed_official	19:112740acecfa	2128	* @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
mbed_official	19:112740acecfa	2129	*
mbed_official	19:112740acecfa	2130	* @param Mode: specifies the LSE mode.
mbed_official	19:112740acecfa	2131	* This parameter can be one of the following values:
mbed_official	19:112740acecfa	2132	* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
mbed_official	19:112740acecfa	2133	* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
mbed_official	19:112740acecfa	2134	* @retval None
mbed_official	19:112740acecfa	2135	*/
mbed_official	19:112740acecfa	2136	void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
mbed_official	19:112740acecfa	2137	{
mbed_official	19:112740acecfa	2138	/* Check the parameters */
mbed_official	19:112740acecfa	2139	assert_param(IS_RCC_LSE_MODE(Mode));
mbed_official	19:112740acecfa	2140	if(Mode == RCC_LSE_HIGHDRIVE_MODE)
mbed_official	19:112740acecfa	2141	{
mbed_official	19:112740acecfa	2142	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
mbed_official	19:112740acecfa	2143	}
mbed_official	19:112740acecfa	2144	else
mbed_official	19:112740acecfa	2145	{
mbed_official	19:112740acecfa	2146	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
mbed_official	19:112740acecfa	2147	}
mbed_official	19:112740acecfa	2148	}
mbed_official	19:112740acecfa	2149
mbed_official	19:112740acecfa	2150	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
mbed_official	19:112740acecfa	2151
mbed_official	19:112740acecfa	2152	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	2153	/**
bogdanm	0:9b334a45a8ff	2154	* @brief Returns the SYSCLK frequency
bogdanm	0:9b334a45a8ff	2155	*
mbed_official	19:112740acecfa	2156	* @note This function implementation is valide only for STM32F446xx devices.
bogdanm	0:9b334a45a8ff	2157	* @note This function add the PLL/PLLR System clock source
bogdanm	0:9b334a45a8ff	2158	*
bogdanm	0:9b334a45a8ff	2159	* @note The system frequency computed by this function is not the real
bogdanm	0:9b334a45a8ff	2160	* frequency in the chip. It is calculated based on the predefined
bogdanm	0:9b334a45a8ff	2161	* constant and the selected clock source:
bogdanm	0:9b334a45a8ff	2162	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm	0:9b334a45a8ff	2163	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official	19:112740acecfa	2164	* @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
bogdanm	0:9b334a45a8ff	2165	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm	0:9b334a45a8ff	2166	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	2167	* 16 MHz) but the real value may vary depending on the variations
bogdanm	0:9b334a45a8ff	2168	* in voltage and temperature.
bogdanm	0:9b334a45a8ff	2169	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	2170	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm	0:9b334a45a8ff	2171	* frequency of the crystal used. Otherwise, this function may
bogdanm	0:9b334a45a8ff	2172	* have wrong result.
bogdanm	0:9b334a45a8ff	2173	*
bogdanm	0:9b334a45a8ff	2174	* @note The result of this function could be not correct when using fractional
bogdanm	0:9b334a45a8ff	2175	* value for HSE crystal.
bogdanm	0:9b334a45a8ff	2176	*
bogdanm	0:9b334a45a8ff	2177	* @note This function can be used by the user application to compute the
bogdanm	0:9b334a45a8ff	2178	* baudrate for the communication peripherals or configure other parameters.
bogdanm	0:9b334a45a8ff	2179	*
bogdanm	0:9b334a45a8ff	2180	* @note Each time SYSCLK changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	2181	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	2182	*
bogdanm	0:9b334a45a8ff	2183	*
bogdanm	0:9b334a45a8ff	2184	* @retval SYSCLK frequency
bogdanm	0:9b334a45a8ff	2185	*/
bogdanm	0:9b334a45a8ff	2186	uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm	0:9b334a45a8ff	2187	{
bogdanm	0:9b334a45a8ff	2188	uint32_t pllm = 0;
bogdanm	0:9b334a45a8ff	2189	uint32_t pllvco = 0;
bogdanm	0:9b334a45a8ff	2190	uint32_t pllp = 0;
bogdanm	0:9b334a45a8ff	2191	uint32_t pllr = 0;
bogdanm	0:9b334a45a8ff	2192	uint32_t sysclockfreq = 0;
bogdanm	0:9b334a45a8ff	2193
bogdanm	0:9b334a45a8ff	2194	/* Get SYSCLK source -------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2195	switch (RCC->CFGR & RCC_CFGR_SWS)
bogdanm	0:9b334a45a8ff	2196	{
bogdanm	0:9b334a45a8ff	2197	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
bogdanm	0:9b334a45a8ff	2198	{
bogdanm	0:9b334a45a8ff	2199	sysclockfreq = HSI_VALUE;
bogdanm	0:9b334a45a8ff	2200	break;
bogdanm	0:9b334a45a8ff	2201	}
bogdanm	0:9b334a45a8ff	2202	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
bogdanm	0:9b334a45a8ff	2203	{
bogdanm	0:9b334a45a8ff	2204	sysclockfreq = HSE_VALUE;
bogdanm	0:9b334a45a8ff	2205	break;
bogdanm	0:9b334a45a8ff	2206	}
bogdanm	0:9b334a45a8ff	2207	case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
bogdanm	0:9b334a45a8ff	2208	{
bogdanm	0:9b334a45a8ff	2209	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
bogdanm	0:9b334a45a8ff	2210	SYSCLK = PLL_VCO / PLLP */
bogdanm	0:9b334a45a8ff	2211	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm	0:9b334a45a8ff	2212	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	2213	{
bogdanm	0:9b334a45a8ff	2214	/* HSE used as PLL clock source */
bogdanm	0:9b334a45a8ff	2215	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	2216	}
bogdanm	0:9b334a45a8ff	2217	else
bogdanm	0:9b334a45a8ff	2218	{
bogdanm	0:9b334a45a8ff	2219	/* HSI used as PLL clock source */
bogdanm	0:9b334a45a8ff	2220	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	2221	}
bogdanm	0:9b334a45a8ff	2222	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
bogdanm	0:9b334a45a8ff	2223
bogdanm	0:9b334a45a8ff	2224	sysclockfreq = pllvco/pllp;
bogdanm	0:9b334a45a8ff	2225	break;
bogdanm	0:9b334a45a8ff	2226	}
bogdanm	0:9b334a45a8ff	2227	case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
bogdanm	0:9b334a45a8ff	2228	{
bogdanm	0:9b334a45a8ff	2229	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
bogdanm	0:9b334a45a8ff	2230	SYSCLK = PLL_VCO / PLLR */
bogdanm	0:9b334a45a8ff	2231	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm	0:9b334a45a8ff	2232	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	2233	{
bogdanm	0:9b334a45a8ff	2234	/* HSE used as PLL clock source */
bogdanm	0:9b334a45a8ff	2235	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	2236	}
bogdanm	0:9b334a45a8ff	2237	else
bogdanm	0:9b334a45a8ff	2238	{
bogdanm	0:9b334a45a8ff	2239	/* HSI used as PLL clock source */
mbed_official	19:112740acecfa	2240	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	2241	}
bogdanm	0:9b334a45a8ff	2242	pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	sysclockfreq = pllvco/pllr;
bogdanm	0:9b334a45a8ff	2245	break;
bogdanm	0:9b334a45a8ff	2246	}
bogdanm	0:9b334a45a8ff	2247	default:
bogdanm	0:9b334a45a8ff	2248	{
bogdanm	0:9b334a45a8ff	2249	sysclockfreq = HSI_VALUE;
bogdanm	0:9b334a45a8ff	2250	break;
bogdanm	0:9b334a45a8ff	2251	}
bogdanm	0:9b334a45a8ff	2252	}
bogdanm	0:9b334a45a8ff	2253	return sysclockfreq;
bogdanm	0:9b334a45a8ff	2254	}
bogdanm	0:9b334a45a8ff	2255	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	2256
bogdanm	0:9b334a45a8ff	2257	/**
bogdanm	0:9b334a45a8ff	2258	* @}
bogdanm	0:9b334a45a8ff	2259	*/
bogdanm	0:9b334a45a8ff	2260
bogdanm	0:9b334a45a8ff	2261	/**
bogdanm	0:9b334a45a8ff	2262	* @}
bogdanm	0:9b334a45a8ff	2263	*/
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265	#endif /* HAL_RCC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2266	/**
bogdanm	0:9b334a45a8ff	2267	* @}
bogdanm	0:9b334a45a8ff	2268	*/
bogdanm	0:9b334a45a8ff	2269
bogdanm	0:9b334a45a8ff	2270	/**
bogdanm	0:9b334a45a8ff	2271	* @}
bogdanm	0:9b334a45a8ff	2272	*/
bogdanm	0:9b334a45a8ff	2273
bogdanm	0:9b334a45a8ff	2274	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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