mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 19:112740acecfa

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_rcc_ex.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.3.2
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Extension RCC HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities RCC extension peripheral:
bogdanm	0:9b334a45a8ff	10	* + Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	11	*
bogdanm	0:9b334a45a8ff	12	******************************************************************************
bogdanm	0:9b334a45a8ff	13	* @attention
bogdanm	0:9b334a45a8ff	14	*
bogdanm	0:9b334a45a8ff	15	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	16	*
bogdanm	0:9b334a45a8ff	17	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	18	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	19	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	20	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	22	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	23	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	25	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	26	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	27	*
bogdanm	0:9b334a45a8ff	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	38	*
bogdanm	0:9b334a45a8ff	39	******************************************************************************
bogdanm	0:9b334a45a8ff	40	*/
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	43	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	44
bogdanm	0:9b334a45a8ff	45	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	46	* @{
bogdanm	0:9b334a45a8ff	47	*/
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @defgroup RCCEx RCCEx
bogdanm	0:9b334a45a8ff	50	* @brief RCCEx HAL module driver
bogdanm	0:9b334a45a8ff	51	* @{
bogdanm	0:9b334a45a8ff	52	*/
bogdanm	0:9b334a45a8ff	53
bogdanm	0:9b334a45a8ff	54	#ifdef HAL_RCC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	57	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @addtogroup RCCEx_Private_Constants
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	/**
bogdanm	0:9b334a45a8ff	62	* @}
bogdanm	0:9b334a45a8ff	63	*/
bogdanm	0:9b334a45a8ff	64	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	65	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	66	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	67	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	68	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm	0:9b334a45a8ff	69	* @{
bogdanm	0:9b334a45a8ff	70	*/
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	73	* @brief Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	74	*
bogdanm	0:9b334a45a8ff	75	@verbatim
bogdanm	0:9b334a45a8ff	76	===============================================================================
bogdanm	0:9b334a45a8ff	77	##### Extended Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	78	===============================================================================
bogdanm	0:9b334a45a8ff	79	[..]
bogdanm	0:9b334a45a8ff	80	This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm	0:9b334a45a8ff	81	frequencies.
bogdanm	0:9b334a45a8ff	82	[..]
bogdanm	0:9b334a45a8ff	83	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm	0:9b334a45a8ff	84	select the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	85	order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	86	the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	87
bogdanm	0:9b334a45a8ff	88	@endverbatim
bogdanm	0:9b334a45a8ff	89	* @{
bogdanm	0:9b334a45a8ff	90	*/
bogdanm	0:9b334a45a8ff	91	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	92	/**
bogdanm	0:9b334a45a8ff	93	* @brief Initializes the RCC extended peripherals clocks according to the specified
bogdanm	0:9b334a45a8ff	94	* parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	95	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	96	* contains the configuration information for the Extended Peripherals
bogdanm	0:9b334a45a8ff	97	* clocks(I2S, SAI, LTDC RTC and TIM).
bogdanm	0:9b334a45a8ff	98	*
bogdanm	0:9b334a45a8ff	99	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm	0:9b334a45a8ff	100	* the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	101	* order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	102	* the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	103	*
bogdanm	0:9b334a45a8ff	104	* @retval HAL status
bogdanm	0:9b334a45a8ff	105	*/
bogdanm	0:9b334a45a8ff	106	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	107	{
bogdanm	0:9b334a45a8ff	108	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	109	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	110	uint32_t plli2sp = 0;
bogdanm	0:9b334a45a8ff	111	uint32_t plli2sq = 0;
bogdanm	0:9b334a45a8ff	112	uint32_t plli2sr = 0;
bogdanm	0:9b334a45a8ff	113	uint32_t pllsaip = 0;
bogdanm	0:9b334a45a8ff	114	uint32_t pllsaiq = 0;
bogdanm	0:9b334a45a8ff	115	uint32_t plli2sused = 0;
bogdanm	0:9b334a45a8ff	116	uint32_t pllsaiused = 0;
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	/* Check the peripheral clock selection parameters */
bogdanm	0:9b334a45a8ff	119	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	/----------------------------------- I2S APB1 configuration ----------------------------------/
bogdanm	0:9b334a45a8ff	122	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
bogdanm	0:9b334a45a8ff	123	{
bogdanm	0:9b334a45a8ff	124	/* Check the parameters */
bogdanm	0:9b334a45a8ff	125	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	/* Configure I2S Clock source */
bogdanm	0:9b334a45a8ff	128	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
bogdanm	0:9b334a45a8ff	129	/* Enable the PLLI2S when it's used as clock source for I2S */
bogdanm	0:9b334a45a8ff	130	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	131	{
bogdanm	0:9b334a45a8ff	132	plli2sused = 1;
bogdanm	0:9b334a45a8ff	133	}
bogdanm	0:9b334a45a8ff	134	}
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	/----------------------------------- I2S APB2 configuration -----------------------------------/
bogdanm	0:9b334a45a8ff	137	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
bogdanm	0:9b334a45a8ff	138	{
bogdanm	0:9b334a45a8ff	139	/* Check the parameters */
bogdanm	0:9b334a45a8ff	140	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/* Configure I2S Clock source */
bogdanm	0:9b334a45a8ff	143	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
bogdanm	0:9b334a45a8ff	144	/* Enable the PLLI2S when it's used as clock source for I2S */
bogdanm	0:9b334a45a8ff	145	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	146	{
bogdanm	0:9b334a45a8ff	147	plli2sused = 1;
bogdanm	0:9b334a45a8ff	148	}
bogdanm	0:9b334a45a8ff	149	}
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/------------------------------------ SAI1 configuration --------------------------------------/
bogdanm	0:9b334a45a8ff	152	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
bogdanm	0:9b334a45a8ff	153	{
bogdanm	0:9b334a45a8ff	154	/* Check the parameters */
bogdanm	0:9b334a45a8ff	155	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157	/* Configure SAI1 Clock source */
bogdanm	0:9b334a45a8ff	158	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
bogdanm	0:9b334a45a8ff	159	/* Enable the PLLI2S when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	160	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	161	{
bogdanm	0:9b334a45a8ff	162	plli2sused = 1;
bogdanm	0:9b334a45a8ff	163	}
bogdanm	0:9b334a45a8ff	164	/* Enable the PLLSAI when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	165	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
bogdanm	0:9b334a45a8ff	166	{
bogdanm	0:9b334a45a8ff	167	pllsaiused = 1;
bogdanm	0:9b334a45a8ff	168	}
bogdanm	0:9b334a45a8ff	169	}
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	/------------------------------------ SAI2 configuration --------------------------------------/
bogdanm	0:9b334a45a8ff	172	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
bogdanm	0:9b334a45a8ff	173	{
bogdanm	0:9b334a45a8ff	174	/* Check the parameters */
bogdanm	0:9b334a45a8ff	175	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/* Configure SAI2 Clock source */
bogdanm	0:9b334a45a8ff	178	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	/* Enable the PLLI2S when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	181	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
bogdanm	0:9b334a45a8ff	182	{
bogdanm	0:9b334a45a8ff	183	plli2sused = 1;
bogdanm	0:9b334a45a8ff	184	}
bogdanm	0:9b334a45a8ff	185	/* Enable the PLLSAI when it's used as clock source for SAI */
bogdanm	0:9b334a45a8ff	186	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
bogdanm	0:9b334a45a8ff	187	{
bogdanm	0:9b334a45a8ff	188	pllsaiused = 1;
bogdanm	0:9b334a45a8ff	189	}
bogdanm	0:9b334a45a8ff	190	}
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	/------------------------------------ RTC configuration --------------------------------------/
bogdanm	0:9b334a45a8ff	193	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	194	{
bogdanm	0:9b334a45a8ff	195	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	196	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	199	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/* Get tick */
bogdanm	0:9b334a45a8ff	202	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	205	{
bogdanm	0:9b334a45a8ff	206	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	207	{
bogdanm	0:9b334a45a8ff	208	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	209	}
bogdanm	0:9b334a45a8ff	210	}
bogdanm	0:9b334a45a8ff	211	/* Reset the Backup domain only if the RTC Clock source selction is modified */
bogdanm	0:9b334a45a8ff	212	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
bogdanm	0:9b334a45a8ff	213	{
bogdanm	0:9b334a45a8ff	214	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	215	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	216	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	217	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	218	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	219	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	220	RCC->BDCR = tmpreg1;
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	/* Wait for LSERDY if LSE was enabled */
bogdanm	0:9b334a45a8ff	223	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	224	{
bogdanm	0:9b334a45a8ff	225	/* Get tick */
bogdanm	0:9b334a45a8ff	226	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	229	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	230	{
bogdanm	0:9b334a45a8ff	231	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	232	{
bogdanm	0:9b334a45a8ff	233	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	234	}
bogdanm	0:9b334a45a8ff	235	}
bogdanm	0:9b334a45a8ff	236	}
bogdanm	0:9b334a45a8ff	237	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	238	}
bogdanm	0:9b334a45a8ff	239	}
bogdanm	0:9b334a45a8ff	240
bogdanm	0:9b334a45a8ff	241	/------------------------------------ TIM configuration --------------------------------------/
bogdanm	0:9b334a45a8ff	242	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
bogdanm	0:9b334a45a8ff	243	{
bogdanm	0:9b334a45a8ff	244	/* Configure Timer Prescaler */
bogdanm	0:9b334a45a8ff	245	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
bogdanm	0:9b334a45a8ff	246	}
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/------------------------------------- FMPI2C1 Configuration ----------------------------------/
bogdanm	0:9b334a45a8ff	249	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	/* Check the parameters */
bogdanm	0:9b334a45a8ff	252	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/* Configure the FMPI2C1 clock source */
bogdanm	0:9b334a45a8ff	255	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
bogdanm	0:9b334a45a8ff	256	}
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/--------------------------------------- CEC Configuration -----------------------------------/
bogdanm	0:9b334a45a8ff	259	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
bogdanm	0:9b334a45a8ff	260	{
bogdanm	0:9b334a45a8ff	261	/* Check the parameters */
bogdanm	0:9b334a45a8ff	262	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/* Configure the CEC clock source */
bogdanm	0:9b334a45a8ff	265	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
bogdanm	0:9b334a45a8ff	266	}
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/-------------------------------------- CK48 Configuration -----------------------------------/
bogdanm	0:9b334a45a8ff	269	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
bogdanm	0:9b334a45a8ff	270	{
bogdanm	0:9b334a45a8ff	271	/* Check the parameters */
bogdanm	0:9b334a45a8ff	272	assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	/* Configure the SDIO clock source */
bogdanm	0:9b334a45a8ff	275	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	/* Enable the PLLSAI when it's used as clock source for CK48 */
bogdanm	0:9b334a45a8ff	278	if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
bogdanm	0:9b334a45a8ff	279	{
bogdanm	0:9b334a45a8ff	280	pllsaiused = 1;
bogdanm	0:9b334a45a8ff	281	}
bogdanm	0:9b334a45a8ff	282	}
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/------------------------------------- SDIO Configuration ------------------------------------/
bogdanm	0:9b334a45a8ff	285	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
bogdanm	0:9b334a45a8ff	286	{
bogdanm	0:9b334a45a8ff	287	/* Check the parameters */
bogdanm	0:9b334a45a8ff	288	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
bogdanm	0:9b334a45a8ff	289
bogdanm	0:9b334a45a8ff	290	/* Configure the SDIO clock source */
bogdanm	0:9b334a45a8ff	291	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
bogdanm	0:9b334a45a8ff	292	}
bogdanm	0:9b334a45a8ff	293
bogdanm	0:9b334a45a8ff	294	/------------------------------------- SPDIFRX Configuration --------------/
bogdanm	0:9b334a45a8ff	295	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
bogdanm	0:9b334a45a8ff	296	{
bogdanm	0:9b334a45a8ff	297	/* Check the parameters */
bogdanm	0:9b334a45a8ff	298	assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* Configure the SPDIFRX clock source */
bogdanm	0:9b334a45a8ff	301	__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
bogdanm	0:9b334a45a8ff	302	/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
bogdanm	0:9b334a45a8ff	303	if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	plli2sused = 1;
bogdanm	0:9b334a45a8ff	306	}
bogdanm	0:9b334a45a8ff	307	}
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	/-------------------------------------- PLLI2S Configuration --------------/
bogdanm	0:9b334a45a8ff	310	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
bogdanm	0:9b334a45a8ff	311	I2S on APB2 or SPDIFRX */
bogdanm	0:9b334a45a8ff	312	if((plli2sused == 1) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
bogdanm	0:9b334a45a8ff	313	{
bogdanm	0:9b334a45a8ff	314	/* Disable the PLLI2S */
bogdanm	0:9b334a45a8ff	315	__HAL_RCC_PLLI2S_DISABLE();
bogdanm	0:9b334a45a8ff	316	/* Get tick */
bogdanm	0:9b334a45a8ff	317	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	318	/* Wait till PLLI2S is disabled */
bogdanm	0:9b334a45a8ff	319	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm	0:9b334a45a8ff	320	{
bogdanm	0:9b334a45a8ff	321	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	322	{
bogdanm	0:9b334a45a8ff	323	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	324	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	325	}
bogdanm	0:9b334a45a8ff	326	}
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	/* check for common PLLI2S Parameters */
bogdanm	0:9b334a45a8ff	329	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
bogdanm	0:9b334a45a8ff	330	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/----------------- In Case of PLLI2S is selected as source clock for I2S -------------------/
bogdanm	0:9b334a45a8ff	333	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
bogdanm	0:9b334a45a8ff	334	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
bogdanm	0:9b334a45a8ff	335	{
bogdanm	0:9b334a45a8ff	336	/* check for Parameters */
bogdanm	0:9b334a45a8ff	337	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
bogdanm	0:9b334a45a8ff	340	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	341	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
bogdanm	0:9b334a45a8ff	342	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	343	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	344	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	345	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	346	}
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/----------------- In Case of PLLI2S is selected as source clock for SAI -------------------/
bogdanm	0:9b334a45a8ff	349	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
bogdanm	0:9b334a45a8ff	350	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	/* Check for PLLI2S Parameters */
bogdanm	0:9b334a45a8ff	353	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
bogdanm	0:9b334a45a8ff	354	/* Check for PLLI2S/DIVQ parameters */
bogdanm	0:9b334a45a8ff	355	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
bogdanm	0:9b334a45a8ff	358	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	359	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	360	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	361	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm	0:9b334a45a8ff	362	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	363	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
bogdanm	0:9b334a45a8ff	364	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
bogdanm	0:9b334a45a8ff	367	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
bogdanm	0:9b334a45a8ff	368	}
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	/----------------- In Case of PLLI2S is selected as source clock for SPDIFRX -------------------/
bogdanm	0:9b334a45a8ff	371	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	/* check for Parameters */
bogdanm	0:9b334a45a8ff	374	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
bogdanm	0:9b334a45a8ff	375	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	376	plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	377	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	378	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	379	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	380	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
bogdanm	0:9b334a45a8ff	381	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
bogdanm	0:9b334a45a8ff	382	}
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	/----------------- In Case of PLLI2S is just selected -----------------/
bogdanm	0:9b334a45a8ff	385	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
bogdanm	0:9b334a45a8ff	386	{
bogdanm	0:9b334a45a8ff	387	/* Check for Parameters */
bogdanm	0:9b334a45a8ff	388	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
bogdanm	0:9b334a45a8ff	389	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	390	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	393	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	394	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	395	}
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/* Enable the PLLI2S */
bogdanm	0:9b334a45a8ff	398	__HAL_RCC_PLLI2S_ENABLE();
bogdanm	0:9b334a45a8ff	399	/* Get tick */
bogdanm	0:9b334a45a8ff	400	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	401	/* Wait till PLLI2S is ready */
bogdanm	0:9b334a45a8ff	402	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm	0:9b334a45a8ff	403	{
bogdanm	0:9b334a45a8ff	404	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	405	{
bogdanm	0:9b334a45a8ff	406	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	407	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	408	}
bogdanm	0:9b334a45a8ff	409	}
bogdanm	0:9b334a45a8ff	410	}
bogdanm	0:9b334a45a8ff	411	/-------------------------------------- PLLSAI Configuration ---------------------------------/
bogdanm	0:9b334a45a8ff	412	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
bogdanm	0:9b334a45a8ff	413	if(pllsaiused == 1)
bogdanm	0:9b334a45a8ff	414	{
bogdanm	0:9b334a45a8ff	415	/* Disable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	416	__HAL_RCC_PLLSAI_DISABLE();
bogdanm	0:9b334a45a8ff	417	/* Get tick */
bogdanm	0:9b334a45a8ff	418	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	419	/* Wait till PLLSAI is disabled */
bogdanm	0:9b334a45a8ff	420	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
bogdanm	0:9b334a45a8ff	421	{
bogdanm	0:9b334a45a8ff	422	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	423	{
bogdanm	0:9b334a45a8ff	424	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	425	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	426	}
bogdanm	0:9b334a45a8ff	427	}
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/* Check the PLLSAI division factors */
bogdanm	0:9b334a45a8ff	430	assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
bogdanm	0:9b334a45a8ff	431	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/----------------- In Case of PLLSAI is selected as source clock for SAI -------------------/
bogdanm	0:9b334a45a8ff	434	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|
bogdanm	0:9b334a45a8ff	435	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
bogdanm	0:9b334a45a8ff	436	{
bogdanm	0:9b334a45a8ff	437	/* check for PLLSAIQ Parameter */
bogdanm	0:9b334a45a8ff	438	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
bogdanm	0:9b334a45a8ff	439	/* check for PLLSAI/DIVQ Parameter */
bogdanm	0:9b334a45a8ff	440	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
bogdanm	0:9b334a45a8ff	443	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	444	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	445	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	446	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
bogdanm	0:9b334a45a8ff	447	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0);
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
bogdanm	0:9b334a45a8ff	450	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
bogdanm	0:9b334a45a8ff	451	}
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453	/----------------- In Case of PLLSAI is selected as source clock for CK48 -------------------/
bogdanm	0:9b334a45a8ff	454	/* In Case of PLLI2S is selected as source clock for CK48 */
bogdanm	0:9b334a45a8ff	455	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
bogdanm	0:9b334a45a8ff	456	{
bogdanm	0:9b334a45a8ff	457	/* check for Parameters */
bogdanm	0:9b334a45a8ff	458	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
bogdanm	0:9b334a45a8ff	459	/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	460	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	461	/* Configure the PLLSAI division factors */
bogdanm	0:9b334a45a8ff	462	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLSAIM) */
bogdanm	0:9b334a45a8ff	463	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
bogdanm	0:9b334a45a8ff	464	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0);
bogdanm	0:9b334a45a8ff	465	}
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Enable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	468	__HAL_RCC_PLLSAI_ENABLE();
bogdanm	0:9b334a45a8ff	469	/* Get tick */
bogdanm	0:9b334a45a8ff	470	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	471	/* Wait till PLLSAI is ready */
bogdanm	0:9b334a45a8ff	472	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
bogdanm	0:9b334a45a8ff	473	{
bogdanm	0:9b334a45a8ff	474	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	475	{
bogdanm	0:9b334a45a8ff	476	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	477	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	478	}
bogdanm	0:9b334a45a8ff	479	}
bogdanm	0:9b334a45a8ff	480	}
bogdanm	0:9b334a45a8ff	481	return HAL_OK;
bogdanm	0:9b334a45a8ff	482	}
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/**
bogdanm	0:9b334a45a8ff	485	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
bogdanm	0:9b334a45a8ff	486	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	487	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	488	* will be configured.
bogdanm	0:9b334a45a8ff	489	* @retval None
bogdanm	0:9b334a45a8ff	490	*/
bogdanm	0:9b334a45a8ff	491	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	492	{
bogdanm	0:9b334a45a8ff	493	uint32_t tempreg;
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	496	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
bogdanm	0:9b334a45a8ff	497	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
bogdanm	0:9b334a45a8ff	498	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
bogdanm	0:9b334a45a8ff	499	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_FMPI2C1 \|\
bogdanm	0:9b334a45a8ff	500	RCC_PERIPHCLK_CK48 \| RCC_PERIPHCLK_SDIO \|\
bogdanm	0:9b334a45a8ff	501	RCC_PERIPHCLK_SPDIFRX;
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	504	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
bogdanm	0:9b334a45a8ff	505	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
bogdanm	0:9b334a45a8ff	506	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	507	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
bogdanm	0:9b334a45a8ff	508	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	509	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	510	PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
bogdanm	0:9b334a45a8ff	511	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
bogdanm	0:9b334a45a8ff	512	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
bogdanm	0:9b334a45a8ff	513	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	514	/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
bogdanm	0:9b334a45a8ff	515	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
bogdanm	0:9b334a45a8ff	516	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	/* Get the SAI1 clock configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	519	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/* Get the SAI2 clock configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	522	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	/* Get the I2S APB1 clock configuration ------------------------------------------*/
bogdanm	0:9b334a45a8ff	525	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/* Get the I2S APB2 clock configuration ------------------------------------------*/
bogdanm	0:9b334a45a8ff	528	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Get the RTC Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	531	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
bogdanm	0:9b334a45a8ff	532	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	533
bogdanm	0:9b334a45a8ff	534	/* Get the CEC clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	535	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/* Get the FMPI2C1 clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	538	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	/* Get the CK48 clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	541	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	/* Get the SDIO clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	544	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/* Get the SPDIFRX clock configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	547	PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	/* Get the TIM Prescaler configuration --------------------------------------------*/
bogdanm	0:9b334a45a8ff	550	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
bogdanm	0:9b334a45a8ff	551	{
bogdanm	0:9b334a45a8ff	552	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
bogdanm	0:9b334a45a8ff	553	}
bogdanm	0:9b334a45a8ff	554	else
bogdanm	0:9b334a45a8ff	555	{
bogdanm	0:9b334a45a8ff	556	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
bogdanm	0:9b334a45a8ff	557	}
bogdanm	0:9b334a45a8ff	558	}
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/**
bogdanm	0:9b334a45a8ff	561	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
bogdanm	0:9b334a45a8ff	562	* @note Return 0 if peripheral clock identifier not managed by this API
bogdanm	0:9b334a45a8ff	563	* @param PeriphClk: Peripheral clock identifier
bogdanm	0:9b334a45a8ff	564	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	565	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
bogdanm	0:9b334a45a8ff	566	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
bogdanm	0:9b334a45a8ff	567	* @retval Frequency in KHz
bogdanm	0:9b334a45a8ff	568	*/
bogdanm	0:9b334a45a8ff	569	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
bogdanm	0:9b334a45a8ff	570	{
bogdanm	0:9b334a45a8ff	571	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	572	/* This variable used to store the SAI clock frequency (value in Hz) */
bogdanm	0:9b334a45a8ff	573	uint32_t frequency = 0;
bogdanm	0:9b334a45a8ff	574	/* This variable used to store the VCO Input (value in Hz) */
bogdanm	0:9b334a45a8ff	575	uint32_t vcoinput = 0;
bogdanm	0:9b334a45a8ff	576	/* This variable used to store the SAI clock source */
bogdanm	0:9b334a45a8ff	577	uint32_t saiclocksource = 0;
bogdanm	0:9b334a45a8ff	578	if ((PeriphClk == RCC_PERIPHCLK_SAI1) \|\| (PeriphClk == RCC_PERIPHCLK_SAI2))
bogdanm	0:9b334a45a8ff	579	{
bogdanm	0:9b334a45a8ff	580	saiclocksource = RCC->DCKCFGR;
bogdanm	0:9b334a45a8ff	581	saiclocksource &= (RCC_DCKCFGR_SAI1SRC \| RCC_DCKCFGR_SAI2SRC);
bogdanm	0:9b334a45a8ff	582	switch (saiclocksource)
bogdanm	0:9b334a45a8ff	583	{
bogdanm	0:9b334a45a8ff	584	case 0: /* PLLSAI is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	585	{
bogdanm	0:9b334a45a8ff	586	/* Configure the PLLSAI division factor */
bogdanm	0:9b334a45a8ff	587	/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
bogdanm	0:9b334a45a8ff	588	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	589	{
bogdanm	0:9b334a45a8ff	590	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	591	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
bogdanm	0:9b334a45a8ff	592	}
bogdanm	0:9b334a45a8ff	593	else
bogdanm	0:9b334a45a8ff	594	{
bogdanm	0:9b334a45a8ff	595	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	596	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
bogdanm	0:9b334a45a8ff	597	}
bogdanm	0:9b334a45a8ff	598	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	599	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
bogdanm	0:9b334a45a8ff	600	tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
bogdanm	0:9b334a45a8ff	601	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg1);
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
bogdanm	0:9b334a45a8ff	604	tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
bogdanm	0:9b334a45a8ff	605	frequency = frequency/(tmpreg1);
bogdanm	0:9b334a45a8ff	606	break;
bogdanm	0:9b334a45a8ff	607	}
bogdanm	0:9b334a45a8ff	608	case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	609	case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	610	{
bogdanm	0:9b334a45a8ff	611	/* Configure the PLLI2S division factor */
bogdanm	0:9b334a45a8ff	612	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm	0:9b334a45a8ff	613	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	616	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
bogdanm	0:9b334a45a8ff	617	}
bogdanm	0:9b334a45a8ff	618	else
bogdanm	0:9b334a45a8ff	619	{
bogdanm	0:9b334a45a8ff	620	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	621	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
bogdanm	0:9b334a45a8ff	622	}
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	625	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
bogdanm	0:9b334a45a8ff	626	tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
bogdanm	0:9b334a45a8ff	627	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg1);
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
bogdanm	0:9b334a45a8ff	630	tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
bogdanm	0:9b334a45a8ff	631	frequency = frequency/(tmpreg1);
bogdanm	0:9b334a45a8ff	632	break;
bogdanm	0:9b334a45a8ff	633	}
bogdanm	0:9b334a45a8ff	634	case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	635	case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	636	{
bogdanm	0:9b334a45a8ff	637	/* Configure the PLLI2S division factor */
bogdanm	0:9b334a45a8ff	638	/* PLL_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	639	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	642	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm	0:9b334a45a8ff	643	}
bogdanm	0:9b334a45a8ff	644	else
bogdanm	0:9b334a45a8ff	645	{
bogdanm	0:9b334a45a8ff	646	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	647	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
bogdanm	0:9b334a45a8ff	648	}
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	/* PLL_VCO Output = PLL_VCO Input * PLLN */
bogdanm	0:9b334a45a8ff	651	/* SAI_CLK_x = PLL_VCO Output/PLLR */
bogdanm	0:9b334a45a8ff	652	tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28;
bogdanm	0:9b334a45a8ff	653	frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6))/(tmpreg1);
bogdanm	0:9b334a45a8ff	654	break;
bogdanm	0:9b334a45a8ff	655	}
bogdanm	0:9b334a45a8ff	656	case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	657	{
bogdanm	0:9b334a45a8ff	658	frequency = EXTERNAL_CLOCK_VALUE;
bogdanm	0:9b334a45a8ff	659	break;
bogdanm	0:9b334a45a8ff	660	}
bogdanm	0:9b334a45a8ff	661	case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
bogdanm	0:9b334a45a8ff	662	{
bogdanm	0:9b334a45a8ff	663	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	664	{
bogdanm	0:9b334a45a8ff	665	/* In Case the PLL Source is HSI (Internal Clock) */
bogdanm	0:9b334a45a8ff	666	frequency = (uint32_t)(HSI_VALUE);
bogdanm	0:9b334a45a8ff	667	}
bogdanm	0:9b334a45a8ff	668	else
bogdanm	0:9b334a45a8ff	669	{
bogdanm	0:9b334a45a8ff	670	/* In Case the PLL Source is HSE (External Clock) */
bogdanm	0:9b334a45a8ff	671	frequency = (uint32_t)(HSE_VALUE);
bogdanm	0:9b334a45a8ff	672	}
bogdanm	0:9b334a45a8ff	673	break;
bogdanm	0:9b334a45a8ff	674	}
bogdanm	0:9b334a45a8ff	675	default :
bogdanm	0:9b334a45a8ff	676	{
bogdanm	0:9b334a45a8ff	677	break;
bogdanm	0:9b334a45a8ff	678	}
bogdanm	0:9b334a45a8ff	679	}
bogdanm	0:9b334a45a8ff	680	}
bogdanm	0:9b334a45a8ff	681	return frequency;
bogdanm	0:9b334a45a8ff	682	}
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	685
bogdanm	0:9b334a45a8ff	686	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	687	/**
bogdanm	0:9b334a45a8ff	688	* @brief Initializes the RCC extended peripherals clocks according to the specified
bogdanm	0:9b334a45a8ff	689	* parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	690	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	691	* contains the configuration information for the Extended Peripherals
bogdanm	0:9b334a45a8ff	692	* clocks(I2S, SAI, LTDC RTC and TIM).
bogdanm	0:9b334a45a8ff	693	*
bogdanm	0:9b334a45a8ff	694	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm	0:9b334a45a8ff	695	* the RTC clock source; in this case the Backup domain will be reset in
bogdanm	0:9b334a45a8ff	696	* order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm	0:9b334a45a8ff	697	* the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm	0:9b334a45a8ff	698	*
bogdanm	0:9b334a45a8ff	699	* @retval HAL status
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	702	{
bogdanm	0:9b334a45a8ff	703	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	704	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	/* Check the parameters */
bogdanm	0:9b334a45a8ff	707	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm	0:9b334a45a8ff	708
bogdanm	0:9b334a45a8ff	709	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------------/
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	/----------------------- Common configuration SAI/I2S ---------------------------/
bogdanm	0:9b334a45a8ff	712	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
bogdanm	0:9b334a45a8ff	713	factor is common parameters for both peripherals */
bogdanm	0:9b334a45a8ff	714	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
bogdanm	0:9b334a45a8ff	715	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
bogdanm	0:9b334a45a8ff	716	{
bogdanm	0:9b334a45a8ff	717	/* check for Parameters */
bogdanm	0:9b334a45a8ff	718	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* Disable the PLLI2S */
bogdanm	0:9b334a45a8ff	721	__HAL_RCC_PLLI2S_DISABLE();
bogdanm	0:9b334a45a8ff	722	/* Get tick */
bogdanm	0:9b334a45a8ff	723	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	724	/* Wait till PLLI2S is disabled */
bogdanm	0:9b334a45a8ff	725	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm	0:9b334a45a8ff	726	{
bogdanm	0:9b334a45a8ff	727	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	728	{
bogdanm	0:9b334a45a8ff	729	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	730	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	731	}
bogdanm	0:9b334a45a8ff	732	}
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/---------------------------- I2S configuration -------------------------------/
bogdanm	0:9b334a45a8ff	735	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
bogdanm	0:9b334a45a8ff	736	only for I2S configuration */
bogdanm	0:9b334a45a8ff	737	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
bogdanm	0:9b334a45a8ff	738	{
bogdanm	0:9b334a45a8ff	739	/* check for Parameters */
bogdanm	0:9b334a45a8ff	740	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	741	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	742	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
bogdanm	0:9b334a45a8ff	743	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	744	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	745	}
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	/---------------------------- SAI configuration -------------------------------/
bogdanm	0:9b334a45a8ff	748	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
bogdanm	0:9b334a45a8ff	749	be added only for SAI configuration */
bogdanm	0:9b334a45a8ff	750	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	/* Check the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	753	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
bogdanm	0:9b334a45a8ff	754	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	757	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	758	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	759	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	760	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm	0:9b334a45a8ff	761	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
bogdanm	0:9b334a45a8ff	762	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
bogdanm	0:9b334a45a8ff	763	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
bogdanm	0:9b334a45a8ff	764	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
bogdanm	0:9b334a45a8ff	765	}
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/* Enable the PLLI2S */
bogdanm	0:9b334a45a8ff	768	__HAL_RCC_PLLI2S_ENABLE();
bogdanm	0:9b334a45a8ff	769	/* Get tick */
bogdanm	0:9b334a45a8ff	770	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	771	/* Wait till PLLI2S is ready */
bogdanm	0:9b334a45a8ff	772	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm	0:9b334a45a8ff	773	{
bogdanm	0:9b334a45a8ff	774	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	775	{
bogdanm	0:9b334a45a8ff	776	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	777	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	778	}
bogdanm	0:9b334a45a8ff	779	}
bogdanm	0:9b334a45a8ff	780	}
bogdanm	0:9b334a45a8ff	781
bogdanm	0:9b334a45a8ff	782	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/----------------------- Common configuration SAI/LTDC --------------------/
bogdanm	0:9b334a45a8ff	785	/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
bogdanm	0:9b334a45a8ff	786	factor is common parameters for both peripherals */
bogdanm	0:9b334a45a8ff	787	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
bogdanm	0:9b334a45a8ff	788	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	/* Check the PLLSAI division factors */
bogdanm	0:9b334a45a8ff	791	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	/* Disable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	794	__HAL_RCC_PLLSAI_DISABLE();
bogdanm	0:9b334a45a8ff	795	/* Get tick */
bogdanm	0:9b334a45a8ff	796	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	797	/* Wait till PLLSAI is disabled */
bogdanm	0:9b334a45a8ff	798	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
bogdanm	0:9b334a45a8ff	799	{
bogdanm	0:9b334a45a8ff	800	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	803	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	804	}
bogdanm	0:9b334a45a8ff	805	}
bogdanm	0:9b334a45a8ff	806
bogdanm	0:9b334a45a8ff	807	/---------------------------- SAI configuration -------------------------/
bogdanm	0:9b334a45a8ff	808	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
bogdanm	0:9b334a45a8ff	809	be added only for SAI configuration */
bogdanm	0:9b334a45a8ff	810	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
bogdanm	0:9b334a45a8ff	813	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
bogdanm	0:9b334a45a8ff	814
bogdanm	0:9b334a45a8ff	815	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	816	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
bogdanm	0:9b334a45a8ff	817	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	818	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	819	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
bogdanm	0:9b334a45a8ff	820	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
bogdanm	0:9b334a45a8ff	821	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
bogdanm	0:9b334a45a8ff	822	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
bogdanm	0:9b334a45a8ff	823	}
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/---------------------------- LTDC configuration ------------------------/
bogdanm	0:9b334a45a8ff	826	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
bogdanm	0:9b334a45a8ff	827	{
bogdanm	0:9b334a45a8ff	828	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
bogdanm	0:9b334a45a8ff	829	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
bogdanm	0:9b334a45a8ff	830
bogdanm	0:9b334a45a8ff	831	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
bogdanm	0:9b334a45a8ff	832	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	833	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
bogdanm	0:9b334a45a8ff	834	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
bogdanm	0:9b334a45a8ff	835	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
bogdanm	0:9b334a45a8ff	836	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
bogdanm	0:9b334a45a8ff	837	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
bogdanm	0:9b334a45a8ff	838	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
bogdanm	0:9b334a45a8ff	839	}
bogdanm	0:9b334a45a8ff	840	/* Enable PLLSAI Clock */
bogdanm	0:9b334a45a8ff	841	__HAL_RCC_PLLSAI_ENABLE();
bogdanm	0:9b334a45a8ff	842	/* Get tick */
bogdanm	0:9b334a45a8ff	843	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	844	/* Wait till PLLSAI is ready */
bogdanm	0:9b334a45a8ff	845	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	848	{
bogdanm	0:9b334a45a8ff	849	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	850	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	851	}
bogdanm	0:9b334a45a8ff	852	}
bogdanm	0:9b334a45a8ff	853	}
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/---------------------------- RTC configuration ---------------------------/
bogdanm	0:9b334a45a8ff	857	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	858	{
bogdanm	0:9b334a45a8ff	859	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	860	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	863	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/* Get tick */
bogdanm	0:9b334a45a8ff	866	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	869	{
bogdanm	0:9b334a45a8ff	870	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	871	{
bogdanm	0:9b334a45a8ff	872	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	873	}
bogdanm	0:9b334a45a8ff	874	}
bogdanm	0:9b334a45a8ff	875	/* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm	0:9b334a45a8ff	876	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
bogdanm	0:9b334a45a8ff	877	{
bogdanm	0:9b334a45a8ff	878	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	879	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	880	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	881	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	882	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	883	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	884	RCC->BDCR = tmpreg1;
bogdanm	0:9b334a45a8ff	885	/* Wait for LSERDY if LSE was enabled */
bogdanm	0:9b334a45a8ff	886	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	887	{
bogdanm	0:9b334a45a8ff	888	/* Get tick */
bogdanm	0:9b334a45a8ff	889	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	892	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	893	{
bogdanm	0:9b334a45a8ff	894	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	895	{
bogdanm	0:9b334a45a8ff	896	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	897	}
bogdanm	0:9b334a45a8ff	898	}
bogdanm	0:9b334a45a8ff	899	}
bogdanm	0:9b334a45a8ff	900	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	901	}
bogdanm	0:9b334a45a8ff	902	}
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/---------------------------- TIM configuration ---------------------------/
bogdanm	0:9b334a45a8ff	905	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
bogdanm	0:9b334a45a8ff	906	{
bogdanm	0:9b334a45a8ff	907	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909	return HAL_OK;
bogdanm	0:9b334a45a8ff	910	}
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	/**
bogdanm	0:9b334a45a8ff	913	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	914	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	915	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	916	* will be configured.
bogdanm	0:9b334a45a8ff	917	* @retval None
bogdanm	0:9b334a45a8ff	918	*/
bogdanm	0:9b334a45a8ff	919	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	920	{
bogdanm	0:9b334a45a8ff	921	uint32_t tempreg;
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	924	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \| RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	927	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
bogdanm	0:9b334a45a8ff	928	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	929	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
bogdanm	0:9b334a45a8ff	930	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	931	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
bogdanm	0:9b334a45a8ff	932	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
bogdanm	0:9b334a45a8ff	933	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
bogdanm	0:9b334a45a8ff	934	/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	935	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
bogdanm	0:9b334a45a8ff	936	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
bogdanm	0:9b334a45a8ff	937	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
bogdanm	0:9b334a45a8ff	938	/* Get the RTC Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	939	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
bogdanm	0:9b334a45a8ff	940	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	941
bogdanm	0:9b334a45a8ff	942	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
bogdanm	0:9b334a45a8ff	943	{
bogdanm	0:9b334a45a8ff	944	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
bogdanm	0:9b334a45a8ff	945	}
bogdanm	0:9b334a45a8ff	946	else
bogdanm	0:9b334a45a8ff	947	{
bogdanm	0:9b334a45a8ff	948	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
bogdanm	0:9b334a45a8ff	949	}
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
bogdanm	0:9b334a45a8ff	955	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	956	/**
bogdanm	0:9b334a45a8ff	957	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
bogdanm	0:9b334a45a8ff	958	* RCC_PeriphCLKInitTypeDef.
bogdanm	0:9b334a45a8ff	959	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	960	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
bogdanm	0:9b334a45a8ff	961	*
bogdanm	0:9b334a45a8ff	962	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
bogdanm	0:9b334a45a8ff	963	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
bogdanm	0:9b334a45a8ff	964	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
bogdanm	0:9b334a45a8ff	965	*
bogdanm	0:9b334a45a8ff	966	* @retval HAL status
bogdanm	0:9b334a45a8ff	967	*/
bogdanm	0:9b334a45a8ff	968	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	969	{
bogdanm	0:9b334a45a8ff	970	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	971	uint32_t tmpreg1 = 0;
bogdanm	0:9b334a45a8ff	972
bogdanm	0:9b334a45a8ff	973	/* Check the parameters */
bogdanm	0:9b334a45a8ff	974	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	/---------------------------- I2S configuration ---------------------------/
bogdanm	0:9b334a45a8ff	977	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
bogdanm	0:9b334a45a8ff	978	{
bogdanm	0:9b334a45a8ff	979	/* check for Parameters */
bogdanm	0:9b334a45a8ff	980	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
bogdanm	0:9b334a45a8ff	981	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
bogdanm	0:9b334a45a8ff	982	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	983	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
bogdanm	0:9b334a45a8ff	984	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	985	/* Disable the PLLI2S */
bogdanm	0:9b334a45a8ff	986	__HAL_RCC_PLLI2S_DISABLE();
bogdanm	0:9b334a45a8ff	987	/* Get tick */
bogdanm	0:9b334a45a8ff	988	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	989	/* Wait till PLLI2S is disabled */
bogdanm	0:9b334a45a8ff	990	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm	0:9b334a45a8ff	991	{
bogdanm	0:9b334a45a8ff	992	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	993	{
bogdanm	0:9b334a45a8ff	994	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	995	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	996	}
bogdanm	0:9b334a45a8ff	997	}
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1000	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	1001	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
bogdanm	0:9b334a45a8ff	1002	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	1003	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	1004	#else
bogdanm	0:9b334a45a8ff	1005	/* Configure the PLLI2S division factors */
bogdanm	0:9b334a45a8ff	1006	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
bogdanm	0:9b334a45a8ff	1007	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
bogdanm	0:9b334a45a8ff	1008	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
bogdanm	0:9b334a45a8ff	1009	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	1010
bogdanm	0:9b334a45a8ff	1011	/* Enable the PLLI2S */
bogdanm	0:9b334a45a8ff	1012	__HAL_RCC_PLLI2S_ENABLE();
bogdanm	0:9b334a45a8ff	1013	/* Get tick */
bogdanm	0:9b334a45a8ff	1014	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1015	/* Wait till PLLI2S is ready */
bogdanm	0:9b334a45a8ff	1016	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm	0:9b334a45a8ff	1017	{
bogdanm	0:9b334a45a8ff	1018	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1019	{
bogdanm	0:9b334a45a8ff	1020	/* return in case of Timeout detected */
bogdanm	0:9b334a45a8ff	1021	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1022	}
bogdanm	0:9b334a45a8ff	1023	}
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/---------------------------- RTC configuration ---------------------------/
bogdanm	0:9b334a45a8ff	1027	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	1028	{
bogdanm	0:9b334a45a8ff	1029	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	1030	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	1033	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/* Get tick */
bogdanm	0:9b334a45a8ff	1036	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	1039	{
bogdanm	0:9b334a45a8ff	1040	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1041	{
bogdanm	0:9b334a45a8ff	1042	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1043	}
bogdanm	0:9b334a45a8ff	1044	}
bogdanm	0:9b334a45a8ff	1045	/* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm	0:9b334a45a8ff	1046	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
bogdanm	0:9b334a45a8ff	1047	{
bogdanm	0:9b334a45a8ff	1048	/* Store the content of BDCR register before the reset of Backup Domain */
bogdanm	0:9b334a45a8ff	1049	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	1050	/* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm	0:9b334a45a8ff	1051	__HAL_RCC_BACKUPRESET_FORCE();
bogdanm	0:9b334a45a8ff	1052	__HAL_RCC_BACKUPRESET_RELEASE();
bogdanm	0:9b334a45a8ff	1053	/* Restore the Content of BDCR register */
bogdanm	0:9b334a45a8ff	1054	RCC->BDCR = tmpreg1;
bogdanm	0:9b334a45a8ff	1055	/* Wait for LSERDY if LSE was enabled */
bogdanm	0:9b334a45a8ff	1056	if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
bogdanm	0:9b334a45a8ff	1057	{
bogdanm	0:9b334a45a8ff	1058	/* Get tick */
bogdanm	0:9b334a45a8ff	1059	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1062	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1063	{
bogdanm	0:9b334a45a8ff	1064	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1065	{
bogdanm	0:9b334a45a8ff	1066	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1067	}
bogdanm	0:9b334a45a8ff	1068	}
bogdanm	0:9b334a45a8ff	1069	}
bogdanm	0:9b334a45a8ff	1070	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm	0:9b334a45a8ff	1071	}
bogdanm	0:9b334a45a8ff	1072	}
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	return HAL_OK;
bogdanm	0:9b334a45a8ff	1075	}
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/**
bogdanm	0:9b334a45a8ff	1078	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1079	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	1080	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1081	* will be configured.
bogdanm	0:9b334a45a8ff	1082	* @retval None
bogdanm	0:9b334a45a8ff	1083	*/
bogdanm	0:9b334a45a8ff	1084	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm	0:9b334a45a8ff	1085	{
bogdanm	0:9b334a45a8ff	1086	uint32_t tempreg;
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/* Set all possible values for the extended clock type parameter------------*/
bogdanm	0:9b334a45a8ff	1089	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_RTC;
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1092	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
bogdanm	0:9b334a45a8ff	1093	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
bogdanm	0:9b334a45a8ff	1094	#if defined(STM32F411xE)
bogdanm	0:9b334a45a8ff	1095	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
bogdanm	0:9b334a45a8ff	1096	#endif /* STM32F411xE */
bogdanm	0:9b334a45a8ff	1097	/* Get the RTC Clock configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1098	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
bogdanm	0:9b334a45a8ff	1099	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	}
bogdanm	0:9b334a45a8ff	1102	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	1105	/**
bogdanm	0:9b334a45a8ff	1106	* @brief Select LSE mode
bogdanm	0:9b334a45a8ff	1107	*
bogdanm	0:9b334a45a8ff	1108	* @note This mode is only available for STM32F411xx devices.
bogdanm	0:9b334a45a8ff	1109	*
bogdanm	0:9b334a45a8ff	1110	* @param Mode: specifies the LSE mode.
bogdanm	0:9b334a45a8ff	1111	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1112	* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
bogdanm	0:9b334a45a8ff	1113	* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
bogdanm	0:9b334a45a8ff	1114	* @retval None
bogdanm	0:9b334a45a8ff	1115	*/
bogdanm	0:9b334a45a8ff	1116	void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
bogdanm	0:9b334a45a8ff	1117	{
bogdanm	0:9b334a45a8ff	1118	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1119	assert_param(IS_RCC_LSE_MODE(Mode));
bogdanm	0:9b334a45a8ff	1120	if(Mode == RCC_LSE_HIGHDRIVE_MODE)
bogdanm	0:9b334a45a8ff	1121	{
bogdanm	0:9b334a45a8ff	1122	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
bogdanm	0:9b334a45a8ff	1123	}
bogdanm	0:9b334a45a8ff	1124	else
bogdanm	0:9b334a45a8ff	1125	{
bogdanm	0:9b334a45a8ff	1126	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
bogdanm	0:9b334a45a8ff	1127	}
bogdanm	0:9b334a45a8ff	1128	}
bogdanm	0:9b334a45a8ff	1129
bogdanm	0:9b334a45a8ff	1130	#endif /* STM32F411xE \|\| STM32F446xx */
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	#if defined(STM32F446xx)
bogdanm	0:9b334a45a8ff	1133	/**
bogdanm	0:9b334a45a8ff	1134	* @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm	0:9b334a45a8ff	1135	* RCC_OscInitTypeDef.
bogdanm	0:9b334a45a8ff	1136	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1137	* contains the configuration information for the RCC Oscillators.
bogdanm	0:9b334a45a8ff	1138	* @note The PLL is not disabled when used as system clock.
bogdanm	0:9b334a45a8ff	1139	* @note This function add the PLL/PLLR factor management during PLL configuration this feature is only available in STM32F446xx devices
bogdanm	0:9b334a45a8ff	1140	* @retval HAL status
bogdanm	0:9b334a45a8ff	1141	*/
bogdanm	0:9b334a45a8ff	1142	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	1143	{
bogdanm	0:9b334a45a8ff	1144	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1147	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm	0:9b334a45a8ff	1148	/------------------------------- HSE Configuration ------------------------/
bogdanm	0:9b334a45a8ff	1149	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm	0:9b334a45a8ff	1150	{
bogdanm	0:9b334a45a8ff	1151	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1152	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm	0:9b334a45a8ff	1153	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
bogdanm	0:9b334a45a8ff	1154	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
bogdanm	0:9b334a45a8ff	1155	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) \|\|\
bogdanm	0:9b334a45a8ff	1156	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
bogdanm	0:9b334a45a8ff	1157	{
bogdanm	0:9b334a45a8ff	1158	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
bogdanm	0:9b334a45a8ff	1159	{
bogdanm	0:9b334a45a8ff	1160	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1161	}
bogdanm	0:9b334a45a8ff	1162	}
bogdanm	0:9b334a45a8ff	1163	else
bogdanm	0:9b334a45a8ff	1164	{
bogdanm	0:9b334a45a8ff	1165	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm	0:9b334a45a8ff	1166	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1169	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/* Wait till HSE is disabled */
bogdanm	0:9b334a45a8ff	1172	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1173	{
bogdanm	0:9b334a45a8ff	1174	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1175	{
bogdanm	0:9b334a45a8ff	1176	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1177	}
bogdanm	0:9b334a45a8ff	1178	}
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	/* Set the new HSE configuration ---------------------------------------*/
bogdanm	0:9b334a45a8ff	1181	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm	0:9b334a45a8ff	1182
bogdanm	0:9b334a45a8ff	1183	/* Check the HSE State */
bogdanm	0:9b334a45a8ff	1184	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
bogdanm	0:9b334a45a8ff	1185	{
bogdanm	0:9b334a45a8ff	1186	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1187	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/* Wait till HSE is ready */
bogdanm	0:9b334a45a8ff	1190	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1191	{
bogdanm	0:9b334a45a8ff	1192	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1193	{
bogdanm	0:9b334a45a8ff	1194	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1195	}
bogdanm	0:9b334a45a8ff	1196	}
bogdanm	0:9b334a45a8ff	1197	}
bogdanm	0:9b334a45a8ff	1198	else
bogdanm	0:9b334a45a8ff	1199	{
bogdanm	0:9b334a45a8ff	1200	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1201	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Wait till HSE is bypassed or disabled */
bogdanm	0:9b334a45a8ff	1204	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1205	{
bogdanm	0:9b334a45a8ff	1206	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1207	{
bogdanm	0:9b334a45a8ff	1208	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1209	}
bogdanm	0:9b334a45a8ff	1210	}
bogdanm	0:9b334a45a8ff	1211	}
bogdanm	0:9b334a45a8ff	1212	}
bogdanm	0:9b334a45a8ff	1213	}
bogdanm	0:9b334a45a8ff	1214	/----------------------------- HSI Configuration --------------------------/
bogdanm	0:9b334a45a8ff	1215	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1218	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm	0:9b334a45a8ff	1219	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm	0:9b334a45a8ff	1222	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
bogdanm	0:9b334a45a8ff	1223	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) \|\|\
bogdanm	0:9b334a45a8ff	1224	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
bogdanm	0:9b334a45a8ff	1225	{
bogdanm	0:9b334a45a8ff	1226	/* When HSI is used as system clock it will not disabled */
bogdanm	0:9b334a45a8ff	1227	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	1228	{
bogdanm	0:9b334a45a8ff	1229	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1230	}
bogdanm	0:9b334a45a8ff	1231	/* Otherwise, just the calibration is allowed */
bogdanm	0:9b334a45a8ff	1232	else
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	1235	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237	}
bogdanm	0:9b334a45a8ff	1238	else
bogdanm	0:9b334a45a8ff	1239	{
bogdanm	0:9b334a45a8ff	1240	/* Check the HSI State */
bogdanm	0:9b334a45a8ff	1241	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
bogdanm	0:9b334a45a8ff	1242	{
bogdanm	0:9b334a45a8ff	1243	/* Enable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	1244	__HAL_RCC_HSI_ENABLE();
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1247	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	1250	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	1251	{
bogdanm	0:9b334a45a8ff	1252	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1253	{
bogdanm	0:9b334a45a8ff	1254	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1255	}
bogdanm	0:9b334a45a8ff	1256	}
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	1259	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	1260	}
bogdanm	0:9b334a45a8ff	1261	else
bogdanm	0:9b334a45a8ff	1262	{
bogdanm	0:9b334a45a8ff	1263	/* Disable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	1264	__HAL_RCC_HSI_DISABLE();
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1267	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	1270	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1273	{
bogdanm	0:9b334a45a8ff	1274	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1275	}
bogdanm	0:9b334a45a8ff	1276	}
bogdanm	0:9b334a45a8ff	1277	}
bogdanm	0:9b334a45a8ff	1278	}
bogdanm	0:9b334a45a8ff	1279	}
bogdanm	0:9b334a45a8ff	1280	/------------------------------ LSI Configuration -------------------------/
bogdanm	0:9b334a45a8ff	1281	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm	0:9b334a45a8ff	1282	{
bogdanm	0:9b334a45a8ff	1283	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1284	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Check the LSI State */
bogdanm	0:9b334a45a8ff	1287	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
bogdanm	0:9b334a45a8ff	1288	{
bogdanm	0:9b334a45a8ff	1289	/* Enable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	1290	__HAL_RCC_LSI_ENABLE();
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1293	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	1296	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	1297	{
bogdanm	0:9b334a45a8ff	1298	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1299	{
bogdanm	0:9b334a45a8ff	1300	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1301	}
bogdanm	0:9b334a45a8ff	1302	}
bogdanm	0:9b334a45a8ff	1303	}
bogdanm	0:9b334a45a8ff	1304	else
bogdanm	0:9b334a45a8ff	1305	{
bogdanm	0:9b334a45a8ff	1306	/* Disable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	1307	__HAL_RCC_LSI_DISABLE();
bogdanm	0:9b334a45a8ff	1308
bogdanm	0:9b334a45a8ff	1309	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1310	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	1313	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	1314	{
bogdanm	0:9b334a45a8ff	1315	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1316	{
bogdanm	0:9b334a45a8ff	1317	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1318	}
bogdanm	0:9b334a45a8ff	1319	}
bogdanm	0:9b334a45a8ff	1320	}
bogdanm	0:9b334a45a8ff	1321	}
bogdanm	0:9b334a45a8ff	1322	/------------------------------ LSE Configuration -------------------------/
bogdanm	0:9b334a45a8ff	1323	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm	0:9b334a45a8ff	1324	{
bogdanm	0:9b334a45a8ff	1325	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1326	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/* Enable Power Clock*/
bogdanm	0:9b334a45a8ff	1329	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/* Enable write access to Backup domain */
bogdanm	0:9b334a45a8ff	1332	PWR->CR \|= PWR_CR_DBP;
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* Wait for Backup domain Write protection disable */
bogdanm	0:9b334a45a8ff	1335	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	1338	{
bogdanm	0:9b334a45a8ff	1339	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1340	{
bogdanm	0:9b334a45a8ff	1341	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1342	}
bogdanm	0:9b334a45a8ff	1343	}
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm	0:9b334a45a8ff	1346	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1349	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1352	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1353	{
bogdanm	0:9b334a45a8ff	1354	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1355	{
bogdanm	0:9b334a45a8ff	1356	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1357	}
bogdanm	0:9b334a45a8ff	1358	}
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360	/* Set the new LSE configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	1361	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm	0:9b334a45a8ff	1362	/* Check the LSE State */
bogdanm	0:9b334a45a8ff	1363	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
bogdanm	0:9b334a45a8ff	1364	{
bogdanm	0:9b334a45a8ff	1365	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1366	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1369	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	1370	{
bogdanm	0:9b334a45a8ff	1371	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1372	{
bogdanm	0:9b334a45a8ff	1373	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1374	}
bogdanm	0:9b334a45a8ff	1375	}
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377	else
bogdanm	0:9b334a45a8ff	1378	{
bogdanm	0:9b334a45a8ff	1379	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1380	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1381
bogdanm	0:9b334a45a8ff	1382	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	1383	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	1384	{
bogdanm	0:9b334a45a8ff	1385	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1386	{
bogdanm	0:9b334a45a8ff	1387	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1388	}
bogdanm	0:9b334a45a8ff	1389	}
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391	}
bogdanm	0:9b334a45a8ff	1392	/-------------------------------- PLL Configuration -----------------------/
bogdanm	0:9b334a45a8ff	1393	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1394	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm	0:9b334a45a8ff	1395	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm	0:9b334a45a8ff	1396	{
bogdanm	0:9b334a45a8ff	1397	/* Check if the PLL is used as system clock or not */
bogdanm	0:9b334a45a8ff	1398	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
bogdanm	0:9b334a45a8ff	1399	{
bogdanm	0:9b334a45a8ff	1400	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm	0:9b334a45a8ff	1401	{
bogdanm	0:9b334a45a8ff	1402	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1403	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm	0:9b334a45a8ff	1404	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
bogdanm	0:9b334a45a8ff	1405	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
bogdanm	0:9b334a45a8ff	1406	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
bogdanm	0:9b334a45a8ff	1407	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
bogdanm	0:9b334a45a8ff	1408	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	1411	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1414	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	1417	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	1418	{
bogdanm	0:9b334a45a8ff	1419	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1420	{
bogdanm	0:9b334a45a8ff	1421	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1422	}
bogdanm	0:9b334a45a8ff	1423	}
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	/* Configure the main PLL clock source, multiplication and division factors. */
bogdanm	0:9b334a45a8ff	1426	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm	0:9b334a45a8ff	1427	RCC_OscInitStruct->PLL.PLLM,
bogdanm	0:9b334a45a8ff	1428	RCC_OscInitStruct->PLL.PLLN,
bogdanm	0:9b334a45a8ff	1429	RCC_OscInitStruct->PLL.PLLP,
bogdanm	0:9b334a45a8ff	1430	RCC_OscInitStruct->PLL.PLLQ,
bogdanm	0:9b334a45a8ff	1431	RCC_OscInitStruct->PLL.PLLR);
bogdanm	0:9b334a45a8ff	1432
bogdanm	0:9b334a45a8ff	1433	/* Enable the main PLL. */
bogdanm	0:9b334a45a8ff	1434	__HAL_RCC_PLL_ENABLE();
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1437	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	1440	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	1441	{
bogdanm	0:9b334a45a8ff	1442	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1443	{
bogdanm	0:9b334a45a8ff	1444	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1445	}
bogdanm	0:9b334a45a8ff	1446	}
bogdanm	0:9b334a45a8ff	1447	}
bogdanm	0:9b334a45a8ff	1448	else
bogdanm	0:9b334a45a8ff	1449	{
bogdanm	0:9b334a45a8ff	1450	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	1451	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	/* Get Start Tick*/
bogdanm	0:9b334a45a8ff	1454	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1455
bogdanm	0:9b334a45a8ff	1456	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	1457	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	1458	{
bogdanm	0:9b334a45a8ff	1459	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	1460	{
bogdanm	0:9b334a45a8ff	1461	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1462	}
bogdanm	0:9b334a45a8ff	1463	}
bogdanm	0:9b334a45a8ff	1464	}
bogdanm	0:9b334a45a8ff	1465	}
bogdanm	0:9b334a45a8ff	1466	else
bogdanm	0:9b334a45a8ff	1467	{
bogdanm	0:9b334a45a8ff	1468	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1469	}
bogdanm	0:9b334a45a8ff	1470	}
bogdanm	0:9b334a45a8ff	1471	return HAL_OK;
bogdanm	0:9b334a45a8ff	1472	}
bogdanm	0:9b334a45a8ff	1473
bogdanm	0:9b334a45a8ff	1474	/**
bogdanm	0:9b334a45a8ff	1475	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1476	* RCC configuration registers.
bogdanm	0:9b334a45a8ff	1477	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
bogdanm	0:9b334a45a8ff	1478	*
bogdanm	0:9b334a45a8ff	1479	* @note This function is only available in case of STM32F446xx devices.
bogdanm	0:9b334a45a8ff	1480	* @note This function add the PLL/PLLR factor management
bogdanm	0:9b334a45a8ff	1481	* @retval None
bogdanm	0:9b334a45a8ff	1482	*/
bogdanm	0:9b334a45a8ff	1483	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	1484	{
bogdanm	0:9b334a45a8ff	1485	/* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm	0:9b334a45a8ff	1486	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	/* Get the HSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1489	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm	0:9b334a45a8ff	1490	{
bogdanm	0:9b334a45a8ff	1491	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm	0:9b334a45a8ff	1492	}
bogdanm	0:9b334a45a8ff	1493	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm	0:9b334a45a8ff	1494	{
bogdanm	0:9b334a45a8ff	1495	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm	0:9b334a45a8ff	1496	}
bogdanm	0:9b334a45a8ff	1497	else
bogdanm	0:9b334a45a8ff	1498	{
bogdanm	0:9b334a45a8ff	1499	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm	0:9b334a45a8ff	1500	}
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	/* Get the HSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1503	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	1504	{
bogdanm	0:9b334a45a8ff	1505	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm	0:9b334a45a8ff	1506	}
bogdanm	0:9b334a45a8ff	1507	else
bogdanm	0:9b334a45a8ff	1508	{
bogdanm	0:9b334a45a8ff	1509	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm	0:9b334a45a8ff	1510	}
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	/* Get the LSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1515	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm	0:9b334a45a8ff	1516	{
bogdanm	0:9b334a45a8ff	1517	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm	0:9b334a45a8ff	1518	}
bogdanm	0:9b334a45a8ff	1519	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm	0:9b334a45a8ff	1520	{
bogdanm	0:9b334a45a8ff	1521	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm	0:9b334a45a8ff	1522	}
bogdanm	0:9b334a45a8ff	1523	else
bogdanm	0:9b334a45a8ff	1524	{
bogdanm	0:9b334a45a8ff	1525	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm	0:9b334a45a8ff	1526	}
bogdanm	0:9b334a45a8ff	1527
bogdanm	0:9b334a45a8ff	1528	/* Get the LSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1529	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1530	{
bogdanm	0:9b334a45a8ff	1531	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm	0:9b334a45a8ff	1532	}
bogdanm	0:9b334a45a8ff	1533	else
bogdanm	0:9b334a45a8ff	1534	{
bogdanm	0:9b334a45a8ff	1535	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm	0:9b334a45a8ff	1536	}
bogdanm	0:9b334a45a8ff	1537
bogdanm	0:9b334a45a8ff	1538	/* Get the PLL configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1539	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1540	{
bogdanm	0:9b334a45a8ff	1541	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm	0:9b334a45a8ff	1542	}
bogdanm	0:9b334a45a8ff	1543	else
bogdanm	0:9b334a45a8ff	1544	{
bogdanm	0:9b334a45a8ff	1545	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm	0:9b334a45a8ff	1546	}
bogdanm	0:9b334a45a8ff	1547	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
bogdanm	0:9b334a45a8ff	1548	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
bogdanm	0:9b334a45a8ff	1549	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
bogdanm	0:9b334a45a8ff	1550	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
bogdanm	0:9b334a45a8ff	1551	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
bogdanm	0:9b334a45a8ff	1552	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
bogdanm	0:9b334a45a8ff	1553	}
bogdanm	0:9b334a45a8ff	1554
bogdanm	0:9b334a45a8ff	1555	/**
bogdanm	0:9b334a45a8ff	1556	* @brief Returns the SYSCLK frequency
bogdanm	0:9b334a45a8ff	1557	*
bogdanm	0:9b334a45a8ff	1558	* @note This function is only available in case of STM32F446xx devices.
bogdanm	0:9b334a45a8ff	1559	* @note This function add the PLL/PLLR System clock source
bogdanm	0:9b334a45a8ff	1560	*
bogdanm	0:9b334a45a8ff	1561	* @note The system frequency computed by this function is not the real
bogdanm	0:9b334a45a8ff	1562	* frequency in the chip. It is calculated based on the predefined
bogdanm	0:9b334a45a8ff	1563	* constant and the selected clock source:
bogdanm	0:9b334a45a8ff	1564	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm	0:9b334a45a8ff	1565	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
bogdanm	0:9b334a45a8ff	1566	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
bogdanm	0:9b334a45a8ff	1567	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm	0:9b334a45a8ff	1568	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	1569	* 16 MHz) but the real value may vary depending on the variations
bogdanm	0:9b334a45a8ff	1570	* in voltage and temperature.
bogdanm	0:9b334a45a8ff	1571	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	1572	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm	0:9b334a45a8ff	1573	* frequency of the crystal used. Otherwise, this function may
bogdanm	0:9b334a45a8ff	1574	* have wrong result.
bogdanm	0:9b334a45a8ff	1575	*
bogdanm	0:9b334a45a8ff	1576	* @note The result of this function could be not correct when using fractional
bogdanm	0:9b334a45a8ff	1577	* value for HSE crystal.
bogdanm	0:9b334a45a8ff	1578	*
bogdanm	0:9b334a45a8ff	1579	* @note This function can be used by the user application to compute the
bogdanm	0:9b334a45a8ff	1580	* baudrate for the communication peripherals or configure other parameters.
bogdanm	0:9b334a45a8ff	1581	*
bogdanm	0:9b334a45a8ff	1582	* @note Each time SYSCLK changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1583	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1584	*
bogdanm	0:9b334a45a8ff	1585	*
bogdanm	0:9b334a45a8ff	1586	* @retval SYSCLK frequency
bogdanm	0:9b334a45a8ff	1587	*/
bogdanm	0:9b334a45a8ff	1588	uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm	0:9b334a45a8ff	1589	{
bogdanm	0:9b334a45a8ff	1590	uint32_t pllm = 0;
bogdanm	0:9b334a45a8ff	1591	uint32_t pllvco = 0;
bogdanm	0:9b334a45a8ff	1592	uint32_t pllp = 0;
bogdanm	0:9b334a45a8ff	1593	uint32_t pllr = 0;
bogdanm	0:9b334a45a8ff	1594	uint32_t sysclockfreq = 0;
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/* Get SYSCLK source -------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1597	switch (RCC->CFGR & RCC_CFGR_SWS)
bogdanm	0:9b334a45a8ff	1598	{
bogdanm	0:9b334a45a8ff	1599	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
bogdanm	0:9b334a45a8ff	1600	{
bogdanm	0:9b334a45a8ff	1601	sysclockfreq = HSI_VALUE;
bogdanm	0:9b334a45a8ff	1602	break;
bogdanm	0:9b334a45a8ff	1603	}
bogdanm	0:9b334a45a8ff	1604	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
bogdanm	0:9b334a45a8ff	1605	{
bogdanm	0:9b334a45a8ff	1606	sysclockfreq = HSE_VALUE;
bogdanm	0:9b334a45a8ff	1607	break;
bogdanm	0:9b334a45a8ff	1608	}
bogdanm	0:9b334a45a8ff	1609	case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
bogdanm	0:9b334a45a8ff	1610	{
bogdanm	0:9b334a45a8ff	1611	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
bogdanm	0:9b334a45a8ff	1612	SYSCLK = PLL_VCO / PLLP */
bogdanm	0:9b334a45a8ff	1613	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm	0:9b334a45a8ff	1614	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	1615	{
bogdanm	0:9b334a45a8ff	1616	/* HSE used as PLL clock source */
bogdanm	0:9b334a45a8ff	1617	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	1618	}
bogdanm	0:9b334a45a8ff	1619	else
bogdanm	0:9b334a45a8ff	1620	{
bogdanm	0:9b334a45a8ff	1621	/* HSI used as PLL clock source */
bogdanm	0:9b334a45a8ff	1622	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	1623	}
bogdanm	0:9b334a45a8ff	1624	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
bogdanm	0:9b334a45a8ff	1625
bogdanm	0:9b334a45a8ff	1626	sysclockfreq = pllvco/pllp;
bogdanm	0:9b334a45a8ff	1627	break;
bogdanm	0:9b334a45a8ff	1628	}
bogdanm	0:9b334a45a8ff	1629	case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
bogdanm	0:9b334a45a8ff	1630	{
bogdanm	0:9b334a45a8ff	1631	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
bogdanm	0:9b334a45a8ff	1632	SYSCLK = PLL_VCO / PLLR */
bogdanm	0:9b334a45a8ff	1633	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm	0:9b334a45a8ff	1634	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
bogdanm	0:9b334a45a8ff	1635	{
bogdanm	0:9b334a45a8ff	1636	/* HSE used as PLL clock source */
bogdanm	0:9b334a45a8ff	1637	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639	else
bogdanm	0:9b334a45a8ff	1640	{
bogdanm	0:9b334a45a8ff	1641	/* HSI used as PLL clock source */
bogdanm	0:9b334a45a8ff	1642	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
bogdanm	0:9b334a45a8ff	1643	}
bogdanm	0:9b334a45a8ff	1644	pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
bogdanm	0:9b334a45a8ff	1645
bogdanm	0:9b334a45a8ff	1646	sysclockfreq = pllvco/pllr;
bogdanm	0:9b334a45a8ff	1647	break;
bogdanm	0:9b334a45a8ff	1648	}
bogdanm	0:9b334a45a8ff	1649	default:
bogdanm	0:9b334a45a8ff	1650	{
bogdanm	0:9b334a45a8ff	1651	sysclockfreq = HSI_VALUE;
bogdanm	0:9b334a45a8ff	1652	break;
bogdanm	0:9b334a45a8ff	1653	}
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655	return sysclockfreq;
bogdanm	0:9b334a45a8ff	1656	}
bogdanm	0:9b334a45a8ff	1657	#endif /* STM32F446xx */
bogdanm	0:9b334a45a8ff	1658
bogdanm	0:9b334a45a8ff	1659	/**
bogdanm	0:9b334a45a8ff	1660	* @}
bogdanm	0:9b334a45a8ff	1661	*/
bogdanm	0:9b334a45a8ff	1662
bogdanm	0:9b334a45a8ff	1663	/**
bogdanm	0:9b334a45a8ff	1664	* @}
bogdanm	0:9b334a45a8ff	1665	*/
bogdanm	0:9b334a45a8ff	1666
bogdanm	0:9b334a45a8ff	1667	#endif /* HAL_RCC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1668	/**
bogdanm	0:9b334a45a8ff	1669	* @}
bogdanm	0:9b334a45a8ff	1670	*/
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	/**
bogdanm	0:9b334a45a8ff	1673	* @}
bogdanm	0:9b334a45a8ff	1674	*/
bogdanm	0:9b334a45a8ff	1675
bogdanm	0:9b334a45a8ff	1676	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
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Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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