mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 124:6a4a5b7d7324

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_rcc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	124:6a4a5b7d7324	5	* @version V1.0.4
mbed_official	124:6a4a5b7d7324	6	* @date 29-April-2016
bogdanm	0:9b334a45a8ff	7	* @brief RCC HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	@verbatim
bogdanm	0:9b334a45a8ff	14	==============================================================================
bogdanm	0:9b334a45a8ff	15	##### RCC specific features #####
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	[..]
bogdanm	0:9b334a45a8ff	18	After reset the device is running from Internal High Speed oscillator
bogdanm	0:9b334a45a8ff	19	(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
bogdanm	0:9b334a45a8ff	20	and all peripherals are off except internal SRAM, Flash and JTAG.
mbed_official	124:6a4a5b7d7324	21	(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
mbed_official	124:6a4a5b7d7324	22	all peripherals mapped on these buses are running at HSI speed.
bogdanm	0:9b334a45a8ff	23	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
bogdanm	0:9b334a45a8ff	24	(+) All GPIOs are in input floating state, except the JTAG pins which
bogdanm	0:9b334a45a8ff	25	are assigned to be used for debug purpose.
mbed_official	124:6a4a5b7d7324	26	[..] Once the device started from reset, the user application has to:
bogdanm	0:9b334a45a8ff	27	(+) Configure the clock source to be used to drive the System clock
bogdanm	0:9b334a45a8ff	28	(if the application needs higher frequency/performance)
bogdanm	0:9b334a45a8ff	29	(+) Configure the System clock frequency and Flash settings
mbed_official	124:6a4a5b7d7324	30	(+) Configure the AHB and APB buses prescalers
bogdanm	0:9b334a45a8ff	31	(+) Enable the clock for the peripheral(s) to be used
bogdanm	0:9b334a45a8ff	32	(+) Configure the clock source(s) for peripherals whose clocks are not
bogdanm	0:9b334a45a8ff	33	derived from the System clock (I2S, RTC, ADC, USB OTG FS)
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	##### RCC Limitations #####
bogdanm	0:9b334a45a8ff	36	==============================================================================
bogdanm	0:9b334a45a8ff	37	[..]
bogdanm	0:9b334a45a8ff	38	A delay between an RCC peripheral clock enable and the effective peripheral
bogdanm	0:9b334a45a8ff	39	enabling should be taken into account in order to manage the peripheral read/write
bogdanm	0:9b334a45a8ff	40	from/to registers.
bogdanm	0:9b334a45a8ff	41	(+) This delay depends on the peripheral mapping.
bogdanm	0:9b334a45a8ff	42	(++) AHB & APB peripherals, 1 dummy read is necessary
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	[..]
bogdanm	0:9b334a45a8ff	45	Workarounds:
bogdanm	0:9b334a45a8ff	46	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
bogdanm	0:9b334a45a8ff	47	inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	@endverbatim
bogdanm	0:9b334a45a8ff	50	******************************************************************************
bogdanm	0:9b334a45a8ff	51	* @attention
bogdanm	0:9b334a45a8ff	52	*
mbed_official	124:6a4a5b7d7324	53	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	54	*
bogdanm	0:9b334a45a8ff	55	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	56	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	57	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	58	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	59	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	60	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	61	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	62	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	63	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	64	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	65	*
bogdanm	0:9b334a45a8ff	66	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	67	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	68	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	69	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	70	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	71	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	72	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	73	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	74	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	75	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	76	*
bogdanm	0:9b334a45a8ff	77	******************************************************************************
mbed_official	124:6a4a5b7d7324	78	*/
mbed_official	124:6a4a5b7d7324	79
bogdanm	0:9b334a45a8ff	80	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	81	#include "stm32f1xx_hal.h"
bogdanm	0:9b334a45a8ff	82
bogdanm	0:9b334a45a8ff	83	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	84	* @{
bogdanm	0:9b334a45a8ff	85	*/
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	/** @defgroup RCC RCC
bogdanm	0:9b334a45a8ff	88	* @brief RCC HAL module driver
bogdanm	0:9b334a45a8ff	89	* @{
bogdanm	0:9b334a45a8ff	90	*/
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	#ifdef HAL_RCC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	95	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	96	/** @defgroup RCC_Private_Constants RCC Private Constants
bogdanm	0:9b334a45a8ff	97	* @{
bogdanm	0:9b334a45a8ff	98	*/
mbed_official	124:6a4a5b7d7324	99	/* Bits position in in the CFGR register */
mbed_official	124:6a4a5b7d7324	100	#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
mbed_official	124:6a4a5b7d7324	101	#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
mbed_official	124:6a4a5b7d7324	102	#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
bogdanm	0:9b334a45a8ff	103	/**
bogdanm	0:9b334a45a8ff	104	* @}
bogdanm	0:9b334a45a8ff	105	*/
bogdanm	0:9b334a45a8ff	106	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	107	/** @defgroup RCC_Private_Macros RCC Private Macros
bogdanm	0:9b334a45a8ff	108	* @{
bogdanm	0:9b334a45a8ff	109	*/
bogdanm	0:9b334a45a8ff	110
mbed_official	124:6a4a5b7d7324	111	#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	112	#define MCO1_GPIO_PORT GPIOA
bogdanm	0:9b334a45a8ff	113	#define MCO1_PIN GPIO_PIN_8
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	/**
bogdanm	0:9b334a45a8ff	116	* @}
bogdanm	0:9b334a45a8ff	117	*/
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	120	/** @defgroup RCC_Private_Variables RCC Private Variables
bogdanm	0:9b334a45a8ff	121	* @{
bogdanm	0:9b334a45a8ff	122	*/
bogdanm	0:9b334a45a8ff	123	/**
bogdanm	0:9b334a45a8ff	124	* @}
bogdanm	0:9b334a45a8ff	125	*/
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	/* Private function prototypes -----------------------------------------------*/
mbed_official	124:6a4a5b7d7324	128	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	/** @defgroup RCC_Exported_Functions RCC Exported Functions
bogdanm	0:9b334a45a8ff	131	* @{
bogdanm	0:9b334a45a8ff	132	*/
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	135	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	136	*
bogdanm	0:9b334a45a8ff	137	@verbatim
bogdanm	0:9b334a45a8ff	138	===============================================================================
mbed_official	124:6a4a5b7d7324	139	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	140	===============================================================================
bogdanm	0:9b334a45a8ff	141	[..]
mbed_official	124:6a4a5b7d7324	142	This section provides functions allowing to configure the internal/external oscillators
mbed_official	124:6a4a5b7d7324	143	(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
bogdanm	0:9b334a45a8ff	144	and APB2).
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	[..] Internal/external clock and PLL configuration
mbed_official	124:6a4a5b7d7324	147	(#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
bogdanm	0:9b334a45a8ff	148	the PLL as System clock source.
mbed_official	124:6a4a5b7d7324	149	(#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
bogdanm	0:9b334a45a8ff	150	clock source.
bogdanm	0:9b334a45a8ff	151
bogdanm	0:9b334a45a8ff	152	(#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
bogdanm	0:9b334a45a8ff	153	through the PLL as System clock source. Can be used also as RTC clock source.
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
bogdanm	0:9b334a45a8ff	156
mbed_official	124:6a4a5b7d7324	157	(#) PLL (clocked by HSI or HSE), featuring different output clocks:
bogdanm	0:9b334a45a8ff	158	(++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
bogdanm	0:9b334a45a8ff	159	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
bogdanm	0:9b334a45a8ff	162	and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official	124:6a4a5b7d7324	163	clock source), the System clocks automatically switched to HSI and an interrupt
bogdanm	0:9b334a45a8ff	164	is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
bogdanm	0:9b334a45a8ff	165	(Non-Maskable Interrupt) exception vector.
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	(#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
bogdanm	0:9b334a45a8ff	168	HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
bogdanm	0:9b334a45a8ff	169
mbed_official	124:6a4a5b7d7324	170	[..] System, AHB and APB buses clocks configuration
mbed_official	124:6a4a5b7d7324	171	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
bogdanm	0:9b334a45a8ff	172	HSE and PLL.
mbed_official	124:6a4a5b7d7324	173	The AHB clock (HCLK) is derived from System clock through configurable
mbed_official	124:6a4a5b7d7324	174	prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official	124:6a4a5b7d7324	175	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
mbed_official	124:6a4a5b7d7324	176	from AHB clock through configurable prescalers and used to clock
mbed_official	124:6a4a5b7d7324	177	the peripherals mapped on these buses. You can use
mbed_official	124:6a4a5b7d7324	178	"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
bogdanm	0:9b334a45a8ff	181	(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
bogdanm	0:9b334a45a8ff	182	divided by 128.
bogdanm	0:9b334a45a8ff	183	(+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
bogdanm	0:9b334a45a8ff	184	to work correctly. This clock is derived of the main PLL through PLL Multiplier.
bogdanm	0:9b334a45a8ff	185	(+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
bogdanm	0:9b334a45a8ff	186	(+@) IWDG clock which is always the LSI clock.
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	(#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
bogdanm	0:9b334a45a8ff	189	For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
mbed_official	124:6a4a5b7d7324	190	Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
mbed_official	124:6a4a5b7d7324	191	@endverbatim
mbed_official	124:6a4a5b7d7324	192	* @{
mbed_official	124:6a4a5b7d7324	193	*/
mbed_official	124:6a4a5b7d7324	194
mbed_official	124:6a4a5b7d7324	195	/*
mbed_official	124:6a4a5b7d7324	196	Additional consideration on the SYSCLK based on Latency settings:
bogdanm	0:9b334a45a8ff	197	+-----------------------------------------------+
bogdanm	0:9b334a45a8ff	198	\| Latency \| SYSCLK clock frequency (MHz) \|
bogdanm	0:9b334a45a8ff	199	\|---------------\|-------------------------------\|
bogdanm	0:9b334a45a8ff	200	\|0WS(1CPU cycle)\| 0 < SYSCLK <= 24 \|
bogdanm	0:9b334a45a8ff	201	\|---------------\|-------------------------------\|
bogdanm	0:9b334a45a8ff	202	\|1WS(2CPU cycle)\| 24 < SYSCLK <= 48 \|
bogdanm	0:9b334a45a8ff	203	\|---------------\|-------------------------------\|
bogdanm	0:9b334a45a8ff	204	\|2WS(3CPU cycle)\| 48 < SYSCLK <= 72 \|
bogdanm	0:9b334a45a8ff	205	+-----------------------------------------------+
bogdanm	0:9b334a45a8ff	206	*/
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	/**
bogdanm	0:9b334a45a8ff	209	* @brief Resets the RCC clock configuration to the default reset state.
bogdanm	0:9b334a45a8ff	210	* @note The default reset state of the clock configuration is given below:
bogdanm	0:9b334a45a8ff	211	* - HSI ON and used as system clock source
bogdanm	0:9b334a45a8ff	212	* - HSE and PLL OFF
bogdanm	0:9b334a45a8ff	213	* - AHB, APB1 and APB2 prescaler set to 1.
bogdanm	0:9b334a45a8ff	214	* - CSS and MCO1 OFF
bogdanm	0:9b334a45a8ff	215	* - All interrupts disabled
mbed_official	124:6a4a5b7d7324	216	* @note This function does not modify the configuration of the
mbed_official	124:6a4a5b7d7324	217	* - Peripheral clocks
mbed_official	124:6a4a5b7d7324	218	* - LSI, LSE and RTC clocks
bogdanm	0:9b334a45a8ff	219	* @retval None
bogdanm	0:9b334a45a8ff	220	*/
mbed_official	124:6a4a5b7d7324	221	void HAL_RCC_DeInit(void)
bogdanm	0:9b334a45a8ff	222	{
bogdanm	0:9b334a45a8ff	223	/* Switch SYSCLK to HSI */
bogdanm	0:9b334a45a8ff	224	CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
mbed_official	124:6a4a5b7d7324	225
bogdanm	0:9b334a45a8ff	226	/* Reset HSEON, CSSON, & PLLON bits */
bogdanm	0:9b334a45a8ff	227	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON);
bogdanm	0:9b334a45a8ff	228
bogdanm	0:9b334a45a8ff	229	/* Reset HSEBYP bit */
bogdanm	0:9b334a45a8ff	230	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/* Reset CFGR register */
bogdanm	0:9b334a45a8ff	233	CLEAR_REG(RCC->CFGR);
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	/* Set HSITRIM bits to the reset value */
bogdanm	0:9b334a45a8ff	236	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
bogdanm	0:9b334a45a8ff	237
mbed_official	124:6a4a5b7d7324	238	#if (defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE))
mbed_official	124:6a4a5b7d7324	239	/* Reset CFGR2 register */
mbed_official	124:6a4a5b7d7324	240	CLEAR_REG(RCC->CFGR2);
mbed_official	124:6a4a5b7d7324	241
mbed_official	124:6a4a5b7d7324	242	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
bogdanm	0:9b334a45a8ff	243	/* Disable all interrupts */
bogdanm	0:9b334a45a8ff	244	CLEAR_REG(RCC->CIR);
mbed_official	124:6a4a5b7d7324	245
mbed_official	124:6a4a5b7d7324	246	/* Update the SystemCoreClock global variable */
mbed_official	124:6a4a5b7d7324	247	SystemCoreClock = HSI_VALUE;
bogdanm	0:9b334a45a8ff	248	}
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/**
bogdanm	0:9b334a45a8ff	251	* @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm	0:9b334a45a8ff	252	* RCC_OscInitTypeDef.
mbed_official	124:6a4a5b7d7324	253	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	254	* contains the configuration information for the RCC Oscillators.
bogdanm	0:9b334a45a8ff	255	* @note The PLL is not disabled when used as system clock.
bogdanm	0:9b334a45a8ff	256	* @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
mbed_official	124:6a4a5b7d7324	257	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
mbed_official	124:6a4a5b7d7324	258	* supported by this macro. User should request a transition to LSE Off
mbed_official	124:6a4a5b7d7324	259	* first and then LSE On or LSE Bypass.
mbed_official	124:6a4a5b7d7324	260	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
mbed_official	124:6a4a5b7d7324	261	* supported by this macro. User should request a transition to HSE Off
mbed_official	124:6a4a5b7d7324	262	* first and then HSE On or HSE Bypass.
bogdanm	0:9b334a45a8ff	263	* @retval HAL status
bogdanm	0:9b334a45a8ff	264	*/
mbed_official	124:6a4a5b7d7324	265	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	266	{
bogdanm	0:9b334a45a8ff	267	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	268
bogdanm	0:9b334a45a8ff	269	/* Check the parameters */
bogdanm	0:9b334a45a8ff	270	assert_param(RCC_OscInitStruct != NULL);
bogdanm	0:9b334a45a8ff	271	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/------------------------------- HSE Configuration ------------------------/
bogdanm	0:9b334a45a8ff	274	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm	0:9b334a45a8ff	275	{
bogdanm	0:9b334a45a8ff	276	/* Check the parameters */
bogdanm	0:9b334a45a8ff	277	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
bogdanm	0:9b334a45a8ff	280	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm	0:9b334a45a8ff	281	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
bogdanm	0:9b334a45a8ff	282	{
mbed_official	124:6a4a5b7d7324	283	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
bogdanm	0:9b334a45a8ff	284	{
bogdanm	0:9b334a45a8ff	285	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	286	}
bogdanm	0:9b334a45a8ff	287	}
bogdanm	0:9b334a45a8ff	288	else
bogdanm	0:9b334a45a8ff	289	{
bogdanm	0:9b334a45a8ff	290	/* Set the new HSE configuration ---------------------------------------*/
bogdanm	0:9b334a45a8ff	291	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm	0:9b334a45a8ff	292
mbed_official	124:6a4a5b7d7324	293
mbed_official	124:6a4a5b7d7324	294	/* Check the HSE State */
bogdanm	0:9b334a45a8ff	295	if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
bogdanm	0:9b334a45a8ff	296	{
mbed_official	124:6a4a5b7d7324	297	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	298	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	299
mbed_official	124:6a4a5b7d7324	300	/* Wait till HSE is ready */
bogdanm	0:9b334a45a8ff	301	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	302	{
bogdanm	0:9b334a45a8ff	303	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	304	{
bogdanm	0:9b334a45a8ff	305	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	306	}
bogdanm	0:9b334a45a8ff	307	}
bogdanm	0:9b334a45a8ff	308	}
bogdanm	0:9b334a45a8ff	309	else
bogdanm	0:9b334a45a8ff	310	{
mbed_official	124:6a4a5b7d7324	311	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	312	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	/* Wait till HSE is disabled */
bogdanm	0:9b334a45a8ff	315	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm	0:9b334a45a8ff	316	{
bogdanm	0:9b334a45a8ff	317	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	318	{
bogdanm	0:9b334a45a8ff	319	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	320	}
bogdanm	0:9b334a45a8ff	321	}
bogdanm	0:9b334a45a8ff	322	}
bogdanm	0:9b334a45a8ff	323	}
bogdanm	0:9b334a45a8ff	324	}
bogdanm	0:9b334a45a8ff	325	/----------------------------- HSI Configuration --------------------------/
bogdanm	0:9b334a45a8ff	326	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm	0:9b334a45a8ff	327	{
bogdanm	0:9b334a45a8ff	328	/* Check the parameters */
bogdanm	0:9b334a45a8ff	329	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm	0:9b334a45a8ff	330	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm	0:9b334a45a8ff	331
bogdanm	0:9b334a45a8ff	332	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm	0:9b334a45a8ff	333	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm	0:9b334a45a8ff	334	\|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
bogdanm	0:9b334a45a8ff	335	{
bogdanm	0:9b334a45a8ff	336	/* When HSI is used as system clock it will not disabled */
bogdanm	0:9b334a45a8ff	337	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	338	{
bogdanm	0:9b334a45a8ff	339	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341	/* Otherwise, just the calibration is allowed */
bogdanm	0:9b334a45a8ff	342	else
bogdanm	0:9b334a45a8ff	343	{
bogdanm	0:9b334a45a8ff	344	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	345	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	346	}
bogdanm	0:9b334a45a8ff	347	}
bogdanm	0:9b334a45a8ff	348	else
bogdanm	0:9b334a45a8ff	349	{
bogdanm	0:9b334a45a8ff	350	/* Check the HSI State */
mbed_official	124:6a4a5b7d7324	351	if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
bogdanm	0:9b334a45a8ff	352	{
mbed_official	124:6a4a5b7d7324	353	/* Enable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	354	__HAL_RCC_HSI_ENABLE();
bogdanm	0:9b334a45a8ff	355
mbed_official	124:6a4a5b7d7324	356	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	357	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	358
mbed_official	124:6a4a5b7d7324	359	/* Wait till HSI is ready */
bogdanm	0:9b334a45a8ff	360	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	361	{
bogdanm	0:9b334a45a8ff	362	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	363	{
bogdanm	0:9b334a45a8ff	364	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	365	}
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm	0:9b334a45a8ff	369	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm	0:9b334a45a8ff	370	}
bogdanm	0:9b334a45a8ff	371	else
bogdanm	0:9b334a45a8ff	372	{
bogdanm	0:9b334a45a8ff	373	/* Disable the Internal High Speed oscillator (HSI). */
bogdanm	0:9b334a45a8ff	374	__HAL_RCC_HSI_DISABLE();
bogdanm	0:9b334a45a8ff	375
mbed_official	124:6a4a5b7d7324	376	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	377	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	378
mbed_official	124:6a4a5b7d7324	379	/* Wait till HSI is disabled */
bogdanm	0:9b334a45a8ff	380	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	381	{
bogdanm	0:9b334a45a8ff	382	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	383	{
bogdanm	0:9b334a45a8ff	384	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	385	}
bogdanm	0:9b334a45a8ff	386	}
bogdanm	0:9b334a45a8ff	387	}
bogdanm	0:9b334a45a8ff	388	}
bogdanm	0:9b334a45a8ff	389	}
bogdanm	0:9b334a45a8ff	390	/------------------------------ LSI Configuration -------------------------/
bogdanm	0:9b334a45a8ff	391	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm	0:9b334a45a8ff	392	{
bogdanm	0:9b334a45a8ff	393	/* Check the parameters */
bogdanm	0:9b334a45a8ff	394	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm	0:9b334a45a8ff	395
bogdanm	0:9b334a45a8ff	396	/* Check the LSI State */
mbed_official	124:6a4a5b7d7324	397	if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
bogdanm	0:9b334a45a8ff	398	{
bogdanm	0:9b334a45a8ff	399	/* Enable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	400	__HAL_RCC_LSI_ENABLE();
bogdanm	0:9b334a45a8ff	401
mbed_official	124:6a4a5b7d7324	402	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	403	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	404
bogdanm	0:9b334a45a8ff	405	/* Wait till LSI is ready */
bogdanm	0:9b334a45a8ff	406	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	407	{
bogdanm	0:9b334a45a8ff	408	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	409	{
bogdanm	0:9b334a45a8ff	410	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	411	}
bogdanm	0:9b334a45a8ff	412	}
mbed_official	124:6a4a5b7d7324	413	/* To have a fully stabilized clock in the specified range, a software delay of 1ms
bogdanm	0:9b334a45a8ff	414	should be added.*/
bogdanm	0:9b334a45a8ff	415	HAL_Delay(1);
bogdanm	0:9b334a45a8ff	416	}
bogdanm	0:9b334a45a8ff	417	else
bogdanm	0:9b334a45a8ff	418	{
bogdanm	0:9b334a45a8ff	419	/* Disable the Internal Low Speed oscillator (LSI). */
bogdanm	0:9b334a45a8ff	420	__HAL_RCC_LSI_DISABLE();
bogdanm	0:9b334a45a8ff	421
mbed_official	124:6a4a5b7d7324	422	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	423	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425	/* Wait till LSI is disabled */
bogdanm	0:9b334a45a8ff	426	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm	0:9b334a45a8ff	427	{
bogdanm	0:9b334a45a8ff	428	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	429	{
bogdanm	0:9b334a45a8ff	430	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	431	}
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433	}
bogdanm	0:9b334a45a8ff	434	}
bogdanm	0:9b334a45a8ff	435	/------------------------------ LSE Configuration -------------------------/
bogdanm	0:9b334a45a8ff	436	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm	0:9b334a45a8ff	437	{
bogdanm	0:9b334a45a8ff	438	/* Check the parameters */
bogdanm	0:9b334a45a8ff	439	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm	0:9b334a45a8ff	440
mbed_official	124:6a4a5b7d7324	441	/* Enable Power Clock*/
mbed_official	124:6a4a5b7d7324	442	__HAL_RCC_PWR_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	443
mbed_official	124:6a4a5b7d7324	444	/* Enable write access to Backup domain */
mbed_official	124:6a4a5b7d7324	445	SET_BIT(PWR->CR, PWR_CR_DBP);
mbed_official	124:6a4a5b7d7324	446
mbed_official	124:6a4a5b7d7324	447	/* Wait for Backup domain Write protection disable */
mbed_official	124:6a4a5b7d7324	448	tickstart = HAL_GetTick();
mbed_official	124:6a4a5b7d7324	449
bogdanm	0:9b334a45a8ff	450	while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm	0:9b334a45a8ff	451	{
mbed_official	124:6a4a5b7d7324	452	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	124:6a4a5b7d7324	453	{
mbed_official	124:6a4a5b7d7324	454	return HAL_TIMEOUT;
mbed_official	124:6a4a5b7d7324	455	}
bogdanm	0:9b334a45a8ff	456	}
mbed_official	124:6a4a5b7d7324	457
bogdanm	0:9b334a45a8ff	458	/* Set the new LSE configuration -----------------------------------------*/
bogdanm	0:9b334a45a8ff	459	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm	0:9b334a45a8ff	460	/* Check the LSE State */
mbed_official	124:6a4a5b7d7324	461	if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
bogdanm	0:9b334a45a8ff	462	{
mbed_official	124:6a4a5b7d7324	463	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	464	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/* Wait till LSE is ready */
bogdanm	0:9b334a45a8ff	467	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm	0:9b334a45a8ff	468	{
bogdanm	0:9b334a45a8ff	469	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	470	{
bogdanm	0:9b334a45a8ff	471	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	472	}
bogdanm	0:9b334a45a8ff	473	}
bogdanm	0:9b334a45a8ff	474	}
bogdanm	0:9b334a45a8ff	475	else
bogdanm	0:9b334a45a8ff	476	{
mbed_official	124:6a4a5b7d7324	477	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	478	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	/* Wait till LSE is disabled */
bogdanm	0:9b334a45a8ff	481	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm	0:9b334a45a8ff	482	{
bogdanm	0:9b334a45a8ff	483	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	484	{
bogdanm	0:9b334a45a8ff	485	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	486	}
bogdanm	0:9b334a45a8ff	487	}
bogdanm	0:9b334a45a8ff	488	}
bogdanm	0:9b334a45a8ff	489	}
bogdanm	0:9b334a45a8ff	490
mbed_official	124:6a4a5b7d7324	491	#if defined(RCC_CR_PLL2ON)
mbed_official	124:6a4a5b7d7324	492	/-------------------------------- PLL2 Configuration -----------------------/
mbed_official	124:6a4a5b7d7324	493	/* Check the parameters */
mbed_official	124:6a4a5b7d7324	494	assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
mbed_official	124:6a4a5b7d7324	495	if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
mbed_official	124:6a4a5b7d7324	496	{
mbed_official	124:6a4a5b7d7324	497	/* This bit can not be cleared if the PLL2 clock is used indirectly as system
mbed_official	124:6a4a5b7d7324	498	clock (i.e. it is used as PLL clock entry that is used as system clock). */
mbed_official	124:6a4a5b7d7324	499	if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
mbed_official	124:6a4a5b7d7324	500	(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
mbed_official	124:6a4a5b7d7324	501	((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
mbed_official	124:6a4a5b7d7324	502	{
mbed_official	124:6a4a5b7d7324	503	return HAL_ERROR;
mbed_official	124:6a4a5b7d7324	504	}
mbed_official	124:6a4a5b7d7324	505	else
mbed_official	124:6a4a5b7d7324	506	{
mbed_official	124:6a4a5b7d7324	507	if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
mbed_official	124:6a4a5b7d7324	508	{
mbed_official	124:6a4a5b7d7324	509	/* Check the parameters */
mbed_official	124:6a4a5b7d7324	510	assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
mbed_official	124:6a4a5b7d7324	511	assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
mbed_official	124:6a4a5b7d7324	512
mbed_official	124:6a4a5b7d7324	513	/* Prediv2 can be written only when the PLLI2S is disabled. */
mbed_official	124:6a4a5b7d7324	514	/* Return an error only if new value is different from the programmed value */
mbed_official	124:6a4a5b7d7324	515	if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
mbed_official	124:6a4a5b7d7324	516	(__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
mbed_official	124:6a4a5b7d7324	517	{
mbed_official	124:6a4a5b7d7324	518	return HAL_ERROR;
mbed_official	124:6a4a5b7d7324	519	}
mbed_official	124:6a4a5b7d7324	520
mbed_official	124:6a4a5b7d7324	521	/* Disable the main PLL2. */
mbed_official	124:6a4a5b7d7324	522	__HAL_RCC_PLL2_DISABLE();
mbed_official	124:6a4a5b7d7324	523
mbed_official	124:6a4a5b7d7324	524	/* Get Start Tick */
mbed_official	124:6a4a5b7d7324	525	tickstart = HAL_GetTick();
mbed_official	124:6a4a5b7d7324	526
mbed_official	124:6a4a5b7d7324	527	/* Wait till PLL2 is disabled */
mbed_official	124:6a4a5b7d7324	528	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
mbed_official	124:6a4a5b7d7324	529	{
mbed_official	124:6a4a5b7d7324	530	if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official	124:6a4a5b7d7324	531	{
mbed_official	124:6a4a5b7d7324	532	return HAL_TIMEOUT;
mbed_official	124:6a4a5b7d7324	533	}
mbed_official	124:6a4a5b7d7324	534	}
mbed_official	124:6a4a5b7d7324	535
mbed_official	124:6a4a5b7d7324	536	/* Configure the HSE prediv2 factor --------------------------------*/
mbed_official	124:6a4a5b7d7324	537	__HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
mbed_official	124:6a4a5b7d7324	538
mbed_official	124:6a4a5b7d7324	539	/* Configure the main PLL2 multiplication factors. */
mbed_official	124:6a4a5b7d7324	540	__HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
mbed_official	124:6a4a5b7d7324	541
mbed_official	124:6a4a5b7d7324	542	/* Enable the main PLL2. */
mbed_official	124:6a4a5b7d7324	543	__HAL_RCC_PLL2_ENABLE();
mbed_official	124:6a4a5b7d7324	544
mbed_official	124:6a4a5b7d7324	545	/* Get Start Tick */
mbed_official	124:6a4a5b7d7324	546	tickstart = HAL_GetTick();
mbed_official	124:6a4a5b7d7324	547
mbed_official	124:6a4a5b7d7324	548	/* Wait till PLL2 is ready */
mbed_official	124:6a4a5b7d7324	549	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
mbed_official	124:6a4a5b7d7324	550	{
mbed_official	124:6a4a5b7d7324	551	if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official	124:6a4a5b7d7324	552	{
mbed_official	124:6a4a5b7d7324	553	return HAL_TIMEOUT;
mbed_official	124:6a4a5b7d7324	554	}
mbed_official	124:6a4a5b7d7324	555	}
mbed_official	124:6a4a5b7d7324	556	}
mbed_official	124:6a4a5b7d7324	557	else
mbed_official	124:6a4a5b7d7324	558	{
mbed_official	124:6a4a5b7d7324	559	/* Set PREDIV1 source to HSE */
mbed_official	124:6a4a5b7d7324	560	CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
mbed_official	124:6a4a5b7d7324	561
mbed_official	124:6a4a5b7d7324	562	/* Disable the main PLL2. */
mbed_official	124:6a4a5b7d7324	563	__HAL_RCC_PLL2_DISABLE();
mbed_official	124:6a4a5b7d7324	564
mbed_official	124:6a4a5b7d7324	565	/* Get Start Tick */
mbed_official	124:6a4a5b7d7324	566	tickstart = HAL_GetTick();
mbed_official	124:6a4a5b7d7324	567
mbed_official	124:6a4a5b7d7324	568	/* Wait till PLL2 is disabled */
mbed_official	124:6a4a5b7d7324	569	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
mbed_official	124:6a4a5b7d7324	570	{
mbed_official	124:6a4a5b7d7324	571	if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official	124:6a4a5b7d7324	572	{
mbed_official	124:6a4a5b7d7324	573	return HAL_TIMEOUT;
mbed_official	124:6a4a5b7d7324	574	}
mbed_official	124:6a4a5b7d7324	575	}
mbed_official	124:6a4a5b7d7324	576	}
mbed_official	124:6a4a5b7d7324	577	}
mbed_official	124:6a4a5b7d7324	578	}
mbed_official	124:6a4a5b7d7324	579
mbed_official	124:6a4a5b7d7324	580	#endif /* RCC_CR_PLL2ON */
bogdanm	0:9b334a45a8ff	581	/-------------------------------- PLL Configuration -----------------------/
bogdanm	0:9b334a45a8ff	582	/* Check the parameters */
bogdanm	0:9b334a45a8ff	583	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm	0:9b334a45a8ff	584	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm	0:9b334a45a8ff	585	{
bogdanm	0:9b334a45a8ff	586	/* Check if the PLL is used as system clock or not */
bogdanm	0:9b334a45a8ff	587	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm	0:9b334a45a8ff	588	{
bogdanm	0:9b334a45a8ff	589	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm	0:9b334a45a8ff	590	{
bogdanm	0:9b334a45a8ff	591	/* Check the parameters */
bogdanm	0:9b334a45a8ff	592	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm	0:9b334a45a8ff	593	assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
mbed_official	124:6a4a5b7d7324	594
bogdanm	0:9b334a45a8ff	595	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	596	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	597
mbed_official	124:6a4a5b7d7324	598	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	599	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	600
mbed_official	124:6a4a5b7d7324	601	/* Wait till PLL is disabled */
bogdanm	0:9b334a45a8ff	602	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	603	{
bogdanm	0:9b334a45a8ff	604	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	605	{
bogdanm	0:9b334a45a8ff	606	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	607	}
bogdanm	0:9b334a45a8ff	608	}
mbed_official	124:6a4a5b7d7324	609
mbed_official	124:6a4a5b7d7324	610	/* Configure the HSE prediv factor --------------------------------*/
bogdanm	0:9b334a45a8ff	611	/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
bogdanm	0:9b334a45a8ff	612	if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
bogdanm	0:9b334a45a8ff	613	{
mbed_official	124:6a4a5b7d7324	614	/* Check the parameter */
bogdanm	0:9b334a45a8ff	615	assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
mbed_official	124:6a4a5b7d7324	616	#if defined(RCC_CFGR2_PREDIV1SRC)
mbed_official	124:6a4a5b7d7324	617	assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
bogdanm	0:9b334a45a8ff	618
mbed_official	124:6a4a5b7d7324	619	/* Set PREDIV1 source */
mbed_official	124:6a4a5b7d7324	620	SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
mbed_official	124:6a4a5b7d7324	621	#endif /* RCC_CFGR2_PREDIV1SRC */
mbed_official	124:6a4a5b7d7324	622
mbed_official	124:6a4a5b7d7324	623	/* Set PREDIV1 Value */
bogdanm	0:9b334a45a8ff	624	__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
bogdanm	0:9b334a45a8ff	625	}
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	/* Configure the main PLL clock source and multiplication factors. */
bogdanm	0:9b334a45a8ff	628	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm	0:9b334a45a8ff	629	RCC_OscInitStruct->PLL.PLLMUL);
bogdanm	0:9b334a45a8ff	630	/* Enable the main PLL. */
bogdanm	0:9b334a45a8ff	631	__HAL_RCC_PLL_ENABLE();
bogdanm	0:9b334a45a8ff	632
mbed_official	124:6a4a5b7d7324	633	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	634	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	/* Wait till PLL is ready */
bogdanm	0:9b334a45a8ff	637	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	638	{
bogdanm	0:9b334a45a8ff	639	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	640	{
bogdanm	0:9b334a45a8ff	641	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643	}
bogdanm	0:9b334a45a8ff	644	}
bogdanm	0:9b334a45a8ff	645	else
bogdanm	0:9b334a45a8ff	646	{
bogdanm	0:9b334a45a8ff	647	/* Disable the main PLL. */
bogdanm	0:9b334a45a8ff	648	__HAL_RCC_PLL_DISABLE();
bogdanm	0:9b334a45a8ff	649
mbed_official	124:6a4a5b7d7324	650	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	651	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	652
bogdanm	0:9b334a45a8ff	653	/* Wait till PLL is disabled */
bogdanm	0:9b334a45a8ff	654	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm	0:9b334a45a8ff	655	{
bogdanm	0:9b334a45a8ff	656	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	657	{
bogdanm	0:9b334a45a8ff	658	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	659	}
bogdanm	0:9b334a45a8ff	660	}
bogdanm	0:9b334a45a8ff	661	}
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663	else
bogdanm	0:9b334a45a8ff	664	{
bogdanm	0:9b334a45a8ff	665	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	666	}
bogdanm	0:9b334a45a8ff	667	}
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	return HAL_OK;
bogdanm	0:9b334a45a8ff	670	}
bogdanm	0:9b334a45a8ff	671
bogdanm	0:9b334a45a8ff	672	/**
mbed_official	124:6a4a5b7d7324	673	* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
bogdanm	0:9b334a45a8ff	674	* parameters in the RCC_ClkInitStruct.
mbed_official	124:6a4a5b7d7324	675	* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	676	* contains the configuration information for the RCC peripheral.
mbed_official	124:6a4a5b7d7324	677	* @param FLatency FLASH Latency
mbed_official	124:6a4a5b7d7324	678	* The value of this parameter depend on device used within the same series
bogdanm	0:9b334a45a8ff	679	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	124:6a4a5b7d7324	680	* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
bogdanm	0:9b334a45a8ff	681	*
bogdanm	0:9b334a45a8ff	682	* @note The HSI is used (enabled by hardware) as system clock source after
mbed_official	124:6a4a5b7d7324	683	* start-up from Reset, wake-up from STOP and STANDBY mode, or in case
bogdanm	0:9b334a45a8ff	684	* of failure of the HSE used directly or indirectly as system clock
bogdanm	0:9b334a45a8ff	685	* (if the Clock Security System CSS is enabled).
bogdanm	0:9b334a45a8ff	686	*
bogdanm	0:9b334a45a8ff	687	* @note A switch from one clock source to another occurs only if the target
mbed_official	124:6a4a5b7d7324	688	* clock source is ready (clock stable after start-up delay or PLL locked).
bogdanm	0:9b334a45a8ff	689	* If a clock source which is not yet ready is selected, the switch will
bogdanm	0:9b334a45a8ff	690	* occur when the clock source will be ready.
mbed_official	124:6a4a5b7d7324	691	* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
bogdanm	0:9b334a45a8ff	692	* currently used as system clock source.
mbed_official	124:6a4a5b7d7324	693	* @retval HAL status
bogdanm	0:9b334a45a8ff	694	*/
mbed_official	124:6a4a5b7d7324	695	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
bogdanm	0:9b334a45a8ff	696	{
bogdanm	0:9b334a45a8ff	697	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699	/* Check the parameters */
bogdanm	0:9b334a45a8ff	700	assert_param(RCC_ClkInitStruct != NULL);
bogdanm	0:9b334a45a8ff	701	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
bogdanm	0:9b334a45a8ff	702	assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official	124:6a4a5b7d7324	703
bogdanm	0:9b334a45a8ff	704	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
bogdanm	0:9b334a45a8ff	705	must be correctly programmed according to the frequency of the CPU clock
bogdanm	0:9b334a45a8ff	706	(HCLK) of the device. */
bogdanm	0:9b334a45a8ff	707
mbed_official	124:6a4a5b7d7324	708	#if defined(FLASH_ACR_LATENCY)
mbed_official	124:6a4a5b7d7324	709	/* Increasing the number of wait states because of higher CPU frequency */
mbed_official	124:6a4a5b7d7324	710	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official	124:6a4a5b7d7324	711	{
mbed_official	124:6a4a5b7d7324	712	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	124:6a4a5b7d7324	713	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	124:6a4a5b7d7324	714
mbed_official	124:6a4a5b7d7324	715	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	124:6a4a5b7d7324	716	memory by reading the FLASH_ACR register */
mbed_official	124:6a4a5b7d7324	717	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	124:6a4a5b7d7324	718	{
mbed_official	124:6a4a5b7d7324	719	return HAL_ERROR;
mbed_official	124:6a4a5b7d7324	720	}
mbed_official	124:6a4a5b7d7324	721	}
mbed_official	124:6a4a5b7d7324	722
mbed_official	124:6a4a5b7d7324	723	#endif /* FLASH_ACR_LATENCY */
bogdanm	0:9b334a45a8ff	724	/-------------------------- HCLK Configuration --------------------------/
bogdanm	0:9b334a45a8ff	725	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm	0:9b334a45a8ff	726	{
bogdanm	0:9b334a45a8ff	727	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm	0:9b334a45a8ff	728	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm	0:9b334a45a8ff	729	}
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	/------------------------- SYSCLK Configuration ---------------------------/
bogdanm	0:9b334a45a8ff	732	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm	0:9b334a45a8ff	733	{
bogdanm	0:9b334a45a8ff	734	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/* HSE is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	737	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm	0:9b334a45a8ff	738	{
bogdanm	0:9b334a45a8ff	739	/* Check the HSE ready flag */
bogdanm	0:9b334a45a8ff	740	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	743	}
bogdanm	0:9b334a45a8ff	744	}
bogdanm	0:9b334a45a8ff	745	/* PLL is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	746	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm	0:9b334a45a8ff	747	{
bogdanm	0:9b334a45a8ff	748	/* Check the PLL ready flag */
bogdanm	0:9b334a45a8ff	749	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm	0:9b334a45a8ff	750	{
bogdanm	0:9b334a45a8ff	751	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	752	}
bogdanm	0:9b334a45a8ff	753	}
bogdanm	0:9b334a45a8ff	754	/* HSI is selected as System Clock Source */
bogdanm	0:9b334a45a8ff	755	else
bogdanm	0:9b334a45a8ff	756	{
bogdanm	0:9b334a45a8ff	757	/* Check the HSI ready flag */
bogdanm	0:9b334a45a8ff	758	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	761	}
bogdanm	0:9b334a45a8ff	762	}
mbed_official	124:6a4a5b7d7324	763	__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
bogdanm	0:9b334a45a8ff	764
mbed_official	124:6a4a5b7d7324	765	/* Get Start Tick */
bogdanm	0:9b334a45a8ff	766	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	767
bogdanm	0:9b334a45a8ff	768	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm	0:9b334a45a8ff	769	{
bogdanm	0:9b334a45a8ff	770	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	773	{
bogdanm	0:9b334a45a8ff	774	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	775	}
bogdanm	0:9b334a45a8ff	776	}
bogdanm	0:9b334a45a8ff	777	}
bogdanm	0:9b334a45a8ff	778	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm	0:9b334a45a8ff	779	{
bogdanm	0:9b334a45a8ff	780	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm	0:9b334a45a8ff	781	{
bogdanm	0:9b334a45a8ff	782	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	783	{
bogdanm	0:9b334a45a8ff	784	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	785	}
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787	}
bogdanm	0:9b334a45a8ff	788	else
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm	0:9b334a45a8ff	791	{
bogdanm	0:9b334a45a8ff	792	if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	795	}
bogdanm	0:9b334a45a8ff	796	}
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798	}
mbed_official	124:6a4a5b7d7324	799	#if defined(FLASH_ACR_LATENCY)
mbed_official	124:6a4a5b7d7324	800	/* Decreasing the number of wait states because of lower CPU frequency */
mbed_official	124:6a4a5b7d7324	801	if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official	124:6a4a5b7d7324	802	{
mbed_official	124:6a4a5b7d7324	803	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	124:6a4a5b7d7324	804	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	124:6a4a5b7d7324	805
mbed_official	124:6a4a5b7d7324	806	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	124:6a4a5b7d7324	807	memory by reading the FLASH_ACR register */
mbed_official	124:6a4a5b7d7324	808	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	124:6a4a5b7d7324	809	{
mbed_official	124:6a4a5b7d7324	810	return HAL_ERROR;
mbed_official	124:6a4a5b7d7324	811	}
mbed_official	124:6a4a5b7d7324	812	}
mbed_official	124:6a4a5b7d7324	813	#endif /* FLASH_ACR_LATENCY */
mbed_official	124:6a4a5b7d7324	814
bogdanm	0:9b334a45a8ff	815	/-------------------------- PCLK1 Configuration ---------------------------/
bogdanm	0:9b334a45a8ff	816	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
bogdanm	0:9b334a45a8ff	817	{
bogdanm	0:9b334a45a8ff	818	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
bogdanm	0:9b334a45a8ff	819	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
bogdanm	0:9b334a45a8ff	820	}
bogdanm	0:9b334a45a8ff	821
bogdanm	0:9b334a45a8ff	822	/-------------------------- PCLK2 Configuration ---------------------------/
bogdanm	0:9b334a45a8ff	823	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
bogdanm	0:9b334a45a8ff	824	{
bogdanm	0:9b334a45a8ff	825	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
bogdanm	0:9b334a45a8ff	826	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
bogdanm	0:9b334a45a8ff	827	}
mbed_official	124:6a4a5b7d7324	828
mbed_official	124:6a4a5b7d7324	829	/* Update the SystemCoreClock global variable */
mbed_official	124:6a4a5b7d7324	830	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
mbed_official	124:6a4a5b7d7324	831
bogdanm	0:9b334a45a8ff	832	/* Configure the source of time base considering new system clocks settings*/
bogdanm	0:9b334a45a8ff	833	HAL_InitTick (TICK_INT_PRIORITY);
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	return HAL_OK;
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837
bogdanm	0:9b334a45a8ff	838	/**
bogdanm	0:9b334a45a8ff	839	* @}
bogdanm	0:9b334a45a8ff	840	*/
bogdanm	0:9b334a45a8ff	841
mbed_official	124:6a4a5b7d7324	842	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
mbed_official	124:6a4a5b7d7324	843	* @brief RCC clocks control functions
bogdanm	0:9b334a45a8ff	844	*
bogdanm	0:9b334a45a8ff	845	@verbatim
bogdanm	0:9b334a45a8ff	846	===============================================================================
bogdanm	0:9b334a45a8ff	847	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	848	===============================================================================
bogdanm	0:9b334a45a8ff	849	[..]
bogdanm	0:9b334a45a8ff	850	This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm	0:9b334a45a8ff	851	frequencies.
bogdanm	0:9b334a45a8ff	852
bogdanm	0:9b334a45a8ff	853	@endverbatim
bogdanm	0:9b334a45a8ff	854	* @{
bogdanm	0:9b334a45a8ff	855	*/
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/**
bogdanm	0:9b334a45a8ff	858	* @brief Selects the clock source to output on MCO pin.
bogdanm	0:9b334a45a8ff	859	* @note MCO pin should be configured in alternate function mode.
mbed_official	124:6a4a5b7d7324	860	* @param RCC_MCOx specifies the output direction for the clock source.
bogdanm	0:9b334a45a8ff	861	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	862	* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
mbed_official	124:6a4a5b7d7324	863	* @param RCC_MCOSource specifies the clock source to output.
bogdanm	0:9b334a45a8ff	864	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	865	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
mbed_official	124:6a4a5b7d7324	866	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
mbed_official	124:6a4a5b7d7324	867	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
mbed_official	124:6a4a5b7d7324	868	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
mbed_official	124:6a4a5b7d7324	869	@if STM32F105xC
mbed_official	124:6a4a5b7d7324	870	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
mbed_official	124:6a4a5b7d7324	871	* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
mbed_official	124:6a4a5b7d7324	872	* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
mbed_official	124:6a4a5b7d7324	873	* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
mbed_official	124:6a4a5b7d7324	874	* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
mbed_official	124:6a4a5b7d7324	875	@endif
mbed_official	124:6a4a5b7d7324	876	@if STM32F107xC
mbed_official	124:6a4a5b7d7324	877	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
mbed_official	124:6a4a5b7d7324	878	* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
mbed_official	124:6a4a5b7d7324	879	* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
mbed_official	124:6a4a5b7d7324	880	* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
mbed_official	124:6a4a5b7d7324	881	* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
mbed_official	124:6a4a5b7d7324	882	@endif
mbed_official	124:6a4a5b7d7324	883	* @param RCC_MCODiv specifies the MCO DIV.
bogdanm	0:9b334a45a8ff	884	* This parameter can be one of the following values:
mbed_official	124:6a4a5b7d7324	885	* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
bogdanm	0:9b334a45a8ff	886	* @retval None
bogdanm	0:9b334a45a8ff	887	*/
bogdanm	0:9b334a45a8ff	888	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
bogdanm	0:9b334a45a8ff	889	{
mbed_official	124:6a4a5b7d7324	890	GPIO_InitTypeDef gpio = {0};
mbed_official	124:6a4a5b7d7324	891
bogdanm	0:9b334a45a8ff	892	/* Check the parameters */
bogdanm	0:9b334a45a8ff	893	assert_param(IS_RCC_MCO(RCC_MCOx));
bogdanm	0:9b334a45a8ff	894	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
bogdanm	0:9b334a45a8ff	895	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
bogdanm	0:9b334a45a8ff	896
mbed_official	124:6a4a5b7d7324	897	/* Configure the MCO1 pin in alternate function mode */
mbed_official	124:6a4a5b7d7324	898	gpio.Mode = GPIO_MODE_AF_PP;
mbed_official	124:6a4a5b7d7324	899	gpio.Speed = GPIO_SPEED_FREQ_HIGH;
mbed_official	124:6a4a5b7d7324	900	gpio.Pull = GPIO_NOPULL;
mbed_official	124:6a4a5b7d7324	901	gpio.Pin = MCO1_PIN;
mbed_official	124:6a4a5b7d7324	902
mbed_official	124:6a4a5b7d7324	903	/* MCO1 Clock Enable */
bogdanm	0:9b334a45a8ff	904	MCO1_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
bogdanm	0:9b334a45a8ff	907
mbed_official	124:6a4a5b7d7324	908	/* Configure the MCO clock source */
mbed_official	124:6a4a5b7d7324	909	__HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
bogdanm	0:9b334a45a8ff	910	}
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912	/**
bogdanm	0:9b334a45a8ff	913	* @brief Enables the Clock Security System.
bogdanm	0:9b334a45a8ff	914	* @note If a failure is detected on the HSE oscillator clock, this oscillator
bogdanm	0:9b334a45a8ff	915	* is automatically disabled and an interrupt is generated to inform the
bogdanm	0:9b334a45a8ff	916	* software about the failure (Clock Security System Interrupt, CSSI),
bogdanm	0:9b334a45a8ff	917	* allowing the MCU to perform rescue operations. The CSSI is linked to
bogdanm	0:9b334a45a8ff	918	* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
bogdanm	0:9b334a45a8ff	919	* @retval None
bogdanm	0:9b334a45a8ff	920	*/
bogdanm	0:9b334a45a8ff	921	void HAL_RCC_EnableCSS(void)
bogdanm	0:9b334a45a8ff	922	{
bogdanm	0:9b334a45a8ff	923	(__IO uint32_t ) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
bogdanm	0:9b334a45a8ff	924	}
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	/**
bogdanm	0:9b334a45a8ff	927	* @brief Disables the Clock Security System.
bogdanm	0:9b334a45a8ff	928	* @retval None
bogdanm	0:9b334a45a8ff	929	*/
bogdanm	0:9b334a45a8ff	930	void HAL_RCC_DisableCSS(void)
bogdanm	0:9b334a45a8ff	931	{
bogdanm	0:9b334a45a8ff	932	(__IO uint32_t ) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/**
bogdanm	0:9b334a45a8ff	936	* @brief Returns the SYSCLK frequency
bogdanm	0:9b334a45a8ff	937	* @note The system frequency computed by this function is not the real
bogdanm	0:9b334a45a8ff	938	* frequency in the chip. It is calculated based on the predefined
bogdanm	0:9b334a45a8ff	939	* constant and the selected clock source:
bogdanm	0:9b334a45a8ff	940	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official	124:6a4a5b7d7324	941	* @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
bogdanm	0:9b334a45a8ff	942	* divided by PREDIV factor(**)
mbed_official	124:6a4a5b7d7324	943	* @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
bogdanm	0:9b334a45a8ff	944	* divided by PREDIV factor(*) or HSI_VALUE() multiplied by the PLL factor.
bogdanm	0:9b334a45a8ff	945	* @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
mbed_official	124:6a4a5b7d7324	946	* 8 MHz) but the real value may vary depending on the variations
mbed_official	124:6a4a5b7d7324	947	* in voltage and temperature.
bogdanm	0:9b334a45a8ff	948	* @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
bogdanm	0:9b334a45a8ff	949	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm	0:9b334a45a8ff	950	* frequency of the crystal used. Otherwise, this function may
bogdanm	0:9b334a45a8ff	951	* have wrong result.
bogdanm	0:9b334a45a8ff	952	*
bogdanm	0:9b334a45a8ff	953	* @note The result of this function could be not correct when using fractional
bogdanm	0:9b334a45a8ff	954	* value for HSE crystal.
bogdanm	0:9b334a45a8ff	955	*
bogdanm	0:9b334a45a8ff	956	* @note This function can be used by the user application to compute the
mbed_official	124:6a4a5b7d7324	957	* baud-rate for the communication peripherals or configure other parameters.
bogdanm	0:9b334a45a8ff	958	*
bogdanm	0:9b334a45a8ff	959	* @note Each time SYSCLK changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	960	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	961	*
bogdanm	0:9b334a45a8ff	962	* @retval SYSCLK frequency
bogdanm	0:9b334a45a8ff	963	*/
mbed_official	124:6a4a5b7d7324	964	uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm	0:9b334a45a8ff	965	{
mbed_official	124:6a4a5b7d7324	966	#if defined(RCC_CFGR2_PREDIV1SRC)
mbed_official	124:6a4a5b7d7324	967	const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
mbed_official	124:6a4a5b7d7324	968	const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
mbed_official	124:6a4a5b7d7324	969	#else
bogdanm	0:9b334a45a8ff	970	const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
mbed_official	124:6a4a5b7d7324	971	#if defined(RCC_CFGR2_PREDIV1)
mbed_official	124:6a4a5b7d7324	972	const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
mbed_official	124:6a4a5b7d7324	973	#else
bogdanm	0:9b334a45a8ff	974	const uint8_t aPredivFactorTable[2] = { 1, 2};
mbed_official	124:6a4a5b7d7324	975	#endif /RCC_CFGR2_PREDIV1/
bogdanm	0:9b334a45a8ff	976
mbed_official	124:6a4a5b7d7324	977	#endif
mbed_official	124:6a4a5b7d7324	978	uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
bogdanm	0:9b334a45a8ff	979	uint32_t sysclockfreq = 0;
mbed_official	124:6a4a5b7d7324	980	#if defined(RCC_CFGR2_PREDIV1SRC)
mbed_official	124:6a4a5b7d7324	981	uint32_t prediv2 = 0, pll2mul = 0;
mbed_official	124:6a4a5b7d7324	982	#endif /RCC_CFGR2_PREDIV1SRC/
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	tmpreg = RCC->CFGR;
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/* Get SYSCLK source -------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	987	switch (tmpreg & RCC_CFGR_SWS)
bogdanm	0:9b334a45a8ff	988	{
mbed_official	124:6a4a5b7d7324	989	case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
bogdanm	0:9b334a45a8ff	990	{
bogdanm	0:9b334a45a8ff	991	sysclockfreq = HSE_VALUE;
bogdanm	0:9b334a45a8ff	992	break;
bogdanm	0:9b334a45a8ff	993	}
mbed_official	124:6a4a5b7d7324	994	case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
bogdanm	0:9b334a45a8ff	995	{
bogdanm	0:9b334a45a8ff	996	pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
bogdanm	0:9b334a45a8ff	997	if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
bogdanm	0:9b334a45a8ff	998	{
mbed_official	124:6a4a5b7d7324	999	#if defined(RCC_CFGR2_PREDIV1)
mbed_official	124:6a4a5b7d7324	1000	prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
mbed_official	124:6a4a5b7d7324	1001	#else
mbed_official	124:6a4a5b7d7324	1002	prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
mbed_official	124:6a4a5b7d7324	1003	#endif /RCC_CFGR2_PREDIV1/
mbed_official	124:6a4a5b7d7324	1004	#if defined(RCC_CFGR2_PREDIV1SRC)
mbed_official	124:6a4a5b7d7324	1005
mbed_official	124:6a4a5b7d7324	1006	if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
mbed_official	124:6a4a5b7d7324	1007	{
mbed_official	124:6a4a5b7d7324	1008	/* PLL2 selected as Prediv1 source */
mbed_official	124:6a4a5b7d7324	1009	/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
mbed_official	124:6a4a5b7d7324	1010	prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
mbed_official	124:6a4a5b7d7324	1011	pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
mbed_official	124:6a4a5b7d7324	1012	pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
mbed_official	124:6a4a5b7d7324	1013	}
mbed_official	124:6a4a5b7d7324	1014	else
mbed_official	124:6a4a5b7d7324	1015	{
mbed_official	124:6a4a5b7d7324	1016	/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
mbed_official	124:6a4a5b7d7324	1017	pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
mbed_official	124:6a4a5b7d7324	1018	}
mbed_official	124:6a4a5b7d7324	1019
mbed_official	124:6a4a5b7d7324	1020	/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
mbed_official	124:6a4a5b7d7324	1021	/* In this case need to divide pllclk by 2 */
mbed_official	124:6a4a5b7d7324	1022	if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
mbed_official	124:6a4a5b7d7324	1023	{
mbed_official	124:6a4a5b7d7324	1024	pllclk = pllclk / 2;
mbed_official	124:6a4a5b7d7324	1025	}
mbed_official	124:6a4a5b7d7324	1026	#else
bogdanm	0:9b334a45a8ff	1027	/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
mbed_official	124:6a4a5b7d7324	1028	pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
mbed_official	124:6a4a5b7d7324	1029	#endif /RCC_CFGR2_PREDIV1SRC/
bogdanm	0:9b334a45a8ff	1030	}
bogdanm	0:9b334a45a8ff	1031	else
bogdanm	0:9b334a45a8ff	1032	{
bogdanm	0:9b334a45a8ff	1033	/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm	0:9b334a45a8ff	1034	pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
bogdanm	0:9b334a45a8ff	1035	}
bogdanm	0:9b334a45a8ff	1036	sysclockfreq = pllclk;
bogdanm	0:9b334a45a8ff	1037	break;
bogdanm	0:9b334a45a8ff	1038	}
mbed_official	124:6a4a5b7d7324	1039	case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
mbed_official	124:6a4a5b7d7324	1040	default: /* HSI used as system clock */
bogdanm	0:9b334a45a8ff	1041	{
bogdanm	0:9b334a45a8ff	1042	sysclockfreq = HSI_VALUE;
bogdanm	0:9b334a45a8ff	1043	break;
bogdanm	0:9b334a45a8ff	1044	}
bogdanm	0:9b334a45a8ff	1045	}
bogdanm	0:9b334a45a8ff	1046	return sysclockfreq;
bogdanm	0:9b334a45a8ff	1047	}
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	/**
bogdanm	0:9b334a45a8ff	1050	* @brief Returns the HCLK frequency
bogdanm	0:9b334a45a8ff	1051	* @note Each time HCLK changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1052	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1053	*
bogdanm	0:9b334a45a8ff	1054	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm	0:9b334a45a8ff	1055	* and updated within this function
bogdanm	0:9b334a45a8ff	1056	* @retval HCLK frequency
bogdanm	0:9b334a45a8ff	1057	*/
bogdanm	0:9b334a45a8ff	1058	uint32_t HAL_RCC_GetHCLKFreq(void)
bogdanm	0:9b334a45a8ff	1059	{
bogdanm	0:9b334a45a8ff	1060	return SystemCoreClock;
bogdanm	0:9b334a45a8ff	1061	}
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/**
bogdanm	0:9b334a45a8ff	1064	* @brief Returns the PCLK1 frequency
bogdanm	0:9b334a45a8ff	1065	* @note Each time PCLK1 changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1066	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1067	* @retval PCLK1 frequency
bogdanm	0:9b334a45a8ff	1068	*/
bogdanm	0:9b334a45a8ff	1069	uint32_t HAL_RCC_GetPCLK1Freq(void)
bogdanm	0:9b334a45a8ff	1070	{
bogdanm	0:9b334a45a8ff	1071	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official	124:6a4a5b7d7324	1072	return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
bogdanm	0:9b334a45a8ff	1073	}
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/**
bogdanm	0:9b334a45a8ff	1076	* @brief Returns the PCLK2 frequency
bogdanm	0:9b334a45a8ff	1077	* @note Each time PCLK2 changes, this function must be called to update the
bogdanm	0:9b334a45a8ff	1078	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm	0:9b334a45a8ff	1079	* @retval PCLK2 frequency
bogdanm	0:9b334a45a8ff	1080	*/
bogdanm	0:9b334a45a8ff	1081	uint32_t HAL_RCC_GetPCLK2Freq(void)
bogdanm	0:9b334a45a8ff	1082	{
bogdanm	0:9b334a45a8ff	1083	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
mbed_official	124:6a4a5b7d7324	1084	return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
bogdanm	0:9b334a45a8ff	1085	}
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/**
bogdanm	0:9b334a45a8ff	1088	* @brief Configures the RCC_OscInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1089	* RCC configuration registers.
mbed_official	124:6a4a5b7d7324	1090	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
bogdanm	0:9b334a45a8ff	1091	* will be configured.
bogdanm	0:9b334a45a8ff	1092	* @retval None
bogdanm	0:9b334a45a8ff	1093	*/
mbed_official	124:6a4a5b7d7324	1094	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm	0:9b334a45a8ff	1095	{
bogdanm	0:9b334a45a8ff	1096	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1097	assert_param(RCC_OscInitStruct != NULL);
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm	0:9b334a45a8ff	1100	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \
bogdanm	0:9b334a45a8ff	1101	\| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
mbed_official	124:6a4a5b7d7324	1102
mbed_official	124:6a4a5b7d7324	1103	#if defined(RCC_CFGR2_PREDIV1SRC)
mbed_official	124:6a4a5b7d7324	1104	/* Get the Prediv1 source --------------------------------------------------*/
mbed_official	124:6a4a5b7d7324	1105	RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
mbed_official	124:6a4a5b7d7324	1106	#endif /* RCC_CFGR2_PREDIV1SRC */
mbed_official	124:6a4a5b7d7324	1107
bogdanm	0:9b334a45a8ff	1108	/* Get the HSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1109	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm	0:9b334a45a8ff	1110	{
bogdanm	0:9b334a45a8ff	1111	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm	0:9b334a45a8ff	1112	}
bogdanm	0:9b334a45a8ff	1113	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm	0:9b334a45a8ff	1114	{
bogdanm	0:9b334a45a8ff	1115	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm	0:9b334a45a8ff	1116	}
bogdanm	0:9b334a45a8ff	1117	else
bogdanm	0:9b334a45a8ff	1118	{
bogdanm	0:9b334a45a8ff	1119	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm	0:9b334a45a8ff	1120	}
bogdanm	0:9b334a45a8ff	1121	RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/* Get the HSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1124	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	1125	{
bogdanm	0:9b334a45a8ff	1126	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm	0:9b334a45a8ff	1127	}
bogdanm	0:9b334a45a8ff	1128	else
bogdanm	0:9b334a45a8ff	1129	{
bogdanm	0:9b334a45a8ff	1130	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm	0:9b334a45a8ff	1131	}
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	/* Get the LSE configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1136	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm	0:9b334a45a8ff	1137	{
bogdanm	0:9b334a45a8ff	1138	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm	0:9b334a45a8ff	1139	}
bogdanm	0:9b334a45a8ff	1140	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm	0:9b334a45a8ff	1141	{
bogdanm	0:9b334a45a8ff	1142	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm	0:9b334a45a8ff	1143	}
bogdanm	0:9b334a45a8ff	1144	else
bogdanm	0:9b334a45a8ff	1145	{
bogdanm	0:9b334a45a8ff	1146	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm	0:9b334a45a8ff	1147	}
bogdanm	0:9b334a45a8ff	1148
bogdanm	0:9b334a45a8ff	1149	/* Get the LSI configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1150	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	1151	{
bogdanm	0:9b334a45a8ff	1152	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm	0:9b334a45a8ff	1153	}
bogdanm	0:9b334a45a8ff	1154	else
bogdanm	0:9b334a45a8ff	1155	{
bogdanm	0:9b334a45a8ff	1156	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm	0:9b334a45a8ff	1157	}
bogdanm	0:9b334a45a8ff	1158
mbed_official	124:6a4a5b7d7324	1159
bogdanm	0:9b334a45a8ff	1160	/* Get the PLL configuration -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1161	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	1162	{
bogdanm	0:9b334a45a8ff	1163	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm	0:9b334a45a8ff	1164	}
bogdanm	0:9b334a45a8ff	1165	else
bogdanm	0:9b334a45a8ff	1166	{
bogdanm	0:9b334a45a8ff	1167	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm	0:9b334a45a8ff	1168	}
bogdanm	0:9b334a45a8ff	1169	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
bogdanm	0:9b334a45a8ff	1170	RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
mbed_official	124:6a4a5b7d7324	1171	#if defined(RCC_CR_PLL2ON)
mbed_official	124:6a4a5b7d7324	1172	/* Get the PLL2 configuration -----------------------------------------------*/
mbed_official	124:6a4a5b7d7324	1173	if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
mbed_official	124:6a4a5b7d7324	1174	{
mbed_official	124:6a4a5b7d7324	1175	RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
mbed_official	124:6a4a5b7d7324	1176	}
mbed_official	124:6a4a5b7d7324	1177	else
mbed_official	124:6a4a5b7d7324	1178	{
mbed_official	124:6a4a5b7d7324	1179	RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
mbed_official	124:6a4a5b7d7324	1180	}
mbed_official	124:6a4a5b7d7324	1181	RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
mbed_official	124:6a4a5b7d7324	1182	RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
mbed_official	124:6a4a5b7d7324	1183	#endif /* RCC_CR_PLL2ON */
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/**
mbed_official	124:6a4a5b7d7324	1187	* @brief Get the RCC_ClkInitStruct according to the internal
bogdanm	0:9b334a45a8ff	1188	* RCC configuration registers.
mbed_official	124:6a4a5b7d7324	1189	* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
mbed_official	124:6a4a5b7d7324	1190	* contains the current clock configuration.
mbed_official	124:6a4a5b7d7324	1191	* @param pFLatency Pointer on the Flash Latency.
bogdanm	0:9b334a45a8ff	1192	* @retval None
bogdanm	0:9b334a45a8ff	1193	*/
mbed_official	124:6a4a5b7d7324	1194	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
bogdanm	0:9b334a45a8ff	1195	{
bogdanm	0:9b334a45a8ff	1196	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1197	assert_param(RCC_ClkInitStruct != NULL);
bogdanm	0:9b334a45a8ff	1198	assert_param(pFLatency != NULL);
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/* Set all possible values for the Clock type parameter --------------------*/
bogdanm	0:9b334a45a8ff	1201	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
bogdanm	0:9b334a45a8ff	1202
bogdanm	0:9b334a45a8ff	1203	/* Get the SYSCLK configuration --------------------------------------------*/
bogdanm	0:9b334a45a8ff	1204	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	/* Get the HCLK configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1207	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/* Get the APB1 configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1210	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* Get the APB2 configuration ----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1213	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
bogdanm	0:9b334a45a8ff	1214
mbed_official	124:6a4a5b7d7324	1215	#if defined(FLASH_ACR_LATENCY)
mbed_official	124:6a4a5b7d7324	1216	/* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official	124:6a4a5b7d7324	1217	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official	124:6a4a5b7d7324	1218	#else
bogdanm	0:9b334a45a8ff	1219	/* For VALUE lines devices, only LATENCY_0 can be set*/
bogdanm	0:9b334a45a8ff	1220	*pFLatency = (uint32_t)FLASH_LATENCY_0;
mbed_official	124:6a4a5b7d7324	1221	#endif
bogdanm	0:9b334a45a8ff	1222	}
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/**
bogdanm	0:9b334a45a8ff	1225	* @brief This function handles the RCC CSS interrupt request.
bogdanm	0:9b334a45a8ff	1226	* @note This API should be called under the NMI_Handler().
bogdanm	0:9b334a45a8ff	1227	* @retval None
bogdanm	0:9b334a45a8ff	1228	*/
bogdanm	0:9b334a45a8ff	1229	void HAL_RCC_NMI_IRQHandler(void)
bogdanm	0:9b334a45a8ff	1230	{
bogdanm	0:9b334a45a8ff	1231	/* Check RCC CSSF flag */
bogdanm	0:9b334a45a8ff	1232	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	/* RCC Clock Security System interrupt user callback */
bogdanm	0:9b334a45a8ff	1235	HAL_RCC_CSSCallback();
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	/* Clear RCC CSS pending bit */
bogdanm	0:9b334a45a8ff	1238	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
bogdanm	0:9b334a45a8ff	1239	}
bogdanm	0:9b334a45a8ff	1240	}
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/**
bogdanm	0:9b334a45a8ff	1243	* @brief RCC Clock Security System interrupt callback
bogdanm	0:9b334a45a8ff	1244	* @retval none
bogdanm	0:9b334a45a8ff	1245	*/
bogdanm	0:9b334a45a8ff	1246	__weak void HAL_RCC_CSSCallback(void)
bogdanm	0:9b334a45a8ff	1247	{
bogdanm	0:9b334a45a8ff	1248	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1249	the HAL_RCC_CSSCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1250	*/
bogdanm	0:9b334a45a8ff	1251	}
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/**
bogdanm	0:9b334a45a8ff	1254	* @}
bogdanm	0:9b334a45a8ff	1255	*/
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	/**
bogdanm	0:9b334a45a8ff	1258	* @}
bogdanm	0:9b334a45a8ff	1259	*/
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	#endif /* HAL_RCC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1262	/**
bogdanm	0:9b334a45a8ff	1263	* @}
bogdanm	0:9b334a45a8ff	1264	*/
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/**
bogdanm	0:9b334a45a8ff	1267	* @}
bogdanm	0:9b334a45a8ff	1268	*/
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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