en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_rcc.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief RCC HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 ##### RCC specific features #####
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 [..]
bogdanm 0:9b334a45a8ff 18 After reset the device is running from Internal High Speed oscillator
bogdanm 0:9b334a45a8ff 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
bogdanm 0:9b334a45a8ff 20 and all peripherals are off except internal SRAM, Flash and JTAG.
bogdanm 0:9b334a45a8ff 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
bogdanm 0:9b334a45a8ff 22 all peripherals mapped on these busses are running at HSI speed.
bogdanm 0:9b334a45a8ff 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
bogdanm 0:9b334a45a8ff 24 (+) All GPIOs are in input floating state, except the JTAG pins which
bogdanm 0:9b334a45a8ff 25 are assigned to be used for debug purpose.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 [..]
bogdanm 0:9b334a45a8ff 28 Once the device started from reset, the user application has to:
bogdanm 0:9b334a45a8ff 29 (+) Configure the clock source to be used to drive the System clock
bogdanm 0:9b334a45a8ff 30 (if the application needs higher frequency/performance)
bogdanm 0:9b334a45a8ff 31 (+) Configure the System clock frequency and Flash settings
bogdanm 0:9b334a45a8ff 32 (+) Configure the AHB and APB busses prescalers
bogdanm 0:9b334a45a8ff 33 (+) Enable the clock for the peripheral(s) to be used
bogdanm 0:9b334a45a8ff 34 (+) Configure the clock source(s) for peripherals whose clocks are not
bogdanm 0:9b334a45a8ff 35 derived from the System clock (I2S, RTC, ADC, USB OTG FS)
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 ##### RCC Limitations #####
bogdanm 0:9b334a45a8ff 38 ==============================================================================
bogdanm 0:9b334a45a8ff 39 [..]
bogdanm 0:9b334a45a8ff 40 A delay between an RCC peripheral clock enable and the effective peripheral
bogdanm 0:9b334a45a8ff 41 enabling should be taken into account in order to manage the peripheral read/write
bogdanm 0:9b334a45a8ff 42 from/to registers.
bogdanm 0:9b334a45a8ff 43 (+) This delay depends on the peripheral mapping.
bogdanm 0:9b334a45a8ff 44 (++) AHB & APB peripherals, 1 dummy read is necessary
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 [..]
bogdanm 0:9b334a45a8ff 47 Workarounds:
bogdanm 0:9b334a45a8ff 48 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
bogdanm 0:9b334a45a8ff 49 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 @endverbatim
bogdanm 0:9b334a45a8ff 52 ******************************************************************************
bogdanm 0:9b334a45a8ff 53 * @attention
bogdanm 0:9b334a45a8ff 54 *
bogdanm 0:9b334a45a8ff 55 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 56 *
bogdanm 0:9b334a45a8ff 57 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 58 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 59 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 60 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 61 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 62 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 63 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 64 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 65 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 66 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 67 *
bogdanm 0:9b334a45a8ff 68 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 69 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 71 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 74 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 75 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 76 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 77 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 78 *
bogdanm 0:9b334a45a8ff 79 ******************************************************************************
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 83 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 86 * @{
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /** @defgroup RCC RCC
bogdanm 0:9b334a45a8ff 90 * @brief RCC HAL module driver
bogdanm 0:9b334a45a8ff 91 * @{
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 97 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 98 /** @defgroup RCC_Private_Constants RCC Private Constants
bogdanm 0:9b334a45a8ff 99 * @{
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101 /**
bogdanm 0:9b334a45a8ff 102 * @}
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 105 /** @defgroup RCC_Private_Macros RCC Private Macros
bogdanm 0:9b334a45a8ff 106 * @{
bogdanm 0:9b334a45a8ff 107 */
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
bogdanm 0:9b334a45a8ff 110 #define MCO1_GPIO_PORT GPIOA
bogdanm 0:9b334a45a8ff 111 #define MCO1_PIN GPIO_PIN_8
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /**
bogdanm 0:9b334a45a8ff 114 * @}
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 /** @defgroup RCC_Private_Variables RCC Private Variables
bogdanm 0:9b334a45a8ff 119 * @{
bogdanm 0:9b334a45a8ff 120 */
bogdanm 0:9b334a45a8ff 121 const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /**
bogdanm 0:9b334a45a8ff 124 * @}
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 128 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /** @defgroup RCC_Exported_Functions RCC Exported Functions
bogdanm 0:9b334a45a8ff 131 * @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 135 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 136 *
bogdanm 0:9b334a45a8ff 137 @verbatim
bogdanm 0:9b334a45a8ff 138 ===============================================================================
bogdanm 0:9b334a45a8ff 139 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 140 ===============================================================================
bogdanm 0:9b334a45a8ff 141 [..]
bogdanm 0:9b334a45a8ff 142 This section provide functions allowing to configure the internal/external oscillators
bogdanm 0:9b334a45a8ff 143 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
bogdanm 0:9b334a45a8ff 144 and APB2).
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 [..] Internal/external clock and PLL configuration
bogdanm 0:9b334a45a8ff 147 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
bogdanm 0:9b334a45a8ff 148 the PLL as System clock source.
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
bogdanm 0:9b334a45a8ff 151 clock source.
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
bogdanm 0:9b334a45a8ff 154 through the PLL as System clock source. Can be used also as RTC clock source.
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
bogdanm 0:9b334a45a8ff 159 (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
bogdanm 0:9b334a45a8ff 160 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
bogdanm 0:9b334a45a8ff 163 and if a HSE clock failure occurs(HSE used directly or through PLL as System
bogdanm 0:9b334a45a8ff 164 clock source), the System clockis automatically switched to HSI and an interrupt
bogdanm 0:9b334a45a8ff 165 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
bogdanm 0:9b334a45a8ff 166 (Non-Maskable Interrupt) exception vector.
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
bogdanm 0:9b334a45a8ff 169 HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 [..] System, AHB and APB busses clocks configuration
bogdanm 0:9b334a45a8ff 172 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
bogdanm 0:9b334a45a8ff 173 HSE and PLL.
bogdanm 0:9b334a45a8ff 174 The AHB clock (HCLK) is derived from System clock through configurable
bogdanm 0:9b334a45a8ff 175 prescaler and used to clock the CPU, memory and peripherals mapped
bogdanm 0:9b334a45a8ff 176 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
bogdanm 0:9b334a45a8ff 177 from AHB clock through configurable prescalers and used to clock
bogdanm 0:9b334a45a8ff 178 the peripherals mapped on these busses. You can use
bogdanm 0:9b334a45a8ff 179 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
bogdanm 0:9b334a45a8ff 182 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
bogdanm 0:9b334a45a8ff 183 divided by 128.
bogdanm 0:9b334a45a8ff 184 (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
bogdanm 0:9b334a45a8ff 185 to work correctly. This clock is derived of the main PLL through PLL Multiplier.
bogdanm 0:9b334a45a8ff 186 (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
bogdanm 0:9b334a45a8ff 187 (+@) IWDG clock which is always the LSI clock.
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
bogdanm 0:9b334a45a8ff 190 For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
bogdanm 0:9b334a45a8ff 191 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
bogdanm 0:9b334a45a8ff 192 +-----------------------------------------------+
bogdanm 0:9b334a45a8ff 193 | Latency | SYSCLK clock frequency (MHz) |
bogdanm 0:9b334a45a8ff 194 |---------------|-------------------------------|
bogdanm 0:9b334a45a8ff 195 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
bogdanm 0:9b334a45a8ff 196 |---------------|-------------------------------|
bogdanm 0:9b334a45a8ff 197 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
bogdanm 0:9b334a45a8ff 198 |---------------|-------------------------------|
bogdanm 0:9b334a45a8ff 199 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
bogdanm 0:9b334a45a8ff 200 +-----------------------------------------------+
bogdanm 0:9b334a45a8ff 201 @endverbatim
bogdanm 0:9b334a45a8ff 202 * @{
bogdanm 0:9b334a45a8ff 203 */
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /**
bogdanm 0:9b334a45a8ff 206 * @brief Resets the RCC clock configuration to the default reset state.
bogdanm 0:9b334a45a8ff 207 * @note The default reset state of the clock configuration is given below:
bogdanm 0:9b334a45a8ff 208 * - HSI ON and used as system clock source
bogdanm 0:9b334a45a8ff 209 * - HSE and PLL OFF
bogdanm 0:9b334a45a8ff 210 * - AHB, APB1 and APB2 prescaler set to 1.
bogdanm 0:9b334a45a8ff 211 * - CSS and MCO1 OFF
bogdanm 0:9b334a45a8ff 212 * - All interrupts disabled
bogdanm 0:9b334a45a8ff 213 * @note This function doesn't modify the configuration of the
bogdanm 0:9b334a45a8ff 214 * - Peripheral clocks
bogdanm 0:9b334a45a8ff 215 * - LSI, LSE and RTC clocks
bogdanm 0:9b334a45a8ff 216 * @retval None
bogdanm 0:9b334a45a8ff 217 */
bogdanm 0:9b334a45a8ff 218 __weak void HAL_RCC_DeInit(void)
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 /* Switch SYSCLK to HSI */
bogdanm 0:9b334a45a8ff 221 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /* Reset HSEON, CSSON, & PLLON bits */
bogdanm 0:9b334a45a8ff 224 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 227 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 230 CLEAR_REG(RCC->CFGR);
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Set HSITRIM bits to the reset value */
bogdanm 0:9b334a45a8ff 233 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 236 CLEAR_REG(RCC->CIR);
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /**
bogdanm 0:9b334a45a8ff 240 * @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm 0:9b334a45a8ff 241 * RCC_OscInitTypeDef.
bogdanm 0:9b334a45a8ff 242 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 243 * contains the configuration information for the RCC Oscillators.
bogdanm 0:9b334a45a8ff 244 * @note The PLL is not disabled when used as system clock.
bogdanm 0:9b334a45a8ff 245 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
bogdanm 0:9b334a45a8ff 246 * @retval HAL status
bogdanm 0:9b334a45a8ff 247 */
bogdanm 0:9b334a45a8ff 248 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 249 {
bogdanm 0:9b334a45a8ff 250 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /* Check the parameters */
bogdanm 0:9b334a45a8ff 253 assert_param(RCC_OscInitStruct != NULL);
bogdanm 0:9b334a45a8ff 254 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /*------------------------------- HSE Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 257 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm 0:9b334a45a8ff 258 {
bogdanm 0:9b334a45a8ff 259 /* Check the parameters */
bogdanm 0:9b334a45a8ff 260 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
bogdanm 0:9b334a45a8ff 263 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 264 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
bogdanm 0:9b334a45a8ff 265 {
bogdanm 0:9b334a45a8ff 266 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271 else
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm 0:9b334a45a8ff 274 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 277 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /* Wait till HSE is disabled */
bogdanm 0:9b334a45a8ff 280 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 281 {
bogdanm 0:9b334a45a8ff 282 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 285 }
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /* Set the new HSE configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 289 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Check the HSE State */
bogdanm 0:9b334a45a8ff 292 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
bogdanm 0:9b334a45a8ff 293 {
bogdanm 0:9b334a45a8ff 294 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 295 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /* Wait till HSE is ready */
bogdanm 0:9b334a45a8ff 298 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 299 {
bogdanm 0:9b334a45a8ff 300 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306 else
bogdanm 0:9b334a45a8ff 307 {
bogdanm 0:9b334a45a8ff 308 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 309 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Wait till HSE is disabled */
bogdanm 0:9b334a45a8ff 312 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 313 {
bogdanm 0:9b334a45a8ff 314 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 315 {
bogdanm 0:9b334a45a8ff 316 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 317 }
bogdanm 0:9b334a45a8ff 318 }
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320 }
bogdanm 0:9b334a45a8ff 321 }
bogdanm 0:9b334a45a8ff 322 /*----------------------------- HSI Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 323 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm 0:9b334a45a8ff 324 {
bogdanm 0:9b334a45a8ff 325 /* Check the parameters */
bogdanm 0:9b334a45a8ff 326 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm 0:9b334a45a8ff 327 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm 0:9b334a45a8ff 330 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 331 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
bogdanm 0:9b334a45a8ff 332 {
bogdanm 0:9b334a45a8ff 333 /* When HSI is used as system clock it will not disabled */
bogdanm 0:9b334a45a8ff 334 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 /* Otherwise, just the calibration is allowed */
bogdanm 0:9b334a45a8ff 339 else
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 342 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344 }
bogdanm 0:9b334a45a8ff 345 else
bogdanm 0:9b334a45a8ff 346 {
bogdanm 0:9b334a45a8ff 347 /* Check the HSI State */
bogdanm 0:9b334a45a8ff 348 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 /* Enable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 351 __HAL_RCC_HSI_ENABLE();
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 354 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 357 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 358 {
bogdanm 0:9b334a45a8ff 359 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 362 }
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 366 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368 else
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 /* Disable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 371 __HAL_RCC_HSI_DISABLE();
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 374 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Wait till HSI is disabled */
bogdanm 0:9b334a45a8ff 377 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 378 {
bogdanm 0:9b334a45a8ff 379 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 380 {
bogdanm 0:9b334a45a8ff 381 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 382 }
bogdanm 0:9b334a45a8ff 383 }
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387 /*------------------------------ LSI Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 388 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 /* Check the parameters */
bogdanm 0:9b334a45a8ff 391 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /* Check the LSI State */
bogdanm 0:9b334a45a8ff 394 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 /* Enable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 397 __HAL_RCC_LSI_ENABLE();
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 400 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 403 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 404 {
bogdanm 0:9b334a45a8ff 405 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 408 }
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410 /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
bogdanm 0:9b334a45a8ff 411 should be added.*/
bogdanm 0:9b334a45a8ff 412 HAL_Delay(1);
bogdanm 0:9b334a45a8ff 413 }
bogdanm 0:9b334a45a8ff 414 else
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 /* Disable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 417 __HAL_RCC_LSI_DISABLE();
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 420 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /* Wait till LSI is disabled */
bogdanm 0:9b334a45a8ff 423 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 424 {
bogdanm 0:9b334a45a8ff 425 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 426 {
bogdanm 0:9b334a45a8ff 427 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430 }
bogdanm 0:9b334a45a8ff 431 }
bogdanm 0:9b334a45a8ff 432 /*------------------------------ LSE Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 433 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm 0:9b334a45a8ff 434 {
bogdanm 0:9b334a45a8ff 435 /* Check the parameters */
bogdanm 0:9b334a45a8ff 436 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 439 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 442 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 445 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 448 {
bogdanm 0:9b334a45a8ff 449 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 450 {
bogdanm 0:9b334a45a8ff 451 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 452 }
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm 0:9b334a45a8ff 456 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 459 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 462 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 467 }
bogdanm 0:9b334a45a8ff 468 }
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /* Set the new LSE configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 471 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm 0:9b334a45a8ff 472 /* Check the LSE State */
bogdanm 0:9b334a45a8ff 473 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
bogdanm 0:9b334a45a8ff 474 {
bogdanm 0:9b334a45a8ff 475 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 476 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 479 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 480 {
bogdanm 0:9b334a45a8ff 481 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485 }
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487 else
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 490 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /* Wait till LSE is disabled */
bogdanm 0:9b334a45a8ff 493 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 494 {
bogdanm 0:9b334a45a8ff 495 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501 }
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 /*-------------------------------- PLL Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 504 /* Check the parameters */
bogdanm 0:9b334a45a8ff 505 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm 0:9b334a45a8ff 506 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 /* Check if the PLL is used as system clock or not */
bogdanm 0:9b334a45a8ff 509 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 510 {
bogdanm 0:9b334a45a8ff 511 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm 0:9b334a45a8ff 512 {
bogdanm 0:9b334a45a8ff 513 /* Check the parameters */
bogdanm 0:9b334a45a8ff 514 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm 0:9b334a45a8ff 515 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 518 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 521 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 524 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 525 {
bogdanm 0:9b334a45a8ff 526 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 527 {
bogdanm 0:9b334a45a8ff 528 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 529 }
bogdanm 0:9b334a45a8ff 530 }
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /* Configure the HSE prediv1 factor --------------------------------*/
bogdanm 0:9b334a45a8ff 533 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
bogdanm 0:9b334a45a8ff 534 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 535 {
bogdanm 0:9b334a45a8ff 536 /* Check the parameters */
bogdanm 0:9b334a45a8ff 537 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
bogdanm 0:9b334a45a8ff 540 }
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Configure the main PLL clock source and multiplication factors. */
bogdanm 0:9b334a45a8ff 543 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm 0:9b334a45a8ff 544 RCC_OscInitStruct->PLL.PLLMUL);
bogdanm 0:9b334a45a8ff 545 /* Enable the main PLL. */
bogdanm 0:9b334a45a8ff 546 __HAL_RCC_PLL_ENABLE();
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 549 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 552 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 553 {
bogdanm 0:9b334a45a8ff 554 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 555 {
bogdanm 0:9b334a45a8ff 556 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559 }
bogdanm 0:9b334a45a8ff 560 else
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 563 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 564
bogdanm 0:9b334a45a8ff 565 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 566 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 /* Wait till PLL is disabled */
bogdanm 0:9b334a45a8ff 569 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 572 {
bogdanm 0:9b334a45a8ff 573 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 574 }
bogdanm 0:9b334a45a8ff 575 }
bogdanm 0:9b334a45a8ff 576 }
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578 else
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582 }
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 return HAL_OK;
bogdanm 0:9b334a45a8ff 585 }
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 /**
bogdanm 0:9b334a45a8ff 588 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
bogdanm 0:9b334a45a8ff 589 * parameters in the RCC_ClkInitStruct.
bogdanm 0:9b334a45a8ff 590 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 591 * contains the configuration information for the RCC peripheral.
bogdanm 0:9b334a45a8ff 592 * @param FLatency: FLASH Latency
bogdanm 0:9b334a45a8ff 593 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 594 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
bogdanm 0:9b334a45a8ff 595 * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
bogdanm 0:9b334a45a8ff 596 * @arg FLASH_LATENCY_2: FLASH 2 Latency cycle
bogdanm 0:9b334a45a8ff 597 *
bogdanm 0:9b334a45a8ff 598 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 599 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
bogdanm 0:9b334a45a8ff 600 *
bogdanm 0:9b334a45a8ff 601 * @note The HSI is used (enabled by hardware) as system clock source after
bogdanm 0:9b334a45a8ff 602 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
bogdanm 0:9b334a45a8ff 603 * of failure of the HSE used directly or indirectly as system clock
bogdanm 0:9b334a45a8ff 604 * (if the Clock Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 605 *
bogdanm 0:9b334a45a8ff 606 * @note A switch from one clock source to another occurs only if the target
bogdanm 0:9b334a45a8ff 607 * clock source is ready (clock stable after startup delay or PLL locked).
bogdanm 0:9b334a45a8ff 608 * If a clock source which is not yet ready is selected, the switch will
bogdanm 0:9b334a45a8ff 609 * occur when the clock source will be ready.
bogdanm 0:9b334a45a8ff 610 * You can use HAL_RCC_GetClockConfig() function to know which clock is
bogdanm 0:9b334a45a8ff 611 * currently used as system clock source.
bogdanm 0:9b334a45a8ff 612 * @retval None
bogdanm 0:9b334a45a8ff 613 */
bogdanm 0:9b334a45a8ff 614 __weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
bogdanm 0:9b334a45a8ff 615 {
bogdanm 0:9b334a45a8ff 616 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /* Check the parameters */
bogdanm 0:9b334a45a8ff 619 assert_param(RCC_ClkInitStruct != NULL);
bogdanm 0:9b334a45a8ff 620 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
bogdanm 0:9b334a45a8ff 621 assert_param(IS_FLASH_LATENCY(FLatency));
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
bogdanm 0:9b334a45a8ff 624 must be correctly programmed according to the frequency of the CPU clock
bogdanm 0:9b334a45a8ff 625 (HCLK) of the device. */
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 628 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 629 {
bogdanm 0:9b334a45a8ff 630 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 631 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 632 }
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 /*------------------------- SYSCLK Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 635 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 636 {
bogdanm 0:9b334a45a8ff 637 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 640 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 641 {
bogdanm 0:9b334a45a8ff 642 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 643 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 644 {
bogdanm 0:9b334a45a8ff 645 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 646 }
bogdanm 0:9b334a45a8ff 647 }
bogdanm 0:9b334a45a8ff 648 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 649 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 650 {
bogdanm 0:9b334a45a8ff 651 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 652 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 653 {
bogdanm 0:9b334a45a8ff 654 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 655 }
bogdanm 0:9b334a45a8ff 656 }
bogdanm 0:9b334a45a8ff 657 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 658 else
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 661 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 662 {
bogdanm 0:9b334a45a8ff 663 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 664 }
bogdanm 0:9b334a45a8ff 665 }
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 670 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 675 {
bogdanm 0:9b334a45a8ff 676 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680 }
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 683 {
bogdanm 0:9b334a45a8ff 684 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 685 {
bogdanm 0:9b334a45a8ff 686 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 687 {
bogdanm 0:9b334a45a8ff 688 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690 }
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692 else
bogdanm 0:9b334a45a8ff 693 {
bogdanm 0:9b334a45a8ff 694 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 695 {
bogdanm 0:9b334a45a8ff 696 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 697 {
bogdanm 0:9b334a45a8ff 698 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 699 }
bogdanm 0:9b334a45a8ff 700 }
bogdanm 0:9b334a45a8ff 701 }
bogdanm 0:9b334a45a8ff 702 }
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /*-------------------------- PCLK1 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 705 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
bogdanm 0:9b334a45a8ff 706 {
bogdanm 0:9b334a45a8ff 707 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
bogdanm 0:9b334a45a8ff 708 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
bogdanm 0:9b334a45a8ff 709 }
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 /*-------------------------- PCLK2 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 712 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
bogdanm 0:9b334a45a8ff 713 {
bogdanm 0:9b334a45a8ff 714 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
bogdanm 0:9b334a45a8ff 715 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
bogdanm 0:9b334a45a8ff 716 }
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 /* Configure the source of time base considering new system clocks settings*/
bogdanm 0:9b334a45a8ff 719 HAL_InitTick (TICK_INT_PRIORITY);
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 return HAL_OK;
bogdanm 0:9b334a45a8ff 722 }
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 /**
bogdanm 0:9b334a45a8ff 725 * @}
bogdanm 0:9b334a45a8ff 726 */
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 729 * @brief RCC clocks control functions
bogdanm 0:9b334a45a8ff 730 *
bogdanm 0:9b334a45a8ff 731 @verbatim
bogdanm 0:9b334a45a8ff 732 ===============================================================================
bogdanm 0:9b334a45a8ff 733 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 734 ===============================================================================
bogdanm 0:9b334a45a8ff 735 [..]
bogdanm 0:9b334a45a8ff 736 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 737 frequencies.
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 @endverbatim
bogdanm 0:9b334a45a8ff 740 * @{
bogdanm 0:9b334a45a8ff 741 */
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /**
bogdanm 0:9b334a45a8ff 744 * @brief Selects the clock source to output on MCO pin.
bogdanm 0:9b334a45a8ff 745 * @note MCO pin should be configured in alternate function mode.
bogdanm 0:9b334a45a8ff 746 * @param RCC_MCOx: specifies the output direction for the clock source.
bogdanm 0:9b334a45a8ff 747 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 748 * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
bogdanm 0:9b334a45a8ff 749 * @param RCC_MCOSource: specifies the clock source to output.
bogdanm 0:9b334a45a8ff 750 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 751 * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
bogdanm 0:9b334a45a8ff 752 * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected as MCO source
bogdanm 0:9b334a45a8ff 753 * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
bogdanm 0:9b334a45a8ff 754 * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
bogdanm 0:9b334a45a8ff 755 * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO source
bogdanm 0:9b334a45a8ff 756 * @arg RCC_MCO1SOURCE_PLL2CLK: PLL2 clock selected as MCO source (only for connectivity line devices)
bogdanm 0:9b334a45a8ff 757 * @arg RCC_MCO1SOURCE_PLL3CLK_DIV2: PLL3 clock divided by 2 selected as MCO source (only for connectivity line devices)
bogdanm 0:9b334a45a8ff 758 * @arg RCC_MCO1SOURCE_EXT_HSE: XT1 external 3-25 MHz oscillator clock selected as MCO source (only for connectivity line devices)
bogdanm 0:9b334a45a8ff 759 * @arg RCC_MCO1SOURCE_PLL3CLK: PLL3 clock selected as MCO source (only for connectivity line devices)
bogdanm 0:9b334a45a8ff 760 * @param RCC_MCODiv: specifies the MCO DIV.
bogdanm 0:9b334a45a8ff 761 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 762 * @arg RCC_MCODIV_1: no division applied to MCO clock
bogdanm 0:9b334a45a8ff 763 * @retval None
bogdanm 0:9b334a45a8ff 764 */
bogdanm 0:9b334a45a8ff 765 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
bogdanm 0:9b334a45a8ff 766 {
bogdanm 0:9b334a45a8ff 767 GPIO_InitTypeDef gpio;
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 /* Check the parameters */
bogdanm 0:9b334a45a8ff 770 assert_param(IS_RCC_MCO(RCC_MCOx));
bogdanm 0:9b334a45a8ff 771 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
bogdanm 0:9b334a45a8ff 772 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /* MCO Clock Enable */
bogdanm 0:9b334a45a8ff 775 MCO1_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 /* Configure the MCO1 pin in alternate function mode */
bogdanm 0:9b334a45a8ff 778 gpio.Pin = MCO1_PIN;
bogdanm 0:9b334a45a8ff 779 gpio.Mode = GPIO_MODE_AF_PP;
bogdanm 0:9b334a45a8ff 780 gpio.Speed = GPIO_SPEED_HIGH;
bogdanm 0:9b334a45a8ff 781 gpio.Pull = GPIO_NOPULL;
bogdanm 0:9b334a45a8ff 782 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */
bogdanm 0:9b334a45a8ff 785 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, RCC_MCOSource);
bogdanm 0:9b334a45a8ff 786 }
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /**
bogdanm 0:9b334a45a8ff 789 * @brief Enables the Clock Security System.
bogdanm 0:9b334a45a8ff 790 * @note If a failure is detected on the HSE oscillator clock, this oscillator
bogdanm 0:9b334a45a8ff 791 * is automatically disabled and an interrupt is generated to inform the
bogdanm 0:9b334a45a8ff 792 * software about the failure (Clock Security System Interrupt, CSSI),
bogdanm 0:9b334a45a8ff 793 * allowing the MCU to perform rescue operations. The CSSI is linked to
bogdanm 0:9b334a45a8ff 794 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
bogdanm 0:9b334a45a8ff 795 * @retval None
bogdanm 0:9b334a45a8ff 796 */
bogdanm 0:9b334a45a8ff 797 void HAL_RCC_EnableCSS(void)
bogdanm 0:9b334a45a8ff 798 {
bogdanm 0:9b334a45a8ff 799 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
bogdanm 0:9b334a45a8ff 800 }
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /**
bogdanm 0:9b334a45a8ff 803 * @brief Disables the Clock Security System.
bogdanm 0:9b334a45a8ff 804 * @retval None
bogdanm 0:9b334a45a8ff 805 */
bogdanm 0:9b334a45a8ff 806 void HAL_RCC_DisableCSS(void)
bogdanm 0:9b334a45a8ff 807 {
bogdanm 0:9b334a45a8ff 808 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
bogdanm 0:9b334a45a8ff 809 }
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 /**
bogdanm 0:9b334a45a8ff 812 * @brief Returns the SYSCLK frequency
bogdanm 0:9b334a45a8ff 813 *
bogdanm 0:9b334a45a8ff 814 * @note The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 815 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 816 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 817 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 818 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 819 * divided by PREDIV factor(**)
bogdanm 0:9b334a45a8ff 820 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 821 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
bogdanm 0:9b334a45a8ff 822 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 823 * 8 MHz).
bogdanm 0:9b334a45a8ff 824 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 825 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 826 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 827 * have wrong result.
bogdanm 0:9b334a45a8ff 828 *
bogdanm 0:9b334a45a8ff 829 * @note The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 830 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 831 *
bogdanm 0:9b334a45a8ff 832 * @note This function can be used by the user application to compute the
bogdanm 0:9b334a45a8ff 833 * baudrate for the communication peripherals or configure other parameters.
bogdanm 0:9b334a45a8ff 834 *
bogdanm 0:9b334a45a8ff 835 * @note Each time SYSCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 836 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 837 *
bogdanm 0:9b334a45a8ff 838 *
bogdanm 0:9b334a45a8ff 839 * @retval SYSCLK frequency
bogdanm 0:9b334a45a8ff 840 */
bogdanm 0:9b334a45a8ff 841 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm 0:9b334a45a8ff 842 {
bogdanm 0:9b334a45a8ff 843 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
bogdanm 0:9b334a45a8ff 844 const uint8_t aPredivFactorTable[2] = { 1, 2};
bogdanm 0:9b334a45a8ff 845
bogdanm 0:9b334a45a8ff 846 uint32_t tmpreg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
bogdanm 0:9b334a45a8ff 847 uint32_t sysclockfreq = 0;
bogdanm 0:9b334a45a8ff 848
bogdanm 0:9b334a45a8ff 849 tmpreg = RCC->CFGR;
bogdanm 0:9b334a45a8ff 850
bogdanm 0:9b334a45a8ff 851 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 852 switch (tmpreg & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 853 {
bogdanm 0:9b334a45a8ff 854 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 855 {
bogdanm 0:9b334a45a8ff 856 sysclockfreq = HSE_VALUE;
bogdanm 0:9b334a45a8ff 857 break;
bogdanm 0:9b334a45a8ff 858 }
bogdanm 0:9b334a45a8ff 859 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 860 {
bogdanm 0:9b334a45a8ff 861 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
bogdanm 0:9b334a45a8ff 862 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
bogdanm 0:9b334a45a8ff 863 {
bogdanm 0:9b334a45a8ff 864 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
bogdanm 0:9b334a45a8ff 865 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
bogdanm 0:9b334a45a8ff 866 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 867 }
bogdanm 0:9b334a45a8ff 868 else
bogdanm 0:9b334a45a8ff 869 {
bogdanm 0:9b334a45a8ff 870 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 871 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
bogdanm 0:9b334a45a8ff 872 }
bogdanm 0:9b334a45a8ff 873 sysclockfreq = pllclk;
bogdanm 0:9b334a45a8ff 874 break;
bogdanm 0:9b334a45a8ff 875 }
bogdanm 0:9b334a45a8ff 876 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 877 default: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 878 {
bogdanm 0:9b334a45a8ff 879 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 880 break;
bogdanm 0:9b334a45a8ff 881 }
bogdanm 0:9b334a45a8ff 882 }
bogdanm 0:9b334a45a8ff 883 return sysclockfreq;
bogdanm 0:9b334a45a8ff 884 }
bogdanm 0:9b334a45a8ff 885
bogdanm 0:9b334a45a8ff 886 /**
bogdanm 0:9b334a45a8ff 887 * @brief Returns the HCLK frequency
bogdanm 0:9b334a45a8ff 888 * @note Each time HCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 889 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 890 *
bogdanm 0:9b334a45a8ff 891 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 892 * and updated within this function
bogdanm 0:9b334a45a8ff 893 * @retval HCLK frequency
bogdanm 0:9b334a45a8ff 894 */
bogdanm 0:9b334a45a8ff 895 uint32_t HAL_RCC_GetHCLKFreq(void)
bogdanm 0:9b334a45a8ff 896 {
bogdanm 0:9b334a45a8ff 897 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
bogdanm 0:9b334a45a8ff 898 return SystemCoreClock;
bogdanm 0:9b334a45a8ff 899 }
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /**
bogdanm 0:9b334a45a8ff 902 * @brief Returns the PCLK1 frequency
bogdanm 0:9b334a45a8ff 903 * @note Each time PCLK1 changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 904 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 905 * @retval PCLK1 frequency
bogdanm 0:9b334a45a8ff 906 */
bogdanm 0:9b334a45a8ff 907 uint32_t HAL_RCC_GetPCLK1Freq(void)
bogdanm 0:9b334a45a8ff 908 {
bogdanm 0:9b334a45a8ff 909 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
bogdanm 0:9b334a45a8ff 910 return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
bogdanm 0:9b334a45a8ff 911 }
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 /**
bogdanm 0:9b334a45a8ff 914 * @brief Returns the PCLK2 frequency
bogdanm 0:9b334a45a8ff 915 * @note Each time PCLK2 changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 916 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 917 * @retval PCLK2 frequency
bogdanm 0:9b334a45a8ff 918 */
bogdanm 0:9b334a45a8ff 919 uint32_t HAL_RCC_GetPCLK2Freq(void)
bogdanm 0:9b334a45a8ff 920 {
bogdanm 0:9b334a45a8ff 921 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
bogdanm 0:9b334a45a8ff 922 return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
bogdanm 0:9b334a45a8ff 923 }
bogdanm 0:9b334a45a8ff 924
bogdanm 0:9b334a45a8ff 925 /**
bogdanm 0:9b334a45a8ff 926 * @brief Configures the RCC_OscInitStruct according to the internal
bogdanm 0:9b334a45a8ff 927 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 928 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 929 * will be configured.
bogdanm 0:9b334a45a8ff 930 * @retval None
bogdanm 0:9b334a45a8ff 931 */
bogdanm 0:9b334a45a8ff 932 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 933 {
bogdanm 0:9b334a45a8ff 934 /* Check the parameters */
bogdanm 0:9b334a45a8ff 935 assert_param(RCC_OscInitStruct != NULL);
bogdanm 0:9b334a45a8ff 936
bogdanm 0:9b334a45a8ff 937 /* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm 0:9b334a45a8ff 938 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
bogdanm 0:9b334a45a8ff 939 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 /* Get the HSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 942 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm 0:9b334a45a8ff 943 {
bogdanm 0:9b334a45a8ff 944 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm 0:9b334a45a8ff 945 }
bogdanm 0:9b334a45a8ff 946 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm 0:9b334a45a8ff 947 {
bogdanm 0:9b334a45a8ff 948 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 949 }
bogdanm 0:9b334a45a8ff 950 else
bogdanm 0:9b334a45a8ff 951 {
bogdanm 0:9b334a45a8ff 952 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 953 }
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
bogdanm 0:9b334a45a8ff 956
bogdanm 0:9b334a45a8ff 957 /* Get the HSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 958 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm 0:9b334a45a8ff 959 {
bogdanm 0:9b334a45a8ff 960 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 961 }
bogdanm 0:9b334a45a8ff 962 else
bogdanm 0:9b334a45a8ff 963 {
bogdanm 0:9b334a45a8ff 964 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 965 }
bogdanm 0:9b334a45a8ff 966
bogdanm 0:9b334a45a8ff 967 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 /* Get the LSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 970 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm 0:9b334a45a8ff 971 {
bogdanm 0:9b334a45a8ff 972 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm 0:9b334a45a8ff 975 {
bogdanm 0:9b334a45a8ff 976 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm 0:9b334a45a8ff 977 }
bogdanm 0:9b334a45a8ff 978 else
bogdanm 0:9b334a45a8ff 979 {
bogdanm 0:9b334a45a8ff 980 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm 0:9b334a45a8ff 981 }
bogdanm 0:9b334a45a8ff 982
bogdanm 0:9b334a45a8ff 983 /* Get the LSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 984 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm 0:9b334a45a8ff 985 {
bogdanm 0:9b334a45a8ff 986 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm 0:9b334a45a8ff 987 }
bogdanm 0:9b334a45a8ff 988 else
bogdanm 0:9b334a45a8ff 989 {
bogdanm 0:9b334a45a8ff 990 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm 0:9b334a45a8ff 991 }
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 /* Get the PLL configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 994 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 995 {
bogdanm 0:9b334a45a8ff 996 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 997 }
bogdanm 0:9b334a45a8ff 998 else
bogdanm 0:9b334a45a8ff 999 {
bogdanm 0:9b334a45a8ff 1000 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm 0:9b334a45a8ff 1001 }
bogdanm 0:9b334a45a8ff 1002 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
bogdanm 0:9b334a45a8ff 1003 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
bogdanm 0:9b334a45a8ff 1004 }
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 /**
bogdanm 0:9b334a45a8ff 1007 * @brief Configures the RCC_ClkInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1008 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1009 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1010 * will be configured.
bogdanm 0:9b334a45a8ff 1011 * @param pFLatency: Pointer on the Flash Latency.
bogdanm 0:9b334a45a8ff 1012 * @retval None
bogdanm 0:9b334a45a8ff 1013 */
bogdanm 0:9b334a45a8ff 1014 __weak void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
bogdanm 0:9b334a45a8ff 1015 {
bogdanm 0:9b334a45a8ff 1016 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1017 assert_param(RCC_ClkInitStruct != NULL);
bogdanm 0:9b334a45a8ff 1018 assert_param(pFLatency != NULL);
bogdanm 0:9b334a45a8ff 1019
bogdanm 0:9b334a45a8ff 1020 /* Set all possible values for the Clock type parameter --------------------*/
bogdanm 0:9b334a45a8ff 1021 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
bogdanm 0:9b334a45a8ff 1022
bogdanm 0:9b334a45a8ff 1023 /* Get the SYSCLK configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 1024 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
bogdanm 0:9b334a45a8ff 1025
bogdanm 0:9b334a45a8ff 1026 /* Get the HCLK configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1027 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
bogdanm 0:9b334a45a8ff 1028
bogdanm 0:9b334a45a8ff 1029 /* Get the APB1 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1030 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
bogdanm 0:9b334a45a8ff 1031
bogdanm 0:9b334a45a8ff 1032 /* Get the APB2 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1033 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 /* For VALUE lines devices, only LATENCY_0 can be set*/
bogdanm 0:9b334a45a8ff 1036 *pFLatency = (uint32_t)FLASH_LATENCY_0;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038
bogdanm 0:9b334a45a8ff 1039 /**
bogdanm 0:9b334a45a8ff 1040 * @brief This function handles the RCC CSS interrupt request.
bogdanm 0:9b334a45a8ff 1041 * @note This API should be called under the NMI_Handler().
bogdanm 0:9b334a45a8ff 1042 * @retval None
bogdanm 0:9b334a45a8ff 1043 */
bogdanm 0:9b334a45a8ff 1044 void HAL_RCC_NMI_IRQHandler(void)
bogdanm 0:9b334a45a8ff 1045 {
bogdanm 0:9b334a45a8ff 1046 /* Check RCC CSSF flag */
bogdanm 0:9b334a45a8ff 1047 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
bogdanm 0:9b334a45a8ff 1048 {
bogdanm 0:9b334a45a8ff 1049 /* RCC Clock Security System interrupt user callback */
bogdanm 0:9b334a45a8ff 1050 HAL_RCC_CSSCallback();
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /* Clear RCC CSS pending bit */
bogdanm 0:9b334a45a8ff 1053 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
bogdanm 0:9b334a45a8ff 1054 }
bogdanm 0:9b334a45a8ff 1055 }
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /**
bogdanm 0:9b334a45a8ff 1058 * @brief RCC Clock Security System interrupt callback
bogdanm 0:9b334a45a8ff 1059 * @retval none
bogdanm 0:9b334a45a8ff 1060 */
bogdanm 0:9b334a45a8ff 1061 __weak void HAL_RCC_CSSCallback(void)
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 1064 the HAL_RCC_CSSCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 1065 */
bogdanm 0:9b334a45a8ff 1066 }
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 /**
bogdanm 0:9b334a45a8ff 1069 * @}
bogdanm 0:9b334a45a8ff 1070 */
bogdanm 0:9b334a45a8ff 1071
bogdanm 0:9b334a45a8ff 1072 /**
bogdanm 0:9b334a45a8ff 1073 * @}
bogdanm 0:9b334a45a8ff 1074 */
bogdanm 0:9b334a45a8ff 1075
bogdanm 0:9b334a45a8ff 1076 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1077 /**
bogdanm 0:9b334a45a8ff 1078 * @}
bogdanm 0:9b334a45a8ff 1079 */
bogdanm 0:9b334a45a8ff 1080
bogdanm 0:9b334a45a8ff 1081 /**
bogdanm 0:9b334a45a8ff 1082 * @}
bogdanm 0:9b334a45a8ff 1083 */
bogdanm 0:9b334a45a8ff 1084
bogdanm 0:9b334a45a8ff 1085 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/