Tobias Naegeli / Mbed 2 deprecated AIT_UWB_Range

Tobi's ubw test branch

Dependencies:   mavlink_bridge mbed

Fork of AIT_UWB_Range by Benjamin Hepp

DW1000/DW1000.h@4:6240b9c7a033, 2014-11-18 (annotated)

Committer:
manumaet
Date:
Tue Nov 18 12:44:22 2014 +0000
Revision:
4:6240b9c7a033
Parent:
0:f50e671ffff7
Child:
7:e634eeafc4d2
managed to get multiple frames via resetRX()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
manumaet 0:f50e671ffff7 1 // by Manuel Stalder & Matthias Grob 2015
manumaet 0:f50e671ffff7 2
manumaet 0:f50e671ffff7 3 #ifndef DW1000_H
manumaet 0:f50e671ffff7 4 #define DW1000_H
manumaet 0:f50e671ffff7 5
manumaet 0:f50e671ffff7 6 #include "mbed.h"
manumaet 0:f50e671ffff7 7
manumaet 0:f50e671ffff7 8 // register addresses
manumaet 0:f50e671ffff7 9 // Mnemonic Address Byte Description
manumaet 0:f50e671ffff7 10 #define DW1000_DEV_ID 0x00 // 4 Device Identifier – includes device type and revision information
manumaet 0:f50e671ffff7 11 #define DW1000_EUI 0x01 // 8 Extended Unique Identifier
manumaet 0:f50e671ffff7 12 #define DW1000_PANADR 0x03 // 4 PAN Identifier and Short Address
manumaet 0:f50e671ffff7 13 #define DW1000_SYS_CFG 0x04 // 4 System Configuration bitmap
manumaet 0:f50e671ffff7 14 #define DW1000_SYS_TIME 0x06 // 5 System Time Counter (40-bit)
manumaet 0:f50e671ffff7 15 #define DW1000_TX_FCTRL 0x08 // 5 Transmit Frame Control
manumaet 0:f50e671ffff7 16 #define DW1000_TX_BUFFER 0x09 // 1024 Transmit Data Buffer
manumaet 0:f50e671ffff7 17 #define DW1000_DX_TIME 0x0A // 5 Delayed Send or Receive Time (40-bit)
manumaet 0:f50e671ffff7 18 #define DW1000_RX_FWTO 0x0C // 2 Receive Frame Wait Timeout Period
manumaet 0:f50e671ffff7 19 #define DW1000_SYS_CTRL 0x0D // 4 System Control Register
manumaet 0:f50e671ffff7 20 #define DW1000_SYS_MASK 0x0E // 4 System Event Mask Register
manumaet 0:f50e671ffff7 21 #define DW1000_SYS_STATUS 0x0F // 5 System Event Status Register
manumaet 0:f50e671ffff7 22 #define DW1000_RX_FINFO 0x10 // 4 RX Frame Information (in double buffer set)
manumaet 0:f50e671ffff7 23 #define DW1000_RX_BUFFER 0x11 // 1024 Receive Data Buffer (in double buffer set)
manumaet 0:f50e671ffff7 24 #define DW1000_RX_FQUAL 0x12 // 8 Rx Frame Quality information (in double buffer set)
manumaet 0:f50e671ffff7 25 #define DW1000_RX_TTCKI 0x13 // 4 Receiver Time Tracking Interval (in double buffer set)
manumaet 0:f50e671ffff7 26 #define DW1000_RX_TTCKO 0x14 // 5 Receiver Time Tracking Offset (in double buffer set)
manumaet 0:f50e671ffff7 27 #define DW1000_RX_TIME 0x15 // 14 Receive Message Time of Arrival (in double buffer set)
manumaet 0:f50e671ffff7 28 #define DW1000_TX_TIME 0x17 // 10 Transmit Message Time of Sending (in double buffer set)
manumaet 0:f50e671ffff7 29 #define DW1000_TX_ANTD 0x18 // 2 16-bit Delay from Transmit to Antenna
manumaet 0:f50e671ffff7 30 #define DW1000_SYS_STATE 0x19 // 5 System State information
manumaet 0:f50e671ffff7 31 #define DW1000_ACK_RESP_T 0x1A // 4 Acknowledgement Time and Response Time
manumaet 0:f50e671ffff7 32 #define DW1000_RX_SNIFF 0x1D // 4 Pulsed Preamble Reception Configuration
manumaet 0:f50e671ffff7 33 #define DW1000_TX_POWER 0x1E // 4 TX Power Control
manumaet 0:f50e671ffff7 34 #define DW1000_CHAN_CTRL 0x1F // 4 Channel Control
manumaet 0:f50e671ffff7 35 #define DW1000_USR_SFD 0x21 // 41 User-specified short/long TX/RX SFD sequences
manumaet 0:f50e671ffff7 36 #define DW1000_AGC_CTRL 0x23 // 32 Automatic Gain Control configuration
manumaet 0:f50e671ffff7 37 #define DW1000_EXT_SYNC 0x24 // 12 External synchronisation control.
manumaet 0:f50e671ffff7 38 #define DW1000_ACC_MEM 0x25 // 4064 Read access to accumulator data
manumaet 0:f50e671ffff7 39 #define DW1000_GPIO_CTRL 0x26 // 44 Peripheral register bus 1 access - GPIO control
manumaet 0:f50e671ffff7 40 #define DW1000_DRX_CONF 0x27 // 44 Digital Receiver configuration
manumaet 0:f50e671ffff7 41 #define DW1000_RF_CONF 0x28 // 58 Analog RF Configuration
manumaet 0:f50e671ffff7 42 #define DW1000_TX_CAL 0x2A // 52 Transmitter calibration block
manumaet 0:f50e671ffff7 43 #define DW1000_FS_CTRL 0x2B // 21 Frequency synthesiser control block
manumaet 0:f50e671ffff7 44 #define DW1000_AON 0x2C // 12 Always-On register set
manumaet 0:f50e671ffff7 45 #define DW1000_OTP_IF 0x2D // 18 One Time Programmable Memory Interface
manumaet 0:f50e671ffff7 46 #define DW1000_LDE_CTRL 0x2E // - Leading edge detection control block
manumaet 0:f50e671ffff7 47 #define DW1000_DIG_DIAG 0x2F // 41 Digital Diagnostics Interface
manumaet 0:f50e671ffff7 48 #define DW1000_PMSC 0x36 // 48 Power Management System Control Block
manumaet 0:f50e671ffff7 49
manumaet 0:f50e671ffff7 50 #define DW1000_WRITE_FLAG 0x80 // First Bit of the address has to be 1 to indicate we want to write
manumaet 0:f50e671ffff7 51 #define DW1000_SUBADDRESS_FLAG 0x40 // if we have a sub address second Bit has to be 1
manumaet 0:f50e671ffff7 52 #define DW1000_2_SUBADDRESS_FLAG 0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part
manumaet 0:f50e671ffff7 53
manumaet 0:f50e671ffff7 54 class DW1000
manumaet 0:f50e671ffff7 55 {
manumaet 0:f50e671ffff7 56 public:
manumaet 0:f50e671ffff7 57 DW1000(PinName MOSI, PinName MISO, PinName SCLK, PinName CS); // constructor, uses SPI class
manumaet 0:f50e671ffff7 58
manumaet 0:f50e671ffff7 59 // Device API
manumaet 0:f50e671ffff7 60 uint32_t getDeviceID();
manumaet 0:f50e671ffff7 61 uint64_t getEUI();
manumaet 0:f50e671ffff7 62 void setEUI(uint64_t EUI);
manumaet 0:f50e671ffff7 63 float getVoltage();
manumaet 0:f50e671ffff7 64
manumaet 4:6240b9c7a033 65 void sendFrame(char* message, int length);
manumaet 4:6240b9c7a033 66 void resetRX();
manumaet 4:6240b9c7a033 67
manumaet 0:f50e671ffff7 68 //private:
manumaet 0:f50e671ffff7 69
manumaet 0:f50e671ffff7 70 // SPI Inteface
manumaet 0:f50e671ffff7 71 SPI spi; // SPI Bus
manumaet 0:f50e671ffff7 72 DigitalOut cs; // Slave selector for SPI-Bus (here explicitly needed to start and end SPI transactions also usable to wake up DW1000)
manumaet 0:f50e671ffff7 73
manumaet 0:f50e671ffff7 74 void readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length);
manumaet 0:f50e671ffff7 75 void writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length);
manumaet 0:f50e671ffff7 76 void setupTransaction(uint8_t reg, uint16_t subaddress, bool write); // writes bytes to SPI to setup a write or read transaction the register address and subaddress
manumaet 0:f50e671ffff7 77 void select(); // selects the only slave for a transaction
manumaet 0:f50e671ffff7 78 void deselect(); // deselects the only slave after transaction
manumaet 0:f50e671ffff7 79 };
manumaet 0:f50e671ffff7 80
manumaet 4:6240b9c7a033 81 #endif
manumaet 4:6240b9c7a033 82
manumaet 0:f50e671ffff7 83 // -------------------------------------------------------------------------------------------------------------------
manumaet 4:6240b9c7a033 84 // structure from original Driver to hold device data (to be REMOVED!)
manumaet 0:f50e671ffff7 85 typedef struct
manumaet 0:f50e671ffff7 86 {
manumaet 0:f50e671ffff7 87 uint32_t deviceID;
manumaet 0:f50e671ffff7 88 uint32_t partID ;
manumaet 0:f50e671ffff7 89 uint32_t lotID ;
manumaet 0:f50e671ffff7 90 uint8_t chan; // added chan here - used in the reading of acc
manumaet 0:f50e671ffff7 91 uint8_t longFrames ; // flag in non-standard long frame mode
manumaet 0:f50e671ffff7 92 uint32_t txFCTRL ; // keep TX_FCTRL register config
manumaet 0:f50e671ffff7 93 uint16_t rfrxDly; // rf delay (delay though the RF blocks before the signal comes out of the antenna i.e. "antenna delay")
manumaet 0:f50e671ffff7 94 uint16_t rftxDly; // rf delay (delay though the RF blocks before the signal comes out of the antenna i.e. "antenna delay")
manumaet 0:f50e671ffff7 95 uint32_t antennaDly; // antenna delay read from OTP 64 PRF value is in high 16 bits and 16M PRF in low 16 bits
manumaet 0:f50e671ffff7 96 uint8_t xtrim; // xtrim value read from OTP
manumaet 0:f50e671ffff7 97 uint32_t sysCFGreg ; // local copy of system config register
manumaet 0:f50e671ffff7 98 uint32_t txPowCfg[12]; // stores the Tx power configuration read from OTP (6 channels consecutively with PRF16 then 64, e.g. Ch 1 PRF16 is index 0 and 64 index 1)
manumaet 0:f50e671ffff7 99 uint8_t dblbuffon; // double rx buffer mode flag
manumaet 0:f50e671ffff7 100 // the dwt_isr() will only process the events that "enabled" (i.e. the ones that generate interrupt)
manumaet 0:f50e671ffff7 101 //dwt_callback_data_t cdata; // callback data structure
manumaet 0:f50e671ffff7 102
manumaet 0:f50e671ffff7 103 uint32_t states[3] ; //MP workaround debug states register
manumaet 0:f50e671ffff7 104 uint8_t statescount ;
manumaet 0:f50e671ffff7 105 uint8_t wait4resp ; //wait 4 response was set with last TX start command
manumaet 0:f50e671ffff7 106 int prfIndex ;
manumaet 0:f50e671ffff7 107
manumaet 0:f50e671ffff7 108 //void (*dwt_txcallback)(const dwt_callback_data_t *txd);
manumaet 0:f50e671ffff7 109 //void (*dwt_rxcallback)(const dwt_callback_data_t *rxd);
manumaet 0:f50e671ffff7 110
manumaet 4:6240b9c7a033 111 } dwt_local_data_t ;