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Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed
Fork of HelloWorld_IKS01A1 by
stm32f4xx_rcc.c File Reference
This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:
- Internal/external clocks, PLL, CSS and MCO configuration
- System, AHB and APB busses clocks configuration
- Peripheral clocks configuration
- Interrupts and flags management.
Go to the source code of this file.
Functions | |
void | RCC_DeInit (void) |
Resets the RCC clock configuration to the default reset state. | |
void | RCC_HSEConfig (uint8_t RCC_HSE) |
Configures the External High Speed oscillator (HSE). | |
ErrorStatus | RCC_WaitForHSEStartUp (void) |
Waits for HSE start-up. | |
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue) |
Adjusts the Internal High Speed oscillator (HSI) calibration value. | |
void | RCC_HSICmd (FunctionalState NewState) |
Enables or disables the Internal High Speed oscillator (HSI). | |
void | RCC_LSEConfig (uint8_t RCC_LSE) |
Configures the External Low Speed oscillator (LSE). | |
void | RCC_LSICmd (FunctionalState NewState) |
Enables or disables the Internal Low Speed oscillator (LSI). | |
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) |
Configures the main PLL clock source, multiplication and division factors. | |
void | RCC_PLLCmd (FunctionalState NewState) |
Enables or disables the main PLL. | |
void | RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR) |
Configures the PLLI2S clock multiplication and division factors. | |
void | RCC_PLLI2SCmd (FunctionalState NewState) |
Enables or disables the PLLI2S. | |
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState) |
Enables or disables the Clock Security System. | |
void | RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) |
Selects the clock source to output on MCO1 pin(PA8). | |
void | RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) |
Selects the clock source to output on MCO2 pin(PC9). | |
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource) |
Configures the system clock (SYSCLK). | |
uint8_t | RCC_GetSYSCLKSource (void) |
Returns the clock source used as system clock. | |
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK) |
Configures the AHB clock (HCLK). | |
void | RCC_PCLK1Config (uint32_t RCC_HCLK) |
Configures the Low Speed APB clock (PCLK1). | |
void | RCC_PCLK2Config (uint32_t RCC_HCLK) |
Configures the High Speed APB clock (PCLK2). | |
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks) |
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. | |
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource) |
Configures the RTC clock (RTCCLK). | |
void | RCC_RTCCLKCmd (FunctionalState NewState) |
Enables or disables the RTC clock. | |
void | RCC_BackupResetCmd (FunctionalState NewState) |
Forces or releases the Backup domain reset. | |
void | RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource) |
Configures the I2S clock source (I2SCLK). | |
void | RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Enables or disables the AHB1 peripheral clock. | |
void | RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Enables or disables the AHB2 peripheral clock. | |
void | RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Enables or disables the AHB3 peripheral clock. | |
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the Low Speed APB (APB1) peripheral clock. | |
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the High Speed APB (APB2) peripheral clock. | |
void | RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Forces or releases AHB1 peripheral reset. | |
void | RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Forces or releases AHB2 peripheral reset. | |
void | RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Forces or releases AHB3 peripheral reset. | |
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Forces or releases Low Speed APB (APB1) peripheral reset. | |
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Forces or releases High Speed APB (APB2) peripheral reset. | |
void | RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState) |
Enables or disables the specified RCC interrupts. | |
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG) |
Checks whether the specified RCC flag is set or not. | |
void | RCC_ClearFlag (void) |
Clears the RCC reset flags. | |
ITStatus | RCC_GetITStatus (uint8_t RCC_IT) |
Checks whether the specified RCC interrupt has occurred or not. | |
void | RCC_ClearITPendingBit (uint8_t RCC_IT) |
Clears the RCC's interrupt pending bits. |
Detailed Description
This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:
- Internal/external clocks, PLL, CSS and MCO configuration
- System, AHB and APB busses clocks configuration
- Peripheral clocks configuration
- Interrupts and flags management.
- Version:
- V1.0.0
- Date:
- 30-September-2011
* * =================================================================== * RCC specific features * =================================================================== * * After reset the device is running from Internal High Speed oscillator * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache * and I-Cache are disabled, and all peripherals are off except internal * SRAM, Flash and JTAG. * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; * all peripherals mapped on these busses are running at HSI speed. * - The clock for all peripherals is switched off, except the SRAM and FLASH. * - All GPIOs are in input floating state, except the JTAG pins which * are assigned to be used for debug purpose. * * Once the device started from reset, the user application has to: * - Configure the clock source to be used to drive the System clock * (if the application needs higher frequency/performance) * - Configure the System clock frequency and Flash settings * - Configure the AHB and APB busses prescalers * - Enable the clock for the peripheral(s) to be used * - Configure the clock source(s) for peripherals which clocks are not * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) * *
- Attention:
THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
© COPYRIGHT 2011 STMicroelectronics
Definition in file stm32f4xx_rcc.c.
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