Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial
Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed
Fork of HelloWorld_IKS01A1 by
Peripheral clocks configuration functions
[RCC_Private_Functions]
Peripheral clocks configuration functions. More...
Functions | |
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource) |
Configures the RTC clock (RTCCLK). | |
void | RCC_RTCCLKCmd (FunctionalState NewState) |
Enables or disables the RTC clock. | |
void | RCC_BackupResetCmd (FunctionalState NewState) |
Forces or releases the Backup domain reset. | |
void | RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource) |
Configures the I2S clock source (I2SCLK). | |
void | RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Enables or disables the AHB1 peripheral clock. | |
void | RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Enables or disables the AHB2 peripheral clock. | |
void | RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Enables or disables the AHB3 peripheral clock. | |
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the Low Speed APB (APB1) peripheral clock. | |
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the High Speed APB (APB2) peripheral clock. | |
void | RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Forces or releases AHB1 peripheral reset. | |
void | RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Forces or releases AHB2 peripheral reset. | |
void | RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Forces or releases AHB3 peripheral reset. | |
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Forces or releases Low Speed APB (APB1) peripheral reset. | |
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Forces or releases High Speed APB (APB2) peripheral reset. | |
void | RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState) |
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState) |
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState) |
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. | |
void | RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. |
Detailed Description
Peripheral clocks configuration functions.
=============================================================================== Peripheral clocks configuration functions =============================================================================== This section provide functions allowing to configure the Peripheral clocks. 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. 2. After restart from Reset or wakeup from STANDBY, all peripherals are off except internal SRAM, Flash and JTAG. Before to start using a peripheral you have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. 3. To reset the peripherals configuration (to the default state after device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions. 4. To further reduce power consumption in SLEEP mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. You can do this using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
Function Documentation
void RCC_AHB1PeriphClockCmd | ( | uint32_t | RCC_AHB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB1 peripheral clock.
- Note:
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
- Parameters:
-
RCC_AHBPeriph,: specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_AHB1Periph_GPIOA: GPIOA clock
- RCC_AHB1Periph_GPIOB: GPIOB clock
- RCC_AHB1Periph_GPIOC: GPIOC clock
- RCC_AHB1Periph_GPIOD: GPIOD clock
- RCC_AHB1Periph_GPIOE: GPIOE clock
- RCC_AHB1Periph_GPIOF: GPIOF clock
- RCC_AHB1Periph_GPIOG: GPIOG clock
- RCC_AHB1Periph_GPIOG: GPIOG clock
- RCC_AHB1Periph_GPIOI: GPIOI clock
- RCC_AHB1Periph_CRC: CRC clock
- RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
- RCC_AHB1Periph_DMA1: DMA1 clock
- RCC_AHB1Periph_DMA2: DMA2 clock
- RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1085 of file stm32f4xx_rcc.c.
void RCC_AHB1PeriphClockLPModeCmd | ( | uint32_t | RCC_AHB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
- Note:
- Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
- After wakeup from SLEEP mode, the peripheral clock is enabled again.
- By default, all peripheral clocks are enabled during SLEEP mode.
- Parameters:
-
RCC_AHBPeriph,: specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_AHB1Periph_GPIOA: GPIOA clock
- RCC_AHB1Periph_GPIOB: GPIOB clock
- RCC_AHB1Periph_GPIOC: GPIOC clock
- RCC_AHB1Periph_GPIOD: GPIOD clock
- RCC_AHB1Periph_GPIOE: GPIOE clock
- RCC_AHB1Periph_GPIOF: GPIOF clock
- RCC_AHB1Periph_GPIOG: GPIOG clock
- RCC_AHB1Periph_GPIOG: GPIOG clock
- RCC_AHB1Periph_GPIOI: GPIOI clock
- RCC_AHB1Periph_CRC: CRC clock
- RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
- RCC_AHB1Periph_DMA1: DMA1 clock
- RCC_AHB1Periph_DMA2: DMA2 clock
- RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
- RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
- RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
- RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1455 of file stm32f4xx_rcc.c.
void RCC_AHB1PeriphResetCmd | ( | uint32_t | RCC_AHB1Periph, |
FunctionalState | NewState | ||
) |
Forces or releases AHB1 peripheral reset.
- Parameters:
-
RCC_AHB1Periph,: specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values: - RCC_AHB1Periph_GPIOA: GPIOA clock
- RCC_AHB1Periph_GPIOB: GPIOB clock
- RCC_AHB1Periph_GPIOC: GPIOC clock
- RCC_AHB1Periph_GPIOD: GPIOD clock
- RCC_AHB1Periph_GPIOE: GPIOE clock
- RCC_AHB1Periph_GPIOF: GPIOF clock
- RCC_AHB1Periph_GPIOG: GPIOG clock
- RCC_AHB1Periph_GPIOG: GPIOG clock
- RCC_AHB1Periph_GPIOI: GPIOI clock
- RCC_AHB1Periph_CRC: CRC clock
- RCC_AHB1Periph_DMA1: DMA1 clock
- RCC_AHB1Periph_DMA2: DMA2 clock
- RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
- RCC_AHB1Periph_OTG_HS: USB OTG HS clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1273 of file stm32f4xx_rcc.c.
void RCC_AHB2PeriphClockCmd | ( | uint32_t | RCC_AHB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB2 peripheral clock.
- Note:
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
- Parameters:
-
RCC_AHBPeriph,: specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_AHB2Periph_DCMI: DCMI clock
- RCC_AHB2Periph_CRYP: CRYP clock
- RCC_AHB2Periph_HASH: HASH clock
- RCC_AHB2Periph_RNG: RNG clock
- RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1117 of file stm32f4xx_rcc.c.
void RCC_AHB2PeriphClockLPModeCmd | ( | uint32_t | RCC_AHB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
- Note:
- Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
- After wakeup from SLEEP mode, the peripheral clock is enabled again.
- By default, all peripheral clocks are enabled during SLEEP mode.
- Parameters:
-
RCC_AHBPeriph,: specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_AHB2Periph_DCMI: DCMI clock
- RCC_AHB2Periph_CRYP: CRYP clock
- RCC_AHB2Periph_HASH: HASH clock
- RCC_AHB2Periph_RNG: RNG clock
- RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1487 of file stm32f4xx_rcc.c.
void RCC_AHB2PeriphResetCmd | ( | uint32_t | RCC_AHB2Periph, |
FunctionalState | NewState | ||
) |
Forces or releases AHB2 peripheral reset.
- Parameters:
-
RCC_AHB2Periph,: specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values: - RCC_AHB2Periph_DCMI: DCMI clock
- RCC_AHB2Periph_CRYP: CRYP clock
- RCC_AHB2Periph_HASH: HASH clock
- RCC_AHB2Periph_RNG: RNG clock
- RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1302 of file stm32f4xx_rcc.c.
void RCC_AHB3PeriphClockCmd | ( | uint32_t | RCC_AHB3Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB3 peripheral clock.
- Note:
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
- Parameters:
-
RCC_AHBPeriph,: specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1144 of file stm32f4xx_rcc.c.
void RCC_AHB3PeriphClockLPModeCmd | ( | uint32_t | RCC_AHB3Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- Note:
- Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
- After wakeup from SLEEP mode, the peripheral clock is enabled again.
- By default, all peripheral clocks are enabled during SLEEP mode.
- Parameters:
-
RCC_AHBPeriph,: specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1514 of file stm32f4xx_rcc.c.
void RCC_AHB3PeriphResetCmd | ( | uint32_t | RCC_AHB3Periph, |
FunctionalState | NewState | ||
) |
Forces or releases AHB3 peripheral reset.
- Parameters:
-
RCC_AHB3Periph,: specifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1326 of file stm32f4xx_rcc.c.
void RCC_APB1PeriphClockCmd | ( | uint32_t | RCC_APB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the Low Speed APB (APB1) peripheral clock.
- Note:
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
- Parameters:
-
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_APB1Periph_TIM2: TIM2 clock
- RCC_APB1Periph_TIM3: TIM3 clock
- RCC_APB1Periph_TIM4: TIM4 clock
- RCC_APB1Periph_TIM5: TIM5 clock
- RCC_APB1Periph_TIM6: TIM6 clock
- RCC_APB1Periph_TIM7: TIM7 clock
- RCC_APB1Periph_TIM12: TIM12 clock
- RCC_APB1Periph_TIM13: TIM13 clock
- RCC_APB1Periph_TIM14: TIM14 clock
- RCC_APB1Periph_WWDG: WWDG clock
- RCC_APB1Periph_SPI2: SPI2 clock
- RCC_APB1Periph_SPI3: SPI3 clock
- RCC_APB1Periph_USART2: USART2 clock
- RCC_APB1Periph_USART3: USART3 clock
- RCC_APB1Periph_UART4: UART4 clock
- RCC_APB1Periph_UART5: UART5 clock
- RCC_APB1Periph_I2C1: I2C1 clock
- RCC_APB1Periph_I2C2: I2C2 clock
- RCC_APB1Periph_I2C3: I2C3 clock
- RCC_APB1Periph_CAN1: CAN1 clock
- RCC_APB1Periph_CAN2: CAN2 clock
- RCC_APB1Periph_PWR: PWR clock
- RCC_APB1Periph_DAC: DAC clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1194 of file stm32f4xx_rcc.c.
void RCC_APB1PeriphClockLPModeCmd | ( | uint32_t | RCC_APB1Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
- Note:
- Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
- After wakeup from SLEEP mode, the peripheral clock is enabled again.
- By default, all peripheral clocks are enabled during SLEEP mode.
- Parameters:
-
RCC_APB1Periph,: specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_APB1Periph_TIM2: TIM2 clock
- RCC_APB1Periph_TIM3: TIM3 clock
- RCC_APB1Periph_TIM4: TIM4 clock
- RCC_APB1Periph_TIM5: TIM5 clock
- RCC_APB1Periph_TIM6: TIM6 clock
- RCC_APB1Periph_TIM7: TIM7 clock
- RCC_APB1Periph_TIM12: TIM12 clock
- RCC_APB1Periph_TIM13: TIM13 clock
- RCC_APB1Periph_TIM14: TIM14 clock
- RCC_APB1Periph_WWDG: WWDG clock
- RCC_APB1Periph_SPI2: SPI2 clock
- RCC_APB1Periph_SPI3: SPI3 clock
- RCC_APB1Periph_USART2: USART2 clock
- RCC_APB1Periph_USART3: USART3 clock
- RCC_APB1Periph_UART4: UART4 clock
- RCC_APB1Periph_UART5: UART5 clock
- RCC_APB1Periph_I2C1: I2C1 clock
- RCC_APB1Periph_I2C2: I2C2 clock
- RCC_APB1Periph_I2C3: I2C3 clock
- RCC_APB1Periph_CAN1: CAN1 clock
- RCC_APB1Periph_CAN2: CAN2 clock
- RCC_APB1Periph_PWR: PWR clock
- RCC_APB1Periph_DAC: DAC clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1564 of file stm32f4xx_rcc.c.
void RCC_APB1PeriphResetCmd | ( | uint32_t | RCC_APB1Periph, |
FunctionalState | NewState | ||
) |
Forces or releases Low Speed APB (APB1) peripheral reset.
- Parameters:
-
RCC_APB1Periph,: specifies the APB1 peripheral to reset. This parameter can be any combination of the following values: - RCC_APB1Periph_TIM2: TIM2 clock
- RCC_APB1Periph_TIM3: TIM3 clock
- RCC_APB1Periph_TIM4: TIM4 clock
- RCC_APB1Periph_TIM5: TIM5 clock
- RCC_APB1Periph_TIM6: TIM6 clock
- RCC_APB1Periph_TIM7: TIM7 clock
- RCC_APB1Periph_TIM12: TIM12 clock
- RCC_APB1Periph_TIM13: TIM13 clock
- RCC_APB1Periph_TIM14: TIM14 clock
- RCC_APB1Periph_WWDG: WWDG clock
- RCC_APB1Periph_SPI2: SPI2 clock
- RCC_APB1Periph_SPI3: SPI3 clock
- RCC_APB1Periph_USART2: USART2 clock
- RCC_APB1Periph_USART3: USART3 clock
- RCC_APB1Periph_UART4: UART4 clock
- RCC_APB1Periph_UART5: UART5 clock
- RCC_APB1Periph_I2C1: I2C1 clock
- RCC_APB1Periph_I2C2: I2C2 clock
- RCC_APB1Periph_I2C3: I2C3 clock
- RCC_APB1Periph_CAN1: CAN1 clock
- RCC_APB1Periph_CAN2: CAN2 clock
- RCC_APB1Periph_PWR: PWR clock
- RCC_APB1Periph_DAC: DAC clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1373 of file stm32f4xx_rcc.c.
void RCC_APB2PeriphClockCmd | ( | uint32_t | RCC_APB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the High Speed APB (APB2) peripheral clock.
- Note:
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
- Parameters:
-
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_APB2Periph_TIM1: TIM1 clock
- RCC_APB2Periph_TIM8: TIM8 clock
- RCC_APB2Periph_USART1: USART1 clock
- RCC_APB2Periph_USART6: USART6 clock
- RCC_APB2Periph_ADC1: ADC1 clock
- RCC_APB2Periph_ADC2: ADC2 clock
- RCC_APB2Periph_ADC3: ADC3 clock
- RCC_APB2Periph_SDIO: SDIO clock
- RCC_APB2Periph_SPI1: SPI1 clock
- RCC_APB2Periph_SYSCFG: SYSCFG clock
- RCC_APB2Periph_TIM9: TIM9 clock
- RCC_APB2Periph_TIM10: TIM10 clock
- RCC_APB2Periph_TIM11: TIM11 clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1234 of file stm32f4xx_rcc.c.
void RCC_APB2PeriphClockLPModeCmd | ( | uint32_t | RCC_APB2Periph, |
FunctionalState | NewState | ||
) |
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
- Note:
- Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
- After wakeup from SLEEP mode, the peripheral clock is enabled again.
- By default, all peripheral clocks are enabled during SLEEP mode.
- Parameters:
-
RCC_APB2Periph,: specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: - RCC_APB2Periph_TIM1: TIM1 clock
- RCC_APB2Periph_TIM8: TIM8 clock
- RCC_APB2Periph_USART1: USART1 clock
- RCC_APB2Periph_USART6: USART6 clock
- RCC_APB2Periph_ADC1: ADC1 clock
- RCC_APB2Periph_ADC2: ADC2 clock
- RCC_APB2Periph_ADC3: ADC3 clock
- RCC_APB2Periph_SDIO: SDIO clock
- RCC_APB2Periph_SPI1: SPI1 clock
- RCC_APB2Periph_SYSCFG: SYSCFG clock
- RCC_APB2Periph_TIM9: TIM9 clock
- RCC_APB2Periph_TIM10: TIM10 clock
- RCC_APB2Periph_TIM11: TIM11 clock
NewState,: new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1604 of file stm32f4xx_rcc.c.
void RCC_APB2PeriphResetCmd | ( | uint32_t | RCC_APB2Periph, |
FunctionalState | NewState | ||
) |
Forces or releases High Speed APB (APB2) peripheral reset.
- Parameters:
-
RCC_APB2Periph,: specifies the APB2 peripheral to reset. This parameter can be any combination of the following values: - RCC_APB2Periph_TIM1: TIM1 clock
- RCC_APB2Periph_TIM8: TIM8 clock
- RCC_APB2Periph_USART1: USART1 clock
- RCC_APB2Periph_USART6: USART6 clock
- RCC_APB2Periph_ADC1: ADC1 clock
- RCC_APB2Periph_ADC2: ADC2 clock
- RCC_APB2Periph_ADC3: ADC3 clock
- RCC_APB2Periph_SDIO: SDIO clock
- RCC_APB2Periph_SPI1: SPI1 clock
- RCC_APB2Periph_SYSCFG: SYSCFG clock
- RCC_APB2Periph_TIM9: TIM9 clock
- RCC_APB2Periph_TIM10: TIM10 clock
- RCC_APB2Periph_TIM11: TIM11 clock
NewState,: new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1409 of file stm32f4xx_rcc.c.
void RCC_BackupResetCmd | ( | FunctionalState | NewState ) |
Forces or releases the Backup domain reset.
- Note:
- This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
- The BKPSRAM is not affected by this reset.
- Parameters:
-
NewState,: new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1029 of file stm32f4xx_rcc.c.
void RCC_I2SCLKConfig | ( | uint32_t | RCC_I2SCLKSource ) |
Configures the I2S clock source (I2SCLK).
- Note:
- This function must be called before enabling the I2S APB clock.
- Parameters:
-
RCC_I2SCLKSource,: specifies the I2S clock source. This parameter can be one of the following values: - RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
- RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
- Return values:
-
None
Definition at line 1046 of file stm32f4xx_rcc.c.
void RCC_RTCCLKCmd | ( | FunctionalState | NewState ) |
Enables or disables the RTC clock.
- Note:
- This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
- Parameters:
-
NewState,: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
- Return values:
-
None
Definition at line 1012 of file stm32f4xx_rcc.c.
void RCC_RTCCLKConfig | ( | uint32_t | RCC_RTCCLKSource ) |
Configures the RTC clock (RTCCLK).
- Note:
- As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
- Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).
- Parameters:
-
RCC_RTCCLKSource,: specifies the RTC clock source. This parameter can be one of the following values: - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]
- Note:
- If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
- The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
- Return values:
-
None
Definition at line 980 of file stm32f4xx_rcc.c.
Generated on Tue Jul 12 2022 19:53:13 by 1.7.2