HelloWorld_IKS01A1 - Simple "hello world" style program for X-NUCLEO-I…

Users » n0tform3 » Code » HelloWorld_IKS01A1

mattia griotti / Mbed 2 deprecated HelloWorld_IKS01A1

Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial

Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed

stm32f4xx_tim.c@8:1c6281289d67, 2015-11-15 (annotated)

Committer:: n0tform3
Date:: Sun Nov 15 09:00:40 2015 +0000
Revision:: 8:1c6281289d67

test with led

Who changed what in which revision?

User	Revision	Line number	New contents of line
n0tform3	8:1c6281289d67	1	/**
n0tform3	8:1c6281289d67	2	******************************************************************************
n0tform3	8:1c6281289d67	3	* @file stm32f4xx_tim.c
n0tform3	8:1c6281289d67	4	* @author MCD Application Team
n0tform3	8:1c6281289d67	5	* @version V1.0.0
n0tform3	8:1c6281289d67	6	* @date 30-September-2011
n0tform3	8:1c6281289d67	7	* @brief This file provides firmware functions to manage the following
n0tform3	8:1c6281289d67	8	* functionalities of the TIM peripheral:
n0tform3	8:1c6281289d67	9	* - TimeBase management
n0tform3	8:1c6281289d67	10	* - Output Compare management
n0tform3	8:1c6281289d67	11	* - Input Capture management
n0tform3	8:1c6281289d67	12	* - Advanced-control timers (TIM1 and TIM8) specific features
n0tform3	8:1c6281289d67	13	* - Interrupts, DMA and flags management
n0tform3	8:1c6281289d67	14	* - Clocks management
n0tform3	8:1c6281289d67	15	* - Synchronization management
n0tform3	8:1c6281289d67	16	* - Specific interface management
n0tform3	8:1c6281289d67	17	* - Specific remapping management
n0tform3	8:1c6281289d67	18	*
n0tform3	8:1c6281289d67	19	* @verbatim
n0tform3	8:1c6281289d67	20	*
n0tform3	8:1c6281289d67	21	* ===================================================================
n0tform3	8:1c6281289d67	22	* How to use this driver
n0tform3	8:1c6281289d67	23	* ===================================================================
n0tform3	8:1c6281289d67	24	* This driver provides functions to configure and program the TIM
n0tform3	8:1c6281289d67	25	* of all STM32F4xx devices.
n0tform3	8:1c6281289d67	26	* These functions are split in 9 groups:
n0tform3	8:1c6281289d67	27	*
n0tform3	8:1c6281289d67	28	* 1. TIM TimeBase management: this group includes all needed functions
n0tform3	8:1c6281289d67	29	* to configure the TM Timebase unit:
n0tform3	8:1c6281289d67	30	* - Set/Get Prescaler
n0tform3	8:1c6281289d67	31	* - Set/Get Autoreload
n0tform3	8:1c6281289d67	32	* - Counter modes configuration
n0tform3	8:1c6281289d67	33	* - Set Clock division
n0tform3	8:1c6281289d67	34	* - Select the One Pulse mode
n0tform3	8:1c6281289d67	35	* - Update Request Configuration
n0tform3	8:1c6281289d67	36	* - Update Disable Configuration
n0tform3	8:1c6281289d67	37	* - Auto-Preload Configuration
n0tform3	8:1c6281289d67	38	* - Enable/Disable the counter
n0tform3	8:1c6281289d67	39	*
n0tform3	8:1c6281289d67	40	* 2. TIM Output Compare management: this group includes all needed
n0tform3	8:1c6281289d67	41	* functions to configure the Capture/Compare unit used in Output
n0tform3	8:1c6281289d67	42	* compare mode:
n0tform3	8:1c6281289d67	43	* - Configure each channel, independently, in Output Compare mode
n0tform3	8:1c6281289d67	44	* - Select the output compare modes
n0tform3	8:1c6281289d67	45	* - Select the Polarities of each channel
n0tform3	8:1c6281289d67	46	* - Set/Get the Capture/Compare register values
n0tform3	8:1c6281289d67	47	* - Select the Output Compare Fast mode
n0tform3	8:1c6281289d67	48	* - Select the Output Compare Forced mode
n0tform3	8:1c6281289d67	49	* - Output Compare-Preload Configuration
n0tform3	8:1c6281289d67	50	* - Clear Output Compare Reference
n0tform3	8:1c6281289d67	51	* - Select the OCREF Clear signal
n0tform3	8:1c6281289d67	52	* - Enable/Disable the Capture/Compare Channels
n0tform3	8:1c6281289d67	53	*
n0tform3	8:1c6281289d67	54	* 3. TIM Input Capture management: this group includes all needed
n0tform3	8:1c6281289d67	55	* functions to configure the Capture/Compare unit used in
n0tform3	8:1c6281289d67	56	* Input Capture mode:
n0tform3	8:1c6281289d67	57	* - Configure each channel in input capture mode
n0tform3	8:1c6281289d67	58	* - Configure Channel1/2 in PWM Input mode
n0tform3	8:1c6281289d67	59	* - Set the Input Capture Prescaler
n0tform3	8:1c6281289d67	60	* - Get the Capture/Compare values
n0tform3	8:1c6281289d67	61	*
n0tform3	8:1c6281289d67	62	* 4. Advanced-control timers (TIM1 and TIM8) specific features
n0tform3	8:1c6281289d67	63	* - Configures the Break input, dead time, Lock level, the OSSI,
n0tform3	8:1c6281289d67	64	* the OSSR State and the AOE(automatic output enable)
n0tform3	8:1c6281289d67	65	* - Enable/Disable the TIM peripheral Main Outputs
n0tform3	8:1c6281289d67	66	* - Select the Commutation event
n0tform3	8:1c6281289d67	67	* - Set/Reset the Capture Compare Preload Control bit
n0tform3	8:1c6281289d67	68	*
n0tform3	8:1c6281289d67	69	* 5. TIM interrupts, DMA and flags management
n0tform3	8:1c6281289d67	70	* - Enable/Disable interrupt sources
n0tform3	8:1c6281289d67	71	* - Get flags status
n0tform3	8:1c6281289d67	72	* - Clear flags/ Pending bits
n0tform3	8:1c6281289d67	73	* - Enable/Disable DMA requests
n0tform3	8:1c6281289d67	74	* - Configure DMA burst mode
n0tform3	8:1c6281289d67	75	* - Select CaptureCompare DMA request
n0tform3	8:1c6281289d67	76	*
n0tform3	8:1c6281289d67	77	* 6. TIM clocks management: this group includes all needed functions
n0tform3	8:1c6281289d67	78	* to configure the clock controller unit:
n0tform3	8:1c6281289d67	79	* - Select internal/External clock
n0tform3	8:1c6281289d67	80	* - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
n0tform3	8:1c6281289d67	81	*
n0tform3	8:1c6281289d67	82	* 7. TIM synchronization management: this group includes all needed
n0tform3	8:1c6281289d67	83	* functions to configure the Synchronization unit:
n0tform3	8:1c6281289d67	84	* - Select Input Trigger
n0tform3	8:1c6281289d67	85	* - Select Output Trigger
n0tform3	8:1c6281289d67	86	* - Select Master Slave Mode
n0tform3	8:1c6281289d67	87	* - ETR Configuration when used as external trigger
n0tform3	8:1c6281289d67	88	*
n0tform3	8:1c6281289d67	89	* 8. TIM specific interface management, this group includes all
n0tform3	8:1c6281289d67	90	* needed functions to use the specific TIM interface:
n0tform3	8:1c6281289d67	91	* - Encoder Interface Configuration
n0tform3	8:1c6281289d67	92	* - Select Hall Sensor
n0tform3	8:1c6281289d67	93	*
n0tform3	8:1c6281289d67	94	* 9. TIM specific remapping management includes the Remapping
n0tform3	8:1c6281289d67	95	* configuration of specific timers
n0tform3	8:1c6281289d67	96	*
n0tform3	8:1c6281289d67	97	* @endverbatim
n0tform3	8:1c6281289d67	98	*
n0tform3	8:1c6281289d67	99	******************************************************************************
n0tform3	8:1c6281289d67	100	* @attention
n0tform3	8:1c6281289d67	101	*
n0tform3	8:1c6281289d67	102	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
n0tform3	8:1c6281289d67	103	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
n0tform3	8:1c6281289d67	104	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
n0tform3	8:1c6281289d67	105	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
n0tform3	8:1c6281289d67	106	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
n0tform3	8:1c6281289d67	107	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
n0tform3	8:1c6281289d67	108	*
n0tform3	8:1c6281289d67	109	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
n0tform3	8:1c6281289d67	110	******************************************************************************
n0tform3	8:1c6281289d67	111	*/
n0tform3	8:1c6281289d67	112
n0tform3	8:1c6281289d67	113	/* Includes ------------------------------------------------------------------*/
n0tform3	8:1c6281289d67	114	#include "stm32f4xx_tim.h"
n0tform3	8:1c6281289d67	115	#include "stm32f4xx_rcc.h"
n0tform3	8:1c6281289d67	116
n0tform3	8:1c6281289d67	117	/** @addtogroup STM32F4xx_StdPeriph_Driver
n0tform3	8:1c6281289d67	118	* @{
n0tform3	8:1c6281289d67	119	*/
n0tform3	8:1c6281289d67	120
n0tform3	8:1c6281289d67	121	/** @defgroup TIM
n0tform3	8:1c6281289d67	122	* @brief TIM driver modules
n0tform3	8:1c6281289d67	123	* @{
n0tform3	8:1c6281289d67	124	*/
n0tform3	8:1c6281289d67	125
n0tform3	8:1c6281289d67	126	/* Private typedef -----------------------------------------------------------*/
n0tform3	8:1c6281289d67	127	/* Private define ------------------------------------------------------------*/
n0tform3	8:1c6281289d67	128
n0tform3	8:1c6281289d67	129	/* ---------------------- TIM registers bit mask ------------------------ */
n0tform3	8:1c6281289d67	130	#define SMCR_ETR_MASK ((uint16_t)0x00FF)
n0tform3	8:1c6281289d67	131	#define CCMR_OFFSET ((uint16_t)0x0018)
n0tform3	8:1c6281289d67	132	#define CCER_CCE_SET ((uint16_t)0x0001)
n0tform3	8:1c6281289d67	133	#define CCER_CCNE_SET ((uint16_t)0x0004)
n0tform3	8:1c6281289d67	134	#define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
n0tform3	8:1c6281289d67	135	#define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
n0tform3	8:1c6281289d67	136
n0tform3	8:1c6281289d67	137	/* Private macro -------------------------------------------------------------*/
n0tform3	8:1c6281289d67	138	/* Private variables ---------------------------------------------------------*/
n0tform3	8:1c6281289d67	139	/* Private function prototypes -----------------------------------------------*/
n0tform3	8:1c6281289d67	140	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	141	uint16_t TIM_ICFilter);
n0tform3	8:1c6281289d67	142	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	143	uint16_t TIM_ICFilter);
n0tform3	8:1c6281289d67	144	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	145	uint16_t TIM_ICFilter);
n0tform3	8:1c6281289d67	146	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	147	uint16_t TIM_ICFilter);
n0tform3	8:1c6281289d67	148
n0tform3	8:1c6281289d67	149	/* Private functions ---------------------------------------------------------*/
n0tform3	8:1c6281289d67	150
n0tform3	8:1c6281289d67	151	/** @defgroup TIM_Private_Functions
n0tform3	8:1c6281289d67	152	* @{
n0tform3	8:1c6281289d67	153	*/
n0tform3	8:1c6281289d67	154
n0tform3	8:1c6281289d67	155	/** @defgroup TIM_Group1 TimeBase management functions
n0tform3	8:1c6281289d67	156	* @brief TimeBase management functions
n0tform3	8:1c6281289d67	157	*
n0tform3	8:1c6281289d67	158	@verbatim
n0tform3	8:1c6281289d67	159	===============================================================================
n0tform3	8:1c6281289d67	160	TimeBase management functions
n0tform3	8:1c6281289d67	161	===============================================================================
n0tform3	8:1c6281289d67	162
n0tform3	8:1c6281289d67	163	===================================================================
n0tform3	8:1c6281289d67	164	TIM Driver: how to use it in Timing(Time base) Mode
n0tform3	8:1c6281289d67	165	===================================================================
n0tform3	8:1c6281289d67	166	To use the Timer in Timing(Time base) mode, the following steps are mandatory:
n0tform3	8:1c6281289d67	167
n0tform3	8:1c6281289d67	168	1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
n0tform3	8:1c6281289d67	169
n0tform3	8:1c6281289d67	170	2. Fill the TIM_TimeBaseInitStruct with the desired parameters.
n0tform3	8:1c6281289d67	171
n0tform3	8:1c6281289d67	172	3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
n0tform3	8:1c6281289d67	173	with the corresponding configuration
n0tform3	8:1c6281289d67	174
n0tform3	8:1c6281289d67	175	4. Enable the NVIC if you need to generate the update interrupt.
n0tform3	8:1c6281289d67	176
n0tform3	8:1c6281289d67	177	5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
n0tform3	8:1c6281289d67	178
n0tform3	8:1c6281289d67	179	6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
n0tform3	8:1c6281289d67	180
n0tform3	8:1c6281289d67	181	Note1: All other functions can be used separately to modify, if needed,
n0tform3	8:1c6281289d67	182	a specific feature of the Timer.
n0tform3	8:1c6281289d67	183
n0tform3	8:1c6281289d67	184	@endverbatim
n0tform3	8:1c6281289d67	185	* @{
n0tform3	8:1c6281289d67	186	*/
n0tform3	8:1c6281289d67	187
n0tform3	8:1c6281289d67	188	/**
n0tform3	8:1c6281289d67	189	* @brief Deinitializes the TIMx peripheral registers to their default reset values.
n0tform3	8:1c6281289d67	190	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	191	* @retval None
n0tform3	8:1c6281289d67	192
n0tform3	8:1c6281289d67	193	*/
n0tform3	8:1c6281289d67	194	void TIM_DeInit(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	195	{
n0tform3	8:1c6281289d67	196	/* Check the parameters */
n0tform3	8:1c6281289d67	197	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	198
n0tform3	8:1c6281289d67	199	if (TIMx == TIM1)
n0tform3	8:1c6281289d67	200	{
n0tform3	8:1c6281289d67	201	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
n0tform3	8:1c6281289d67	202	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
n0tform3	8:1c6281289d67	203	}
n0tform3	8:1c6281289d67	204	else if (TIMx == TIM2)
n0tform3	8:1c6281289d67	205	{
n0tform3	8:1c6281289d67	206	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
n0tform3	8:1c6281289d67	207	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
n0tform3	8:1c6281289d67	208	}
n0tform3	8:1c6281289d67	209	else if (TIMx == TIM3)
n0tform3	8:1c6281289d67	210	{
n0tform3	8:1c6281289d67	211	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
n0tform3	8:1c6281289d67	212	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
n0tform3	8:1c6281289d67	213	}
n0tform3	8:1c6281289d67	214	else if (TIMx == TIM4)
n0tform3	8:1c6281289d67	215	{
n0tform3	8:1c6281289d67	216	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
n0tform3	8:1c6281289d67	217	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
n0tform3	8:1c6281289d67	218	}
n0tform3	8:1c6281289d67	219	else if (TIMx == TIM5)
n0tform3	8:1c6281289d67	220	{
n0tform3	8:1c6281289d67	221	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
n0tform3	8:1c6281289d67	222	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
n0tform3	8:1c6281289d67	223	}
n0tform3	8:1c6281289d67	224	else if (TIMx == TIM6)
n0tform3	8:1c6281289d67	225	{
n0tform3	8:1c6281289d67	226	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
n0tform3	8:1c6281289d67	227	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
n0tform3	8:1c6281289d67	228	}
n0tform3	8:1c6281289d67	229	else if (TIMx == TIM7)
n0tform3	8:1c6281289d67	230	{
n0tform3	8:1c6281289d67	231	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
n0tform3	8:1c6281289d67	232	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
n0tform3	8:1c6281289d67	233	}
n0tform3	8:1c6281289d67	234	else if (TIMx == TIM8)
n0tform3	8:1c6281289d67	235	{
n0tform3	8:1c6281289d67	236	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
n0tform3	8:1c6281289d67	237	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
n0tform3	8:1c6281289d67	238	}
n0tform3	8:1c6281289d67	239	else if (TIMx == TIM9)
n0tform3	8:1c6281289d67	240	{
n0tform3	8:1c6281289d67	241	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
n0tform3	8:1c6281289d67	242	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
n0tform3	8:1c6281289d67	243	}
n0tform3	8:1c6281289d67	244	else if (TIMx == TIM10)
n0tform3	8:1c6281289d67	245	{
n0tform3	8:1c6281289d67	246	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
n0tform3	8:1c6281289d67	247	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
n0tform3	8:1c6281289d67	248	}
n0tform3	8:1c6281289d67	249	else if (TIMx == TIM11)
n0tform3	8:1c6281289d67	250	{
n0tform3	8:1c6281289d67	251	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
n0tform3	8:1c6281289d67	252	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
n0tform3	8:1c6281289d67	253	}
n0tform3	8:1c6281289d67	254	else if (TIMx == TIM12)
n0tform3	8:1c6281289d67	255	{
n0tform3	8:1c6281289d67	256	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
n0tform3	8:1c6281289d67	257	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
n0tform3	8:1c6281289d67	258	}
n0tform3	8:1c6281289d67	259	else if (TIMx == TIM13)
n0tform3	8:1c6281289d67	260	{
n0tform3	8:1c6281289d67	261	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
n0tform3	8:1c6281289d67	262	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
n0tform3	8:1c6281289d67	263	}
n0tform3	8:1c6281289d67	264	else
n0tform3	8:1c6281289d67	265	{
n0tform3	8:1c6281289d67	266	if (TIMx == TIM14)
n0tform3	8:1c6281289d67	267	{
n0tform3	8:1c6281289d67	268	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
n0tform3	8:1c6281289d67	269	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
n0tform3	8:1c6281289d67	270	}
n0tform3	8:1c6281289d67	271	}
n0tform3	8:1c6281289d67	272	}
n0tform3	8:1c6281289d67	273
n0tform3	8:1c6281289d67	274	/**
n0tform3	8:1c6281289d67	275	* @brief Initializes the TIMx Time Base Unit peripheral according to
n0tform3	8:1c6281289d67	276	* the specified parameters in the TIM_TimeBaseInitStruct.
n0tform3	8:1c6281289d67	277	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	278	* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
n0tform3	8:1c6281289d67	279	* that contains the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	280	* @retval None
n0tform3	8:1c6281289d67	281	*/
n0tform3	8:1c6281289d67	282	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
n0tform3	8:1c6281289d67	283	{
n0tform3	8:1c6281289d67	284	uint16_t tmpcr1 = 0;
n0tform3	8:1c6281289d67	285
n0tform3	8:1c6281289d67	286	/* Check the parameters */
n0tform3	8:1c6281289d67	287	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	288	assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
n0tform3	8:1c6281289d67	289	assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
n0tform3	8:1c6281289d67	290
n0tform3	8:1c6281289d67	291	tmpcr1 = TIMx->CR1;
n0tform3	8:1c6281289d67	292
n0tform3	8:1c6281289d67	293	if((TIMx == TIM1) \|\| (TIMx == TIM8)\|\|
n0tform3	8:1c6281289d67	294	(TIMx == TIM2) \|\| (TIMx == TIM3)\|\|
n0tform3	8:1c6281289d67	295	(TIMx == TIM4) \|\| (TIMx == TIM5))
n0tform3	8:1c6281289d67	296	{
n0tform3	8:1c6281289d67	297	/* Select the Counter Mode */
n0tform3	8:1c6281289d67	298	tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR \| TIM_CR1_CMS));
n0tform3	8:1c6281289d67	299	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
n0tform3	8:1c6281289d67	300	}
n0tform3	8:1c6281289d67	301
n0tform3	8:1c6281289d67	302	if((TIMx != TIM6) && (TIMx != TIM7))
n0tform3	8:1c6281289d67	303	{
n0tform3	8:1c6281289d67	304	/* Set the clock division */
n0tform3	8:1c6281289d67	305	tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
n0tform3	8:1c6281289d67	306	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
n0tform3	8:1c6281289d67	307	}
n0tform3	8:1c6281289d67	308
n0tform3	8:1c6281289d67	309	TIMx->CR1 = tmpcr1;
n0tform3	8:1c6281289d67	310
n0tform3	8:1c6281289d67	311	/* Set the Autoreload value */
n0tform3	8:1c6281289d67	312	TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
n0tform3	8:1c6281289d67	313
n0tform3	8:1c6281289d67	314	/* Set the Prescaler value */
n0tform3	8:1c6281289d67	315	TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
n0tform3	8:1c6281289d67	316
n0tform3	8:1c6281289d67	317	if ((TIMx == TIM1) \|\| (TIMx == TIM8))
n0tform3	8:1c6281289d67	318	{
n0tform3	8:1c6281289d67	319	/* Set the Repetition Counter value */
n0tform3	8:1c6281289d67	320	TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
n0tform3	8:1c6281289d67	321	}
n0tform3	8:1c6281289d67	322
n0tform3	8:1c6281289d67	323	/* Generate an update event to reload the Prescaler
n0tform3	8:1c6281289d67	324	and the repetition counter(only for TIM1 and TIM8) value immediatly */
n0tform3	8:1c6281289d67	325	TIMx->EGR = TIM_PSCReloadMode_Immediate;
n0tform3	8:1c6281289d67	326	}
n0tform3	8:1c6281289d67	327
n0tform3	8:1c6281289d67	328	/**
n0tform3	8:1c6281289d67	329	* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
n0tform3	8:1c6281289d67	330	* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
n0tform3	8:1c6281289d67	331	* structure which will be initialized.
n0tform3	8:1c6281289d67	332	* @retval None
n0tform3	8:1c6281289d67	333	*/
n0tform3	8:1c6281289d67	334	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
n0tform3	8:1c6281289d67	335	{
n0tform3	8:1c6281289d67	336	/* Set the default configuration */
n0tform3	8:1c6281289d67	337	TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
n0tform3	8:1c6281289d67	338	TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
n0tform3	8:1c6281289d67	339	TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
n0tform3	8:1c6281289d67	340	TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
n0tform3	8:1c6281289d67	341	TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
n0tform3	8:1c6281289d67	342	}
n0tform3	8:1c6281289d67	343
n0tform3	8:1c6281289d67	344	/**
n0tform3	8:1c6281289d67	345	* @brief Configures the TIMx Prescaler.
n0tform3	8:1c6281289d67	346	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	347	* @param Prescaler: specifies the Prescaler Register value
n0tform3	8:1c6281289d67	348	* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
n0tform3	8:1c6281289d67	349	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	350	* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
n0tform3	8:1c6281289d67	351	* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
n0tform3	8:1c6281289d67	352	* @retval None
n0tform3	8:1c6281289d67	353	*/
n0tform3	8:1c6281289d67	354	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
n0tform3	8:1c6281289d67	355	{
n0tform3	8:1c6281289d67	356	/* Check the parameters */
n0tform3	8:1c6281289d67	357	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	358	assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
n0tform3	8:1c6281289d67	359	/* Set the Prescaler value */
n0tform3	8:1c6281289d67	360	TIMx->PSC = Prescaler;
n0tform3	8:1c6281289d67	361	/* Set or reset the UG Bit */
n0tform3	8:1c6281289d67	362	TIMx->EGR = TIM_PSCReloadMode;
n0tform3	8:1c6281289d67	363	}
n0tform3	8:1c6281289d67	364
n0tform3	8:1c6281289d67	365	/**
n0tform3	8:1c6281289d67	366	* @brief Specifies the TIMx Counter Mode to be used.
n0tform3	8:1c6281289d67	367	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	368	* @param TIM_CounterMode: specifies the Counter Mode to be used
n0tform3	8:1c6281289d67	369	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	370	* @arg TIM_CounterMode_Up: TIM Up Counting Mode
n0tform3	8:1c6281289d67	371	* @arg TIM_CounterMode_Down: TIM Down Counting Mode
n0tform3	8:1c6281289d67	372	* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
n0tform3	8:1c6281289d67	373	* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
n0tform3	8:1c6281289d67	374	* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
n0tform3	8:1c6281289d67	375	* @retval None
n0tform3	8:1c6281289d67	376	*/
n0tform3	8:1c6281289d67	377	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
n0tform3	8:1c6281289d67	378	{
n0tform3	8:1c6281289d67	379	uint16_t tmpcr1 = 0;
n0tform3	8:1c6281289d67	380
n0tform3	8:1c6281289d67	381	/* Check the parameters */
n0tform3	8:1c6281289d67	382	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	383	assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
n0tform3	8:1c6281289d67	384
n0tform3	8:1c6281289d67	385	tmpcr1 = TIMx->CR1;
n0tform3	8:1c6281289d67	386
n0tform3	8:1c6281289d67	387	/* Reset the CMS and DIR Bits */
n0tform3	8:1c6281289d67	388	tmpcr1 &= (uint16_t)~(TIM_CR1_DIR \| TIM_CR1_CMS);
n0tform3	8:1c6281289d67	389
n0tform3	8:1c6281289d67	390	/* Set the Counter Mode */
n0tform3	8:1c6281289d67	391	tmpcr1 \|= TIM_CounterMode;
n0tform3	8:1c6281289d67	392
n0tform3	8:1c6281289d67	393	/* Write to TIMx CR1 register */
n0tform3	8:1c6281289d67	394	TIMx->CR1 = tmpcr1;
n0tform3	8:1c6281289d67	395	}
n0tform3	8:1c6281289d67	396
n0tform3	8:1c6281289d67	397	/**
n0tform3	8:1c6281289d67	398	* @brief Sets the TIMx Counter Register value
n0tform3	8:1c6281289d67	399	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	400	* @param Counter: specifies the Counter register new value.
n0tform3	8:1c6281289d67	401	* @retval None
n0tform3	8:1c6281289d67	402	*/
n0tform3	8:1c6281289d67	403	void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
n0tform3	8:1c6281289d67	404	{
n0tform3	8:1c6281289d67	405	/* Check the parameters */
n0tform3	8:1c6281289d67	406	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	407
n0tform3	8:1c6281289d67	408	/* Set the Counter Register value */
n0tform3	8:1c6281289d67	409	TIMx->CNT = Counter;
n0tform3	8:1c6281289d67	410	}
n0tform3	8:1c6281289d67	411
n0tform3	8:1c6281289d67	412	/**
n0tform3	8:1c6281289d67	413	* @brief Sets the TIMx Autoreload Register value
n0tform3	8:1c6281289d67	414	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	415	* @param Autoreload: specifies the Autoreload register new value.
n0tform3	8:1c6281289d67	416	* @retval None
n0tform3	8:1c6281289d67	417	*/
n0tform3	8:1c6281289d67	418	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
n0tform3	8:1c6281289d67	419	{
n0tform3	8:1c6281289d67	420	/* Check the parameters */
n0tform3	8:1c6281289d67	421	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	422
n0tform3	8:1c6281289d67	423	/* Set the Autoreload Register value */
n0tform3	8:1c6281289d67	424	TIMx->ARR = Autoreload;
n0tform3	8:1c6281289d67	425	}
n0tform3	8:1c6281289d67	426
n0tform3	8:1c6281289d67	427	/**
n0tform3	8:1c6281289d67	428	* @brief Gets the TIMx Counter value.
n0tform3	8:1c6281289d67	429	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	430	* @retval Counter Register value
n0tform3	8:1c6281289d67	431	*/
n0tform3	8:1c6281289d67	432	uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	433	{
n0tform3	8:1c6281289d67	434	/* Check the parameters */
n0tform3	8:1c6281289d67	435	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	436
n0tform3	8:1c6281289d67	437	/* Get the Counter Register value */
n0tform3	8:1c6281289d67	438	return TIMx->CNT;
n0tform3	8:1c6281289d67	439	}
n0tform3	8:1c6281289d67	440
n0tform3	8:1c6281289d67	441	/**
n0tform3	8:1c6281289d67	442	* @brief Gets the TIMx Prescaler value.
n0tform3	8:1c6281289d67	443	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	444	* @retval Prescaler Register value.
n0tform3	8:1c6281289d67	445	*/
n0tform3	8:1c6281289d67	446	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	447	{
n0tform3	8:1c6281289d67	448	/* Check the parameters */
n0tform3	8:1c6281289d67	449	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	450
n0tform3	8:1c6281289d67	451	/* Get the Prescaler Register value */
n0tform3	8:1c6281289d67	452	return TIMx->PSC;
n0tform3	8:1c6281289d67	453	}
n0tform3	8:1c6281289d67	454
n0tform3	8:1c6281289d67	455	/**
n0tform3	8:1c6281289d67	456	* @brief Enables or Disables the TIMx Update event.
n0tform3	8:1c6281289d67	457	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	458	* @param NewState: new state of the TIMx UDIS bit
n0tform3	8:1c6281289d67	459	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	460	* @retval None
n0tform3	8:1c6281289d67	461	*/
n0tform3	8:1c6281289d67	462	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	463	{
n0tform3	8:1c6281289d67	464	/* Check the parameters */
n0tform3	8:1c6281289d67	465	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	466	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	467
n0tform3	8:1c6281289d67	468	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	469	{
n0tform3	8:1c6281289d67	470	/* Set the Update Disable Bit */
n0tform3	8:1c6281289d67	471	TIMx->CR1 \|= TIM_CR1_UDIS;
n0tform3	8:1c6281289d67	472	}
n0tform3	8:1c6281289d67	473	else
n0tform3	8:1c6281289d67	474	{
n0tform3	8:1c6281289d67	475	/* Reset the Update Disable Bit */
n0tform3	8:1c6281289d67	476	TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
n0tform3	8:1c6281289d67	477	}
n0tform3	8:1c6281289d67	478	}
n0tform3	8:1c6281289d67	479
n0tform3	8:1c6281289d67	480	/**
n0tform3	8:1c6281289d67	481	* @brief Configures the TIMx Update Request Interrupt source.
n0tform3	8:1c6281289d67	482	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	483	* @param TIM_UpdateSource: specifies the Update source.
n0tform3	8:1c6281289d67	484	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	485	* @arg TIM_UpdateSource_Global: Source of update is the counter
n0tform3	8:1c6281289d67	486	* overflow/underflow or the setting of UG bit, or an update
n0tform3	8:1c6281289d67	487	* generation through the slave mode controller.
n0tform3	8:1c6281289d67	488	* @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
n0tform3	8:1c6281289d67	489	* @retval None
n0tform3	8:1c6281289d67	490	*/
n0tform3	8:1c6281289d67	491	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
n0tform3	8:1c6281289d67	492	{
n0tform3	8:1c6281289d67	493	/* Check the parameters */
n0tform3	8:1c6281289d67	494	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	495	assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
n0tform3	8:1c6281289d67	496
n0tform3	8:1c6281289d67	497	if (TIM_UpdateSource != TIM_UpdateSource_Global)
n0tform3	8:1c6281289d67	498	{
n0tform3	8:1c6281289d67	499	/* Set the URS Bit */
n0tform3	8:1c6281289d67	500	TIMx->CR1 \|= TIM_CR1_URS;
n0tform3	8:1c6281289d67	501	}
n0tform3	8:1c6281289d67	502	else
n0tform3	8:1c6281289d67	503	{
n0tform3	8:1c6281289d67	504	/* Reset the URS Bit */
n0tform3	8:1c6281289d67	505	TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
n0tform3	8:1c6281289d67	506	}
n0tform3	8:1c6281289d67	507	}
n0tform3	8:1c6281289d67	508
n0tform3	8:1c6281289d67	509	/**
n0tform3	8:1c6281289d67	510	* @brief Enables or disables TIMx peripheral Preload register on ARR.
n0tform3	8:1c6281289d67	511	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	512	* @param NewState: new state of the TIMx peripheral Preload register
n0tform3	8:1c6281289d67	513	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	514	* @retval None
n0tform3	8:1c6281289d67	515	*/
n0tform3	8:1c6281289d67	516	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	517	{
n0tform3	8:1c6281289d67	518	/* Check the parameters */
n0tform3	8:1c6281289d67	519	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	520	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	521
n0tform3	8:1c6281289d67	522	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	523	{
n0tform3	8:1c6281289d67	524	/* Set the ARR Preload Bit */
n0tform3	8:1c6281289d67	525	TIMx->CR1 \|= TIM_CR1_ARPE;
n0tform3	8:1c6281289d67	526	}
n0tform3	8:1c6281289d67	527	else
n0tform3	8:1c6281289d67	528	{
n0tform3	8:1c6281289d67	529	/* Reset the ARR Preload Bit */
n0tform3	8:1c6281289d67	530	TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
n0tform3	8:1c6281289d67	531	}
n0tform3	8:1c6281289d67	532	}
n0tform3	8:1c6281289d67	533
n0tform3	8:1c6281289d67	534	/**
n0tform3	8:1c6281289d67	535	* @brief Selects the TIMx's One Pulse Mode.
n0tform3	8:1c6281289d67	536	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	537	* @param TIM_OPMode: specifies the OPM Mode to be used.
n0tform3	8:1c6281289d67	538	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	539	* @arg TIM_OPMode_Single
n0tform3	8:1c6281289d67	540	* @arg TIM_OPMode_Repetitive
n0tform3	8:1c6281289d67	541	* @retval None
n0tform3	8:1c6281289d67	542	*/
n0tform3	8:1c6281289d67	543	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
n0tform3	8:1c6281289d67	544	{
n0tform3	8:1c6281289d67	545	/* Check the parameters */
n0tform3	8:1c6281289d67	546	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	547	assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
n0tform3	8:1c6281289d67	548
n0tform3	8:1c6281289d67	549	/* Reset the OPM Bit */
n0tform3	8:1c6281289d67	550	TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
n0tform3	8:1c6281289d67	551
n0tform3	8:1c6281289d67	552	/* Configure the OPM Mode */
n0tform3	8:1c6281289d67	553	TIMx->CR1 \|= TIM_OPMode;
n0tform3	8:1c6281289d67	554	}
n0tform3	8:1c6281289d67	555
n0tform3	8:1c6281289d67	556	/**
n0tform3	8:1c6281289d67	557	* @brief Sets the TIMx Clock Division value.
n0tform3	8:1c6281289d67	558	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	559	* @param TIM_CKD: specifies the clock division value.
n0tform3	8:1c6281289d67	560	* This parameter can be one of the following value:
n0tform3	8:1c6281289d67	561	* @arg TIM_CKD_DIV1: TDTS = Tck_tim
n0tform3	8:1c6281289d67	562	* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
n0tform3	8:1c6281289d67	563	* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
n0tform3	8:1c6281289d67	564	* @retval None
n0tform3	8:1c6281289d67	565	*/
n0tform3	8:1c6281289d67	566	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
n0tform3	8:1c6281289d67	567	{
n0tform3	8:1c6281289d67	568	/* Check the parameters */
n0tform3	8:1c6281289d67	569	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	570	assert_param(IS_TIM_CKD_DIV(TIM_CKD));
n0tform3	8:1c6281289d67	571
n0tform3	8:1c6281289d67	572	/* Reset the CKD Bits */
n0tform3	8:1c6281289d67	573	TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
n0tform3	8:1c6281289d67	574
n0tform3	8:1c6281289d67	575	/* Set the CKD value */
n0tform3	8:1c6281289d67	576	TIMx->CR1 \|= TIM_CKD;
n0tform3	8:1c6281289d67	577	}
n0tform3	8:1c6281289d67	578
n0tform3	8:1c6281289d67	579	/**
n0tform3	8:1c6281289d67	580	* @brief Enables or disables the specified TIM peripheral.
n0tform3	8:1c6281289d67	581	* @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
n0tform3	8:1c6281289d67	582	* @param NewState: new state of the TIMx peripheral.
n0tform3	8:1c6281289d67	583	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	584	* @retval None
n0tform3	8:1c6281289d67	585	*/
n0tform3	8:1c6281289d67	586	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	587	{
n0tform3	8:1c6281289d67	588	/* Check the parameters */
n0tform3	8:1c6281289d67	589	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	590	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	591
n0tform3	8:1c6281289d67	592	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	593	{
n0tform3	8:1c6281289d67	594	/* Enable the TIM Counter */
n0tform3	8:1c6281289d67	595	TIMx->CR1 \|= TIM_CR1_CEN;
n0tform3	8:1c6281289d67	596	}
n0tform3	8:1c6281289d67	597	else
n0tform3	8:1c6281289d67	598	{
n0tform3	8:1c6281289d67	599	/* Disable the TIM Counter */
n0tform3	8:1c6281289d67	600	TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
n0tform3	8:1c6281289d67	601	}
n0tform3	8:1c6281289d67	602	}
n0tform3	8:1c6281289d67	603	/**
n0tform3	8:1c6281289d67	604	* @}
n0tform3	8:1c6281289d67	605	*/
n0tform3	8:1c6281289d67	606
n0tform3	8:1c6281289d67	607	/** @defgroup TIM_Group2 Output Compare management functions
n0tform3	8:1c6281289d67	608	* @brief Output Compare management functions
n0tform3	8:1c6281289d67	609	*
n0tform3	8:1c6281289d67	610	@verbatim
n0tform3	8:1c6281289d67	611	===============================================================================
n0tform3	8:1c6281289d67	612	Output Compare management functions
n0tform3	8:1c6281289d67	613	===============================================================================
n0tform3	8:1c6281289d67	614
n0tform3	8:1c6281289d67	615	===================================================================
n0tform3	8:1c6281289d67	616	TIM Driver: how to use it in Output Compare Mode
n0tform3	8:1c6281289d67	617	===================================================================
n0tform3	8:1c6281289d67	618	To use the Timer in Output Compare mode, the following steps are mandatory:
n0tform3	8:1c6281289d67	619
n0tform3	8:1c6281289d67	620	1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
n0tform3	8:1c6281289d67	621
n0tform3	8:1c6281289d67	622	2. Configure the TIM pins by configuring the corresponding GPIO pins
n0tform3	8:1c6281289d67	623
n0tform3	8:1c6281289d67	624	2. Configure the Time base unit as described in the first part of this driver,
n0tform3	8:1c6281289d67	625	if needed, else the Timer will run with the default configuration:
n0tform3	8:1c6281289d67	626	- Autoreload value = 0xFFFF
n0tform3	8:1c6281289d67	627	- Prescaler value = 0x0000
n0tform3	8:1c6281289d67	628	- Counter mode = Up counting
n0tform3	8:1c6281289d67	629	- Clock Division = TIM_CKD_DIV1
n0tform3	8:1c6281289d67	630
n0tform3	8:1c6281289d67	631	3. Fill the TIM_OCInitStruct with the desired parameters including:
n0tform3	8:1c6281289d67	632	- The TIM Output Compare mode: TIM_OCMode
n0tform3	8:1c6281289d67	633	- TIM Output State: TIM_OutputState
n0tform3	8:1c6281289d67	634	- TIM Pulse value: TIM_Pulse
n0tform3	8:1c6281289d67	635	- TIM Output Compare Polarity : TIM_OCPolarity
n0tform3	8:1c6281289d67	636
n0tform3	8:1c6281289d67	637	4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
n0tform3	8:1c6281289d67	638	corresponding configuration
n0tform3	8:1c6281289d67	639
n0tform3	8:1c6281289d67	640	5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
n0tform3	8:1c6281289d67	641
n0tform3	8:1c6281289d67	642	Note1: All other functions can be used separately to modify, if needed,
n0tform3	8:1c6281289d67	643	a specific feature of the Timer.
n0tform3	8:1c6281289d67	644
n0tform3	8:1c6281289d67	645	Note2: In case of PWM mode, this function is mandatory:
n0tform3	8:1c6281289d67	646	TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
n0tform3	8:1c6281289d67	647
n0tform3	8:1c6281289d67	648	Note3: If the corresponding interrupt or DMA request are needed, the user should:
n0tform3	8:1c6281289d67	649	1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
n0tform3	8:1c6281289d67	650	2. Enable the corresponding interrupt (or DMA request) using the function
n0tform3	8:1c6281289d67	651	TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
n0tform3	8:1c6281289d67	652
n0tform3	8:1c6281289d67	653	@endverbatim
n0tform3	8:1c6281289d67	654	* @{
n0tform3	8:1c6281289d67	655	*/
n0tform3	8:1c6281289d67	656
n0tform3	8:1c6281289d67	657	/**
n0tform3	8:1c6281289d67	658	* @brief Initializes the TIMx Channel1 according to the specified parameters in
n0tform3	8:1c6281289d67	659	* the TIM_OCInitStruct.
n0tform3	8:1c6281289d67	660	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	661	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
n0tform3	8:1c6281289d67	662	* the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	663	* @retval None
n0tform3	8:1c6281289d67	664	*/
n0tform3	8:1c6281289d67	665	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
n0tform3	8:1c6281289d67	666	{
n0tform3	8:1c6281289d67	667	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
n0tform3	8:1c6281289d67	668
n0tform3	8:1c6281289d67	669	/* Check the parameters */
n0tform3	8:1c6281289d67	670	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	671	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
n0tform3	8:1c6281289d67	672	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
n0tform3	8:1c6281289d67	673	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
n0tform3	8:1c6281289d67	674
n0tform3	8:1c6281289d67	675	/* Disable the Channel 1: Reset the CC1E Bit */
n0tform3	8:1c6281289d67	676	TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
n0tform3	8:1c6281289d67	677
n0tform3	8:1c6281289d67	678	/* Get the TIMx CCER register value */
n0tform3	8:1c6281289d67	679	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	680	/* Get the TIMx CR2 register value */
n0tform3	8:1c6281289d67	681	tmpcr2 = TIMx->CR2;
n0tform3	8:1c6281289d67	682
n0tform3	8:1c6281289d67	683	/* Get the TIMx CCMR1 register value */
n0tform3	8:1c6281289d67	684	tmpccmrx = TIMx->CCMR1;
n0tform3	8:1c6281289d67	685
n0tform3	8:1c6281289d67	686	/* Reset the Output Compare Mode Bits */
n0tform3	8:1c6281289d67	687	tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
n0tform3	8:1c6281289d67	688	tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
n0tform3	8:1c6281289d67	689	/* Select the Output Compare Mode */
n0tform3	8:1c6281289d67	690	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
n0tform3	8:1c6281289d67	691
n0tform3	8:1c6281289d67	692	/* Reset the Output Polarity level */
n0tform3	8:1c6281289d67	693	tmpccer &= (uint16_t)~TIM_CCER_CC1P;
n0tform3	8:1c6281289d67	694	/* Set the Output Compare Polarity */
n0tform3	8:1c6281289d67	695	tmpccer \|= TIM_OCInitStruct->TIM_OCPolarity;
n0tform3	8:1c6281289d67	696
n0tform3	8:1c6281289d67	697	/* Set the Output State */
n0tform3	8:1c6281289d67	698	tmpccer \|= TIM_OCInitStruct->TIM_OutputState;
n0tform3	8:1c6281289d67	699
n0tform3	8:1c6281289d67	700	if((TIMx == TIM1) \|\| (TIMx == TIM8))
n0tform3	8:1c6281289d67	701	{
n0tform3	8:1c6281289d67	702	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
n0tform3	8:1c6281289d67	703	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
n0tform3	8:1c6281289d67	704	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
n0tform3	8:1c6281289d67	705	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
n0tform3	8:1c6281289d67	706
n0tform3	8:1c6281289d67	707	/* Reset the Output N Polarity level */
n0tform3	8:1c6281289d67	708	tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
n0tform3	8:1c6281289d67	709	/* Set the Output N Polarity */
n0tform3	8:1c6281289d67	710	tmpccer \|= TIM_OCInitStruct->TIM_OCNPolarity;
n0tform3	8:1c6281289d67	711	/* Reset the Output N State */
n0tform3	8:1c6281289d67	712	tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
n0tform3	8:1c6281289d67	713
n0tform3	8:1c6281289d67	714	/* Set the Output N State */
n0tform3	8:1c6281289d67	715	tmpccer \|= TIM_OCInitStruct->TIM_OutputNState;
n0tform3	8:1c6281289d67	716	/* Reset the Output Compare and Output Compare N IDLE State */
n0tform3	8:1c6281289d67	717	tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
n0tform3	8:1c6281289d67	718	tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
n0tform3	8:1c6281289d67	719	/* Set the Output Idle state */
n0tform3	8:1c6281289d67	720	tmpcr2 \|= TIM_OCInitStruct->TIM_OCIdleState;
n0tform3	8:1c6281289d67	721	/* Set the Output N Idle state */
n0tform3	8:1c6281289d67	722	tmpcr2 \|= TIM_OCInitStruct->TIM_OCNIdleState;
n0tform3	8:1c6281289d67	723	}
n0tform3	8:1c6281289d67	724	/* Write to TIMx CR2 */
n0tform3	8:1c6281289d67	725	TIMx->CR2 = tmpcr2;
n0tform3	8:1c6281289d67	726
n0tform3	8:1c6281289d67	727	/* Write to TIMx CCMR1 */
n0tform3	8:1c6281289d67	728	TIMx->CCMR1 = tmpccmrx;
n0tform3	8:1c6281289d67	729
n0tform3	8:1c6281289d67	730	/* Set the Capture Compare Register value */
n0tform3	8:1c6281289d67	731	TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
n0tform3	8:1c6281289d67	732
n0tform3	8:1c6281289d67	733	/* Write to TIMx CCER */
n0tform3	8:1c6281289d67	734	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	735	}
n0tform3	8:1c6281289d67	736
n0tform3	8:1c6281289d67	737	/**
n0tform3	8:1c6281289d67	738	* @brief Initializes the TIMx Channel2 according to the specified parameters
n0tform3	8:1c6281289d67	739	* in the TIM_OCInitStruct.
n0tform3	8:1c6281289d67	740	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	741	* peripheral.
n0tform3	8:1c6281289d67	742	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
n0tform3	8:1c6281289d67	743	* the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	744	* @retval None
n0tform3	8:1c6281289d67	745	*/
n0tform3	8:1c6281289d67	746	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
n0tform3	8:1c6281289d67	747	{
n0tform3	8:1c6281289d67	748	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
n0tform3	8:1c6281289d67	749
n0tform3	8:1c6281289d67	750	/* Check the parameters */
n0tform3	8:1c6281289d67	751	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	752	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
n0tform3	8:1c6281289d67	753	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
n0tform3	8:1c6281289d67	754	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
n0tform3	8:1c6281289d67	755
n0tform3	8:1c6281289d67	756	/* Disable the Channel 2: Reset the CC2E Bit */
n0tform3	8:1c6281289d67	757	TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
n0tform3	8:1c6281289d67	758
n0tform3	8:1c6281289d67	759	/* Get the TIMx CCER register value */
n0tform3	8:1c6281289d67	760	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	761	/* Get the TIMx CR2 register value */
n0tform3	8:1c6281289d67	762	tmpcr2 = TIMx->CR2;
n0tform3	8:1c6281289d67	763
n0tform3	8:1c6281289d67	764	/* Get the TIMx CCMR1 register value */
n0tform3	8:1c6281289d67	765	tmpccmrx = TIMx->CCMR1;
n0tform3	8:1c6281289d67	766
n0tform3	8:1c6281289d67	767	/* Reset the Output Compare mode and Capture/Compare selection Bits */
n0tform3	8:1c6281289d67	768	tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
n0tform3	8:1c6281289d67	769	tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
n0tform3	8:1c6281289d67	770
n0tform3	8:1c6281289d67	771	/* Select the Output Compare Mode */
n0tform3	8:1c6281289d67	772	tmpccmrx \|= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
n0tform3	8:1c6281289d67	773
n0tform3	8:1c6281289d67	774	/* Reset the Output Polarity level */
n0tform3	8:1c6281289d67	775	tmpccer &= (uint16_t)~TIM_CCER_CC2P;
n0tform3	8:1c6281289d67	776	/* Set the Output Compare Polarity */
n0tform3	8:1c6281289d67	777	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
n0tform3	8:1c6281289d67	778
n0tform3	8:1c6281289d67	779	/* Set the Output State */
n0tform3	8:1c6281289d67	780	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
n0tform3	8:1c6281289d67	781
n0tform3	8:1c6281289d67	782	if((TIMx == TIM1) \|\| (TIMx == TIM8))
n0tform3	8:1c6281289d67	783	{
n0tform3	8:1c6281289d67	784	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
n0tform3	8:1c6281289d67	785	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
n0tform3	8:1c6281289d67	786	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
n0tform3	8:1c6281289d67	787	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
n0tform3	8:1c6281289d67	788
n0tform3	8:1c6281289d67	789	/* Reset the Output N Polarity level */
n0tform3	8:1c6281289d67	790	tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
n0tform3	8:1c6281289d67	791	/* Set the Output N Polarity */
n0tform3	8:1c6281289d67	792	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
n0tform3	8:1c6281289d67	793	/* Reset the Output N State */
n0tform3	8:1c6281289d67	794	tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
n0tform3	8:1c6281289d67	795
n0tform3	8:1c6281289d67	796	/* Set the Output N State */
n0tform3	8:1c6281289d67	797	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
n0tform3	8:1c6281289d67	798	/* Reset the Output Compare and Output Compare N IDLE State */
n0tform3	8:1c6281289d67	799	tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
n0tform3	8:1c6281289d67	800	tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
n0tform3	8:1c6281289d67	801	/* Set the Output Idle state */
n0tform3	8:1c6281289d67	802	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
n0tform3	8:1c6281289d67	803	/* Set the Output N Idle state */
n0tform3	8:1c6281289d67	804	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
n0tform3	8:1c6281289d67	805	}
n0tform3	8:1c6281289d67	806	/* Write to TIMx CR2 */
n0tform3	8:1c6281289d67	807	TIMx->CR2 = tmpcr2;
n0tform3	8:1c6281289d67	808
n0tform3	8:1c6281289d67	809	/* Write to TIMx CCMR1 */
n0tform3	8:1c6281289d67	810	TIMx->CCMR1 = tmpccmrx;
n0tform3	8:1c6281289d67	811
n0tform3	8:1c6281289d67	812	/* Set the Capture Compare Register value */
n0tform3	8:1c6281289d67	813	TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
n0tform3	8:1c6281289d67	814
n0tform3	8:1c6281289d67	815	/* Write to TIMx CCER */
n0tform3	8:1c6281289d67	816	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	817	}
n0tform3	8:1c6281289d67	818
n0tform3	8:1c6281289d67	819	/**
n0tform3	8:1c6281289d67	820	* @brief Initializes the TIMx Channel3 according to the specified parameters
n0tform3	8:1c6281289d67	821	* in the TIM_OCInitStruct.
n0tform3	8:1c6281289d67	822	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	823	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
n0tform3	8:1c6281289d67	824	* the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	825	* @retval None
n0tform3	8:1c6281289d67	826	*/
n0tform3	8:1c6281289d67	827	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
n0tform3	8:1c6281289d67	828	{
n0tform3	8:1c6281289d67	829	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
n0tform3	8:1c6281289d67	830
n0tform3	8:1c6281289d67	831	/* Check the parameters */
n0tform3	8:1c6281289d67	832	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	833	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
n0tform3	8:1c6281289d67	834	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
n0tform3	8:1c6281289d67	835	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
n0tform3	8:1c6281289d67	836
n0tform3	8:1c6281289d67	837	/* Disable the Channel 3: Reset the CC2E Bit */
n0tform3	8:1c6281289d67	838	TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
n0tform3	8:1c6281289d67	839
n0tform3	8:1c6281289d67	840	/* Get the TIMx CCER register value */
n0tform3	8:1c6281289d67	841	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	842	/* Get the TIMx CR2 register value */
n0tform3	8:1c6281289d67	843	tmpcr2 = TIMx->CR2;
n0tform3	8:1c6281289d67	844
n0tform3	8:1c6281289d67	845	/* Get the TIMx CCMR2 register value */
n0tform3	8:1c6281289d67	846	tmpccmrx = TIMx->CCMR2;
n0tform3	8:1c6281289d67	847
n0tform3	8:1c6281289d67	848	/* Reset the Output Compare mode and Capture/Compare selection Bits */
n0tform3	8:1c6281289d67	849	tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
n0tform3	8:1c6281289d67	850	tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
n0tform3	8:1c6281289d67	851	/* Select the Output Compare Mode */
n0tform3	8:1c6281289d67	852	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
n0tform3	8:1c6281289d67	853
n0tform3	8:1c6281289d67	854	/* Reset the Output Polarity level */
n0tform3	8:1c6281289d67	855	tmpccer &= (uint16_t)~TIM_CCER_CC3P;
n0tform3	8:1c6281289d67	856	/* Set the Output Compare Polarity */
n0tform3	8:1c6281289d67	857	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
n0tform3	8:1c6281289d67	858
n0tform3	8:1c6281289d67	859	/* Set the Output State */
n0tform3	8:1c6281289d67	860	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
n0tform3	8:1c6281289d67	861
n0tform3	8:1c6281289d67	862	if((TIMx == TIM1) \|\| (TIMx == TIM8))
n0tform3	8:1c6281289d67	863	{
n0tform3	8:1c6281289d67	864	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
n0tform3	8:1c6281289d67	865	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
n0tform3	8:1c6281289d67	866	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
n0tform3	8:1c6281289d67	867	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
n0tform3	8:1c6281289d67	868
n0tform3	8:1c6281289d67	869	/* Reset the Output N Polarity level */
n0tform3	8:1c6281289d67	870	tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
n0tform3	8:1c6281289d67	871	/* Set the Output N Polarity */
n0tform3	8:1c6281289d67	872	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
n0tform3	8:1c6281289d67	873	/* Reset the Output N State */
n0tform3	8:1c6281289d67	874	tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
n0tform3	8:1c6281289d67	875
n0tform3	8:1c6281289d67	876	/* Set the Output N State */
n0tform3	8:1c6281289d67	877	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
n0tform3	8:1c6281289d67	878	/* Reset the Output Compare and Output Compare N IDLE State */
n0tform3	8:1c6281289d67	879	tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
n0tform3	8:1c6281289d67	880	tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
n0tform3	8:1c6281289d67	881	/* Set the Output Idle state */
n0tform3	8:1c6281289d67	882	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
n0tform3	8:1c6281289d67	883	/* Set the Output N Idle state */
n0tform3	8:1c6281289d67	884	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
n0tform3	8:1c6281289d67	885	}
n0tform3	8:1c6281289d67	886	/* Write to TIMx CR2 */
n0tform3	8:1c6281289d67	887	TIMx->CR2 = tmpcr2;
n0tform3	8:1c6281289d67	888
n0tform3	8:1c6281289d67	889	/* Write to TIMx CCMR2 */
n0tform3	8:1c6281289d67	890	TIMx->CCMR2 = tmpccmrx;
n0tform3	8:1c6281289d67	891
n0tform3	8:1c6281289d67	892	/* Set the Capture Compare Register value */
n0tform3	8:1c6281289d67	893	TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
n0tform3	8:1c6281289d67	894
n0tform3	8:1c6281289d67	895	/* Write to TIMx CCER */
n0tform3	8:1c6281289d67	896	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	897	}
n0tform3	8:1c6281289d67	898
n0tform3	8:1c6281289d67	899	/**
n0tform3	8:1c6281289d67	900	* @brief Initializes the TIMx Channel4 according to the specified parameters
n0tform3	8:1c6281289d67	901	* in the TIM_OCInitStruct.
n0tform3	8:1c6281289d67	902	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	903	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
n0tform3	8:1c6281289d67	904	* the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	905	* @retval None
n0tform3	8:1c6281289d67	906	*/
n0tform3	8:1c6281289d67	907	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
n0tform3	8:1c6281289d67	908	{
n0tform3	8:1c6281289d67	909	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
n0tform3	8:1c6281289d67	910
n0tform3	8:1c6281289d67	911	/* Check the parameters */
n0tform3	8:1c6281289d67	912	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	913	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
n0tform3	8:1c6281289d67	914	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
n0tform3	8:1c6281289d67	915	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
n0tform3	8:1c6281289d67	916
n0tform3	8:1c6281289d67	917	/* Disable the Channel 4: Reset the CC4E Bit */
n0tform3	8:1c6281289d67	918	TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
n0tform3	8:1c6281289d67	919
n0tform3	8:1c6281289d67	920	/* Get the TIMx CCER register value */
n0tform3	8:1c6281289d67	921	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	922	/* Get the TIMx CR2 register value */
n0tform3	8:1c6281289d67	923	tmpcr2 = TIMx->CR2;
n0tform3	8:1c6281289d67	924
n0tform3	8:1c6281289d67	925	/* Get the TIMx CCMR2 register value */
n0tform3	8:1c6281289d67	926	tmpccmrx = TIMx->CCMR2;
n0tform3	8:1c6281289d67	927
n0tform3	8:1c6281289d67	928	/* Reset the Output Compare mode and Capture/Compare selection Bits */
n0tform3	8:1c6281289d67	929	tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
n0tform3	8:1c6281289d67	930	tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
n0tform3	8:1c6281289d67	931
n0tform3	8:1c6281289d67	932	/* Select the Output Compare Mode */
n0tform3	8:1c6281289d67	933	tmpccmrx \|= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
n0tform3	8:1c6281289d67	934
n0tform3	8:1c6281289d67	935	/* Reset the Output Polarity level */
n0tform3	8:1c6281289d67	936	tmpccer &= (uint16_t)~TIM_CCER_CC4P;
n0tform3	8:1c6281289d67	937	/* Set the Output Compare Polarity */
n0tform3	8:1c6281289d67	938	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
n0tform3	8:1c6281289d67	939
n0tform3	8:1c6281289d67	940	/* Set the Output State */
n0tform3	8:1c6281289d67	941	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
n0tform3	8:1c6281289d67	942
n0tform3	8:1c6281289d67	943	if((TIMx == TIM1) \|\| (TIMx == TIM8))
n0tform3	8:1c6281289d67	944	{
n0tform3	8:1c6281289d67	945	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
n0tform3	8:1c6281289d67	946	/* Reset the Output Compare IDLE State */
n0tform3	8:1c6281289d67	947	tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
n0tform3	8:1c6281289d67	948	/* Set the Output Idle state */
n0tform3	8:1c6281289d67	949	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
n0tform3	8:1c6281289d67	950	}
n0tform3	8:1c6281289d67	951	/* Write to TIMx CR2 */
n0tform3	8:1c6281289d67	952	TIMx->CR2 = tmpcr2;
n0tform3	8:1c6281289d67	953
n0tform3	8:1c6281289d67	954	/* Write to TIMx CCMR2 */
n0tform3	8:1c6281289d67	955	TIMx->CCMR2 = tmpccmrx;
n0tform3	8:1c6281289d67	956
n0tform3	8:1c6281289d67	957	/* Set the Capture Compare Register value */
n0tform3	8:1c6281289d67	958	TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
n0tform3	8:1c6281289d67	959
n0tform3	8:1c6281289d67	960	/* Write to TIMx CCER */
n0tform3	8:1c6281289d67	961	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	962	}
n0tform3	8:1c6281289d67	963
n0tform3	8:1c6281289d67	964	/**
n0tform3	8:1c6281289d67	965	* @brief Fills each TIM_OCInitStruct member with its default value.
n0tform3	8:1c6281289d67	966	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
n0tform3	8:1c6281289d67	967	* be initialized.
n0tform3	8:1c6281289d67	968	* @retval None
n0tform3	8:1c6281289d67	969	*/
n0tform3	8:1c6281289d67	970	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
n0tform3	8:1c6281289d67	971	{
n0tform3	8:1c6281289d67	972	/* Set the default configuration */
n0tform3	8:1c6281289d67	973	TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
n0tform3	8:1c6281289d67	974	TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
n0tform3	8:1c6281289d67	975	TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
n0tform3	8:1c6281289d67	976	TIM_OCInitStruct->TIM_Pulse = 0x00000000;
n0tform3	8:1c6281289d67	977	TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
n0tform3	8:1c6281289d67	978	TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
n0tform3	8:1c6281289d67	979	TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
n0tform3	8:1c6281289d67	980	TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
n0tform3	8:1c6281289d67	981	}
n0tform3	8:1c6281289d67	982
n0tform3	8:1c6281289d67	983	/**
n0tform3	8:1c6281289d67	984	* @brief Selects the TIM Output Compare Mode.
n0tform3	8:1c6281289d67	985	* @note This function disables the selected channel before changing the Output
n0tform3	8:1c6281289d67	986	* Compare Mode. If needed, user has to enable this channel using
n0tform3	8:1c6281289d67	987	* TIM_CCxCmd() and TIM_CCxNCmd() functions.
n0tform3	8:1c6281289d67	988	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	989	* @param TIM_Channel: specifies the TIM Channel
n0tform3	8:1c6281289d67	990	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	991	* @arg TIM_Channel_1: TIM Channel 1
n0tform3	8:1c6281289d67	992	* @arg TIM_Channel_2: TIM Channel 2
n0tform3	8:1c6281289d67	993	* @arg TIM_Channel_3: TIM Channel 3
n0tform3	8:1c6281289d67	994	* @arg TIM_Channel_4: TIM Channel 4
n0tform3	8:1c6281289d67	995	* @param TIM_OCMode: specifies the TIM Output Compare Mode.
n0tform3	8:1c6281289d67	996	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	997	* @arg TIM_OCMode_Timing
n0tform3	8:1c6281289d67	998	* @arg TIM_OCMode_Active
n0tform3	8:1c6281289d67	999	* @arg TIM_OCMode_Toggle
n0tform3	8:1c6281289d67	1000	* @arg TIM_OCMode_PWM1
n0tform3	8:1c6281289d67	1001	* @arg TIM_OCMode_PWM2
n0tform3	8:1c6281289d67	1002	* @arg TIM_ForcedAction_Active
n0tform3	8:1c6281289d67	1003	* @arg TIM_ForcedAction_InActive
n0tform3	8:1c6281289d67	1004	* @retval None
n0tform3	8:1c6281289d67	1005	*/
n0tform3	8:1c6281289d67	1006	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
n0tform3	8:1c6281289d67	1007	{
n0tform3	8:1c6281289d67	1008	uint32_t tmp = 0;
n0tform3	8:1c6281289d67	1009	uint16_t tmp1 = 0;
n0tform3	8:1c6281289d67	1010
n0tform3	8:1c6281289d67	1011	/* Check the parameters */
n0tform3	8:1c6281289d67	1012	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1013	assert_param(IS_TIM_CHANNEL(TIM_Channel));
n0tform3	8:1c6281289d67	1014	assert_param(IS_TIM_OCM(TIM_OCMode));
n0tform3	8:1c6281289d67	1015
n0tform3	8:1c6281289d67	1016	tmp = (uint32_t) TIMx;
n0tform3	8:1c6281289d67	1017	tmp += CCMR_OFFSET;
n0tform3	8:1c6281289d67	1018
n0tform3	8:1c6281289d67	1019	tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
n0tform3	8:1c6281289d67	1020
n0tform3	8:1c6281289d67	1021	/* Disable the Channel: Reset the CCxE Bit */
n0tform3	8:1c6281289d67	1022	TIMx->CCER &= (uint16_t) ~tmp1;
n0tform3	8:1c6281289d67	1023
n0tform3	8:1c6281289d67	1024	if((TIM_Channel == TIM_Channel_1) \|\|(TIM_Channel == TIM_Channel_3))
n0tform3	8:1c6281289d67	1025	{
n0tform3	8:1c6281289d67	1026	tmp += (TIM_Channel>>1);
n0tform3	8:1c6281289d67	1027
n0tform3	8:1c6281289d67	1028	/* Reset the OCxM bits in the CCMRx register */
n0tform3	8:1c6281289d67	1029	(__IO uint32_t ) tmp &= CCMR_OC13M_MASK;
n0tform3	8:1c6281289d67	1030
n0tform3	8:1c6281289d67	1031	/* Configure the OCxM bits in the CCMRx register */
n0tform3	8:1c6281289d67	1032	(__IO uint32_t ) tmp \|= TIM_OCMode;
n0tform3	8:1c6281289d67	1033	}
n0tform3	8:1c6281289d67	1034	else
n0tform3	8:1c6281289d67	1035	{
n0tform3	8:1c6281289d67	1036	tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
n0tform3	8:1c6281289d67	1037
n0tform3	8:1c6281289d67	1038	/* Reset the OCxM bits in the CCMRx register */
n0tform3	8:1c6281289d67	1039	(__IO uint32_t ) tmp &= CCMR_OC24M_MASK;
n0tform3	8:1c6281289d67	1040
n0tform3	8:1c6281289d67	1041	/* Configure the OCxM bits in the CCMRx register */
n0tform3	8:1c6281289d67	1042	(__IO uint32_t ) tmp \|= (uint16_t)(TIM_OCMode << 8);
n0tform3	8:1c6281289d67	1043	}
n0tform3	8:1c6281289d67	1044	}
n0tform3	8:1c6281289d67	1045
n0tform3	8:1c6281289d67	1046	/**
n0tform3	8:1c6281289d67	1047	* @brief Sets the TIMx Capture Compare1 Register value
n0tform3	8:1c6281289d67	1048	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1049	* @param Compare1: specifies the Capture Compare1 register new value.
n0tform3	8:1c6281289d67	1050	* @retval None
n0tform3	8:1c6281289d67	1051	*/
n0tform3	8:1c6281289d67	1052	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
n0tform3	8:1c6281289d67	1053	{
n0tform3	8:1c6281289d67	1054	/* Check the parameters */
n0tform3	8:1c6281289d67	1055	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1056
n0tform3	8:1c6281289d67	1057	/* Set the Capture Compare1 Register value */
n0tform3	8:1c6281289d67	1058	TIMx->CCR1 = Compare1;
n0tform3	8:1c6281289d67	1059	}
n0tform3	8:1c6281289d67	1060
n0tform3	8:1c6281289d67	1061	/**
n0tform3	8:1c6281289d67	1062	* @brief Sets the TIMx Capture Compare2 Register value
n0tform3	8:1c6281289d67	1063	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1064	* peripheral.
n0tform3	8:1c6281289d67	1065	* @param Compare2: specifies the Capture Compare2 register new value.
n0tform3	8:1c6281289d67	1066	* @retval None
n0tform3	8:1c6281289d67	1067	*/
n0tform3	8:1c6281289d67	1068	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
n0tform3	8:1c6281289d67	1069	{
n0tform3	8:1c6281289d67	1070	/* Check the parameters */
n0tform3	8:1c6281289d67	1071	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1072
n0tform3	8:1c6281289d67	1073	/* Set the Capture Compare2 Register value */
n0tform3	8:1c6281289d67	1074	TIMx->CCR2 = Compare2;
n0tform3	8:1c6281289d67	1075	}
n0tform3	8:1c6281289d67	1076
n0tform3	8:1c6281289d67	1077	/**
n0tform3	8:1c6281289d67	1078	* @brief Sets the TIMx Capture Compare3 Register value
n0tform3	8:1c6281289d67	1079	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1080	* @param Compare3: specifies the Capture Compare3 register new value.
n0tform3	8:1c6281289d67	1081	* @retval None
n0tform3	8:1c6281289d67	1082	*/
n0tform3	8:1c6281289d67	1083	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
n0tform3	8:1c6281289d67	1084	{
n0tform3	8:1c6281289d67	1085	/* Check the parameters */
n0tform3	8:1c6281289d67	1086	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1087
n0tform3	8:1c6281289d67	1088	/* Set the Capture Compare3 Register value */
n0tform3	8:1c6281289d67	1089	TIMx->CCR3 = Compare3;
n0tform3	8:1c6281289d67	1090	}
n0tform3	8:1c6281289d67	1091
n0tform3	8:1c6281289d67	1092	/**
n0tform3	8:1c6281289d67	1093	* @brief Sets the TIMx Capture Compare4 Register value
n0tform3	8:1c6281289d67	1094	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1095	* @param Compare4: specifies the Capture Compare4 register new value.
n0tform3	8:1c6281289d67	1096	* @retval None
n0tform3	8:1c6281289d67	1097	*/
n0tform3	8:1c6281289d67	1098	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
n0tform3	8:1c6281289d67	1099	{
n0tform3	8:1c6281289d67	1100	/* Check the parameters */
n0tform3	8:1c6281289d67	1101	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1102
n0tform3	8:1c6281289d67	1103	/* Set the Capture Compare4 Register value */
n0tform3	8:1c6281289d67	1104	TIMx->CCR4 = Compare4;
n0tform3	8:1c6281289d67	1105	}
n0tform3	8:1c6281289d67	1106
n0tform3	8:1c6281289d67	1107	/**
n0tform3	8:1c6281289d67	1108	* @brief Forces the TIMx output 1 waveform to active or inactive level.
n0tform3	8:1c6281289d67	1109	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1110	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
n0tform3	8:1c6281289d67	1111	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1112	* @arg TIM_ForcedAction_Active: Force active level on OC1REF
n0tform3	8:1c6281289d67	1113	* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
n0tform3	8:1c6281289d67	1114	* @retval None
n0tform3	8:1c6281289d67	1115	*/
n0tform3	8:1c6281289d67	1116	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
n0tform3	8:1c6281289d67	1117	{
n0tform3	8:1c6281289d67	1118	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1119
n0tform3	8:1c6281289d67	1120	/* Check the parameters */
n0tform3	8:1c6281289d67	1121	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1122	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
n0tform3	8:1c6281289d67	1123	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1124
n0tform3	8:1c6281289d67	1125	/* Reset the OC1M Bits */
n0tform3	8:1c6281289d67	1126	tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
n0tform3	8:1c6281289d67	1127
n0tform3	8:1c6281289d67	1128	/* Configure The Forced output Mode */
n0tform3	8:1c6281289d67	1129	tmpccmr1 \|= TIM_ForcedAction;
n0tform3	8:1c6281289d67	1130
n0tform3	8:1c6281289d67	1131	/* Write to TIMx CCMR1 register */
n0tform3	8:1c6281289d67	1132	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1133	}
n0tform3	8:1c6281289d67	1134
n0tform3	8:1c6281289d67	1135	/**
n0tform3	8:1c6281289d67	1136	* @brief Forces the TIMx output 2 waveform to active or inactive level.
n0tform3	8:1c6281289d67	1137	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1138	* peripheral.
n0tform3	8:1c6281289d67	1139	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
n0tform3	8:1c6281289d67	1140	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1141	* @arg TIM_ForcedAction_Active: Force active level on OC2REF
n0tform3	8:1c6281289d67	1142	* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
n0tform3	8:1c6281289d67	1143	* @retval None
n0tform3	8:1c6281289d67	1144	*/
n0tform3	8:1c6281289d67	1145	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
n0tform3	8:1c6281289d67	1146	{
n0tform3	8:1c6281289d67	1147	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1148
n0tform3	8:1c6281289d67	1149	/* Check the parameters */
n0tform3	8:1c6281289d67	1150	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1151	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
n0tform3	8:1c6281289d67	1152	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1153
n0tform3	8:1c6281289d67	1154	/* Reset the OC2M Bits */
n0tform3	8:1c6281289d67	1155	tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
n0tform3	8:1c6281289d67	1156
n0tform3	8:1c6281289d67	1157	/* Configure The Forced output Mode */
n0tform3	8:1c6281289d67	1158	tmpccmr1 \|= (uint16_t)(TIM_ForcedAction << 8);
n0tform3	8:1c6281289d67	1159
n0tform3	8:1c6281289d67	1160	/* Write to TIMx CCMR1 register */
n0tform3	8:1c6281289d67	1161	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1162	}
n0tform3	8:1c6281289d67	1163
n0tform3	8:1c6281289d67	1164	/**
n0tform3	8:1c6281289d67	1165	* @brief Forces the TIMx output 3 waveform to active or inactive level.
n0tform3	8:1c6281289d67	1166	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1167	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
n0tform3	8:1c6281289d67	1168	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1169	* @arg TIM_ForcedAction_Active: Force active level on OC3REF
n0tform3	8:1c6281289d67	1170	* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
n0tform3	8:1c6281289d67	1171	* @retval None
n0tform3	8:1c6281289d67	1172	*/
n0tform3	8:1c6281289d67	1173	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
n0tform3	8:1c6281289d67	1174	{
n0tform3	8:1c6281289d67	1175	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1176
n0tform3	8:1c6281289d67	1177	/* Check the parameters */
n0tform3	8:1c6281289d67	1178	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1179	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
n0tform3	8:1c6281289d67	1180
n0tform3	8:1c6281289d67	1181	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1182
n0tform3	8:1c6281289d67	1183	/* Reset the OC1M Bits */
n0tform3	8:1c6281289d67	1184	tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
n0tform3	8:1c6281289d67	1185
n0tform3	8:1c6281289d67	1186	/* Configure The Forced output Mode */
n0tform3	8:1c6281289d67	1187	tmpccmr2 \|= TIM_ForcedAction;
n0tform3	8:1c6281289d67	1188
n0tform3	8:1c6281289d67	1189	/* Write to TIMx CCMR2 register */
n0tform3	8:1c6281289d67	1190	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1191	}
n0tform3	8:1c6281289d67	1192
n0tform3	8:1c6281289d67	1193	/**
n0tform3	8:1c6281289d67	1194	* @brief Forces the TIMx output 4 waveform to active or inactive level.
n0tform3	8:1c6281289d67	1195	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1196	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
n0tform3	8:1c6281289d67	1197	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1198	* @arg TIM_ForcedAction_Active: Force active level on OC4REF
n0tform3	8:1c6281289d67	1199	* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
n0tform3	8:1c6281289d67	1200	* @retval None
n0tform3	8:1c6281289d67	1201	*/
n0tform3	8:1c6281289d67	1202	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
n0tform3	8:1c6281289d67	1203	{
n0tform3	8:1c6281289d67	1204	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1205
n0tform3	8:1c6281289d67	1206	/* Check the parameters */
n0tform3	8:1c6281289d67	1207	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1208	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
n0tform3	8:1c6281289d67	1209	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1210
n0tform3	8:1c6281289d67	1211	/* Reset the OC2M Bits */
n0tform3	8:1c6281289d67	1212	tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
n0tform3	8:1c6281289d67	1213
n0tform3	8:1c6281289d67	1214	/* Configure The Forced output Mode */
n0tform3	8:1c6281289d67	1215	tmpccmr2 \|= (uint16_t)(TIM_ForcedAction << 8);
n0tform3	8:1c6281289d67	1216
n0tform3	8:1c6281289d67	1217	/* Write to TIMx CCMR2 register */
n0tform3	8:1c6281289d67	1218	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1219	}
n0tform3	8:1c6281289d67	1220
n0tform3	8:1c6281289d67	1221	/**
n0tform3	8:1c6281289d67	1222	* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
n0tform3	8:1c6281289d67	1223	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1224	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
n0tform3	8:1c6281289d67	1225	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1226	* @arg TIM_OCPreload_Enable
n0tform3	8:1c6281289d67	1227	* @arg TIM_OCPreload_Disable
n0tform3	8:1c6281289d67	1228	* @retval None
n0tform3	8:1c6281289d67	1229	*/
n0tform3	8:1c6281289d67	1230	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
n0tform3	8:1c6281289d67	1231	{
n0tform3	8:1c6281289d67	1232	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1233
n0tform3	8:1c6281289d67	1234	/* Check the parameters */
n0tform3	8:1c6281289d67	1235	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1236	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
n0tform3	8:1c6281289d67	1237
n0tform3	8:1c6281289d67	1238	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1239
n0tform3	8:1c6281289d67	1240	/* Reset the OC1PE Bit */
n0tform3	8:1c6281289d67	1241	tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
n0tform3	8:1c6281289d67	1242
n0tform3	8:1c6281289d67	1243	/* Enable or Disable the Output Compare Preload feature */
n0tform3	8:1c6281289d67	1244	tmpccmr1 \|= TIM_OCPreload;
n0tform3	8:1c6281289d67	1245
n0tform3	8:1c6281289d67	1246	/* Write to TIMx CCMR1 register */
n0tform3	8:1c6281289d67	1247	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1248	}
n0tform3	8:1c6281289d67	1249
n0tform3	8:1c6281289d67	1250	/**
n0tform3	8:1c6281289d67	1251	* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
n0tform3	8:1c6281289d67	1252	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1253	* peripheral.
n0tform3	8:1c6281289d67	1254	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
n0tform3	8:1c6281289d67	1255	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1256	* @arg TIM_OCPreload_Enable
n0tform3	8:1c6281289d67	1257	* @arg TIM_OCPreload_Disable
n0tform3	8:1c6281289d67	1258	* @retval None
n0tform3	8:1c6281289d67	1259	*/
n0tform3	8:1c6281289d67	1260	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
n0tform3	8:1c6281289d67	1261	{
n0tform3	8:1c6281289d67	1262	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1263
n0tform3	8:1c6281289d67	1264	/* Check the parameters */
n0tform3	8:1c6281289d67	1265	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1266	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
n0tform3	8:1c6281289d67	1267
n0tform3	8:1c6281289d67	1268	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1269
n0tform3	8:1c6281289d67	1270	/* Reset the OC2PE Bit */
n0tform3	8:1c6281289d67	1271	tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
n0tform3	8:1c6281289d67	1272
n0tform3	8:1c6281289d67	1273	/* Enable or Disable the Output Compare Preload feature */
n0tform3	8:1c6281289d67	1274	tmpccmr1 \|= (uint16_t)(TIM_OCPreload << 8);
n0tform3	8:1c6281289d67	1275
n0tform3	8:1c6281289d67	1276	/* Write to TIMx CCMR1 register */
n0tform3	8:1c6281289d67	1277	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1278	}
n0tform3	8:1c6281289d67	1279
n0tform3	8:1c6281289d67	1280	/**
n0tform3	8:1c6281289d67	1281	* @brief Enables or disables the TIMx peripheral Preload register on CCR3.
n0tform3	8:1c6281289d67	1282	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1283	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
n0tform3	8:1c6281289d67	1284	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1285	* @arg TIM_OCPreload_Enable
n0tform3	8:1c6281289d67	1286	* @arg TIM_OCPreload_Disable
n0tform3	8:1c6281289d67	1287	* @retval None
n0tform3	8:1c6281289d67	1288	*/
n0tform3	8:1c6281289d67	1289	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
n0tform3	8:1c6281289d67	1290	{
n0tform3	8:1c6281289d67	1291	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1292
n0tform3	8:1c6281289d67	1293	/* Check the parameters */
n0tform3	8:1c6281289d67	1294	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1295	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
n0tform3	8:1c6281289d67	1296
n0tform3	8:1c6281289d67	1297	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1298
n0tform3	8:1c6281289d67	1299	/* Reset the OC3PE Bit */
n0tform3	8:1c6281289d67	1300	tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
n0tform3	8:1c6281289d67	1301
n0tform3	8:1c6281289d67	1302	/* Enable or Disable the Output Compare Preload feature */
n0tform3	8:1c6281289d67	1303	tmpccmr2 \|= TIM_OCPreload;
n0tform3	8:1c6281289d67	1304
n0tform3	8:1c6281289d67	1305	/* Write to TIMx CCMR2 register */
n0tform3	8:1c6281289d67	1306	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1307	}
n0tform3	8:1c6281289d67	1308
n0tform3	8:1c6281289d67	1309	/**
n0tform3	8:1c6281289d67	1310	* @brief Enables or disables the TIMx peripheral Preload register on CCR4.
n0tform3	8:1c6281289d67	1311	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1312	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
n0tform3	8:1c6281289d67	1313	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1314	* @arg TIM_OCPreload_Enable
n0tform3	8:1c6281289d67	1315	* @arg TIM_OCPreload_Disable
n0tform3	8:1c6281289d67	1316	* @retval None
n0tform3	8:1c6281289d67	1317	*/
n0tform3	8:1c6281289d67	1318	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
n0tform3	8:1c6281289d67	1319	{
n0tform3	8:1c6281289d67	1320	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1321
n0tform3	8:1c6281289d67	1322	/* Check the parameters */
n0tform3	8:1c6281289d67	1323	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1324	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
n0tform3	8:1c6281289d67	1325
n0tform3	8:1c6281289d67	1326	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1327
n0tform3	8:1c6281289d67	1328	/* Reset the OC4PE Bit */
n0tform3	8:1c6281289d67	1329	tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
n0tform3	8:1c6281289d67	1330
n0tform3	8:1c6281289d67	1331	/* Enable or Disable the Output Compare Preload feature */
n0tform3	8:1c6281289d67	1332	tmpccmr2 \|= (uint16_t)(TIM_OCPreload << 8);
n0tform3	8:1c6281289d67	1333
n0tform3	8:1c6281289d67	1334	/* Write to TIMx CCMR2 register */
n0tform3	8:1c6281289d67	1335	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1336	}
n0tform3	8:1c6281289d67	1337
n0tform3	8:1c6281289d67	1338	/**
n0tform3	8:1c6281289d67	1339	* @brief Configures the TIMx Output Compare 1 Fast feature.
n0tform3	8:1c6281289d67	1340	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1341	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
n0tform3	8:1c6281289d67	1342	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1343	* @arg TIM_OCFast_Enable: TIM output compare fast enable
n0tform3	8:1c6281289d67	1344	* @arg TIM_OCFast_Disable: TIM output compare fast disable
n0tform3	8:1c6281289d67	1345	* @retval None
n0tform3	8:1c6281289d67	1346	*/
n0tform3	8:1c6281289d67	1347	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
n0tform3	8:1c6281289d67	1348	{
n0tform3	8:1c6281289d67	1349	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1350
n0tform3	8:1c6281289d67	1351	/* Check the parameters */
n0tform3	8:1c6281289d67	1352	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1353	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
n0tform3	8:1c6281289d67	1354
n0tform3	8:1c6281289d67	1355	/* Get the TIMx CCMR1 register value */
n0tform3	8:1c6281289d67	1356	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1357
n0tform3	8:1c6281289d67	1358	/* Reset the OC1FE Bit */
n0tform3	8:1c6281289d67	1359	tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
n0tform3	8:1c6281289d67	1360
n0tform3	8:1c6281289d67	1361	/* Enable or Disable the Output Compare Fast Bit */
n0tform3	8:1c6281289d67	1362	tmpccmr1 \|= TIM_OCFast;
n0tform3	8:1c6281289d67	1363
n0tform3	8:1c6281289d67	1364	/* Write to TIMx CCMR1 */
n0tform3	8:1c6281289d67	1365	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1366	}
n0tform3	8:1c6281289d67	1367
n0tform3	8:1c6281289d67	1368	/**
n0tform3	8:1c6281289d67	1369	* @brief Configures the TIMx Output Compare 2 Fast feature.
n0tform3	8:1c6281289d67	1370	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1371	* peripheral.
n0tform3	8:1c6281289d67	1372	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
n0tform3	8:1c6281289d67	1373	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1374	* @arg TIM_OCFast_Enable: TIM output compare fast enable
n0tform3	8:1c6281289d67	1375	* @arg TIM_OCFast_Disable: TIM output compare fast disable
n0tform3	8:1c6281289d67	1376	* @retval None
n0tform3	8:1c6281289d67	1377	*/
n0tform3	8:1c6281289d67	1378	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
n0tform3	8:1c6281289d67	1379	{
n0tform3	8:1c6281289d67	1380	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1381
n0tform3	8:1c6281289d67	1382	/* Check the parameters */
n0tform3	8:1c6281289d67	1383	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1384	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
n0tform3	8:1c6281289d67	1385
n0tform3	8:1c6281289d67	1386	/* Get the TIMx CCMR1 register value */
n0tform3	8:1c6281289d67	1387	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1388
n0tform3	8:1c6281289d67	1389	/* Reset the OC2FE Bit */
n0tform3	8:1c6281289d67	1390	tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
n0tform3	8:1c6281289d67	1391
n0tform3	8:1c6281289d67	1392	/* Enable or Disable the Output Compare Fast Bit */
n0tform3	8:1c6281289d67	1393	tmpccmr1 \|= (uint16_t)(TIM_OCFast << 8);
n0tform3	8:1c6281289d67	1394
n0tform3	8:1c6281289d67	1395	/* Write to TIMx CCMR1 */
n0tform3	8:1c6281289d67	1396	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1397	}
n0tform3	8:1c6281289d67	1398
n0tform3	8:1c6281289d67	1399	/**
n0tform3	8:1c6281289d67	1400	* @brief Configures the TIMx Output Compare 3 Fast feature.
n0tform3	8:1c6281289d67	1401	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1402	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
n0tform3	8:1c6281289d67	1403	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1404	* @arg TIM_OCFast_Enable: TIM output compare fast enable
n0tform3	8:1c6281289d67	1405	* @arg TIM_OCFast_Disable: TIM output compare fast disable
n0tform3	8:1c6281289d67	1406	* @retval None
n0tform3	8:1c6281289d67	1407	*/
n0tform3	8:1c6281289d67	1408	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
n0tform3	8:1c6281289d67	1409	{
n0tform3	8:1c6281289d67	1410	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1411
n0tform3	8:1c6281289d67	1412	/* Check the parameters */
n0tform3	8:1c6281289d67	1413	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1414	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
n0tform3	8:1c6281289d67	1415
n0tform3	8:1c6281289d67	1416	/* Get the TIMx CCMR2 register value */
n0tform3	8:1c6281289d67	1417	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1418
n0tform3	8:1c6281289d67	1419	/* Reset the OC3FE Bit */
n0tform3	8:1c6281289d67	1420	tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
n0tform3	8:1c6281289d67	1421
n0tform3	8:1c6281289d67	1422	/* Enable or Disable the Output Compare Fast Bit */
n0tform3	8:1c6281289d67	1423	tmpccmr2 \|= TIM_OCFast;
n0tform3	8:1c6281289d67	1424
n0tform3	8:1c6281289d67	1425	/* Write to TIMx CCMR2 */
n0tform3	8:1c6281289d67	1426	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1427	}
n0tform3	8:1c6281289d67	1428
n0tform3	8:1c6281289d67	1429	/**
n0tform3	8:1c6281289d67	1430	* @brief Configures the TIMx Output Compare 4 Fast feature.
n0tform3	8:1c6281289d67	1431	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1432	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
n0tform3	8:1c6281289d67	1433	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1434	* @arg TIM_OCFast_Enable: TIM output compare fast enable
n0tform3	8:1c6281289d67	1435	* @arg TIM_OCFast_Disable: TIM output compare fast disable
n0tform3	8:1c6281289d67	1436	* @retval None
n0tform3	8:1c6281289d67	1437	*/
n0tform3	8:1c6281289d67	1438	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
n0tform3	8:1c6281289d67	1439	{
n0tform3	8:1c6281289d67	1440	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1441
n0tform3	8:1c6281289d67	1442	/* Check the parameters */
n0tform3	8:1c6281289d67	1443	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1444	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
n0tform3	8:1c6281289d67	1445
n0tform3	8:1c6281289d67	1446	/* Get the TIMx CCMR2 register value */
n0tform3	8:1c6281289d67	1447	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1448
n0tform3	8:1c6281289d67	1449	/* Reset the OC4FE Bit */
n0tform3	8:1c6281289d67	1450	tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
n0tform3	8:1c6281289d67	1451
n0tform3	8:1c6281289d67	1452	/* Enable or Disable the Output Compare Fast Bit */
n0tform3	8:1c6281289d67	1453	tmpccmr2 \|= (uint16_t)(TIM_OCFast << 8);
n0tform3	8:1c6281289d67	1454
n0tform3	8:1c6281289d67	1455	/* Write to TIMx CCMR2 */
n0tform3	8:1c6281289d67	1456	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1457	}
n0tform3	8:1c6281289d67	1458
n0tform3	8:1c6281289d67	1459	/**
n0tform3	8:1c6281289d67	1460	* @brief Clears or safeguards the OCREF1 signal on an external event
n0tform3	8:1c6281289d67	1461	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1462	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
n0tform3	8:1c6281289d67	1463	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1464	* @arg TIM_OCClear_Enable: TIM Output clear enable
n0tform3	8:1c6281289d67	1465	* @arg TIM_OCClear_Disable: TIM Output clear disable
n0tform3	8:1c6281289d67	1466	* @retval None
n0tform3	8:1c6281289d67	1467	*/
n0tform3	8:1c6281289d67	1468	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
n0tform3	8:1c6281289d67	1469	{
n0tform3	8:1c6281289d67	1470	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1471
n0tform3	8:1c6281289d67	1472	/* Check the parameters */
n0tform3	8:1c6281289d67	1473	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1474	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
n0tform3	8:1c6281289d67	1475
n0tform3	8:1c6281289d67	1476	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1477
n0tform3	8:1c6281289d67	1478	/* Reset the OC1CE Bit */
n0tform3	8:1c6281289d67	1479	tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
n0tform3	8:1c6281289d67	1480
n0tform3	8:1c6281289d67	1481	/* Enable or Disable the Output Compare Clear Bit */
n0tform3	8:1c6281289d67	1482	tmpccmr1 \|= TIM_OCClear;
n0tform3	8:1c6281289d67	1483
n0tform3	8:1c6281289d67	1484	/* Write to TIMx CCMR1 register */
n0tform3	8:1c6281289d67	1485	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1486	}
n0tform3	8:1c6281289d67	1487
n0tform3	8:1c6281289d67	1488	/**
n0tform3	8:1c6281289d67	1489	* @brief Clears or safeguards the OCREF2 signal on an external event
n0tform3	8:1c6281289d67	1490	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1491	* peripheral.
n0tform3	8:1c6281289d67	1492	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
n0tform3	8:1c6281289d67	1493	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1494	* @arg TIM_OCClear_Enable: TIM Output clear enable
n0tform3	8:1c6281289d67	1495	* @arg TIM_OCClear_Disable: TIM Output clear disable
n0tform3	8:1c6281289d67	1496	* @retval None
n0tform3	8:1c6281289d67	1497	*/
n0tform3	8:1c6281289d67	1498	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
n0tform3	8:1c6281289d67	1499	{
n0tform3	8:1c6281289d67	1500	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	1501
n0tform3	8:1c6281289d67	1502	/* Check the parameters */
n0tform3	8:1c6281289d67	1503	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1504	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
n0tform3	8:1c6281289d67	1505
n0tform3	8:1c6281289d67	1506	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	1507
n0tform3	8:1c6281289d67	1508	/* Reset the OC2CE Bit */
n0tform3	8:1c6281289d67	1509	tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
n0tform3	8:1c6281289d67	1510
n0tform3	8:1c6281289d67	1511	/* Enable or Disable the Output Compare Clear Bit */
n0tform3	8:1c6281289d67	1512	tmpccmr1 \|= (uint16_t)(TIM_OCClear << 8);
n0tform3	8:1c6281289d67	1513
n0tform3	8:1c6281289d67	1514	/* Write to TIMx CCMR1 register */
n0tform3	8:1c6281289d67	1515	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	1516	}
n0tform3	8:1c6281289d67	1517
n0tform3	8:1c6281289d67	1518	/**
n0tform3	8:1c6281289d67	1519	* @brief Clears or safeguards the OCREF3 signal on an external event
n0tform3	8:1c6281289d67	1520	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1521	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
n0tform3	8:1c6281289d67	1522	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1523	* @arg TIM_OCClear_Enable: TIM Output clear enable
n0tform3	8:1c6281289d67	1524	* @arg TIM_OCClear_Disable: TIM Output clear disable
n0tform3	8:1c6281289d67	1525	* @retval None
n0tform3	8:1c6281289d67	1526	*/
n0tform3	8:1c6281289d67	1527	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
n0tform3	8:1c6281289d67	1528	{
n0tform3	8:1c6281289d67	1529	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1530
n0tform3	8:1c6281289d67	1531	/* Check the parameters */
n0tform3	8:1c6281289d67	1532	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1533	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
n0tform3	8:1c6281289d67	1534
n0tform3	8:1c6281289d67	1535	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1536
n0tform3	8:1c6281289d67	1537	/* Reset the OC3CE Bit */
n0tform3	8:1c6281289d67	1538	tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
n0tform3	8:1c6281289d67	1539
n0tform3	8:1c6281289d67	1540	/* Enable or Disable the Output Compare Clear Bit */
n0tform3	8:1c6281289d67	1541	tmpccmr2 \|= TIM_OCClear;
n0tform3	8:1c6281289d67	1542
n0tform3	8:1c6281289d67	1543	/* Write to TIMx CCMR2 register */
n0tform3	8:1c6281289d67	1544	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1545	}
n0tform3	8:1c6281289d67	1546
n0tform3	8:1c6281289d67	1547	/**
n0tform3	8:1c6281289d67	1548	* @brief Clears or safeguards the OCREF4 signal on an external event
n0tform3	8:1c6281289d67	1549	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1550	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
n0tform3	8:1c6281289d67	1551	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1552	* @arg TIM_OCClear_Enable: TIM Output clear enable
n0tform3	8:1c6281289d67	1553	* @arg TIM_OCClear_Disable: TIM Output clear disable
n0tform3	8:1c6281289d67	1554	* @retval None
n0tform3	8:1c6281289d67	1555	*/
n0tform3	8:1c6281289d67	1556	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
n0tform3	8:1c6281289d67	1557	{
n0tform3	8:1c6281289d67	1558	uint16_t tmpccmr2 = 0;
n0tform3	8:1c6281289d67	1559
n0tform3	8:1c6281289d67	1560	/* Check the parameters */
n0tform3	8:1c6281289d67	1561	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1562	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
n0tform3	8:1c6281289d67	1563
n0tform3	8:1c6281289d67	1564	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	1565
n0tform3	8:1c6281289d67	1566	/* Reset the OC4CE Bit */
n0tform3	8:1c6281289d67	1567	tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
n0tform3	8:1c6281289d67	1568
n0tform3	8:1c6281289d67	1569	/* Enable or Disable the Output Compare Clear Bit */
n0tform3	8:1c6281289d67	1570	tmpccmr2 \|= (uint16_t)(TIM_OCClear << 8);
n0tform3	8:1c6281289d67	1571
n0tform3	8:1c6281289d67	1572	/* Write to TIMx CCMR2 register */
n0tform3	8:1c6281289d67	1573	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	1574	}
n0tform3	8:1c6281289d67	1575
n0tform3	8:1c6281289d67	1576	/**
n0tform3	8:1c6281289d67	1577	* @brief Configures the TIMx channel 1 polarity.
n0tform3	8:1c6281289d67	1578	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1579	* @param TIM_OCPolarity: specifies the OC1 Polarity
n0tform3	8:1c6281289d67	1580	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1581	* @arg TIM_OCPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1582	* @arg TIM_OCPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1583	* @retval None
n0tform3	8:1c6281289d67	1584	*/
n0tform3	8:1c6281289d67	1585	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
n0tform3	8:1c6281289d67	1586	{
n0tform3	8:1c6281289d67	1587	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1588
n0tform3	8:1c6281289d67	1589	/* Check the parameters */
n0tform3	8:1c6281289d67	1590	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1591	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
n0tform3	8:1c6281289d67	1592
n0tform3	8:1c6281289d67	1593	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1594
n0tform3	8:1c6281289d67	1595	/* Set or Reset the CC1P Bit */
n0tform3	8:1c6281289d67	1596	tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
n0tform3	8:1c6281289d67	1597	tmpccer \|= TIM_OCPolarity;
n0tform3	8:1c6281289d67	1598
n0tform3	8:1c6281289d67	1599	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1600	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1601	}
n0tform3	8:1c6281289d67	1602
n0tform3	8:1c6281289d67	1603	/**
n0tform3	8:1c6281289d67	1604	* @brief Configures the TIMx Channel 1N polarity.
n0tform3	8:1c6281289d67	1605	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1606	* @param TIM_OCNPolarity: specifies the OC1N Polarity
n0tform3	8:1c6281289d67	1607	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1608	* @arg TIM_OCNPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1609	* @arg TIM_OCNPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1610	* @retval None
n0tform3	8:1c6281289d67	1611	*/
n0tform3	8:1c6281289d67	1612	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
n0tform3	8:1c6281289d67	1613	{
n0tform3	8:1c6281289d67	1614	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1615	/* Check the parameters */
n0tform3	8:1c6281289d67	1616	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1617	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
n0tform3	8:1c6281289d67	1618
n0tform3	8:1c6281289d67	1619	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1620
n0tform3	8:1c6281289d67	1621	/* Set or Reset the CC1NP Bit */
n0tform3	8:1c6281289d67	1622	tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
n0tform3	8:1c6281289d67	1623	tmpccer \|= TIM_OCNPolarity;
n0tform3	8:1c6281289d67	1624
n0tform3	8:1c6281289d67	1625	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1626	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1627	}
n0tform3	8:1c6281289d67	1628
n0tform3	8:1c6281289d67	1629	/**
n0tform3	8:1c6281289d67	1630	* @brief Configures the TIMx channel 2 polarity.
n0tform3	8:1c6281289d67	1631	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1632	* peripheral.
n0tform3	8:1c6281289d67	1633	* @param TIM_OCPolarity: specifies the OC2 Polarity
n0tform3	8:1c6281289d67	1634	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1635	* @arg TIM_OCPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1636	* @arg TIM_OCPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1637	* @retval None
n0tform3	8:1c6281289d67	1638	*/
n0tform3	8:1c6281289d67	1639	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
n0tform3	8:1c6281289d67	1640	{
n0tform3	8:1c6281289d67	1641	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1642
n0tform3	8:1c6281289d67	1643	/* Check the parameters */
n0tform3	8:1c6281289d67	1644	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1645	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
n0tform3	8:1c6281289d67	1646
n0tform3	8:1c6281289d67	1647	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1648
n0tform3	8:1c6281289d67	1649	/* Set or Reset the CC2P Bit */
n0tform3	8:1c6281289d67	1650	tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
n0tform3	8:1c6281289d67	1651	tmpccer \|= (uint16_t)(TIM_OCPolarity << 4);
n0tform3	8:1c6281289d67	1652
n0tform3	8:1c6281289d67	1653	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1654	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1655	}
n0tform3	8:1c6281289d67	1656
n0tform3	8:1c6281289d67	1657	/**
n0tform3	8:1c6281289d67	1658	* @brief Configures the TIMx Channel 2N polarity.
n0tform3	8:1c6281289d67	1659	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1660	* @param TIM_OCNPolarity: specifies the OC2N Polarity
n0tform3	8:1c6281289d67	1661	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1662	* @arg TIM_OCNPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1663	* @arg TIM_OCNPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1664	* @retval None
n0tform3	8:1c6281289d67	1665	*/
n0tform3	8:1c6281289d67	1666	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
n0tform3	8:1c6281289d67	1667	{
n0tform3	8:1c6281289d67	1668	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1669
n0tform3	8:1c6281289d67	1670	/* Check the parameters */
n0tform3	8:1c6281289d67	1671	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1672	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
n0tform3	8:1c6281289d67	1673
n0tform3	8:1c6281289d67	1674	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1675
n0tform3	8:1c6281289d67	1676	/* Set or Reset the CC2NP Bit */
n0tform3	8:1c6281289d67	1677	tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
n0tform3	8:1c6281289d67	1678	tmpccer \|= (uint16_t)(TIM_OCNPolarity << 4);
n0tform3	8:1c6281289d67	1679
n0tform3	8:1c6281289d67	1680	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1681	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1682	}
n0tform3	8:1c6281289d67	1683
n0tform3	8:1c6281289d67	1684	/**
n0tform3	8:1c6281289d67	1685	* @brief Configures the TIMx channel 3 polarity.
n0tform3	8:1c6281289d67	1686	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1687	* @param TIM_OCPolarity: specifies the OC3 Polarity
n0tform3	8:1c6281289d67	1688	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1689	* @arg TIM_OCPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1690	* @arg TIM_OCPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1691	* @retval None
n0tform3	8:1c6281289d67	1692	*/
n0tform3	8:1c6281289d67	1693	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
n0tform3	8:1c6281289d67	1694	{
n0tform3	8:1c6281289d67	1695	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1696
n0tform3	8:1c6281289d67	1697	/* Check the parameters */
n0tform3	8:1c6281289d67	1698	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1699	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
n0tform3	8:1c6281289d67	1700
n0tform3	8:1c6281289d67	1701	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1702
n0tform3	8:1c6281289d67	1703	/* Set or Reset the CC3P Bit */
n0tform3	8:1c6281289d67	1704	tmpccer &= (uint16_t)~TIM_CCER_CC3P;
n0tform3	8:1c6281289d67	1705	tmpccer \|= (uint16_t)(TIM_OCPolarity << 8);
n0tform3	8:1c6281289d67	1706
n0tform3	8:1c6281289d67	1707	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1708	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1709	}
n0tform3	8:1c6281289d67	1710
n0tform3	8:1c6281289d67	1711	/**
n0tform3	8:1c6281289d67	1712	* @brief Configures the TIMx Channel 3N polarity.
n0tform3	8:1c6281289d67	1713	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1714	* @param TIM_OCNPolarity: specifies the OC3N Polarity
n0tform3	8:1c6281289d67	1715	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1716	* @arg TIM_OCNPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1717	* @arg TIM_OCNPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1718	* @retval None
n0tform3	8:1c6281289d67	1719	*/
n0tform3	8:1c6281289d67	1720	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
n0tform3	8:1c6281289d67	1721	{
n0tform3	8:1c6281289d67	1722	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1723
n0tform3	8:1c6281289d67	1724	/* Check the parameters */
n0tform3	8:1c6281289d67	1725	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1726	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
n0tform3	8:1c6281289d67	1727
n0tform3	8:1c6281289d67	1728	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1729
n0tform3	8:1c6281289d67	1730	/* Set or Reset the CC3NP Bit */
n0tform3	8:1c6281289d67	1731	tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
n0tform3	8:1c6281289d67	1732	tmpccer \|= (uint16_t)(TIM_OCNPolarity << 8);
n0tform3	8:1c6281289d67	1733
n0tform3	8:1c6281289d67	1734	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1735	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1736	}
n0tform3	8:1c6281289d67	1737
n0tform3	8:1c6281289d67	1738	/**
n0tform3	8:1c6281289d67	1739	* @brief Configures the TIMx channel 4 polarity.
n0tform3	8:1c6281289d67	1740	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1741	* @param TIM_OCPolarity: specifies the OC4 Polarity
n0tform3	8:1c6281289d67	1742	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1743	* @arg TIM_OCPolarity_High: Output Compare active high
n0tform3	8:1c6281289d67	1744	* @arg TIM_OCPolarity_Low: Output Compare active low
n0tform3	8:1c6281289d67	1745	* @retval None
n0tform3	8:1c6281289d67	1746	*/
n0tform3	8:1c6281289d67	1747	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
n0tform3	8:1c6281289d67	1748	{
n0tform3	8:1c6281289d67	1749	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	1750
n0tform3	8:1c6281289d67	1751	/* Check the parameters */
n0tform3	8:1c6281289d67	1752	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1753	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
n0tform3	8:1c6281289d67	1754
n0tform3	8:1c6281289d67	1755	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	1756
n0tform3	8:1c6281289d67	1757	/* Set or Reset the CC4P Bit */
n0tform3	8:1c6281289d67	1758	tmpccer &= (uint16_t)~TIM_CCER_CC4P;
n0tform3	8:1c6281289d67	1759	tmpccer \|= (uint16_t)(TIM_OCPolarity << 12);
n0tform3	8:1c6281289d67	1760
n0tform3	8:1c6281289d67	1761	/* Write to TIMx CCER register */
n0tform3	8:1c6281289d67	1762	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	1763	}
n0tform3	8:1c6281289d67	1764
n0tform3	8:1c6281289d67	1765	/**
n0tform3	8:1c6281289d67	1766	* @brief Enables or disables the TIM Capture Compare Channel x.
n0tform3	8:1c6281289d67	1767	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1768	* @param TIM_Channel: specifies the TIM Channel
n0tform3	8:1c6281289d67	1769	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1770	* @arg TIM_Channel_1: TIM Channel 1
n0tform3	8:1c6281289d67	1771	* @arg TIM_Channel_2: TIM Channel 2
n0tform3	8:1c6281289d67	1772	* @arg TIM_Channel_3: TIM Channel 3
n0tform3	8:1c6281289d67	1773	* @arg TIM_Channel_4: TIM Channel 4
n0tform3	8:1c6281289d67	1774	* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
n0tform3	8:1c6281289d67	1775	* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
n0tform3	8:1c6281289d67	1776	* @retval None
n0tform3	8:1c6281289d67	1777	*/
n0tform3	8:1c6281289d67	1778	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
n0tform3	8:1c6281289d67	1779	{
n0tform3	8:1c6281289d67	1780	uint16_t tmp = 0;
n0tform3	8:1c6281289d67	1781
n0tform3	8:1c6281289d67	1782	/* Check the parameters */
n0tform3	8:1c6281289d67	1783	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1784	assert_param(IS_TIM_CHANNEL(TIM_Channel));
n0tform3	8:1c6281289d67	1785	assert_param(IS_TIM_CCX(TIM_CCx));
n0tform3	8:1c6281289d67	1786
n0tform3	8:1c6281289d67	1787	tmp = CCER_CCE_SET << TIM_Channel;
n0tform3	8:1c6281289d67	1788
n0tform3	8:1c6281289d67	1789	/* Reset the CCxE Bit */
n0tform3	8:1c6281289d67	1790	TIMx->CCER &= (uint16_t)~ tmp;
n0tform3	8:1c6281289d67	1791
n0tform3	8:1c6281289d67	1792	/* Set or reset the CCxE Bit */
n0tform3	8:1c6281289d67	1793	TIMx->CCER \|= (uint16_t)(TIM_CCx << TIM_Channel);
n0tform3	8:1c6281289d67	1794	}
n0tform3	8:1c6281289d67	1795
n0tform3	8:1c6281289d67	1796	/**
n0tform3	8:1c6281289d67	1797	* @brief Enables or disables the TIM Capture Compare Channel xN.
n0tform3	8:1c6281289d67	1798	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	1799	* @param TIM_Channel: specifies the TIM Channel
n0tform3	8:1c6281289d67	1800	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1801	* @arg TIM_Channel_1: TIM Channel 1
n0tform3	8:1c6281289d67	1802	* @arg TIM_Channel_2: TIM Channel 2
n0tform3	8:1c6281289d67	1803	* @arg TIM_Channel_3: TIM Channel 3
n0tform3	8:1c6281289d67	1804	* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
n0tform3	8:1c6281289d67	1805	* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
n0tform3	8:1c6281289d67	1806	* @retval None
n0tform3	8:1c6281289d67	1807	*/
n0tform3	8:1c6281289d67	1808	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
n0tform3	8:1c6281289d67	1809	{
n0tform3	8:1c6281289d67	1810	uint16_t tmp = 0;
n0tform3	8:1c6281289d67	1811
n0tform3	8:1c6281289d67	1812	/* Check the parameters */
n0tform3	8:1c6281289d67	1813	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1814	assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
n0tform3	8:1c6281289d67	1815	assert_param(IS_TIM_CCXN(TIM_CCxN));
n0tform3	8:1c6281289d67	1816
n0tform3	8:1c6281289d67	1817	tmp = CCER_CCNE_SET << TIM_Channel;
n0tform3	8:1c6281289d67	1818
n0tform3	8:1c6281289d67	1819	/* Reset the CCxNE Bit */
n0tform3	8:1c6281289d67	1820	TIMx->CCER &= (uint16_t) ~tmp;
n0tform3	8:1c6281289d67	1821
n0tform3	8:1c6281289d67	1822	/* Set or reset the CCxNE Bit */
n0tform3	8:1c6281289d67	1823	TIMx->CCER \|= (uint16_t)(TIM_CCxN << TIM_Channel);
n0tform3	8:1c6281289d67	1824	}
n0tform3	8:1c6281289d67	1825	/**
n0tform3	8:1c6281289d67	1826	* @}
n0tform3	8:1c6281289d67	1827	*/
n0tform3	8:1c6281289d67	1828
n0tform3	8:1c6281289d67	1829	/** @defgroup TIM_Group3 Input Capture management functions
n0tform3	8:1c6281289d67	1830	* @brief Input Capture management functions
n0tform3	8:1c6281289d67	1831	*
n0tform3	8:1c6281289d67	1832	@verbatim
n0tform3	8:1c6281289d67	1833	===============================================================================
n0tform3	8:1c6281289d67	1834	Input Capture management functions
n0tform3	8:1c6281289d67	1835	===============================================================================
n0tform3	8:1c6281289d67	1836
n0tform3	8:1c6281289d67	1837	===================================================================
n0tform3	8:1c6281289d67	1838	TIM Driver: how to use it in Input Capture Mode
n0tform3	8:1c6281289d67	1839	===================================================================
n0tform3	8:1c6281289d67	1840	To use the Timer in Input Capture mode, the following steps are mandatory:
n0tform3	8:1c6281289d67	1841
n0tform3	8:1c6281289d67	1842	1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
n0tform3	8:1c6281289d67	1843
n0tform3	8:1c6281289d67	1844	2. Configure the TIM pins by configuring the corresponding GPIO pins
n0tform3	8:1c6281289d67	1845
n0tform3	8:1c6281289d67	1846	2. Configure the Time base unit as described in the first part of this driver,
n0tform3	8:1c6281289d67	1847	if needed, else the Timer will run with the default configuration:
n0tform3	8:1c6281289d67	1848	- Autoreload value = 0xFFFF
n0tform3	8:1c6281289d67	1849	- Prescaler value = 0x0000
n0tform3	8:1c6281289d67	1850	- Counter mode = Up counting
n0tform3	8:1c6281289d67	1851	- Clock Division = TIM_CKD_DIV1
n0tform3	8:1c6281289d67	1852
n0tform3	8:1c6281289d67	1853	3. Fill the TIM_ICInitStruct with the desired parameters including:
n0tform3	8:1c6281289d67	1854	- TIM Channel: TIM_Channel
n0tform3	8:1c6281289d67	1855	- TIM Input Capture polarity: TIM_ICPolarity
n0tform3	8:1c6281289d67	1856	- TIM Input Capture selection: TIM_ICSelection
n0tform3	8:1c6281289d67	1857	- TIM Input Capture Prescaler: TIM_ICPrescaler
n0tform3	8:1c6281289d67	1858	- TIM Input CApture filter value: TIM_ICFilter
n0tform3	8:1c6281289d67	1859
n0tform3	8:1c6281289d67	1860	4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
n0tform3	8:1c6281289d67	1861	corresponding configuration and to measure only frequency or duty cycle of the input signal,
n0tform3	8:1c6281289d67	1862	or,
n0tform3	8:1c6281289d67	1863	Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
n0tform3	8:1c6281289d67	1864	corresponding configuration and to measure the frequency and the duty cycle of the input signal
n0tform3	8:1c6281289d67	1865
n0tform3	8:1c6281289d67	1866	5. Enable the NVIC or the DMA to read the measured frequency.
n0tform3	8:1c6281289d67	1867
n0tform3	8:1c6281289d67	1868	6. Enable the corresponding interrupt (or DMA request) to read the Captured value,
n0tform3	8:1c6281289d67	1869	using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
n0tform3	8:1c6281289d67	1870
n0tform3	8:1c6281289d67	1871	7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
n0tform3	8:1c6281289d67	1872
n0tform3	8:1c6281289d67	1873	8. Use TIM_GetCapturex(TIMx); to read the captured value.
n0tform3	8:1c6281289d67	1874
n0tform3	8:1c6281289d67	1875	Note1: All other functions can be used separately to modify, if needed,
n0tform3	8:1c6281289d67	1876	a specific feature of the Timer.
n0tform3	8:1c6281289d67	1877
n0tform3	8:1c6281289d67	1878	@endverbatim
n0tform3	8:1c6281289d67	1879	* @{
n0tform3	8:1c6281289d67	1880	*/
n0tform3	8:1c6281289d67	1881
n0tform3	8:1c6281289d67	1882	/**
n0tform3	8:1c6281289d67	1883	* @brief Initializes the TIM peripheral according to the specified parameters
n0tform3	8:1c6281289d67	1884	* in the TIM_ICInitStruct.
n0tform3	8:1c6281289d67	1885	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	1886	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
n0tform3	8:1c6281289d67	1887	* the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	1888	* @retval None
n0tform3	8:1c6281289d67	1889	*/
n0tform3	8:1c6281289d67	1890	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
n0tform3	8:1c6281289d67	1891	{
n0tform3	8:1c6281289d67	1892	/* Check the parameters */
n0tform3	8:1c6281289d67	1893	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1894	assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
n0tform3	8:1c6281289d67	1895	assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
n0tform3	8:1c6281289d67	1896	assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
n0tform3	8:1c6281289d67	1897	assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
n0tform3	8:1c6281289d67	1898
n0tform3	8:1c6281289d67	1899	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
n0tform3	8:1c6281289d67	1900	{
n0tform3	8:1c6281289d67	1901	/* TI1 Configuration */
n0tform3	8:1c6281289d67	1902	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
n0tform3	8:1c6281289d67	1903	TIM_ICInitStruct->TIM_ICSelection,
n0tform3	8:1c6281289d67	1904	TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	1905	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	1906	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	1907	}
n0tform3	8:1c6281289d67	1908	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
n0tform3	8:1c6281289d67	1909	{
n0tform3	8:1c6281289d67	1910	/* TI2 Configuration */
n0tform3	8:1c6281289d67	1911	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1912	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
n0tform3	8:1c6281289d67	1913	TIM_ICInitStruct->TIM_ICSelection,
n0tform3	8:1c6281289d67	1914	TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	1915	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	1916	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	1917	}
n0tform3	8:1c6281289d67	1918	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
n0tform3	8:1c6281289d67	1919	{
n0tform3	8:1c6281289d67	1920	/* TI3 Configuration */
n0tform3	8:1c6281289d67	1921	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1922	TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
n0tform3	8:1c6281289d67	1923	TIM_ICInitStruct->TIM_ICSelection,
n0tform3	8:1c6281289d67	1924	TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	1925	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	1926	TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	1927	}
n0tform3	8:1c6281289d67	1928	else
n0tform3	8:1c6281289d67	1929	{
n0tform3	8:1c6281289d67	1930	/* TI4 Configuration */
n0tform3	8:1c6281289d67	1931	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1932	TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
n0tform3	8:1c6281289d67	1933	TIM_ICInitStruct->TIM_ICSelection,
n0tform3	8:1c6281289d67	1934	TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	1935	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	1936	TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	1937	}
n0tform3	8:1c6281289d67	1938	}
n0tform3	8:1c6281289d67	1939
n0tform3	8:1c6281289d67	1940	/**
n0tform3	8:1c6281289d67	1941	* @brief Fills each TIM_ICInitStruct member with its default value.
n0tform3	8:1c6281289d67	1942	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
n0tform3	8:1c6281289d67	1943	* be initialized.
n0tform3	8:1c6281289d67	1944	* @retval None
n0tform3	8:1c6281289d67	1945	*/
n0tform3	8:1c6281289d67	1946	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
n0tform3	8:1c6281289d67	1947	{
n0tform3	8:1c6281289d67	1948	/* Set the default configuration */
n0tform3	8:1c6281289d67	1949	TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
n0tform3	8:1c6281289d67	1950	TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
n0tform3	8:1c6281289d67	1951	TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
n0tform3	8:1c6281289d67	1952	TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
n0tform3	8:1c6281289d67	1953	TIM_ICInitStruct->TIM_ICFilter = 0x00;
n0tform3	8:1c6281289d67	1954	}
n0tform3	8:1c6281289d67	1955
n0tform3	8:1c6281289d67	1956	/**
n0tform3	8:1c6281289d67	1957	* @brief Configures the TIM peripheral according to the specified parameters
n0tform3	8:1c6281289d67	1958	* in the TIM_ICInitStruct to measure an external PWM signal.
n0tform3	8:1c6281289d67	1959	* @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	1960	* peripheral.
n0tform3	8:1c6281289d67	1961	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
n0tform3	8:1c6281289d67	1962	* the configuration information for the specified TIM peripheral.
n0tform3	8:1c6281289d67	1963	* @retval None
n0tform3	8:1c6281289d67	1964	*/
n0tform3	8:1c6281289d67	1965	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
n0tform3	8:1c6281289d67	1966	{
n0tform3	8:1c6281289d67	1967	uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
n0tform3	8:1c6281289d67	1968	uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
n0tform3	8:1c6281289d67	1969
n0tform3	8:1c6281289d67	1970	/* Check the parameters */
n0tform3	8:1c6281289d67	1971	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	1972
n0tform3	8:1c6281289d67	1973	/* Select the Opposite Input Polarity */
n0tform3	8:1c6281289d67	1974	if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
n0tform3	8:1c6281289d67	1975	{
n0tform3	8:1c6281289d67	1976	icoppositepolarity = TIM_ICPolarity_Falling;
n0tform3	8:1c6281289d67	1977	}
n0tform3	8:1c6281289d67	1978	else
n0tform3	8:1c6281289d67	1979	{
n0tform3	8:1c6281289d67	1980	icoppositepolarity = TIM_ICPolarity_Rising;
n0tform3	8:1c6281289d67	1981	}
n0tform3	8:1c6281289d67	1982	/* Select the Opposite Input */
n0tform3	8:1c6281289d67	1983	if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
n0tform3	8:1c6281289d67	1984	{
n0tform3	8:1c6281289d67	1985	icoppositeselection = TIM_ICSelection_IndirectTI;
n0tform3	8:1c6281289d67	1986	}
n0tform3	8:1c6281289d67	1987	else
n0tform3	8:1c6281289d67	1988	{
n0tform3	8:1c6281289d67	1989	icoppositeselection = TIM_ICSelection_DirectTI;
n0tform3	8:1c6281289d67	1990	}
n0tform3	8:1c6281289d67	1991	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
n0tform3	8:1c6281289d67	1992	{
n0tform3	8:1c6281289d67	1993	/* TI1 Configuration */
n0tform3	8:1c6281289d67	1994	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
n0tform3	8:1c6281289d67	1995	TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	1996	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	1997	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	1998	/* TI2 Configuration */
n0tform3	8:1c6281289d67	1999	TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	2000	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	2001	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	2002	}
n0tform3	8:1c6281289d67	2003	else
n0tform3	8:1c6281289d67	2004	{
n0tform3	8:1c6281289d67	2005	/* TI2 Configuration */
n0tform3	8:1c6281289d67	2006	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
n0tform3	8:1c6281289d67	2007	TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	2008	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	2009	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	2010	/* TI1 Configuration */
n0tform3	8:1c6281289d67	2011	TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
n0tform3	8:1c6281289d67	2012	/* Set the Input Capture Prescaler value */
n0tform3	8:1c6281289d67	2013	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
n0tform3	8:1c6281289d67	2014	}
n0tform3	8:1c6281289d67	2015	}
n0tform3	8:1c6281289d67	2016
n0tform3	8:1c6281289d67	2017	/**
n0tform3	8:1c6281289d67	2018	* @brief Gets the TIMx Input Capture 1 value.
n0tform3	8:1c6281289d67	2019	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	2020	* @retval Capture Compare 1 Register value.
n0tform3	8:1c6281289d67	2021	*/
n0tform3	8:1c6281289d67	2022	uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	2023	{
n0tform3	8:1c6281289d67	2024	/* Check the parameters */
n0tform3	8:1c6281289d67	2025	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2026
n0tform3	8:1c6281289d67	2027	/* Get the Capture 1 Register value */
n0tform3	8:1c6281289d67	2028	return TIMx->CCR1;
n0tform3	8:1c6281289d67	2029	}
n0tform3	8:1c6281289d67	2030
n0tform3	8:1c6281289d67	2031	/**
n0tform3	8:1c6281289d67	2032	* @brief Gets the TIMx Input Capture 2 value.
n0tform3	8:1c6281289d67	2033	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	2034	* peripheral.
n0tform3	8:1c6281289d67	2035	* @retval Capture Compare 2 Register value.
n0tform3	8:1c6281289d67	2036	*/
n0tform3	8:1c6281289d67	2037	uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	2038	{
n0tform3	8:1c6281289d67	2039	/* Check the parameters */
n0tform3	8:1c6281289d67	2040	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2041
n0tform3	8:1c6281289d67	2042	/* Get the Capture 2 Register value */
n0tform3	8:1c6281289d67	2043	return TIMx->CCR2;
n0tform3	8:1c6281289d67	2044	}
n0tform3	8:1c6281289d67	2045
n0tform3	8:1c6281289d67	2046	/**
n0tform3	8:1c6281289d67	2047	* @brief Gets the TIMx Input Capture 3 value.
n0tform3	8:1c6281289d67	2048	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2049	* @retval Capture Compare 3 Register value.
n0tform3	8:1c6281289d67	2050	*/
n0tform3	8:1c6281289d67	2051	uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	2052	{
n0tform3	8:1c6281289d67	2053	/* Check the parameters */
n0tform3	8:1c6281289d67	2054	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2055
n0tform3	8:1c6281289d67	2056	/* Get the Capture 3 Register value */
n0tform3	8:1c6281289d67	2057	return TIMx->CCR3;
n0tform3	8:1c6281289d67	2058	}
n0tform3	8:1c6281289d67	2059
n0tform3	8:1c6281289d67	2060	/**
n0tform3	8:1c6281289d67	2061	* @brief Gets the TIMx Input Capture 4 value.
n0tform3	8:1c6281289d67	2062	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2063	* @retval Capture Compare 4 Register value.
n0tform3	8:1c6281289d67	2064	*/
n0tform3	8:1c6281289d67	2065	uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	2066	{
n0tform3	8:1c6281289d67	2067	/* Check the parameters */
n0tform3	8:1c6281289d67	2068	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2069
n0tform3	8:1c6281289d67	2070	/* Get the Capture 4 Register value */
n0tform3	8:1c6281289d67	2071	return TIMx->CCR4;
n0tform3	8:1c6281289d67	2072	}
n0tform3	8:1c6281289d67	2073
n0tform3	8:1c6281289d67	2074	/**
n0tform3	8:1c6281289d67	2075	* @brief Sets the TIMx Input Capture 1 prescaler.
n0tform3	8:1c6281289d67	2076	* @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
n0tform3	8:1c6281289d67	2077	* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
n0tform3	8:1c6281289d67	2078	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2079	* @arg TIM_ICPSC_DIV1: no prescaler
n0tform3	8:1c6281289d67	2080	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
n0tform3	8:1c6281289d67	2081	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
n0tform3	8:1c6281289d67	2082	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
n0tform3	8:1c6281289d67	2083	* @retval None
n0tform3	8:1c6281289d67	2084	*/
n0tform3	8:1c6281289d67	2085	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
n0tform3	8:1c6281289d67	2086	{
n0tform3	8:1c6281289d67	2087	/* Check the parameters */
n0tform3	8:1c6281289d67	2088	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2089	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
n0tform3	8:1c6281289d67	2090
n0tform3	8:1c6281289d67	2091	/* Reset the IC1PSC Bits */
n0tform3	8:1c6281289d67	2092	TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
n0tform3	8:1c6281289d67	2093
n0tform3	8:1c6281289d67	2094	/* Set the IC1PSC value */
n0tform3	8:1c6281289d67	2095	TIMx->CCMR1 \|= TIM_ICPSC;
n0tform3	8:1c6281289d67	2096	}
n0tform3	8:1c6281289d67	2097
n0tform3	8:1c6281289d67	2098	/**
n0tform3	8:1c6281289d67	2099	* @brief Sets the TIMx Input Capture 2 prescaler.
n0tform3	8:1c6281289d67	2100	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	2101	* peripheral.
n0tform3	8:1c6281289d67	2102	* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
n0tform3	8:1c6281289d67	2103	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2104	* @arg TIM_ICPSC_DIV1: no prescaler
n0tform3	8:1c6281289d67	2105	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
n0tform3	8:1c6281289d67	2106	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
n0tform3	8:1c6281289d67	2107	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
n0tform3	8:1c6281289d67	2108	* @retval None
n0tform3	8:1c6281289d67	2109	*/
n0tform3	8:1c6281289d67	2110	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
n0tform3	8:1c6281289d67	2111	{
n0tform3	8:1c6281289d67	2112	/* Check the parameters */
n0tform3	8:1c6281289d67	2113	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2114	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
n0tform3	8:1c6281289d67	2115
n0tform3	8:1c6281289d67	2116	/* Reset the IC2PSC Bits */
n0tform3	8:1c6281289d67	2117	TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
n0tform3	8:1c6281289d67	2118
n0tform3	8:1c6281289d67	2119	/* Set the IC2PSC value */
n0tform3	8:1c6281289d67	2120	TIMx->CCMR1 \|= (uint16_t)(TIM_ICPSC << 8);
n0tform3	8:1c6281289d67	2121	}
n0tform3	8:1c6281289d67	2122
n0tform3	8:1c6281289d67	2123	/**
n0tform3	8:1c6281289d67	2124	* @brief Sets the TIMx Input Capture 3 prescaler.
n0tform3	8:1c6281289d67	2125	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2126	* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
n0tform3	8:1c6281289d67	2127	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2128	* @arg TIM_ICPSC_DIV1: no prescaler
n0tform3	8:1c6281289d67	2129	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
n0tform3	8:1c6281289d67	2130	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
n0tform3	8:1c6281289d67	2131	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
n0tform3	8:1c6281289d67	2132	* @retval None
n0tform3	8:1c6281289d67	2133	*/
n0tform3	8:1c6281289d67	2134	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
n0tform3	8:1c6281289d67	2135	{
n0tform3	8:1c6281289d67	2136	/* Check the parameters */
n0tform3	8:1c6281289d67	2137	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2138	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
n0tform3	8:1c6281289d67	2139
n0tform3	8:1c6281289d67	2140	/* Reset the IC3PSC Bits */
n0tform3	8:1c6281289d67	2141	TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
n0tform3	8:1c6281289d67	2142
n0tform3	8:1c6281289d67	2143	/* Set the IC3PSC value */
n0tform3	8:1c6281289d67	2144	TIMx->CCMR2 \|= TIM_ICPSC;
n0tform3	8:1c6281289d67	2145	}
n0tform3	8:1c6281289d67	2146
n0tform3	8:1c6281289d67	2147	/**
n0tform3	8:1c6281289d67	2148	* @brief Sets the TIMx Input Capture 4 prescaler.
n0tform3	8:1c6281289d67	2149	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2150	* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
n0tform3	8:1c6281289d67	2151	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2152	* @arg TIM_ICPSC_DIV1: no prescaler
n0tform3	8:1c6281289d67	2153	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
n0tform3	8:1c6281289d67	2154	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
n0tform3	8:1c6281289d67	2155	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
n0tform3	8:1c6281289d67	2156	* @retval None
n0tform3	8:1c6281289d67	2157	*/
n0tform3	8:1c6281289d67	2158	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
n0tform3	8:1c6281289d67	2159	{
n0tform3	8:1c6281289d67	2160	/* Check the parameters */
n0tform3	8:1c6281289d67	2161	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2162	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
n0tform3	8:1c6281289d67	2163
n0tform3	8:1c6281289d67	2164	/* Reset the IC4PSC Bits */
n0tform3	8:1c6281289d67	2165	TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
n0tform3	8:1c6281289d67	2166
n0tform3	8:1c6281289d67	2167	/* Set the IC4PSC value */
n0tform3	8:1c6281289d67	2168	TIMx->CCMR2 \|= (uint16_t)(TIM_ICPSC << 8);
n0tform3	8:1c6281289d67	2169	}
n0tform3	8:1c6281289d67	2170	/**
n0tform3	8:1c6281289d67	2171	* @}
n0tform3	8:1c6281289d67	2172	*/
n0tform3	8:1c6281289d67	2173
n0tform3	8:1c6281289d67	2174	/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
n0tform3	8:1c6281289d67	2175	* @brief Advanced-control timers (TIM1 and TIM8) specific features
n0tform3	8:1c6281289d67	2176	*
n0tform3	8:1c6281289d67	2177	@verbatim
n0tform3	8:1c6281289d67	2178	===============================================================================
n0tform3	8:1c6281289d67	2179	Advanced-control timers (TIM1 and TIM8) specific features
n0tform3	8:1c6281289d67	2180	===============================================================================
n0tform3	8:1c6281289d67	2181
n0tform3	8:1c6281289d67	2182	===================================================================
n0tform3	8:1c6281289d67	2183	TIM Driver: how to use the Break feature
n0tform3	8:1c6281289d67	2184	===================================================================
n0tform3	8:1c6281289d67	2185	After configuring the Timer channel(s) in the appropriate Output Compare mode:
n0tform3	8:1c6281289d67	2186
n0tform3	8:1c6281289d67	2187	1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
n0tform3	8:1c6281289d67	2188	Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
n0tform3	8:1c6281289d67	2189	AOE(automatic output enable).
n0tform3	8:1c6281289d67	2190
n0tform3	8:1c6281289d67	2191	2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
n0tform3	8:1c6281289d67	2192
n0tform3	8:1c6281289d67	2193	3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
n0tform3	8:1c6281289d67	2194
n0tform3	8:1c6281289d67	2195	4. Once the break even occurs, the Timer's output signals are put in reset
n0tform3	8:1c6281289d67	2196	state or in a known state (according to the configuration made in
n0tform3	8:1c6281289d67	2197	TIM_BDTRConfig() function).
n0tform3	8:1c6281289d67	2198
n0tform3	8:1c6281289d67	2199	@endverbatim
n0tform3	8:1c6281289d67	2200	* @{
n0tform3	8:1c6281289d67	2201	*/
n0tform3	8:1c6281289d67	2202
n0tform3	8:1c6281289d67	2203	/**
n0tform3	8:1c6281289d67	2204	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
n0tform3	8:1c6281289d67	2205	* and the AOE(automatic output enable).
n0tform3	8:1c6281289d67	2206	* @param TIMx: where x can be 1 or 8 to select the TIM
n0tform3	8:1c6281289d67	2207	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
n0tform3	8:1c6281289d67	2208	* contains the BDTR Register configuration information for the TIM peripheral.
n0tform3	8:1c6281289d67	2209	* @retval None
n0tform3	8:1c6281289d67	2210	*/
n0tform3	8:1c6281289d67	2211	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
n0tform3	8:1c6281289d67	2212	{
n0tform3	8:1c6281289d67	2213	/* Check the parameters */
n0tform3	8:1c6281289d67	2214	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2215	assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
n0tform3	8:1c6281289d67	2216	assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
n0tform3	8:1c6281289d67	2217	assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
n0tform3	8:1c6281289d67	2218	assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
n0tform3	8:1c6281289d67	2219	assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
n0tform3	8:1c6281289d67	2220	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
n0tform3	8:1c6281289d67	2221
n0tform3	8:1c6281289d67	2222	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
n0tform3	8:1c6281289d67	2223	the OSSI State, the dead time value and the Automatic Output Enable Bit */
n0tform3	8:1c6281289d67	2224	TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState \| TIM_BDTRInitStruct->TIM_OSSIState \|
n0tform3	8:1c6281289d67	2225	TIM_BDTRInitStruct->TIM_LOCKLevel \| TIM_BDTRInitStruct->TIM_DeadTime \|
n0tform3	8:1c6281289d67	2226	TIM_BDTRInitStruct->TIM_Break \| TIM_BDTRInitStruct->TIM_BreakPolarity \|
n0tform3	8:1c6281289d67	2227	TIM_BDTRInitStruct->TIM_AutomaticOutput;
n0tform3	8:1c6281289d67	2228	}
n0tform3	8:1c6281289d67	2229
n0tform3	8:1c6281289d67	2230	/**
n0tform3	8:1c6281289d67	2231	* @brief Fills each TIM_BDTRInitStruct member with its default value.
n0tform3	8:1c6281289d67	2232	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
n0tform3	8:1c6281289d67	2233	* will be initialized.
n0tform3	8:1c6281289d67	2234	* @retval None
n0tform3	8:1c6281289d67	2235	*/
n0tform3	8:1c6281289d67	2236	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
n0tform3	8:1c6281289d67	2237	{
n0tform3	8:1c6281289d67	2238	/* Set the default configuration */
n0tform3	8:1c6281289d67	2239	TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
n0tform3	8:1c6281289d67	2240	TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
n0tform3	8:1c6281289d67	2241	TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
n0tform3	8:1c6281289d67	2242	TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
n0tform3	8:1c6281289d67	2243	TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
n0tform3	8:1c6281289d67	2244	TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
n0tform3	8:1c6281289d67	2245	TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
n0tform3	8:1c6281289d67	2246	}
n0tform3	8:1c6281289d67	2247
n0tform3	8:1c6281289d67	2248	/**
n0tform3	8:1c6281289d67	2249	* @brief Enables or disables the TIM peripheral Main Outputs.
n0tform3	8:1c6281289d67	2250	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
n0tform3	8:1c6281289d67	2251	* @param NewState: new state of the TIM peripheral Main Outputs.
n0tform3	8:1c6281289d67	2252	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	2253	* @retval None
n0tform3	8:1c6281289d67	2254	*/
n0tform3	8:1c6281289d67	2255	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	2256	{
n0tform3	8:1c6281289d67	2257	/* Check the parameters */
n0tform3	8:1c6281289d67	2258	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2259	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	2260
n0tform3	8:1c6281289d67	2261	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	2262	{
n0tform3	8:1c6281289d67	2263	/* Enable the TIM Main Output */
n0tform3	8:1c6281289d67	2264	TIMx->BDTR \|= TIM_BDTR_MOE;
n0tform3	8:1c6281289d67	2265	}
n0tform3	8:1c6281289d67	2266	else
n0tform3	8:1c6281289d67	2267	{
n0tform3	8:1c6281289d67	2268	/* Disable the TIM Main Output */
n0tform3	8:1c6281289d67	2269	TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
n0tform3	8:1c6281289d67	2270	}
n0tform3	8:1c6281289d67	2271	}
n0tform3	8:1c6281289d67	2272
n0tform3	8:1c6281289d67	2273	/**
n0tform3	8:1c6281289d67	2274	* @brief Selects the TIM peripheral Commutation event.
n0tform3	8:1c6281289d67	2275	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
n0tform3	8:1c6281289d67	2276	* @param NewState: new state of the Commutation event.
n0tform3	8:1c6281289d67	2277	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	2278	* @retval None
n0tform3	8:1c6281289d67	2279	*/
n0tform3	8:1c6281289d67	2280	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	2281	{
n0tform3	8:1c6281289d67	2282	/* Check the parameters */
n0tform3	8:1c6281289d67	2283	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2284	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	2285
n0tform3	8:1c6281289d67	2286	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	2287	{
n0tform3	8:1c6281289d67	2288	/* Set the COM Bit */
n0tform3	8:1c6281289d67	2289	TIMx->CR2 \|= TIM_CR2_CCUS;
n0tform3	8:1c6281289d67	2290	}
n0tform3	8:1c6281289d67	2291	else
n0tform3	8:1c6281289d67	2292	{
n0tform3	8:1c6281289d67	2293	/* Reset the COM Bit */
n0tform3	8:1c6281289d67	2294	TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
n0tform3	8:1c6281289d67	2295	}
n0tform3	8:1c6281289d67	2296	}
n0tform3	8:1c6281289d67	2297
n0tform3	8:1c6281289d67	2298	/**
n0tform3	8:1c6281289d67	2299	* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
n0tform3	8:1c6281289d67	2300	* @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
n0tform3	8:1c6281289d67	2301	* @param NewState: new state of the Capture Compare Preload Control bit
n0tform3	8:1c6281289d67	2302	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	2303	* @retval None
n0tform3	8:1c6281289d67	2304	*/
n0tform3	8:1c6281289d67	2305	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	2306	{
n0tform3	8:1c6281289d67	2307	/* Check the parameters */
n0tform3	8:1c6281289d67	2308	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2309	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	2310	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	2311	{
n0tform3	8:1c6281289d67	2312	/* Set the CCPC Bit */
n0tform3	8:1c6281289d67	2313	TIMx->CR2 \|= TIM_CR2_CCPC;
n0tform3	8:1c6281289d67	2314	}
n0tform3	8:1c6281289d67	2315	else
n0tform3	8:1c6281289d67	2316	{
n0tform3	8:1c6281289d67	2317	/* Reset the CCPC Bit */
n0tform3	8:1c6281289d67	2318	TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
n0tform3	8:1c6281289d67	2319	}
n0tform3	8:1c6281289d67	2320	}
n0tform3	8:1c6281289d67	2321	/**
n0tform3	8:1c6281289d67	2322	* @}
n0tform3	8:1c6281289d67	2323	*/
n0tform3	8:1c6281289d67	2324
n0tform3	8:1c6281289d67	2325	/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
n0tform3	8:1c6281289d67	2326	* @brief Interrupts, DMA and flags management functions
n0tform3	8:1c6281289d67	2327	*
n0tform3	8:1c6281289d67	2328	@verbatim
n0tform3	8:1c6281289d67	2329	===============================================================================
n0tform3	8:1c6281289d67	2330	Interrupts, DMA and flags management functions
n0tform3	8:1c6281289d67	2331	===============================================================================
n0tform3	8:1c6281289d67	2332
n0tform3	8:1c6281289d67	2333	@endverbatim
n0tform3	8:1c6281289d67	2334	* @{
n0tform3	8:1c6281289d67	2335	*/
n0tform3	8:1c6281289d67	2336
n0tform3	8:1c6281289d67	2337	/**
n0tform3	8:1c6281289d67	2338	* @brief Enables or disables the specified TIM interrupts.
n0tform3	8:1c6281289d67	2339	* @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
n0tform3	8:1c6281289d67	2340	* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
n0tform3	8:1c6281289d67	2341	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	2342	* @arg TIM_IT_Update: TIM update Interrupt source
n0tform3	8:1c6281289d67	2343	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
n0tform3	8:1c6281289d67	2344	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
n0tform3	8:1c6281289d67	2345	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
n0tform3	8:1c6281289d67	2346	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
n0tform3	8:1c6281289d67	2347	* @arg TIM_IT_COM: TIM Commutation Interrupt source
n0tform3	8:1c6281289d67	2348	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
n0tform3	8:1c6281289d67	2349	* @arg TIM_IT_Break: TIM Break Interrupt source
n0tform3	8:1c6281289d67	2350	*
n0tform3	8:1c6281289d67	2351	* @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
n0tform3	8:1c6281289d67	2352	* @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
n0tform3	8:1c6281289d67	2353	* TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
n0tform3	8:1c6281289d67	2354	* @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
n0tform3	8:1c6281289d67	2355	* be used: TIM_IT_Update or TIM_IT_CC1
n0tform3	8:1c6281289d67	2356	* @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
n0tform3	8:1c6281289d67	2357	*
n0tform3	8:1c6281289d67	2358	* @param NewState: new state of the TIM interrupts.
n0tform3	8:1c6281289d67	2359	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	2360	* @retval None
n0tform3	8:1c6281289d67	2361	*/
n0tform3	8:1c6281289d67	2362	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
n0tform3	8:1c6281289d67	2363	{
n0tform3	8:1c6281289d67	2364	/* Check the parameters */
n0tform3	8:1c6281289d67	2365	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2366	assert_param(IS_TIM_IT(TIM_IT));
n0tform3	8:1c6281289d67	2367	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	2368
n0tform3	8:1c6281289d67	2369	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	2370	{
n0tform3	8:1c6281289d67	2371	/* Enable the Interrupt sources */
n0tform3	8:1c6281289d67	2372	TIMx->DIER \|= TIM_IT;
n0tform3	8:1c6281289d67	2373	}
n0tform3	8:1c6281289d67	2374	else
n0tform3	8:1c6281289d67	2375	{
n0tform3	8:1c6281289d67	2376	/* Disable the Interrupt sources */
n0tform3	8:1c6281289d67	2377	TIMx->DIER &= (uint16_t)~TIM_IT;
n0tform3	8:1c6281289d67	2378	}
n0tform3	8:1c6281289d67	2379	}
n0tform3	8:1c6281289d67	2380
n0tform3	8:1c6281289d67	2381	/**
n0tform3	8:1c6281289d67	2382	* @brief Configures the TIMx event to be generate by software.
n0tform3	8:1c6281289d67	2383	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2384	* @param TIM_EventSource: specifies the event source.
n0tform3	8:1c6281289d67	2385	* This parameter can be one or more of the following values:
n0tform3	8:1c6281289d67	2386	* @arg TIM_EventSource_Update: Timer update Event source
n0tform3	8:1c6281289d67	2387	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
n0tform3	8:1c6281289d67	2388	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
n0tform3	8:1c6281289d67	2389	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
n0tform3	8:1c6281289d67	2390	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
n0tform3	8:1c6281289d67	2391	* @arg TIM_EventSource_COM: Timer COM event source
n0tform3	8:1c6281289d67	2392	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
n0tform3	8:1c6281289d67	2393	* @arg TIM_EventSource_Break: Timer Break event source
n0tform3	8:1c6281289d67	2394	*
n0tform3	8:1c6281289d67	2395	* @note TIM6 and TIM7 can only generate an update event.
n0tform3	8:1c6281289d67	2396	* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
n0tform3	8:1c6281289d67	2397	*
n0tform3	8:1c6281289d67	2398	* @retval None
n0tform3	8:1c6281289d67	2399	*/
n0tform3	8:1c6281289d67	2400	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
n0tform3	8:1c6281289d67	2401	{
n0tform3	8:1c6281289d67	2402	/* Check the parameters */
n0tform3	8:1c6281289d67	2403	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2404	assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
n0tform3	8:1c6281289d67	2405
n0tform3	8:1c6281289d67	2406	/* Set the event sources */
n0tform3	8:1c6281289d67	2407	TIMx->EGR = TIM_EventSource;
n0tform3	8:1c6281289d67	2408	}
n0tform3	8:1c6281289d67	2409
n0tform3	8:1c6281289d67	2410	/**
n0tform3	8:1c6281289d67	2411	* @brief Checks whether the specified TIM flag is set or not.
n0tform3	8:1c6281289d67	2412	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2413	* @param TIM_FLAG: specifies the flag to check.
n0tform3	8:1c6281289d67	2414	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2415	* @arg TIM_FLAG_Update: TIM update Flag
n0tform3	8:1c6281289d67	2416	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
n0tform3	8:1c6281289d67	2417	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
n0tform3	8:1c6281289d67	2418	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
n0tform3	8:1c6281289d67	2419	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
n0tform3	8:1c6281289d67	2420	* @arg TIM_FLAG_COM: TIM Commutation Flag
n0tform3	8:1c6281289d67	2421	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
n0tform3	8:1c6281289d67	2422	* @arg TIM_FLAG_Break: TIM Break Flag
n0tform3	8:1c6281289d67	2423	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
n0tform3	8:1c6281289d67	2424	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
n0tform3	8:1c6281289d67	2425	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
n0tform3	8:1c6281289d67	2426	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
n0tform3	8:1c6281289d67	2427	*
n0tform3	8:1c6281289d67	2428	* @note TIM6 and TIM7 can have only one update flag.
n0tform3	8:1c6281289d67	2429	* @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
n0tform3	8:1c6281289d67	2430	*
n0tform3	8:1c6281289d67	2431	* @retval The new state of TIM_FLAG (SET or RESET).
n0tform3	8:1c6281289d67	2432	*/
n0tform3	8:1c6281289d67	2433	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
n0tform3	8:1c6281289d67	2434	{
n0tform3	8:1c6281289d67	2435	ITStatus bitstatus = RESET;
n0tform3	8:1c6281289d67	2436	/* Check the parameters */
n0tform3	8:1c6281289d67	2437	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2438	assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
n0tform3	8:1c6281289d67	2439
n0tform3	8:1c6281289d67	2440
n0tform3	8:1c6281289d67	2441	if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
n0tform3	8:1c6281289d67	2442	{
n0tform3	8:1c6281289d67	2443	bitstatus = SET;
n0tform3	8:1c6281289d67	2444	}
n0tform3	8:1c6281289d67	2445	else
n0tform3	8:1c6281289d67	2446	{
n0tform3	8:1c6281289d67	2447	bitstatus = RESET;
n0tform3	8:1c6281289d67	2448	}
n0tform3	8:1c6281289d67	2449	return bitstatus;
n0tform3	8:1c6281289d67	2450	}
n0tform3	8:1c6281289d67	2451
n0tform3	8:1c6281289d67	2452	/**
n0tform3	8:1c6281289d67	2453	* @brief Clears the TIMx's pending flags.
n0tform3	8:1c6281289d67	2454	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2455	* @param TIM_FLAG: specifies the flag bit to clear.
n0tform3	8:1c6281289d67	2456	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	2457	* @arg TIM_FLAG_Update: TIM update Flag
n0tform3	8:1c6281289d67	2458	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
n0tform3	8:1c6281289d67	2459	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
n0tform3	8:1c6281289d67	2460	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
n0tform3	8:1c6281289d67	2461	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
n0tform3	8:1c6281289d67	2462	* @arg TIM_FLAG_COM: TIM Commutation Flag
n0tform3	8:1c6281289d67	2463	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
n0tform3	8:1c6281289d67	2464	* @arg TIM_FLAG_Break: TIM Break Flag
n0tform3	8:1c6281289d67	2465	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
n0tform3	8:1c6281289d67	2466	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
n0tform3	8:1c6281289d67	2467	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
n0tform3	8:1c6281289d67	2468	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
n0tform3	8:1c6281289d67	2469	*
n0tform3	8:1c6281289d67	2470	* @note TIM6 and TIM7 can have only one update flag.
n0tform3	8:1c6281289d67	2471	* @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
n0tform3	8:1c6281289d67	2472	*
n0tform3	8:1c6281289d67	2473	* @retval None
n0tform3	8:1c6281289d67	2474	*/
n0tform3	8:1c6281289d67	2475	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
n0tform3	8:1c6281289d67	2476	{
n0tform3	8:1c6281289d67	2477	/* Check the parameters */
n0tform3	8:1c6281289d67	2478	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2479
n0tform3	8:1c6281289d67	2480	/* Clear the flags */
n0tform3	8:1c6281289d67	2481	TIMx->SR = (uint16_t)~TIM_FLAG;
n0tform3	8:1c6281289d67	2482	}
n0tform3	8:1c6281289d67	2483
n0tform3	8:1c6281289d67	2484	/**
n0tform3	8:1c6281289d67	2485	* @brief Checks whether the TIM interrupt has occurred or not.
n0tform3	8:1c6281289d67	2486	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2487	* @param TIM_IT: specifies the TIM interrupt source to check.
n0tform3	8:1c6281289d67	2488	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2489	* @arg TIM_IT_Update: TIM update Interrupt source
n0tform3	8:1c6281289d67	2490	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
n0tform3	8:1c6281289d67	2491	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
n0tform3	8:1c6281289d67	2492	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
n0tform3	8:1c6281289d67	2493	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
n0tform3	8:1c6281289d67	2494	* @arg TIM_IT_COM: TIM Commutation Interrupt source
n0tform3	8:1c6281289d67	2495	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
n0tform3	8:1c6281289d67	2496	* @arg TIM_IT_Break: TIM Break Interrupt source
n0tform3	8:1c6281289d67	2497	*
n0tform3	8:1c6281289d67	2498	* @note TIM6 and TIM7 can generate only an update interrupt.
n0tform3	8:1c6281289d67	2499	* @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
n0tform3	8:1c6281289d67	2500	*
n0tform3	8:1c6281289d67	2501	* @retval The new state of the TIM_IT(SET or RESET).
n0tform3	8:1c6281289d67	2502	*/
n0tform3	8:1c6281289d67	2503	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
n0tform3	8:1c6281289d67	2504	{
n0tform3	8:1c6281289d67	2505	ITStatus bitstatus = RESET;
n0tform3	8:1c6281289d67	2506	uint16_t itstatus = 0x0, itenable = 0x0;
n0tform3	8:1c6281289d67	2507	/* Check the parameters */
n0tform3	8:1c6281289d67	2508	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2509	assert_param(IS_TIM_GET_IT(TIM_IT));
n0tform3	8:1c6281289d67	2510
n0tform3	8:1c6281289d67	2511	itstatus = TIMx->SR & TIM_IT;
n0tform3	8:1c6281289d67	2512
n0tform3	8:1c6281289d67	2513	itenable = TIMx->DIER & TIM_IT;
n0tform3	8:1c6281289d67	2514	if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
n0tform3	8:1c6281289d67	2515	{
n0tform3	8:1c6281289d67	2516	bitstatus = SET;
n0tform3	8:1c6281289d67	2517	}
n0tform3	8:1c6281289d67	2518	else
n0tform3	8:1c6281289d67	2519	{
n0tform3	8:1c6281289d67	2520	bitstatus = RESET;
n0tform3	8:1c6281289d67	2521	}
n0tform3	8:1c6281289d67	2522	return bitstatus;
n0tform3	8:1c6281289d67	2523	}
n0tform3	8:1c6281289d67	2524
n0tform3	8:1c6281289d67	2525	/**
n0tform3	8:1c6281289d67	2526	* @brief Clears the TIMx's interrupt pending bits.
n0tform3	8:1c6281289d67	2527	* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2528	* @param TIM_IT: specifies the pending bit to clear.
n0tform3	8:1c6281289d67	2529	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	2530	* @arg TIM_IT_Update: TIM1 update Interrupt source
n0tform3	8:1c6281289d67	2531	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
n0tform3	8:1c6281289d67	2532	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
n0tform3	8:1c6281289d67	2533	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
n0tform3	8:1c6281289d67	2534	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
n0tform3	8:1c6281289d67	2535	* @arg TIM_IT_COM: TIM Commutation Interrupt source
n0tform3	8:1c6281289d67	2536	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
n0tform3	8:1c6281289d67	2537	* @arg TIM_IT_Break: TIM Break Interrupt source
n0tform3	8:1c6281289d67	2538	*
n0tform3	8:1c6281289d67	2539	* @note TIM6 and TIM7 can generate only an update interrupt.
n0tform3	8:1c6281289d67	2540	* @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
n0tform3	8:1c6281289d67	2541	*
n0tform3	8:1c6281289d67	2542	* @retval None
n0tform3	8:1c6281289d67	2543	*/
n0tform3	8:1c6281289d67	2544	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
n0tform3	8:1c6281289d67	2545	{
n0tform3	8:1c6281289d67	2546	/* Check the parameters */
n0tform3	8:1c6281289d67	2547	assert_param(IS_TIM_ALL_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2548
n0tform3	8:1c6281289d67	2549	/* Clear the IT pending Bit */
n0tform3	8:1c6281289d67	2550	TIMx->SR = (uint16_t)~TIM_IT;
n0tform3	8:1c6281289d67	2551	}
n0tform3	8:1c6281289d67	2552
n0tform3	8:1c6281289d67	2553	/**
n0tform3	8:1c6281289d67	2554	* @brief Configures the TIMx's DMA interface.
n0tform3	8:1c6281289d67	2555	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2556	* @param TIM_DMABase: DMA Base address.
n0tform3	8:1c6281289d67	2557	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2558	* @arg TIM_DMABase_CR1
n0tform3	8:1c6281289d67	2559	* @arg TIM_DMABase_CR2
n0tform3	8:1c6281289d67	2560	* @arg TIM_DMABase_SMCR
n0tform3	8:1c6281289d67	2561	* @arg TIM_DMABase_DIER
n0tform3	8:1c6281289d67	2562	* @arg TIM1_DMABase_SR
n0tform3	8:1c6281289d67	2563	* @arg TIM_DMABase_EGR
n0tform3	8:1c6281289d67	2564	* @arg TIM_DMABase_CCMR1
n0tform3	8:1c6281289d67	2565	* @arg TIM_DMABase_CCMR2
n0tform3	8:1c6281289d67	2566	* @arg TIM_DMABase_CCER
n0tform3	8:1c6281289d67	2567	* @arg TIM_DMABase_CNT
n0tform3	8:1c6281289d67	2568	* @arg TIM_DMABase_PSC
n0tform3	8:1c6281289d67	2569	* @arg TIM_DMABase_ARR
n0tform3	8:1c6281289d67	2570	* @arg TIM_DMABase_RCR
n0tform3	8:1c6281289d67	2571	* @arg TIM_DMABase_CCR1
n0tform3	8:1c6281289d67	2572	* @arg TIM_DMABase_CCR2
n0tform3	8:1c6281289d67	2573	* @arg TIM_DMABase_CCR3
n0tform3	8:1c6281289d67	2574	* @arg TIM_DMABase_CCR4
n0tform3	8:1c6281289d67	2575	* @arg TIM_DMABase_BDTR
n0tform3	8:1c6281289d67	2576	* @arg TIM_DMABase_DCR
n0tform3	8:1c6281289d67	2577	* @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
n0tform3	8:1c6281289d67	2578	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
n0tform3	8:1c6281289d67	2579	* @retval None
n0tform3	8:1c6281289d67	2580	*/
n0tform3	8:1c6281289d67	2581	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
n0tform3	8:1c6281289d67	2582	{
n0tform3	8:1c6281289d67	2583	/* Check the parameters */
n0tform3	8:1c6281289d67	2584	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2585	assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
n0tform3	8:1c6281289d67	2586	assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
n0tform3	8:1c6281289d67	2587
n0tform3	8:1c6281289d67	2588	/* Set the DMA Base and the DMA Burst Length */
n0tform3	8:1c6281289d67	2589	TIMx->DCR = TIM_DMABase \| TIM_DMABurstLength;
n0tform3	8:1c6281289d67	2590	}
n0tform3	8:1c6281289d67	2591
n0tform3	8:1c6281289d67	2592	/**
n0tform3	8:1c6281289d67	2593	* @brief Enables or disables the TIMx's DMA Requests.
n0tform3	8:1c6281289d67	2594	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2595	* @param TIM_DMASource: specifies the DMA Request sources.
n0tform3	8:1c6281289d67	2596	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	2597	* @arg TIM_DMA_Update: TIM update Interrupt source
n0tform3	8:1c6281289d67	2598	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
n0tform3	8:1c6281289d67	2599	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
n0tform3	8:1c6281289d67	2600	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
n0tform3	8:1c6281289d67	2601	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
n0tform3	8:1c6281289d67	2602	* @arg TIM_DMA_COM: TIM Commutation DMA source
n0tform3	8:1c6281289d67	2603	* @arg TIM_DMA_Trigger: TIM Trigger DMA source
n0tform3	8:1c6281289d67	2604	* @param NewState: new state of the DMA Request sources.
n0tform3	8:1c6281289d67	2605	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	2606	* @retval None
n0tform3	8:1c6281289d67	2607	*/
n0tform3	8:1c6281289d67	2608	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
n0tform3	8:1c6281289d67	2609	{
n0tform3	8:1c6281289d67	2610	/* Check the parameters */
n0tform3	8:1c6281289d67	2611	assert_param(IS_TIM_LIST5_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2612	assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
n0tform3	8:1c6281289d67	2613	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	2614
n0tform3	8:1c6281289d67	2615	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	2616	{
n0tform3	8:1c6281289d67	2617	/* Enable the DMA sources */
n0tform3	8:1c6281289d67	2618	TIMx->DIER \|= TIM_DMASource;
n0tform3	8:1c6281289d67	2619	}
n0tform3	8:1c6281289d67	2620	else
n0tform3	8:1c6281289d67	2621	{
n0tform3	8:1c6281289d67	2622	/* Disable the DMA sources */
n0tform3	8:1c6281289d67	2623	TIMx->DIER &= (uint16_t)~TIM_DMASource;
n0tform3	8:1c6281289d67	2624	}
n0tform3	8:1c6281289d67	2625	}
n0tform3	8:1c6281289d67	2626
n0tform3	8:1c6281289d67	2627	/**
n0tform3	8:1c6281289d67	2628	* @brief Selects the TIMx peripheral Capture Compare DMA source.
n0tform3	8:1c6281289d67	2629	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2630	* @param NewState: new state of the Capture Compare DMA source
n0tform3	8:1c6281289d67	2631	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	2632	* @retval None
n0tform3	8:1c6281289d67	2633	*/
n0tform3	8:1c6281289d67	2634	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	2635	{
n0tform3	8:1c6281289d67	2636	/* Check the parameters */
n0tform3	8:1c6281289d67	2637	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2638	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	2639
n0tform3	8:1c6281289d67	2640	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	2641	{
n0tform3	8:1c6281289d67	2642	/* Set the CCDS Bit */
n0tform3	8:1c6281289d67	2643	TIMx->CR2 \|= TIM_CR2_CCDS;
n0tform3	8:1c6281289d67	2644	}
n0tform3	8:1c6281289d67	2645	else
n0tform3	8:1c6281289d67	2646	{
n0tform3	8:1c6281289d67	2647	/* Reset the CCDS Bit */
n0tform3	8:1c6281289d67	2648	TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
n0tform3	8:1c6281289d67	2649	}
n0tform3	8:1c6281289d67	2650	}
n0tform3	8:1c6281289d67	2651	/**
n0tform3	8:1c6281289d67	2652	* @}
n0tform3	8:1c6281289d67	2653	*/
n0tform3	8:1c6281289d67	2654
n0tform3	8:1c6281289d67	2655	/** @defgroup TIM_Group6 Clocks management functions
n0tform3	8:1c6281289d67	2656	* @brief Clocks management functions
n0tform3	8:1c6281289d67	2657	*
n0tform3	8:1c6281289d67	2658	@verbatim
n0tform3	8:1c6281289d67	2659	===============================================================================
n0tform3	8:1c6281289d67	2660	Clocks management functions
n0tform3	8:1c6281289d67	2661	===============================================================================
n0tform3	8:1c6281289d67	2662
n0tform3	8:1c6281289d67	2663	@endverbatim
n0tform3	8:1c6281289d67	2664	* @{
n0tform3	8:1c6281289d67	2665	*/
n0tform3	8:1c6281289d67	2666
n0tform3	8:1c6281289d67	2667	/**
n0tform3	8:1c6281289d67	2668	* @brief Configures the TIMx internal Clock
n0tform3	8:1c6281289d67	2669	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	2670	* peripheral.
n0tform3	8:1c6281289d67	2671	* @retval None
n0tform3	8:1c6281289d67	2672	*/
n0tform3	8:1c6281289d67	2673	void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
n0tform3	8:1c6281289d67	2674	{
n0tform3	8:1c6281289d67	2675	/* Check the parameters */
n0tform3	8:1c6281289d67	2676	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2677
n0tform3	8:1c6281289d67	2678	/* Disable slave mode to clock the prescaler directly with the internal clock */
n0tform3	8:1c6281289d67	2679	TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
n0tform3	8:1c6281289d67	2680	}
n0tform3	8:1c6281289d67	2681
n0tform3	8:1c6281289d67	2682	/**
n0tform3	8:1c6281289d67	2683	* @brief Configures the TIMx Internal Trigger as External Clock
n0tform3	8:1c6281289d67	2684	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	2685	* peripheral.
n0tform3	8:1c6281289d67	2686	* @param TIM_InputTriggerSource: Trigger source.
n0tform3	8:1c6281289d67	2687	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2688	* @arg TIM_TS_ITR0: Internal Trigger 0
n0tform3	8:1c6281289d67	2689	* @arg TIM_TS_ITR1: Internal Trigger 1
n0tform3	8:1c6281289d67	2690	* @arg TIM_TS_ITR2: Internal Trigger 2
n0tform3	8:1c6281289d67	2691	* @arg TIM_TS_ITR3: Internal Trigger 3
n0tform3	8:1c6281289d67	2692	* @retval None
n0tform3	8:1c6281289d67	2693	*/
n0tform3	8:1c6281289d67	2694	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
n0tform3	8:1c6281289d67	2695	{
n0tform3	8:1c6281289d67	2696	/* Check the parameters */
n0tform3	8:1c6281289d67	2697	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2698	assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
n0tform3	8:1c6281289d67	2699
n0tform3	8:1c6281289d67	2700	/* Select the Internal Trigger */
n0tform3	8:1c6281289d67	2701	TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
n0tform3	8:1c6281289d67	2702
n0tform3	8:1c6281289d67	2703	/* Select the External clock mode1 */
n0tform3	8:1c6281289d67	2704	TIMx->SMCR \|= TIM_SlaveMode_External1;
n0tform3	8:1c6281289d67	2705	}
n0tform3	8:1c6281289d67	2706
n0tform3	8:1c6281289d67	2707	/**
n0tform3	8:1c6281289d67	2708	* @brief Configures the TIMx Trigger as External Clock
n0tform3	8:1c6281289d67	2709	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
n0tform3	8:1c6281289d67	2710	* to select the TIM peripheral.
n0tform3	8:1c6281289d67	2711	* @param TIM_TIxExternalCLKSource: Trigger source.
n0tform3	8:1c6281289d67	2712	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2713	* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
n0tform3	8:1c6281289d67	2714	* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
n0tform3	8:1c6281289d67	2715	* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
n0tform3	8:1c6281289d67	2716	* @param TIM_ICPolarity: specifies the TIx Polarity.
n0tform3	8:1c6281289d67	2717	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2718	* @arg TIM_ICPolarity_Rising
n0tform3	8:1c6281289d67	2719	* @arg TIM_ICPolarity_Falling
n0tform3	8:1c6281289d67	2720	* @param ICFilter: specifies the filter value.
n0tform3	8:1c6281289d67	2721	* This parameter must be a value between 0x0 and 0xF.
n0tform3	8:1c6281289d67	2722	* @retval None
n0tform3	8:1c6281289d67	2723	*/
n0tform3	8:1c6281289d67	2724	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
n0tform3	8:1c6281289d67	2725	uint16_t TIM_ICPolarity, uint16_t ICFilter)
n0tform3	8:1c6281289d67	2726	{
n0tform3	8:1c6281289d67	2727	/* Check the parameters */
n0tform3	8:1c6281289d67	2728	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2729	assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
n0tform3	8:1c6281289d67	2730	assert_param(IS_TIM_IC_FILTER(ICFilter));
n0tform3	8:1c6281289d67	2731
n0tform3	8:1c6281289d67	2732	/* Configure the Timer Input Clock Source */
n0tform3	8:1c6281289d67	2733	if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
n0tform3	8:1c6281289d67	2734	{
n0tform3	8:1c6281289d67	2735	TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
n0tform3	8:1c6281289d67	2736	}
n0tform3	8:1c6281289d67	2737	else
n0tform3	8:1c6281289d67	2738	{
n0tform3	8:1c6281289d67	2739	TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
n0tform3	8:1c6281289d67	2740	}
n0tform3	8:1c6281289d67	2741	/* Select the Trigger source */
n0tform3	8:1c6281289d67	2742	TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
n0tform3	8:1c6281289d67	2743	/* Select the External clock mode1 */
n0tform3	8:1c6281289d67	2744	TIMx->SMCR \|= TIM_SlaveMode_External1;
n0tform3	8:1c6281289d67	2745	}
n0tform3	8:1c6281289d67	2746
n0tform3	8:1c6281289d67	2747	/**
n0tform3	8:1c6281289d67	2748	* @brief Configures the External clock Mode1
n0tform3	8:1c6281289d67	2749	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2750	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
n0tform3	8:1c6281289d67	2751	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2752	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
n0tform3	8:1c6281289d67	2753	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
n0tform3	8:1c6281289d67	2754	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
n0tform3	8:1c6281289d67	2755	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
n0tform3	8:1c6281289d67	2756	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
n0tform3	8:1c6281289d67	2757	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2758	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
n0tform3	8:1c6281289d67	2759	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
n0tform3	8:1c6281289d67	2760	* @param ExtTRGFilter: External Trigger Filter.
n0tform3	8:1c6281289d67	2761	* This parameter must be a value between 0x00 and 0x0F
n0tform3	8:1c6281289d67	2762	* @retval None
n0tform3	8:1c6281289d67	2763	*/
n0tform3	8:1c6281289d67	2764	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
n0tform3	8:1c6281289d67	2765	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
n0tform3	8:1c6281289d67	2766	{
n0tform3	8:1c6281289d67	2767	uint16_t tmpsmcr = 0;
n0tform3	8:1c6281289d67	2768
n0tform3	8:1c6281289d67	2769	/* Check the parameters */
n0tform3	8:1c6281289d67	2770	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2771	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
n0tform3	8:1c6281289d67	2772	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
n0tform3	8:1c6281289d67	2773	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
n0tform3	8:1c6281289d67	2774	/* Configure the ETR Clock source */
n0tform3	8:1c6281289d67	2775	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
n0tform3	8:1c6281289d67	2776
n0tform3	8:1c6281289d67	2777	/* Get the TIMx SMCR register value */
n0tform3	8:1c6281289d67	2778	tmpsmcr = TIMx->SMCR;
n0tform3	8:1c6281289d67	2779
n0tform3	8:1c6281289d67	2780	/* Reset the SMS Bits */
n0tform3	8:1c6281289d67	2781	tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
n0tform3	8:1c6281289d67	2782
n0tform3	8:1c6281289d67	2783	/* Select the External clock mode1 */
n0tform3	8:1c6281289d67	2784	tmpsmcr \|= TIM_SlaveMode_External1;
n0tform3	8:1c6281289d67	2785
n0tform3	8:1c6281289d67	2786	/* Select the Trigger selection : ETRF */
n0tform3	8:1c6281289d67	2787	tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
n0tform3	8:1c6281289d67	2788	tmpsmcr \|= TIM_TS_ETRF;
n0tform3	8:1c6281289d67	2789
n0tform3	8:1c6281289d67	2790	/* Write to TIMx SMCR */
n0tform3	8:1c6281289d67	2791	TIMx->SMCR = tmpsmcr;
n0tform3	8:1c6281289d67	2792	}
n0tform3	8:1c6281289d67	2793
n0tform3	8:1c6281289d67	2794	/**
n0tform3	8:1c6281289d67	2795	* @brief Configures the External clock Mode2
n0tform3	8:1c6281289d67	2796	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2797	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
n0tform3	8:1c6281289d67	2798	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2799	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
n0tform3	8:1c6281289d67	2800	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
n0tform3	8:1c6281289d67	2801	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
n0tform3	8:1c6281289d67	2802	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
n0tform3	8:1c6281289d67	2803	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
n0tform3	8:1c6281289d67	2804	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2805	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
n0tform3	8:1c6281289d67	2806	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
n0tform3	8:1c6281289d67	2807	* @param ExtTRGFilter: External Trigger Filter.
n0tform3	8:1c6281289d67	2808	* This parameter must be a value between 0x00 and 0x0F
n0tform3	8:1c6281289d67	2809	* @retval None
n0tform3	8:1c6281289d67	2810	*/
n0tform3	8:1c6281289d67	2811	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
n0tform3	8:1c6281289d67	2812	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
n0tform3	8:1c6281289d67	2813	{
n0tform3	8:1c6281289d67	2814	/* Check the parameters */
n0tform3	8:1c6281289d67	2815	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2816	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
n0tform3	8:1c6281289d67	2817	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
n0tform3	8:1c6281289d67	2818	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
n0tform3	8:1c6281289d67	2819
n0tform3	8:1c6281289d67	2820	/* Configure the ETR Clock source */
n0tform3	8:1c6281289d67	2821	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
n0tform3	8:1c6281289d67	2822
n0tform3	8:1c6281289d67	2823	/* Enable the External clock mode2 */
n0tform3	8:1c6281289d67	2824	TIMx->SMCR \|= TIM_SMCR_ECE;
n0tform3	8:1c6281289d67	2825	}
n0tform3	8:1c6281289d67	2826	/**
n0tform3	8:1c6281289d67	2827	* @}
n0tform3	8:1c6281289d67	2828	*/
n0tform3	8:1c6281289d67	2829
n0tform3	8:1c6281289d67	2830	/** @defgroup TIM_Group7 Synchronization management functions
n0tform3	8:1c6281289d67	2831	* @brief Synchronization management functions
n0tform3	8:1c6281289d67	2832	*
n0tform3	8:1c6281289d67	2833	@verbatim
n0tform3	8:1c6281289d67	2834	===============================================================================
n0tform3	8:1c6281289d67	2835	Synchronization management functions
n0tform3	8:1c6281289d67	2836	===============================================================================
n0tform3	8:1c6281289d67	2837
n0tform3	8:1c6281289d67	2838	===================================================================
n0tform3	8:1c6281289d67	2839	TIM Driver: how to use it in synchronization Mode
n0tform3	8:1c6281289d67	2840	===================================================================
n0tform3	8:1c6281289d67	2841	Case of two/several Timers
n0tform3	8:1c6281289d67	2842	**************************
n0tform3	8:1c6281289d67	2843	1. Configure the Master Timers using the following functions:
n0tform3	8:1c6281289d67	2844	- void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
n0tform3	8:1c6281289d67	2845	- void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
n0tform3	8:1c6281289d67	2846	2. Configure the Slave Timers using the following functions:
n0tform3	8:1c6281289d67	2847	- void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
n0tform3	8:1c6281289d67	2848	- void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
n0tform3	8:1c6281289d67	2849
n0tform3	8:1c6281289d67	2850	Case of Timers and external trigger(ETR pin)
n0tform3	8:1c6281289d67	2851	********************************************
n0tform3	8:1c6281289d67	2852	1. Configure the External trigger using this function:
n0tform3	8:1c6281289d67	2853	- void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
n0tform3	8:1c6281289d67	2854	uint16_t ExtTRGFilter);
n0tform3	8:1c6281289d67	2855	2. Configure the Slave Timers using the following functions:
n0tform3	8:1c6281289d67	2856	- void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
n0tform3	8:1c6281289d67	2857	- void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
n0tform3	8:1c6281289d67	2858
n0tform3	8:1c6281289d67	2859	@endverbatim
n0tform3	8:1c6281289d67	2860	* @{
n0tform3	8:1c6281289d67	2861	*/
n0tform3	8:1c6281289d67	2862
n0tform3	8:1c6281289d67	2863	/**
n0tform3	8:1c6281289d67	2864	* @brief Selects the Input Trigger source
n0tform3	8:1c6281289d67	2865	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
n0tform3	8:1c6281289d67	2866	* to select the TIM peripheral.
n0tform3	8:1c6281289d67	2867	* @param TIM_InputTriggerSource: The Input Trigger source.
n0tform3	8:1c6281289d67	2868	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2869	* @arg TIM_TS_ITR0: Internal Trigger 0
n0tform3	8:1c6281289d67	2870	* @arg TIM_TS_ITR1: Internal Trigger 1
n0tform3	8:1c6281289d67	2871	* @arg TIM_TS_ITR2: Internal Trigger 2
n0tform3	8:1c6281289d67	2872	* @arg TIM_TS_ITR3: Internal Trigger 3
n0tform3	8:1c6281289d67	2873	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
n0tform3	8:1c6281289d67	2874	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
n0tform3	8:1c6281289d67	2875	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
n0tform3	8:1c6281289d67	2876	* @arg TIM_TS_ETRF: External Trigger input
n0tform3	8:1c6281289d67	2877	* @retval None
n0tform3	8:1c6281289d67	2878	*/
n0tform3	8:1c6281289d67	2879	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
n0tform3	8:1c6281289d67	2880	{
n0tform3	8:1c6281289d67	2881	uint16_t tmpsmcr = 0;
n0tform3	8:1c6281289d67	2882
n0tform3	8:1c6281289d67	2883	/* Check the parameters */
n0tform3	8:1c6281289d67	2884	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2885	assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
n0tform3	8:1c6281289d67	2886
n0tform3	8:1c6281289d67	2887	/* Get the TIMx SMCR register value */
n0tform3	8:1c6281289d67	2888	tmpsmcr = TIMx->SMCR;
n0tform3	8:1c6281289d67	2889
n0tform3	8:1c6281289d67	2890	/* Reset the TS Bits */
n0tform3	8:1c6281289d67	2891	tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
n0tform3	8:1c6281289d67	2892
n0tform3	8:1c6281289d67	2893	/* Set the Input Trigger source */
n0tform3	8:1c6281289d67	2894	tmpsmcr \|= TIM_InputTriggerSource;
n0tform3	8:1c6281289d67	2895
n0tform3	8:1c6281289d67	2896	/* Write to TIMx SMCR */
n0tform3	8:1c6281289d67	2897	TIMx->SMCR = tmpsmcr;
n0tform3	8:1c6281289d67	2898	}
n0tform3	8:1c6281289d67	2899
n0tform3	8:1c6281289d67	2900	/**
n0tform3	8:1c6281289d67	2901	* @brief Selects the TIMx Trigger Output Mode.
n0tform3	8:1c6281289d67	2902	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2903	*
n0tform3	8:1c6281289d67	2904	* @param TIM_TRGOSource: specifies the Trigger Output source.
n0tform3	8:1c6281289d67	2905	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2906	*
n0tform3	8:1c6281289d67	2907	* - For all TIMx
n0tform3	8:1c6281289d67	2908	* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2909	* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2910	* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2911	*
n0tform3	8:1c6281289d67	2912	* - For all TIMx except TIM6 and TIM7
n0tform3	8:1c6281289d67	2913	* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
n0tform3	8:1c6281289d67	2914	* is to be set, as soon as a capture or compare match occurs(TRGO)
n0tform3	8:1c6281289d67	2915	* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2916	* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2917	* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2918	* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
n0tform3	8:1c6281289d67	2919	*
n0tform3	8:1c6281289d67	2920	* @retval None
n0tform3	8:1c6281289d67	2921	*/
n0tform3	8:1c6281289d67	2922	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
n0tform3	8:1c6281289d67	2923	{
n0tform3	8:1c6281289d67	2924	/* Check the parameters */
n0tform3	8:1c6281289d67	2925	assert_param(IS_TIM_LIST5_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2926	assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
n0tform3	8:1c6281289d67	2927
n0tform3	8:1c6281289d67	2928	/* Reset the MMS Bits */
n0tform3	8:1c6281289d67	2929	TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
n0tform3	8:1c6281289d67	2930	/* Select the TRGO source */
n0tform3	8:1c6281289d67	2931	TIMx->CR2 \|= TIM_TRGOSource;
n0tform3	8:1c6281289d67	2932	}
n0tform3	8:1c6281289d67	2933
n0tform3	8:1c6281289d67	2934	/**
n0tform3	8:1c6281289d67	2935	* @brief Selects the TIMx Slave Mode.
n0tform3	8:1c6281289d67	2936	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2937	* @param TIM_SlaveMode: specifies the Timer Slave Mode.
n0tform3	8:1c6281289d67	2938	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2939	* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
n0tform3	8:1c6281289d67	2940	* the counter and triggers an update of the registers
n0tform3	8:1c6281289d67	2941	* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
n0tform3	8:1c6281289d67	2942	* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
n0tform3	8:1c6281289d67	2943	* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
n0tform3	8:1c6281289d67	2944	* @retval None
n0tform3	8:1c6281289d67	2945	*/
n0tform3	8:1c6281289d67	2946	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
n0tform3	8:1c6281289d67	2947	{
n0tform3	8:1c6281289d67	2948	/* Check the parameters */
n0tform3	8:1c6281289d67	2949	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2950	assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
n0tform3	8:1c6281289d67	2951
n0tform3	8:1c6281289d67	2952	/* Reset the SMS Bits */
n0tform3	8:1c6281289d67	2953	TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
n0tform3	8:1c6281289d67	2954
n0tform3	8:1c6281289d67	2955	/* Select the Slave Mode */
n0tform3	8:1c6281289d67	2956	TIMx->SMCR \|= TIM_SlaveMode;
n0tform3	8:1c6281289d67	2957	}
n0tform3	8:1c6281289d67	2958
n0tform3	8:1c6281289d67	2959	/**
n0tform3	8:1c6281289d67	2960	* @brief Sets or Resets the TIMx Master/Slave Mode.
n0tform3	8:1c6281289d67	2961	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2962	* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
n0tform3	8:1c6281289d67	2963	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2964	* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
n0tform3	8:1c6281289d67	2965	* and its slaves (through TRGO)
n0tform3	8:1c6281289d67	2966	* @arg TIM_MasterSlaveMode_Disable: No action
n0tform3	8:1c6281289d67	2967	* @retval None
n0tform3	8:1c6281289d67	2968	*/
n0tform3	8:1c6281289d67	2969	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
n0tform3	8:1c6281289d67	2970	{
n0tform3	8:1c6281289d67	2971	/* Check the parameters */
n0tform3	8:1c6281289d67	2972	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	2973	assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
n0tform3	8:1c6281289d67	2974
n0tform3	8:1c6281289d67	2975	/* Reset the MSM Bit */
n0tform3	8:1c6281289d67	2976	TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
n0tform3	8:1c6281289d67	2977
n0tform3	8:1c6281289d67	2978	/* Set or Reset the MSM Bit */
n0tform3	8:1c6281289d67	2979	TIMx->SMCR \|= TIM_MasterSlaveMode;
n0tform3	8:1c6281289d67	2980	}
n0tform3	8:1c6281289d67	2981
n0tform3	8:1c6281289d67	2982	/**
n0tform3	8:1c6281289d67	2983	* @brief Configures the TIMx External Trigger (ETR).
n0tform3	8:1c6281289d67	2984	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	2985	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
n0tform3	8:1c6281289d67	2986	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2987	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
n0tform3	8:1c6281289d67	2988	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
n0tform3	8:1c6281289d67	2989	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
n0tform3	8:1c6281289d67	2990	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
n0tform3	8:1c6281289d67	2991	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
n0tform3	8:1c6281289d67	2992	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	2993	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
n0tform3	8:1c6281289d67	2994	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
n0tform3	8:1c6281289d67	2995	* @param ExtTRGFilter: External Trigger Filter.
n0tform3	8:1c6281289d67	2996	* This parameter must be a value between 0x00 and 0x0F
n0tform3	8:1c6281289d67	2997	* @retval None
n0tform3	8:1c6281289d67	2998	*/
n0tform3	8:1c6281289d67	2999	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
n0tform3	8:1c6281289d67	3000	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
n0tform3	8:1c6281289d67	3001	{
n0tform3	8:1c6281289d67	3002	uint16_t tmpsmcr = 0;
n0tform3	8:1c6281289d67	3003
n0tform3	8:1c6281289d67	3004	/* Check the parameters */
n0tform3	8:1c6281289d67	3005	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
n0tform3	8:1c6281289d67	3006	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
n0tform3	8:1c6281289d67	3007	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
n0tform3	8:1c6281289d67	3008	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
n0tform3	8:1c6281289d67	3009
n0tform3	8:1c6281289d67	3010	tmpsmcr = TIMx->SMCR;
n0tform3	8:1c6281289d67	3011
n0tform3	8:1c6281289d67	3012	/* Reset the ETR Bits */
n0tform3	8:1c6281289d67	3013	tmpsmcr &= SMCR_ETR_MASK;
n0tform3	8:1c6281289d67	3014
n0tform3	8:1c6281289d67	3015	/* Set the Prescaler, the Filter value and the Polarity */
n0tform3	8:1c6281289d67	3016	tmpsmcr \|= (uint16_t)(TIM_ExtTRGPrescaler \| (uint16_t)(TIM_ExtTRGPolarity \| (uint16_t)(ExtTRGFilter << (uint16_t)8)));
n0tform3	8:1c6281289d67	3017
n0tform3	8:1c6281289d67	3018	/* Write to TIMx SMCR */
n0tform3	8:1c6281289d67	3019	TIMx->SMCR = tmpsmcr;
n0tform3	8:1c6281289d67	3020	}
n0tform3	8:1c6281289d67	3021	/**
n0tform3	8:1c6281289d67	3022	* @}
n0tform3	8:1c6281289d67	3023	*/
n0tform3	8:1c6281289d67	3024
n0tform3	8:1c6281289d67	3025	/** @defgroup TIM_Group8 Specific interface management functions
n0tform3	8:1c6281289d67	3026	* @brief Specific interface management functions
n0tform3	8:1c6281289d67	3027	*
n0tform3	8:1c6281289d67	3028	@verbatim
n0tform3	8:1c6281289d67	3029	===============================================================================
n0tform3	8:1c6281289d67	3030	Specific interface management functions
n0tform3	8:1c6281289d67	3031	===============================================================================
n0tform3	8:1c6281289d67	3032
n0tform3	8:1c6281289d67	3033	@endverbatim
n0tform3	8:1c6281289d67	3034	* @{
n0tform3	8:1c6281289d67	3035	*/
n0tform3	8:1c6281289d67	3036
n0tform3	8:1c6281289d67	3037	/**
n0tform3	8:1c6281289d67	3038	* @brief Configures the TIMx Encoder Interface.
n0tform3	8:1c6281289d67	3039	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	3040	* peripheral.
n0tform3	8:1c6281289d67	3041	* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
n0tform3	8:1c6281289d67	3042	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3043	* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
n0tform3	8:1c6281289d67	3044	* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
n0tform3	8:1c6281289d67	3045	* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
n0tform3	8:1c6281289d67	3046	* on the level of the other input.
n0tform3	8:1c6281289d67	3047	* @param TIM_IC1Polarity: specifies the IC1 Polarity
n0tform3	8:1c6281289d67	3048	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3049	* @arg TIM_ICPolarity_Falling: IC Falling edge.
n0tform3	8:1c6281289d67	3050	* @arg TIM_ICPolarity_Rising: IC Rising edge.
n0tform3	8:1c6281289d67	3051	* @param TIM_IC2Polarity: specifies the IC2 Polarity
n0tform3	8:1c6281289d67	3052	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3053	* @arg TIM_ICPolarity_Falling: IC Falling edge.
n0tform3	8:1c6281289d67	3054	* @arg TIM_ICPolarity_Rising: IC Rising edge.
n0tform3	8:1c6281289d67	3055	* @retval None
n0tform3	8:1c6281289d67	3056	*/
n0tform3	8:1c6281289d67	3057	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
n0tform3	8:1c6281289d67	3058	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
n0tform3	8:1c6281289d67	3059	{
n0tform3	8:1c6281289d67	3060	uint16_t tmpsmcr = 0;
n0tform3	8:1c6281289d67	3061	uint16_t tmpccmr1 = 0;
n0tform3	8:1c6281289d67	3062	uint16_t tmpccer = 0;
n0tform3	8:1c6281289d67	3063
n0tform3	8:1c6281289d67	3064	/* Check the parameters */
n0tform3	8:1c6281289d67	3065	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	3066	assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
n0tform3	8:1c6281289d67	3067	assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
n0tform3	8:1c6281289d67	3068	assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
n0tform3	8:1c6281289d67	3069
n0tform3	8:1c6281289d67	3070	/* Get the TIMx SMCR register value */
n0tform3	8:1c6281289d67	3071	tmpsmcr = TIMx->SMCR;
n0tform3	8:1c6281289d67	3072
n0tform3	8:1c6281289d67	3073	/* Get the TIMx CCMR1 register value */
n0tform3	8:1c6281289d67	3074	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	3075
n0tform3	8:1c6281289d67	3076	/* Get the TIMx CCER register value */
n0tform3	8:1c6281289d67	3077	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	3078
n0tform3	8:1c6281289d67	3079	/* Set the encoder Mode */
n0tform3	8:1c6281289d67	3080	tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
n0tform3	8:1c6281289d67	3081	tmpsmcr \|= TIM_EncoderMode;
n0tform3	8:1c6281289d67	3082
n0tform3	8:1c6281289d67	3083	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
n0tform3	8:1c6281289d67	3084	tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
n0tform3	8:1c6281289d67	3085	tmpccmr1 \|= TIM_CCMR1_CC1S_0 \| TIM_CCMR1_CC2S_0;
n0tform3	8:1c6281289d67	3086
n0tform3	8:1c6281289d67	3087	/* Set the TI1 and the TI2 Polarities */
n0tform3	8:1c6281289d67	3088	tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
n0tform3	8:1c6281289d67	3089	tmpccer \|= (uint16_t)(TIM_IC1Polarity \| (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
n0tform3	8:1c6281289d67	3090
n0tform3	8:1c6281289d67	3091	/* Write to TIMx SMCR */
n0tform3	8:1c6281289d67	3092	TIMx->SMCR = tmpsmcr;
n0tform3	8:1c6281289d67	3093
n0tform3	8:1c6281289d67	3094	/* Write to TIMx CCMR1 */
n0tform3	8:1c6281289d67	3095	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	3096
n0tform3	8:1c6281289d67	3097	/* Write to TIMx CCER */
n0tform3	8:1c6281289d67	3098	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	3099	}
n0tform3	8:1c6281289d67	3100
n0tform3	8:1c6281289d67	3101	/**
n0tform3	8:1c6281289d67	3102	* @brief Enables or disables the TIMx's Hall sensor interface.
n0tform3	8:1c6281289d67	3103	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	3104	* peripheral.
n0tform3	8:1c6281289d67	3105	* @param NewState: new state of the TIMx Hall sensor interface.
n0tform3	8:1c6281289d67	3106	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	3107	* @retval None
n0tform3	8:1c6281289d67	3108	*/
n0tform3	8:1c6281289d67	3109	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
n0tform3	8:1c6281289d67	3110	{
n0tform3	8:1c6281289d67	3111	/* Check the parameters */
n0tform3	8:1c6281289d67	3112	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
n0tform3	8:1c6281289d67	3113	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	3114
n0tform3	8:1c6281289d67	3115	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	3116	{
n0tform3	8:1c6281289d67	3117	/* Set the TI1S Bit */
n0tform3	8:1c6281289d67	3118	TIMx->CR2 \|= TIM_CR2_TI1S;
n0tform3	8:1c6281289d67	3119	}
n0tform3	8:1c6281289d67	3120	else
n0tform3	8:1c6281289d67	3121	{
n0tform3	8:1c6281289d67	3122	/* Reset the TI1S Bit */
n0tform3	8:1c6281289d67	3123	TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
n0tform3	8:1c6281289d67	3124	}
n0tform3	8:1c6281289d67	3125	}
n0tform3	8:1c6281289d67	3126	/**
n0tform3	8:1c6281289d67	3127	* @}
n0tform3	8:1c6281289d67	3128	*/
n0tform3	8:1c6281289d67	3129
n0tform3	8:1c6281289d67	3130	/** @defgroup TIM_Group9 Specific remapping management function
n0tform3	8:1c6281289d67	3131	* @brief Specific remapping management function
n0tform3	8:1c6281289d67	3132	*
n0tform3	8:1c6281289d67	3133	@verbatim
n0tform3	8:1c6281289d67	3134	===============================================================================
n0tform3	8:1c6281289d67	3135	Specific remapping management function
n0tform3	8:1c6281289d67	3136	===============================================================================
n0tform3	8:1c6281289d67	3137
n0tform3	8:1c6281289d67	3138	@endverbatim
n0tform3	8:1c6281289d67	3139	* @{
n0tform3	8:1c6281289d67	3140	*/
n0tform3	8:1c6281289d67	3141
n0tform3	8:1c6281289d67	3142	/**
n0tform3	8:1c6281289d67	3143	* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
n0tform3	8:1c6281289d67	3144	* @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
n0tform3	8:1c6281289d67	3145	* @param TIM_Remap: specifies the TIM input remapping source.
n0tform3	8:1c6281289d67	3146	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3147	* @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
n0tform3	8:1c6281289d67	3148	* @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
n0tform3	8:1c6281289d67	3149	* @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
n0tform3	8:1c6281289d67	3150	* @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
n0tform3	8:1c6281289d67	3151	* @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
n0tform3	8:1c6281289d67	3152	* @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
n0tform3	8:1c6281289d67	3153	* @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
n0tform3	8:1c6281289d67	3154	* @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
n0tform3	8:1c6281289d67	3155	* @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
n0tform3	8:1c6281289d67	3156	* @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
n0tform3	8:1c6281289d67	3157	* (HSE divided by a programmable prescaler)
n0tform3	8:1c6281289d67	3158	* @retval None
n0tform3	8:1c6281289d67	3159	*/
n0tform3	8:1c6281289d67	3160	void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
n0tform3	8:1c6281289d67	3161	{
n0tform3	8:1c6281289d67	3162	/* Check the parameters */
n0tform3	8:1c6281289d67	3163	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
n0tform3	8:1c6281289d67	3164	assert_param(IS_TIM_REMAP(TIM_Remap));
n0tform3	8:1c6281289d67	3165
n0tform3	8:1c6281289d67	3166	/* Set the Timer remapping configuration */
n0tform3	8:1c6281289d67	3167	TIMx->OR = TIM_Remap;
n0tform3	8:1c6281289d67	3168	}
n0tform3	8:1c6281289d67	3169	/**
n0tform3	8:1c6281289d67	3170	* @}
n0tform3	8:1c6281289d67	3171	*/
n0tform3	8:1c6281289d67	3172
n0tform3	8:1c6281289d67	3173	/**
n0tform3	8:1c6281289d67	3174	* @brief Configure the TI1 as Input.
n0tform3	8:1c6281289d67	3175	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
n0tform3	8:1c6281289d67	3176	* to select the TIM peripheral.
n0tform3	8:1c6281289d67	3177	* @param TIM_ICPolarity : The Input Polarity.
n0tform3	8:1c6281289d67	3178	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3179	* @arg TIM_ICPolarity_Rising
n0tform3	8:1c6281289d67	3180	* @arg TIM_ICPolarity_Falling
n0tform3	8:1c6281289d67	3181	* @arg TIM_ICPolarity_BothEdge
n0tform3	8:1c6281289d67	3182	* @param TIM_ICSelection: specifies the input to be used.
n0tform3	8:1c6281289d67	3183	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3184	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
n0tform3	8:1c6281289d67	3185	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
n0tform3	8:1c6281289d67	3186	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
n0tform3	8:1c6281289d67	3187	* @param TIM_ICFilter: Specifies the Input Capture Filter.
n0tform3	8:1c6281289d67	3188	* This parameter must be a value between 0x00 and 0x0F.
n0tform3	8:1c6281289d67	3189	* @retval None
n0tform3	8:1c6281289d67	3190	*/
n0tform3	8:1c6281289d67	3191	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	3192	uint16_t TIM_ICFilter)
n0tform3	8:1c6281289d67	3193	{
n0tform3	8:1c6281289d67	3194	uint16_t tmpccmr1 = 0, tmpccer = 0;
n0tform3	8:1c6281289d67	3195
n0tform3	8:1c6281289d67	3196	/* Disable the Channel 1: Reset the CC1E Bit */
n0tform3	8:1c6281289d67	3197	TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
n0tform3	8:1c6281289d67	3198	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	3199	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	3200
n0tform3	8:1c6281289d67	3201	/* Select the Input and set the filter */
n0tform3	8:1c6281289d67	3202	tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
n0tform3	8:1c6281289d67	3203	tmpccmr1 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
n0tform3	8:1c6281289d67	3204
n0tform3	8:1c6281289d67	3205	/* Select the Polarity and set the CC1E Bit */
n0tform3	8:1c6281289d67	3206	tmpccer &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
n0tform3	8:1c6281289d67	3207	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC1E);
n0tform3	8:1c6281289d67	3208
n0tform3	8:1c6281289d67	3209	/* Write to TIMx CCMR1 and CCER registers */
n0tform3	8:1c6281289d67	3210	TIMx->CCMR1 = tmpccmr1;
n0tform3	8:1c6281289d67	3211	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	3212	}
n0tform3	8:1c6281289d67	3213
n0tform3	8:1c6281289d67	3214	/**
n0tform3	8:1c6281289d67	3215	* @brief Configure the TI2 as Input.
n0tform3	8:1c6281289d67	3216	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
n0tform3	8:1c6281289d67	3217	* peripheral.
n0tform3	8:1c6281289d67	3218	* @param TIM_ICPolarity : The Input Polarity.
n0tform3	8:1c6281289d67	3219	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3220	* @arg TIM_ICPolarity_Rising
n0tform3	8:1c6281289d67	3221	* @arg TIM_ICPolarity_Falling
n0tform3	8:1c6281289d67	3222	* @arg TIM_ICPolarity_BothEdge
n0tform3	8:1c6281289d67	3223	* @param TIM_ICSelection: specifies the input to be used.
n0tform3	8:1c6281289d67	3224	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3225	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
n0tform3	8:1c6281289d67	3226	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
n0tform3	8:1c6281289d67	3227	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
n0tform3	8:1c6281289d67	3228	* @param TIM_ICFilter: Specifies the Input Capture Filter.
n0tform3	8:1c6281289d67	3229	* This parameter must be a value between 0x00 and 0x0F.
n0tform3	8:1c6281289d67	3230	* @retval None
n0tform3	8:1c6281289d67	3231	*/
n0tform3	8:1c6281289d67	3232	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	3233	uint16_t TIM_ICFilter)
n0tform3	8:1c6281289d67	3234	{
n0tform3	8:1c6281289d67	3235	uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
n0tform3	8:1c6281289d67	3236
n0tform3	8:1c6281289d67	3237	/* Disable the Channel 2: Reset the CC2E Bit */
n0tform3	8:1c6281289d67	3238	TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
n0tform3	8:1c6281289d67	3239	tmpccmr1 = TIMx->CCMR1;
n0tform3	8:1c6281289d67	3240	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	3241	tmp = (uint16_t)(TIM_ICPolarity << 4);
n0tform3	8:1c6281289d67	3242
n0tform3	8:1c6281289d67	3243	/* Select the Input and set the filter */
n0tform3	8:1c6281289d67	3244	tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
n0tform3	8:1c6281289d67	3245	tmpccmr1 \|= (uint16_t)(TIM_ICFilter << 12);
n0tform3	8:1c6281289d67	3246	tmpccmr1 \|= (uint16_t)(TIM_ICSelection << 8);
n0tform3	8:1c6281289d67	3247
n0tform3	8:1c6281289d67	3248	/* Select the Polarity and set the CC2E Bit */
n0tform3	8:1c6281289d67	3249	tmpccer &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
n0tform3	8:1c6281289d67	3250	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC2E);
n0tform3	8:1c6281289d67	3251
n0tform3	8:1c6281289d67	3252	/* Write to TIMx CCMR1 and CCER registers */
n0tform3	8:1c6281289d67	3253	TIMx->CCMR1 = tmpccmr1 ;
n0tform3	8:1c6281289d67	3254	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	3255	}
n0tform3	8:1c6281289d67	3256
n0tform3	8:1c6281289d67	3257	/**
n0tform3	8:1c6281289d67	3258	* @brief Configure the TI3 as Input.
n0tform3	8:1c6281289d67	3259	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	3260	* @param TIM_ICPolarity : The Input Polarity.
n0tform3	8:1c6281289d67	3261	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3262	* @arg TIM_ICPolarity_Rising
n0tform3	8:1c6281289d67	3263	* @arg TIM_ICPolarity_Falling
n0tform3	8:1c6281289d67	3264	* @arg TIM_ICPolarity_BothEdge
n0tform3	8:1c6281289d67	3265	* @param TIM_ICSelection: specifies the input to be used.
n0tform3	8:1c6281289d67	3266	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3267	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
n0tform3	8:1c6281289d67	3268	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
n0tform3	8:1c6281289d67	3269	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
n0tform3	8:1c6281289d67	3270	* @param TIM_ICFilter: Specifies the Input Capture Filter.
n0tform3	8:1c6281289d67	3271	* This parameter must be a value between 0x00 and 0x0F.
n0tform3	8:1c6281289d67	3272	* @retval None
n0tform3	8:1c6281289d67	3273	*/
n0tform3	8:1c6281289d67	3274	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	3275	uint16_t TIM_ICFilter)
n0tform3	8:1c6281289d67	3276	{
n0tform3	8:1c6281289d67	3277	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
n0tform3	8:1c6281289d67	3278
n0tform3	8:1c6281289d67	3279	/* Disable the Channel 3: Reset the CC3E Bit */
n0tform3	8:1c6281289d67	3280	TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
n0tform3	8:1c6281289d67	3281	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	3282	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	3283	tmp = (uint16_t)(TIM_ICPolarity << 8);
n0tform3	8:1c6281289d67	3284
n0tform3	8:1c6281289d67	3285	/* Select the Input and set the filter */
n0tform3	8:1c6281289d67	3286	tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
n0tform3	8:1c6281289d67	3287	tmpccmr2 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
n0tform3	8:1c6281289d67	3288
n0tform3	8:1c6281289d67	3289	/* Select the Polarity and set the CC3E Bit */
n0tform3	8:1c6281289d67	3290	tmpccer &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
n0tform3	8:1c6281289d67	3291	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC3E);
n0tform3	8:1c6281289d67	3292
n0tform3	8:1c6281289d67	3293	/* Write to TIMx CCMR2 and CCER registers */
n0tform3	8:1c6281289d67	3294	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	3295	TIMx->CCER = tmpccer;
n0tform3	8:1c6281289d67	3296	}
n0tform3	8:1c6281289d67	3297
n0tform3	8:1c6281289d67	3298	/**
n0tform3	8:1c6281289d67	3299	* @brief Configure the TI4 as Input.
n0tform3	8:1c6281289d67	3300	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
n0tform3	8:1c6281289d67	3301	* @param TIM_ICPolarity : The Input Polarity.
n0tform3	8:1c6281289d67	3302	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3303	* @arg TIM_ICPolarity_Rising
n0tform3	8:1c6281289d67	3304	* @arg TIM_ICPolarity_Falling
n0tform3	8:1c6281289d67	3305	* @arg TIM_ICPolarity_BothEdge
n0tform3	8:1c6281289d67	3306	* @param TIM_ICSelection: specifies the input to be used.
n0tform3	8:1c6281289d67	3307	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	3308	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
n0tform3	8:1c6281289d67	3309	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
n0tform3	8:1c6281289d67	3310	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
n0tform3	8:1c6281289d67	3311	* @param TIM_ICFilter: Specifies the Input Capture Filter.
n0tform3	8:1c6281289d67	3312	* This parameter must be a value between 0x00 and 0x0F.
n0tform3	8:1c6281289d67	3313	* @retval None
n0tform3	8:1c6281289d67	3314	*/
n0tform3	8:1c6281289d67	3315	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
n0tform3	8:1c6281289d67	3316	uint16_t TIM_ICFilter)
n0tform3	8:1c6281289d67	3317	{
n0tform3	8:1c6281289d67	3318	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
n0tform3	8:1c6281289d67	3319
n0tform3	8:1c6281289d67	3320	/* Disable the Channel 4: Reset the CC4E Bit */
n0tform3	8:1c6281289d67	3321	TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
n0tform3	8:1c6281289d67	3322	tmpccmr2 = TIMx->CCMR2;
n0tform3	8:1c6281289d67	3323	tmpccer = TIMx->CCER;
n0tform3	8:1c6281289d67	3324	tmp = (uint16_t)(TIM_ICPolarity << 12);
n0tform3	8:1c6281289d67	3325
n0tform3	8:1c6281289d67	3326	/* Select the Input and set the filter */
n0tform3	8:1c6281289d67	3327	tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
n0tform3	8:1c6281289d67	3328	tmpccmr2 \|= (uint16_t)(TIM_ICSelection << 8);
n0tform3	8:1c6281289d67	3329	tmpccmr2 \|= (uint16_t)(TIM_ICFilter << 12);
n0tform3	8:1c6281289d67	3330
n0tform3	8:1c6281289d67	3331	/* Select the Polarity and set the CC4E Bit */
n0tform3	8:1c6281289d67	3332	tmpccer &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
n0tform3	8:1c6281289d67	3333	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC4E);
n0tform3	8:1c6281289d67	3334
n0tform3	8:1c6281289d67	3335	/* Write to TIMx CCMR2 and CCER registers */
n0tform3	8:1c6281289d67	3336	TIMx->CCMR2 = tmpccmr2;
n0tform3	8:1c6281289d67	3337	TIMx->CCER = tmpccer ;
n0tform3	8:1c6281289d67	3338	}
n0tform3	8:1c6281289d67	3339
n0tform3	8:1c6281289d67	3340	/**
n0tform3	8:1c6281289d67	3341	* @}
n0tform3	8:1c6281289d67	3342	*/
n0tform3	8:1c6281289d67	3343
n0tform3	8:1c6281289d67	3344	/**
n0tform3	8:1c6281289d67	3345	* @}
n0tform3	8:1c6281289d67	3346	*/
n0tform3	8:1c6281289d67	3347
n0tform3	8:1c6281289d67	3348	/**
n0tform3	8:1c6281289d67	3349	* @}
n0tform3	8:1c6281289d67	3350	*/
n0tform3	8:1c6281289d67	3351
n0tform3	8:1c6281289d67	3352	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/
n0tform3	8:1c6281289d67	3353

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	15 Nov 2015
Imports:	67
Forks:	0
Commits:	9
Dependents:	0
Dependencies:	4
Followers:	1

stm32f4xx_tim.c@8:1c6281289d67, 2015-11-15 (annotated)

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