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Diff: Watchdog.cpp
- Revision:
- 10:673dff2b0ee6
- Parent:
- 9:90619245fb0a
- Child:
- 11:a1611543c454
diff -r 90619245fb0a -r 673dff2b0ee6 Watchdog.cpp
--- a/Watchdog.cpp Tue Sep 13 18:21:01 2016 +0000
+++ b/Watchdog.cpp Wed Sep 14 07:14:43 2016 +0000
@@ -125,17 +125,24 @@
s = s * WDT_CLOCK; // Newer Nucleo boards have 32.768 kHz crystal. Without it, the internal
// RC clock would have an average frequency of 40 kHz (variable between 30 and 60 kHz)
int scale = calcExponent16bit(((int)s + 4095) / 4096);
+ int residual; // The value for the RLR register
+
if (scale < 2)
+ {
scale = 2;
- int residual = s / (1 << scale); // The value for the RLR register
- if (residual < 1)
residual = 1;
-
- if (scale > 8) //STM32 allows a maximum time of around 26.2 seconds for the Watchdog timer
+ }
+ else if (scale > 8) // STM32 allows a maximum time of around 26.2 seconds for the Watchdog timer
{
scale = 8;
residual = 4096;
}
+ else
+ {
+ residual = s / (1 << scale); // The value for the RLR register
+ if (residual < 1)
+ residual = 1;
+ }
IWDG->KR = 0x5555; // enable write to PR, RLR
IWDG->PR = scale - 2; // Prescaler has values of multiples of 4 (i.e. 2 ^2), page 486 Reference Manual
@@ -151,17 +158,24 @@
// RC clock would have an average frequency of 40 kHz (variable between 30 and 60 kHz)
int scale = calcExponent16bit((ms + 4095) >> 12);
+ int residual; // The value for the RLR register
+
if (scale < 2)
+ {
scale = 2;
- int residual = ms / (1 << scale); // The value for the RLR register
- if (residual < 1)
residual = 1;
-
- if (scale > 8) // STM32 allows a maximum time of around 26.2 seconds for the Watchdog timer
+ }
+ else if (scale > 8) // STM32 allows a maximum time of around 26.2 seconds for the Watchdog timer
{
scale = 8;
residual = 4096;
}
+ else
+ {
+ residual = ms / (1 << scale); // The value for the RLR register
+ if (residual < 1)
+ residual = 1;
+ }
IWDG->KR = 0x5555; // enable write to PR, RLR
IWDG->PR = scale - 2; // Prescaler has values of multiples of 4 (i.e. 2 ^2), page 486 Reference Manual
