Tomonori Kuroki / MuWatchdog

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Fork of Watchdog by David Smart

Watchdog.cpp@18:edfbf294c9e2, 2018-03-19 (annotated)

Committer:
mutech
Date:
Mon Mar 19 04:35:39 2018 +0000
Revision:
18:edfbf294c9e2
Parent:
17:ccd155378a9b
Child:
19:3b172e42d8ee
MuWatchdog

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mutech 11:a1611543c454 1 /// @file Watchdog.cpp provides the interface to the Watchdog module
WiredHome 2:2873f068f325 2 ///
WiredHome 2:2873f068f325 3 /// This provides basic Watchdog service for the mbed. You can configure
WiredHome 2:2873f068f325 4 /// various timeout intervals that meet your system needs. Additionally,
WiredHome 2:2873f068f325 5 /// it is possible to identify if the Watchdog was the cause of any
WiredHome 2:2873f068f325 6 /// system restart.
WiredHome 2:2873f068f325 7 ///
WiredHome 2:2873f068f325 8 /// Adapted from Simon's Watchdog code from http://mbed.org/forum/mbed/topic/508/
WiredHome 2:2873f068f325 9 ///
WiredHome 2:2873f068f325 10 /// @note Copyright © 2011 by Smartware Computing, all rights reserved.
WiredHome 2:2873f068f325 11 /// This software may be used to derive new software, as long as
WiredHome 2:2873f068f325 12 /// this copyright statement remains in the source file.
WiredHome 2:2873f068f325 13 /// @author David Smart
WiredHome 2:2873f068f325 14 ///
mutech 7:3814d72b8166 15 /// \li v2.10 - 20160914: Changed TARGET_STM by mutech, t.kuroki
mutech 7:3814d72b8166 16
WiredHome 0:7a316f14da9c 17 #include "Watchdog.h"
WiredHome 0:7a316f14da9c 18
WiredHome 5:2dad2a78ffbd 19 #if defined( TARGET_LPC1768 )
WiredHome 0:7a316f14da9c 20 /// Watchdog gets instantiated at the module level
WiredHome 0:7a316f14da9c 21 Watchdog::Watchdog() {
mutech 15:e0e4c2268558 22 _wdreset = (LPC_WDT->WDMOD >> 2) & 1; // capture the cause of the previous reset
WiredHome 0:7a316f14da9c 23 }
WiredHome 0:7a316f14da9c 24
WiredHome 0:7a316f14da9c 25 /// Load timeout value in watchdog timer and enable
WiredHome 0:7a316f14da9c 26 void Watchdog::Configure(float s) {
WiredHome 0:7a316f14da9c 27 LPC_WDT->WDCLKSEL = 0x1; // Set CLK src to PCLK
WiredHome 0:7a316f14da9c 28 uint32_t clk = SystemCoreClock / 16; // WD has a fixed /4 prescaler, PCLK default is /4
WiredHome 2:2873f068f325 29 LPC_WDT->WDTC = (uint32_t)(s * (float)clk);
WiredHome 0:7a316f14da9c 30 LPC_WDT->WDMOD = 0x3; // Enabled and Reset
WiredHome 0:7a316f14da9c 31 Service();
WiredHome 0:7a316f14da9c 32 }
WiredHome 0:7a316f14da9c 33
mutech 7:3814d72b8166 34 void Watchdog::Configure(int ms) {
mutech 7:3814d72b8166 35 LPC_WDT->WDCLKSEL = 0x1; // Set CLK src to PCLK
mutech 7:3814d72b8166 36 uint32_t clk = SystemCoreClock / 1000; //
mutech 7:3814d72b8166 37 LPC_WDT->WDTC = (ms * clk) / 16; // WD has a fixed /4 prescaler, PCLK default is /4
mutech 7:3814d72b8166 38 LPC_WDT->WDMOD = 0x3; // Enabled and Reset
mutech 7:3814d72b8166 39 Service();
mutech 7:3814d72b8166 40 }
mutech 7:3814d72b8166 41
WiredHome 0:7a316f14da9c 42 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
WiredHome 0:7a316f14da9c 43 /// by writing this required bit pattern
WiredHome 0:7a316f14da9c 44 void Watchdog::Service() {
WiredHome 0:7a316f14da9c 45 LPC_WDT->WDFEED = 0xAA;
WiredHome 0:7a316f14da9c 46 LPC_WDT->WDFEED = 0x55;
WiredHome 0:7a316f14da9c 47 }
WiredHome 0:7a316f14da9c 48
WiredHome 0:7a316f14da9c 49 /// get the flag to indicate if the watchdog causes the reset
WiredHome 0:7a316f14da9c 50 bool Watchdog::WatchdogCausedReset() {
mutech 15:e0e4c2268558 51 return _wdreset;
WiredHome 0:7a316f14da9c 52 }
WiredHome 5:2dad2a78ffbd 53 #elif defined( TARGET_LPC4088 )
WiredHome 5:2dad2a78ffbd 54 // from Gesotec Gesotec
WiredHome 5:2dad2a78ffbd 55 /// Watchdog gets instantiated at the module level
WiredHome 5:2dad2a78ffbd 56 Watchdog::Watchdog() {
mutech 15:e0e4c2268558 57 _wdreset = (LPC_WDT->MOD >> 2) & 1; // capture the cause of the previous reset
WiredHome 5:2dad2a78ffbd 58 }
WiredHome 5:2dad2a78ffbd 59
WiredHome 5:2dad2a78ffbd 60 /// Load timeout value in watchdog timer and enable
WiredHome 5:2dad2a78ffbd 61 void Watchdog::Configure(float s) {
WiredHome 5:2dad2a78ffbd 62 //LPC_WDT->CLKSEL = 0x1; // Set CLK src to PCLK
WiredHome 5:2dad2a78ffbd 63 uint32_t clk = 500000 / 4; // WD has a fixed /4 prescaler, and a 500khz oscillator
WiredHome 5:2dad2a78ffbd 64 LPC_WDT->TC = (uint32_t)(s * (float)clk);
WiredHome 5:2dad2a78ffbd 65 LPC_WDT->MOD = 0x3; // Enabled and Reset
WiredHome 5:2dad2a78ffbd 66 Service();
WiredHome 5:2dad2a78ffbd 67 }
mutech 7:3814d72b8166 68
mutech 7:3814d72b8166 69 void Watchdog::Configure(int ms) {
mutech 7:3814d72b8166 70 //LPC_WDT->CLKSEL = 0x1; // Set CLK src to PCLK
mutech 7:3814d72b8166 71 uint32_t clk = 500000 / 4; // WD has a fixed /4 prescaler, and a 500khz oscillator
mutech 7:3814d72b8166 72 LPC_WDT->TC = (ms * clk) / 1000;
mutech 7:3814d72b8166 73 LPC_WDT->MOD = 0x3; // Enabled and Reset
mutech 7:3814d72b8166 74 Service();
mutech 7:3814d72b8166 75 }
mutech 7:3814d72b8166 76
WiredHome 5:2dad2a78ffbd 77 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
WiredHome 5:2dad2a78ffbd 78 /// by writing this required bit pattern
WiredHome 5:2dad2a78ffbd 79 void Watchdog::Service() {
WiredHome 5:2dad2a78ffbd 80 LPC_WDT->FEED = 0xAA;
WiredHome 5:2dad2a78ffbd 81 LPC_WDT->FEED = 0x55;
WiredHome 5:2dad2a78ffbd 82 }
WiredHome 5:2dad2a78ffbd 83
WiredHome 5:2dad2a78ffbd 84 /// get the flag to indicate if the watchdog causes the reset
WiredHome 5:2dad2a78ffbd 85 bool Watchdog::WatchdogCausedReset() {
mutech 15:e0e4c2268558 86 return _wdreset;
WiredHome 5:2dad2a78ffbd 87 }
mutech 17:ccd155378a9b 88
mutech 17:ccd155378a9b 89 #elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X)
mutech 18:edfbf294c9e2 90
mutech 17:ccd155378a9b 91 // from Gesotec Gesotec
mutech 17:ccd155378a9b 92 /// Watchdog gets instantiated at the module level
mutech 17:ccd155378a9b 93 Watchdog::Watchdog()
mutech 17:ccd155378a9b 94 {
mutech 17:ccd155378a9b 95 _wdreset = (LPC_WWDT->MOD >> 2) & 1; // capture the cause of the previous reset
mutech 17:ccd155378a9b 96 }
mutech 17:ccd155378a9b 97
mutech 17:ccd155378a9b 98 /// Load timeout value in watchdog timer and enable
mutech 17:ccd155378a9b 99 void Watchdog::Configure(float s)
mutech 17:ccd155378a9b 100 {
mutech 17:ccd155378a9b 101 Configure((int)(s * 1000));
mutech 17:ccd155378a9b 102 }
mutech 17:ccd155378a9b 103
mutech 17:ccd155378a9b 104 void Watchdog::Configure(int ms)
mutech 17:ccd155378a9b 105 {
mutech 18:edfbf294c9e2 106 #if 0
mutech 18:edfbf294c9e2 107 uint32_t clk = get_wdtclock() / 4; // WD has a fixed /4 prescaler, and a 500khz oscillator
mutech 18:edfbf294c9e2 108 LPC_WWDT->TC = (ms * clk) / 1000;
mutech 18:edfbf294c9e2 109 #else
mutech 18:edfbf294c9e2 110 LPC_SYSCON->WDTOSCCTRL = (0xA << 5); // wdt_osc_clk = Fclkana/2, Fclkana = 3.5MHz
mutech 18:edfbf294c9e2 111 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 17); // Enable Clock WWDT
mutech 18:edfbf294c9e2 112 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); // Enable Power WDTOSC_PD
mutech 18:edfbf294c9e2 113 uint32_t clk = ((3500000/2)/4); // COUNT = wdt_osc_clk/4
mutech 18:edfbf294c9e2 114 LPC_WWDT->TC = (ms * clk) / 1000;
mutech 18:edfbf294c9e2 115 #endif
mutech 18:edfbf294c9e2 116 LPC_WWDT->MOD = 0x3; // Enabled and Reset
mutech 18:edfbf294c9e2 117 Service();
mutech 18:edfbf294c9e2 118 }
mutech 18:edfbf294c9e2 119
mutech 18:edfbf294c9e2 120 uint32_t Watchdog::get_wdtclock()
mutech 18:edfbf294c9e2 121 {
mutech 17:ccd155378a9b 122 uint32_t wdt_osc = 0;
mutech 18:edfbf294c9e2 123
mutech 17:ccd155378a9b 124 /* Determine clock frequency according to clock register values */
mutech 17:ccd155378a9b 125 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F)
mutech 17:ccd155378a9b 126 {
mutech 17:ccd155378a9b 127 case 0: wdt_osc = 0; break;
mutech 18:edfbf294c9e2 128 case 1: wdt_osc = 600000; break;
mutech 18:edfbf294c9e2 129 case 2: wdt_osc = 1050000; break;
mutech 18:edfbf294c9e2 130 case 3: wdt_osc = 1400000; break;
mutech 18:edfbf294c9e2 131 case 4: wdt_osc = 1750000; break;
mutech 18:edfbf294c9e2 132 case 5: wdt_osc = 2100000; break;
mutech 18:edfbf294c9e2 133 case 6: wdt_osc = 2400000; break;
mutech 18:edfbf294c9e2 134 case 7: wdt_osc = 2700000; break;
mutech 18:edfbf294c9e2 135 case 8: wdt_osc = 3000000; break;
mutech 18:edfbf294c9e2 136 case 9: wdt_osc = 3250000; break;
mutech 18:edfbf294c9e2 137 case 10: wdt_osc = 3500000; break;
mutech 18:edfbf294c9e2 138 case 11: wdt_osc = 3750000; break;
mutech 18:edfbf294c9e2 139 case 12: wdt_osc = 4000000; break;
mutech 18:edfbf294c9e2 140 case 13: wdt_osc = 4200000; break;
mutech 18:edfbf294c9e2 141 case 14: wdt_osc = 4400000; break;
mutech 18:edfbf294c9e2 142 case 15: wdt_osc = 4600000; break;
mutech 17:ccd155378a9b 143 }
mutech 18:edfbf294c9e2 144 // wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
mutech 18:edfbf294c9e2 145 return wdt_osc;
mutech 17:ccd155378a9b 146 }
mutech 17:ccd155378a9b 147
mutech 17:ccd155378a9b 148 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
mutech 17:ccd155378a9b 149 /// by writing this required bit pattern
mutech 17:ccd155378a9b 150 void Watchdog::Service()
mutech 17:ccd155378a9b 151 {
mutech 17:ccd155378a9b 152 LPC_WWDT->FEED = 0xAA;
mutech 17:ccd155378a9b 153 LPC_WWDT->FEED = 0x55;
mutech 17:ccd155378a9b 154 }
mutech 17:ccd155378a9b 155
mutech 17:ccd155378a9b 156 /// get the flag to indicate if the watchdog causes the reset
mutech 17:ccd155378a9b 157 bool Watchdog::WatchdogCausedReset()
mutech 17:ccd155378a9b 158 {
mutech 17:ccd155378a9b 159 return _wdreset;
mutech 17:ccd155378a9b 160 }
mutech 17:ccd155378a9b 161
mutech 7:3814d72b8166 162 #elif defined(TARGET_STM)
mutech 7:3814d72b8166 163 Watchdog::Watchdog()
mutech 7:3814d72b8166 164 {
mutech 15:e0e4c2268558 165 _rcc_csr = RCC->CSR;
mutech 15:e0e4c2268558 166 RCC->CSR |= RCC_CSR_RMVF; // clear reset flag
WiredHome 5:2dad2a78ffbd 167 }
WiredHome 0:7a316f14da9c 168
mutech 11:a1611543c454 169 // 整数Xを含む最小のべき乗指数
mutech 11:a1611543c454 170 int Watchdog::calcExponent16bit(uint16_t v)
mutech 11:a1611543c454 171 {
mutech 11:a1611543c454 172 // return (v == 0) ? 0 : MSB16bit(v - 1) + 1;
mutech 11:a1611543c454 173 if (!v)
mutech 11:a1611543c454 174 return 0;
mutech 11:a1611543c454 175 --v;
mutech 7:3814d72b8166 176 // 最大有効ビット数（MSB：Most Significant Bit）
mutech 7:3814d72b8166 177 v |= (v >> 1);
mutech 7:3814d72b8166 178 v |= (v >> 2);
mutech 7:3814d72b8166 179 v |= (v >> 4);
mutech 7:3814d72b8166 180 v |= (v >> 8);
mutech 7:3814d72b8166 181 // return count16bit(v) - 1;
mutech 7:3814d72b8166 182 // 立っているビットの数を数える
mutech 7:3814d72b8166 183 v = (v & 0x5555) + ((v >> 1) & 0x5555);
mutech 7:3814d72b8166 184 v = (v & 0x3333) + ((v >> 2) & 0x3333);
mutech 7:3814d72b8166 185 v = (v & 0x0f0f) + ((v >> 4) & 0x0f0f);
mutech 11:a1611543c454 186 return (v & 0x00ff) + ((v >> 8) & 0x00ff);
mutech 7:3814d72b8166 187 }
mutech 7:3814d72b8166 188
mutech 14:30665d9afe68 189 #if defined(TARGET_STM32F0)
mutech 14:30665d9afe68 190 #define WDT_CLOCK 40000U // 40 kHz
mutech 14:30665d9afe68 191 #else
mutech 14:30665d9afe68 192 #define WDT_CLOCK 32768U // 32.768 kHz
mutech 14:30665d9afe68 193 #endif
mutech 7:3814d72b8166 194
WiredHome 5:2dad2a78ffbd 195 /// Load timeout value in watchdog timer and enable
mutech 7:3814d72b8166 196 void Watchdog::Configure(float s)
mutech 7:3814d72b8166 197 {
WiredHome 5:2dad2a78ffbd 198 // http://www.st.com/web/en/resource/technical/document/reference_manual/CD00171190.pdf
mutech 7:3814d72b8166 199
mutech 11:a1611543c454 200 // Newer Nucleo boards have 32.768 kHz crystal. Without it, the internal
mutech 7:3814d72b8166 201 // RC clock would have an average frequency of 40 kHz (variable between 30 and 60 kHz)
mutech 11:a1611543c454 202 uint32_t tick = (uint32_t)(s * WDT_CLOCK + 0.5f);
mutech 11:a1611543c454 203 // The RLR register is 12 bits and beyond that a prescaler should be used
mutech 11:a1611543c454 204 int scale = calcExponent16bit((tick + 4095) >> 12);
mutech 7:3814d72b8166 205 if (scale < 2)
mutech 7:3814d72b8166 206 scale = 2;
mutech 10:673dff2b0ee6 207 else if (scale > 8) // STM32 allows a maximum time of around 26.2 seconds for the Watchdog timer
mutech 7:3814d72b8166 208 scale = 8;
mutech 11:a1611543c454 209
mutech 11:a1611543c454 210 int residual = tick / (1 << scale); // The value for the RLR register
mutech 11:a1611543c454 211 if (residual < 1)
mutech 11:a1611543c454 212 residual = 1;
mutech 11:a1611543c454 213 else if (residual > 4096)
mutech 7:3814d72b8166 214 residual = 4096;
mutech 7:3814d72b8166 215
WiredHome 5:2dad2a78ffbd 216 IWDG->KR = 0x5555; // enable write to PR, RLR
mutech 7:3814d72b8166 217 IWDG->PR = scale - 2; // Prescaler has values of multiples of 4 (i.e. 2 ^2), page 486 Reference Manual
mutech 7:3814d72b8166 218 IWDG->RLR = residual - 1; // Init RLR
mutech 7:3814d72b8166 219 IWDG->KR = 0xAAAA; // Reload the watchdog
mutech 7:3814d72b8166 220 IWDG->KR = 0xCCCC; // Starts the WD
mutech 7:3814d72b8166 221 }
mutech 7:3814d72b8166 222
mutech 7:3814d72b8166 223 void Watchdog::Configure(int ms)
mutech 7:3814d72b8166 224 {
mutech 7:3814d72b8166 225 // http://www.st.com/web/en/resource/technical/document/reference_manual/CD00171190.pdf
mutech 7:3814d72b8166 226
mutech 11:a1611543c454 227 // Newer Nucleo boards have 32.768 kHz crystal. Without it, the internal
mutech 11:a1611543c454 228 // RC clock would have an average frequency of 40 kHz (variable between 30 and 60 kHz)
mutech 11:a1611543c454 229 // tick = (ms / (1/WDT_CLOCK))/1000;
mutech 11:a1611543c454 230 uint32_t tick = ((uint32_t)ms * WDT_CLOCK + 500U) / 1000U;
mutech 11:a1611543c454 231 // The RLR register is 12 bits and beyond that a prescaler should be used
mutech 11:a1611543c454 232 int scale = calcExponent16bit((tick + 4095) >> 12);
mutech 11:a1611543c454 233 if (scale < 2)
mutech 11:a1611543c454 234 scale = 2;
mutech 11:a1611543c454 235 else if (scale > 8) // STM32 allows a maximum time of around 26.2 seconds for the Watchdog timer
mutech 11:a1611543c454 236 scale = 8;
mutech 10:673dff2b0ee6 237
mutech 11:a1611543c454 238 int residual = tick / (1 << scale); // The value for the RLR register
mutech 11:a1611543c454 239 if (residual < 1)
mutech 7:3814d72b8166 240 residual = 1;
mutech 11:a1611543c454 241 else if (residual > 4096)
mutech 7:3814d72b8166 242 residual = 4096;
mutech 7:3814d72b8166 243
mutech 7:3814d72b8166 244 IWDG->KR = 0x5555; // enable write to PR, RLR
mutech 7:3814d72b8166 245 IWDG->PR = scale - 2; // Prescaler has values of multiples of 4 (i.e. 2 ^2), page 486 Reference Manual
mutech 7:3814d72b8166 246 IWDG->RLR = residual - 1; // Init RLR
WiredHome 5:2dad2a78ffbd 247 IWDG->KR = 0xAAAA; // Reload the watchdog
WiredHome 5:2dad2a78ffbd 248 IWDG->KR = 0xCCCC; // Starts the WD
WiredHome 5:2dad2a78ffbd 249 }
WiredHome 0:7a316f14da9c 250
WiredHome 5:2dad2a78ffbd 251 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
mutech 7:3814d72b8166 252 void Watchdog::Service()
mutech 7:3814d72b8166 253 {
WiredHome 5:2dad2a78ffbd 254 IWDG->KR = 0xAAAA;
WiredHome 5:2dad2a78ffbd 255 }
WiredHome 5:2dad2a78ffbd 256
WiredHome 5:2dad2a78ffbd 257 /// get the flag to indicate if the watchdog causes the reset
mutech 7:3814d72b8166 258 bool Watchdog::WatchdogCausedReset()
mutech 7:3814d72b8166 259 {
mutech 15:e0e4c2268558 260 return (_rcc_csr & (RCC_CSR_IWDGRSTF | RCC_CSR_WWDGRSTF)) != 0; // read the IWDGRSTF (Independent WD, not the windows WD)
WiredHome 5:2dad2a78ffbd 261 }
WiredHome 5:2dad2a78ffbd 262 #endif