Tomonori Kuroki / MuWatchdog

Fork of Watchdog by David Smart

Revision:
27:b16166a526a2
Parent:
26:f7ccf62c4dd0
Child:
29:d84c025e8c8e
--- a/Watchdog.cpp	Wed May 08 10:53:46 2019 +0000
+++ b/Watchdog.cpp	Sat May 25 09:03:50 2019 +0000
@@ -1,4 +1,4 @@
-    /// @file Watchdog.cpp provides the interface to the Watchdog module
+/// @file Watchdog.cpp provides the interface to the Watchdog module
 ///
 /// This provides basic Watchdog service for the mbed. You can configure
 /// various timeout intervals that meet your system needs. Additionally,
@@ -16,76 +16,90 @@
 
 #include "Watchdog.h"
 
+//-----------------------------------------------------------------------------
 #if defined( TARGET_LPC1768 )
 /// Watchdog gets instantiated at the module level
-Watchdog::Watchdog() {
+Watchdog::Watchdog()
+{
     _wdreset = (LPC_WDT->WDMOD >> 2) & 1;    // capture the cause of the previous reset
 }
 
 /// Load timeout value in watchdog timer and enable
-void Watchdog::Configure(float s) {
+void Watchdog::begin(float sec)
+{
     LPC_WDT->WDCLKSEL = 0x1;                // Set CLK src to PCLK
     uint32_t clk = SystemCoreClock / 16;    // WD has a fixed /4 prescaler, PCLK default is /4
-    LPC_WDT->WDTC = (uint32_t)(s * (float)clk);
+    LPC_WDT->WDTC = (uint32_t)(sec * (float)clk);
     LPC_WDT->WDMOD = 0x3;                   // Enabled and Reset
-    Service();
+    clear();
 }
 
-void Watchdog::Configure(int ms) {
+void Watchdog::begin(int ms)
+{
     LPC_WDT->WDCLKSEL = 0x1;                // Set CLK src to PCLK
     uint32_t clk = SystemCoreClock / 1000;  // 
     LPC_WDT->WDTC = (ms * clk) / 16;        // WD has a fixed /4 prescaler, PCLK default is /4
     LPC_WDT->WDMOD = 0x3;                   // Enabled and Reset
-    Service();
+    clear();
 }
 
 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
 /// by writing this required bit pattern
-void Watchdog::Service() {
+void Watchdog::clear()
+{
     LPC_WDT->WDFEED = 0xAA;
     LPC_WDT->WDFEED = 0x55;
 }
 
 /// get the flag to indicate if the watchdog causes the reset
-bool Watchdog::WatchdogCausedReset() {
+bool Watchdog::WatchdogCausedReset()
+{
     return _wdreset;
 }
+
+//-----------------------------------------------------------------------------
 #elif defined( TARGET_LPC4088 )
 // from Gesotec Gesotec
 /// Watchdog gets instantiated at the module level
-Watchdog::Watchdog() {
+Watchdog::Watchdog()
+{
     _wdreset = (LPC_WDT->MOD >> 2) & 1;    // capture the cause of the previous reset
 }
  
 /// Load timeout value in watchdog timer and enable
-void Watchdog::Configure(float s) {
+void Watchdog::begin(float sec)
+{
     //LPC_WDT->CLKSEL = 0x1;                // Set CLK src to PCLK
     uint32_t clk = 500000 / 4;    // WD has a fixed /4 prescaler, and a 500khz oscillator
-    LPC_WDT->TC = (uint32_t)(s * (float)clk);
+    LPC_WDT->TC = (uint32_t)(sec * (float)clk);
     LPC_WDT->MOD = 0x3;                   // Enabled and Reset
-    Service();
+    clear();
 }
 
-void Watchdog::Configure(int ms) {
+void Watchdog::begin(int ms)
+{
     //LPC_WDT->CLKSEL = 0x1;                // Set CLK src to PCLK
     uint32_t clk = 500000 / 4;    // WD has a fixed /4 prescaler, and a 500khz oscillator
     LPC_WDT->TC = (ms * clk) / 1000;
     LPC_WDT->MOD = 0x3;                   // Enabled and Reset
-    Service();
+    clear();
 }
 
 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
 /// by writing this required bit pattern
-void Watchdog::Service() {
+void Watchdog::clear()
+{
     LPC_WDT->FEED = 0xAA;
     LPC_WDT->FEED = 0x55;
 }
  
 /// get the flag to indicate if the watchdog causes the reset
-bool Watchdog::WatchdogCausedReset() {
+bool Watchdog::WatchdogCausedReset()
+{
     return _wdreset;
 }
 
+//-----------------------------------------------------------------------------
 #elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X)
 
 // from Gesotec Gesotec
@@ -96,14 +110,14 @@
 }
  
 /// Load timeout value in watchdog timer and enable
-void Watchdog::Configure(float s)
+void Watchdog::begin(float sec)
 {
-    Configure((int)(s * 1000));
+    begin((int)(s * 1000));
 }
 
 #define WDTOSCCTRL_Val(clk, div)    ((((uint32_t)(clk)) << 5) | (((div) >> 1) - 1))
 
-void Watchdog::Configure(int ms)
+void Watchdog::begin(int ms)
 {
 #if 0
     uint32_t clk = get_wdtclock() / 4;    // WD has a fixed /4 prescaler, and a 500khz oscillator
@@ -116,7 +130,7 @@
     LPC_WWDT->TC = (ms * clk) / 1000;
 #endif
     LPC_WWDT->MOD = 0x3;                    // Enabled and Reset
-    Service();
+    clear();
 }
 
 uint32_t Watchdog::get_wdtclock()
@@ -173,7 +187,7 @@
 
 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
 /// by writing this required bit pattern
-void Watchdog::Service()
+void Watchdog::clear()
 {
     LPC_WWDT->FEED = 0xAA;
     LPC_WWDT->FEED = 0x55;
@@ -185,15 +199,11 @@
     return _wdreset;
 }
 
+//-----------------------------------------------------------------------------
 #elif defined(TARGET_STM)
-Watchdog::Watchdog()
-{
-    _rcc_csr = RCC->CSR;
-    RCC->CSR |= RCC_CSR_RMVF; // clear reset flag
-}
 
 // 整数Xを含む最小のべき乗指数
-int Watchdog::calcExponent16bit(uint16_t v)
+static int calcExponent16bit(uint16_t v)
 {
 //  return (v == 0) ? 0 : MSB16bit(v - 1) + 1;
     if (!v)
@@ -212,6 +222,12 @@
     return  (v & 0x00ff) + ((v >> 8) & 0x00ff);
 }
 
+Watchdog::Watchdog()
+{
+    _rcc_csr = RCC->CSR;
+    RCC->CSR |= RCC_CSR_RMVF; // clear reset flag
+}
+
 #if defined(TARGET_STM32F0) || defined(TARGET_STM32F1) || defined(TARGET_STM32F3)
   #define WDT_CLOCK     40000U      // 40 kHz
 #else
@@ -220,13 +236,13 @@
 #endif
 
 /// Load timeout value in watchdog timer and enable
-void Watchdog::begin(float s)
+void Watchdog::begin(float sec)
 {
     // http://www.st.com/web/en/resource/technical/document/reference_manual/CD00171190.pdf
 
     // Newer Nucleo boards have 32.768 kHz crystal. Without it, the internal 
                                 // RC clock would have an average frequency of 40 kHz (variable between 30 and 60 kHz)
-    uint32_t tick = (uint32_t)(s * WDT_CLOCK + 0.5f);
+    uint32_t tick = (uint32_t)(sec * WDT_CLOCK + 0.5f);
     // The RLR register is 12 bits and beyond that a prescaler should be used
     int scale = calcExponent16bit((tick + 4095) >> 12);
     if (scale < 2)
@@ -275,18 +291,8 @@
     IWDG->KR  = 0xCCCC;         // Starts the WD
 }
 
-void Watchdog::Configure(float s)
-{
-    begin(s);
-}
-
-void Watchdog::Configure(int ms)
-{
-    begin(ms);
-}
-
 /// "Service", "kick" or "feed" the dog - reset the watchdog timer
-void Watchdog::Service()
+void Watchdog::clear()
 {
     IWDG->KR  = 0xAAAA;
 }
@@ -301,4 +307,7 @@
     return (_rcc_csr & (RCC_CSR_WDGRSTF | RCC_CSR_WWDGRSTF)) != 0;  // read the IWDGRSTF (Independent WD, not the windows WD)
 #endif
 }
+
+//-----------------------------------------------------------------------------
 #endif
+