t k / Mbed 2 deprecated MovPlayer

This program plays QuickTime movies on GR-Peach

Dependencies:   AsciiFont GR-PEACH_video GraphicsFramework LCD_shield_config R_BSP TLV320_RBSP mbed-rtos mbed

Requirements

  • GR-Peach
  • GR-Peach Audio Camera Shield or I²S compatible audio DAC
  • GR-Peach LCD Shield
  • USB memory stick

How to play movie files

  • Encode movie files

encode movies with ffmpeg

$ ffmpeg -i <input -ar 44100 -acodec pcm_s16le -s 480x270 -vcodec mjpeg -q:v 3 -movflags faststart -threads 4 -vf fps=30 <output>.mov
  • Copy movies to the root directory of USB memory
  • Build and upload this program
  • Run it

USBHost/USBHost/USBHALHost_LPC17.cpp@0:d0f130e27d32, 2017-03-10 (annotated)

Committer:
mtkrtk
Date:
Fri Mar 10 11:30:02 2017 +0000
Revision:
0:d0f130e27d32
initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mtkrtk 0:d0f130e27d32 1 /* mbed USBHost Library
mtkrtk 0:d0f130e27d32 2 * Copyright (c) 2006-2013 ARM Limited
mtkrtk 0:d0f130e27d32 3 *
mtkrtk 0:d0f130e27d32 4 * Licensed under the Apache License, Version 2.0 (the "License");
mtkrtk 0:d0f130e27d32 5 * you may not use this file except in compliance with the License.
mtkrtk 0:d0f130e27d32 6 * You may obtain a copy of the License at
mtkrtk 0:d0f130e27d32 7 *
mtkrtk 0:d0f130e27d32 8 * http://www.apache.org/licenses/LICENSE-2.0
mtkrtk 0:d0f130e27d32 9 *
mtkrtk 0:d0f130e27d32 10 * Unless required by applicable law or agreed to in writing, software
mtkrtk 0:d0f130e27d32 11 * distributed under the License is distributed on an "AS IS" BASIS,
mtkrtk 0:d0f130e27d32 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mtkrtk 0:d0f130e27d32 13 * See the License for the specific language governing permissions and
mtkrtk 0:d0f130e27d32 14 * limitations under the License.
mtkrtk 0:d0f130e27d32 15 */
mtkrtk 0:d0f130e27d32 16
mtkrtk 0:d0f130e27d32 17 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2460)
mtkrtk 0:d0f130e27d32 18
mtkrtk 0:d0f130e27d32 19 #include "mbed.h"
mtkrtk 0:d0f130e27d32 20 #include "USBHALHost.h"
mtkrtk 0:d0f130e27d32 21 #include "dbg.h"
mtkrtk 0:d0f130e27d32 22
mtkrtk 0:d0f130e27d32 23 // bits of the USB/OTG clock control register
mtkrtk 0:d0f130e27d32 24 #define HOST_CLK_EN (1<<0)
mtkrtk 0:d0f130e27d32 25 #define DEV_CLK_EN (1<<1)
mtkrtk 0:d0f130e27d32 26 #define PORTSEL_CLK_EN (1<<3)
mtkrtk 0:d0f130e27d32 27 #define AHB_CLK_EN (1<<4)
mtkrtk 0:d0f130e27d32 28
mtkrtk 0:d0f130e27d32 29 // bits of the USB/OTG clock status register
mtkrtk 0:d0f130e27d32 30 #define HOST_CLK_ON (1<<0)
mtkrtk 0:d0f130e27d32 31 #define DEV_CLK_ON (1<<1)
mtkrtk 0:d0f130e27d32 32 #define PORTSEL_CLK_ON (1<<3)
mtkrtk 0:d0f130e27d32 33 #define AHB_CLK_ON (1<<4)
mtkrtk 0:d0f130e27d32 34
mtkrtk 0:d0f130e27d32 35 // we need host clock, OTG/portsel clock and AHB clock
mtkrtk 0:d0f130e27d32 36 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
mtkrtk 0:d0f130e27d32 37
mtkrtk 0:d0f130e27d32 38 #define HCCA_SIZE sizeof(HCCA)
mtkrtk 0:d0f130e27d32 39 #define ED_SIZE sizeof(HCED)
mtkrtk 0:d0f130e27d32 40 #define TD_SIZE sizeof(HCTD)
mtkrtk 0:d0f130e27d32 41
mtkrtk 0:d0f130e27d32 42 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
mtkrtk 0:d0f130e27d32 43
mtkrtk 0:d0f130e27d32 44 static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
mtkrtk 0:d0f130e27d32 45
mtkrtk 0:d0f130e27d32 46 USBHALHost * USBHALHost::instHost;
mtkrtk 0:d0f130e27d32 47
mtkrtk 0:d0f130e27d32 48 USBHALHost::USBHALHost() {
mtkrtk 0:d0f130e27d32 49 instHost = this;
mtkrtk 0:d0f130e27d32 50 memInit();
mtkrtk 0:d0f130e27d32 51 memset((void*)usb_hcca, 0, HCCA_SIZE);
mtkrtk 0:d0f130e27d32 52 for (int i = 0; i < MAX_ENDPOINT; i++) {
mtkrtk 0:d0f130e27d32 53 edBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 54 }
mtkrtk 0:d0f130e27d32 55 for (int i = 0; i < MAX_TD; i++) {
mtkrtk 0:d0f130e27d32 56 tdBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 57 }
mtkrtk 0:d0f130e27d32 58 }
mtkrtk 0:d0f130e27d32 59
mtkrtk 0:d0f130e27d32 60 void USBHALHost::init() {
mtkrtk 0:d0f130e27d32 61 NVIC_DisableIRQ(USB_IRQn);
mtkrtk 0:d0f130e27d32 62
mtkrtk 0:d0f130e27d32 63 //Cut power
mtkrtk 0:d0f130e27d32 64 LPC_SC->PCONP &= ~(1UL<<31);
mtkrtk 0:d0f130e27d32 65 wait_ms(100);
mtkrtk 0:d0f130e27d32 66
mtkrtk 0:d0f130e27d32 67 // turn on power for USB
mtkrtk 0:d0f130e27d32 68 LPC_SC->PCONP |= (1UL<<31);
mtkrtk 0:d0f130e27d32 69
mtkrtk 0:d0f130e27d32 70 // Enable USB host clock, port selection and AHB clock
mtkrtk 0:d0f130e27d32 71 LPC_USB->USBClkCtrl |= CLOCK_MASK;
mtkrtk 0:d0f130e27d32 72
mtkrtk 0:d0f130e27d32 73 // Wait for clocks to become available
mtkrtk 0:d0f130e27d32 74 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
mtkrtk 0:d0f130e27d32 75
mtkrtk 0:d0f130e27d32 76 // it seems the bits[0:1] mean the following
mtkrtk 0:d0f130e27d32 77 // 0: U1=device, U2=host
mtkrtk 0:d0f130e27d32 78 // 1: U1=host, U2=host
mtkrtk 0:d0f130e27d32 79 // 2: reserved
mtkrtk 0:d0f130e27d32 80 // 3: U1=host, U2=device
mtkrtk 0:d0f130e27d32 81 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
mtkrtk 0:d0f130e27d32 82 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
mtkrtk 0:d0f130e27d32 83 LPC_USB->OTGStCtrl |= 1;
mtkrtk 0:d0f130e27d32 84
mtkrtk 0:d0f130e27d32 85 // now that we've configured the ports, we can turn off the portsel clock
mtkrtk 0:d0f130e27d32 86 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
mtkrtk 0:d0f130e27d32 87
mtkrtk 0:d0f130e27d32 88 // configure USB D+/D- pins
mtkrtk 0:d0f130e27d32 89 // P0[29] = USB_D+, 01
mtkrtk 0:d0f130e27d32 90 // P0[30] = USB_D-, 01
mtkrtk 0:d0f130e27d32 91 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
mtkrtk 0:d0f130e27d32 92 LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
mtkrtk 0:d0f130e27d32 93
mtkrtk 0:d0f130e27d32 94 LPC_USB->HcControl = 0; // HARDWARE RESET
mtkrtk 0:d0f130e27d32 95 LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
mtkrtk 0:d0f130e27d32 96 LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
mtkrtk 0:d0f130e27d32 97
mtkrtk 0:d0f130e27d32 98 // Wait 100 ms before apply reset
mtkrtk 0:d0f130e27d32 99 wait_ms(100);
mtkrtk 0:d0f130e27d32 100
mtkrtk 0:d0f130e27d32 101 // software reset
mtkrtk 0:d0f130e27d32 102 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
mtkrtk 0:d0f130e27d32 103
mtkrtk 0:d0f130e27d32 104 // Write Fm Interval and Largest Data Packet Counter
mtkrtk 0:d0f130e27d32 105 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
mtkrtk 0:d0f130e27d32 106 LPC_USB->HcPeriodicStart = FI * 90 / 100;
mtkrtk 0:d0f130e27d32 107
mtkrtk 0:d0f130e27d32 108 // Put HC in operational state
mtkrtk 0:d0f130e27d32 109 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
mtkrtk 0:d0f130e27d32 110 // Set Global Power
mtkrtk 0:d0f130e27d32 111 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
mtkrtk 0:d0f130e27d32 112
mtkrtk 0:d0f130e27d32 113 LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
mtkrtk 0:d0f130e27d32 114
mtkrtk 0:d0f130e27d32 115 // Clear Interrrupt Status
mtkrtk 0:d0f130e27d32 116 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
mtkrtk 0:d0f130e27d32 117
mtkrtk 0:d0f130e27d32 118 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
mtkrtk 0:d0f130e27d32 119
mtkrtk 0:d0f130e27d32 120 // Enable the USB Interrupt
mtkrtk 0:d0f130e27d32 121 NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
mtkrtk 0:d0f130e27d32 122 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
mtkrtk 0:d0f130e27d32 123 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
mtkrtk 0:d0f130e27d32 124
mtkrtk 0:d0f130e27d32 125 NVIC_EnableIRQ(USB_IRQn);
mtkrtk 0:d0f130e27d32 126
mtkrtk 0:d0f130e27d32 127 // Check for any connected devices
mtkrtk 0:d0f130e27d32 128 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
mtkrtk 0:d0f130e27d32 129 //Device connected
mtkrtk 0:d0f130e27d32 130 wait_ms(150);
mtkrtk 0:d0f130e27d32 131 USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
mtkrtk 0:d0f130e27d32 132 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
mtkrtk 0:d0f130e27d32 133 }
mtkrtk 0:d0f130e27d32 134 }
mtkrtk 0:d0f130e27d32 135
mtkrtk 0:d0f130e27d32 136 uint32_t USBHALHost::controlHeadED() {
mtkrtk 0:d0f130e27d32 137 return LPC_USB->HcControlHeadED;
mtkrtk 0:d0f130e27d32 138 }
mtkrtk 0:d0f130e27d32 139
mtkrtk 0:d0f130e27d32 140 uint32_t USBHALHost::bulkHeadED() {
mtkrtk 0:d0f130e27d32 141 return LPC_USB->HcBulkHeadED;
mtkrtk 0:d0f130e27d32 142 }
mtkrtk 0:d0f130e27d32 143
mtkrtk 0:d0f130e27d32 144 uint32_t USBHALHost::interruptHeadED() {
mtkrtk 0:d0f130e27d32 145 return usb_hcca->IntTable[0];
mtkrtk 0:d0f130e27d32 146 }
mtkrtk 0:d0f130e27d32 147
mtkrtk 0:d0f130e27d32 148 void USBHALHost::updateBulkHeadED(uint32_t addr) {
mtkrtk 0:d0f130e27d32 149 LPC_USB->HcBulkHeadED = addr;
mtkrtk 0:d0f130e27d32 150 }
mtkrtk 0:d0f130e27d32 151
mtkrtk 0:d0f130e27d32 152
mtkrtk 0:d0f130e27d32 153 void USBHALHost::updateControlHeadED(uint32_t addr) {
mtkrtk 0:d0f130e27d32 154 LPC_USB->HcControlHeadED = addr;
mtkrtk 0:d0f130e27d32 155 }
mtkrtk 0:d0f130e27d32 156
mtkrtk 0:d0f130e27d32 157 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
mtkrtk 0:d0f130e27d32 158 usb_hcca->IntTable[0] = addr;
mtkrtk 0:d0f130e27d32 159 }
mtkrtk 0:d0f130e27d32 160
mtkrtk 0:d0f130e27d32 161
mtkrtk 0:d0f130e27d32 162 void USBHALHost::enableList(ENDPOINT_TYPE type) {
mtkrtk 0:d0f130e27d32 163 switch(type) {
mtkrtk 0:d0f130e27d32 164 case CONTROL_ENDPOINT:
mtkrtk 0:d0f130e27d32 165 LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
mtkrtk 0:d0f130e27d32 166 LPC_USB->HcControl |= OR_CONTROL_CLE;
mtkrtk 0:d0f130e27d32 167 break;
mtkrtk 0:d0f130e27d32 168 case ISOCHRONOUS_ENDPOINT:
mtkrtk 0:d0f130e27d32 169 break;
mtkrtk 0:d0f130e27d32 170 case BULK_ENDPOINT:
mtkrtk 0:d0f130e27d32 171 LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
mtkrtk 0:d0f130e27d32 172 LPC_USB->HcControl |= OR_CONTROL_BLE;
mtkrtk 0:d0f130e27d32 173 break;
mtkrtk 0:d0f130e27d32 174 case INTERRUPT_ENDPOINT:
mtkrtk 0:d0f130e27d32 175 LPC_USB->HcControl |= OR_CONTROL_PLE;
mtkrtk 0:d0f130e27d32 176 break;
mtkrtk 0:d0f130e27d32 177 }
mtkrtk 0:d0f130e27d32 178 }
mtkrtk 0:d0f130e27d32 179
mtkrtk 0:d0f130e27d32 180
mtkrtk 0:d0f130e27d32 181 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
mtkrtk 0:d0f130e27d32 182 switch(type) {
mtkrtk 0:d0f130e27d32 183 case CONTROL_ENDPOINT:
mtkrtk 0:d0f130e27d32 184 if(LPC_USB->HcControl & OR_CONTROL_CLE) {
mtkrtk 0:d0f130e27d32 185 LPC_USB->HcControl &= ~OR_CONTROL_CLE;
mtkrtk 0:d0f130e27d32 186 return true;
mtkrtk 0:d0f130e27d32 187 }
mtkrtk 0:d0f130e27d32 188 return false;
mtkrtk 0:d0f130e27d32 189 case ISOCHRONOUS_ENDPOINT:
mtkrtk 0:d0f130e27d32 190 return false;
mtkrtk 0:d0f130e27d32 191 case BULK_ENDPOINT:
mtkrtk 0:d0f130e27d32 192 if(LPC_USB->HcControl & OR_CONTROL_BLE){
mtkrtk 0:d0f130e27d32 193 LPC_USB->HcControl &= ~OR_CONTROL_BLE;
mtkrtk 0:d0f130e27d32 194 return true;
mtkrtk 0:d0f130e27d32 195 }
mtkrtk 0:d0f130e27d32 196 return false;
mtkrtk 0:d0f130e27d32 197 case INTERRUPT_ENDPOINT:
mtkrtk 0:d0f130e27d32 198 if(LPC_USB->HcControl & OR_CONTROL_PLE) {
mtkrtk 0:d0f130e27d32 199 LPC_USB->HcControl &= ~OR_CONTROL_PLE;
mtkrtk 0:d0f130e27d32 200 return true;
mtkrtk 0:d0f130e27d32 201 }
mtkrtk 0:d0f130e27d32 202 return false;
mtkrtk 0:d0f130e27d32 203 }
mtkrtk 0:d0f130e27d32 204 return false;
mtkrtk 0:d0f130e27d32 205 }
mtkrtk 0:d0f130e27d32 206
mtkrtk 0:d0f130e27d32 207
mtkrtk 0:d0f130e27d32 208 void USBHALHost::memInit() {
mtkrtk 0:d0f130e27d32 209 usb_hcca = (volatile HCCA *)usb_buf;
mtkrtk 0:d0f130e27d32 210 usb_edBuf = usb_buf + HCCA_SIZE;
mtkrtk 0:d0f130e27d32 211 usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
mtkrtk 0:d0f130e27d32 212 }
mtkrtk 0:d0f130e27d32 213
mtkrtk 0:d0f130e27d32 214 volatile uint8_t * USBHALHost::getED() {
mtkrtk 0:d0f130e27d32 215 for (int i = 0; i < MAX_ENDPOINT; i++) {
mtkrtk 0:d0f130e27d32 216 if ( !edBufAlloc[i] ) {
mtkrtk 0:d0f130e27d32 217 edBufAlloc[i] = true;
mtkrtk 0:d0f130e27d32 218 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
mtkrtk 0:d0f130e27d32 219 }
mtkrtk 0:d0f130e27d32 220 }
mtkrtk 0:d0f130e27d32 221 perror("Could not allocate ED\r\n");
mtkrtk 0:d0f130e27d32 222 return NULL; //Could not alloc ED
mtkrtk 0:d0f130e27d32 223 }
mtkrtk 0:d0f130e27d32 224
mtkrtk 0:d0f130e27d32 225 volatile uint8_t * USBHALHost::getTD() {
mtkrtk 0:d0f130e27d32 226 int i;
mtkrtk 0:d0f130e27d32 227 for (i = 0; i < MAX_TD; i++) {
mtkrtk 0:d0f130e27d32 228 if ( !tdBufAlloc[i] ) {
mtkrtk 0:d0f130e27d32 229 tdBufAlloc[i] = true;
mtkrtk 0:d0f130e27d32 230 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
mtkrtk 0:d0f130e27d32 231 }
mtkrtk 0:d0f130e27d32 232 }
mtkrtk 0:d0f130e27d32 233 perror("Could not allocate TD\r\n");
mtkrtk 0:d0f130e27d32 234 return NULL; //Could not alloc TD
mtkrtk 0:d0f130e27d32 235 }
mtkrtk 0:d0f130e27d32 236
mtkrtk 0:d0f130e27d32 237
mtkrtk 0:d0f130e27d32 238 void USBHALHost::freeED(volatile uint8_t * ed) {
mtkrtk 0:d0f130e27d32 239 int i;
mtkrtk 0:d0f130e27d32 240 i = (ed - usb_edBuf) / ED_SIZE;
mtkrtk 0:d0f130e27d32 241 edBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 242 }
mtkrtk 0:d0f130e27d32 243
mtkrtk 0:d0f130e27d32 244 void USBHALHost::freeTD(volatile uint8_t * td) {
mtkrtk 0:d0f130e27d32 245 int i;
mtkrtk 0:d0f130e27d32 246 i = (td - usb_tdBuf) / TD_SIZE;
mtkrtk 0:d0f130e27d32 247 tdBufAlloc[i] = false;
mtkrtk 0:d0f130e27d32 248 }
mtkrtk 0:d0f130e27d32 249
mtkrtk 0:d0f130e27d32 250
mtkrtk 0:d0f130e27d32 251 void USBHALHost::resetRootHub() {
mtkrtk 0:d0f130e27d32 252 // Initiate port reset
mtkrtk 0:d0f130e27d32 253 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
mtkrtk 0:d0f130e27d32 254
mtkrtk 0:d0f130e27d32 255 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
mtkrtk 0:d0f130e27d32 256
mtkrtk 0:d0f130e27d32 257 // ...and clear port reset signal
mtkrtk 0:d0f130e27d32 258 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
mtkrtk 0:d0f130e27d32 259 }
mtkrtk 0:d0f130e27d32 260
mtkrtk 0:d0f130e27d32 261
mtkrtk 0:d0f130e27d32 262 void USBHALHost::_usbisr(void) {
mtkrtk 0:d0f130e27d32 263 if (instHost) {
mtkrtk 0:d0f130e27d32 264 instHost->UsbIrqhandler();
mtkrtk 0:d0f130e27d32 265 }
mtkrtk 0:d0f130e27d32 266 }
mtkrtk 0:d0f130e27d32 267
mtkrtk 0:d0f130e27d32 268 void USBHALHost::UsbIrqhandler() {
mtkrtk 0:d0f130e27d32 269 if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
mtkrtk 0:d0f130e27d32 270 {
mtkrtk 0:d0f130e27d32 271
mtkrtk 0:d0f130e27d32 272 uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
mtkrtk 0:d0f130e27d32 273
mtkrtk 0:d0f130e27d32 274 // Root hub status change interrupt
mtkrtk 0:d0f130e27d32 275 if (int_status & OR_INTR_STATUS_RHSC) {
mtkrtk 0:d0f130e27d32 276 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
mtkrtk 0:d0f130e27d32 277 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
mtkrtk 0:d0f130e27d32 278 // When DRWE is on, Connect Status Change
mtkrtk 0:d0f130e27d32 279 // means a remote wakeup event.
mtkrtk 0:d0f130e27d32 280 } else {
mtkrtk 0:d0f130e27d32 281
mtkrtk 0:d0f130e27d32 282 //Root device connected
mtkrtk 0:d0f130e27d32 283 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
mtkrtk 0:d0f130e27d32 284
mtkrtk 0:d0f130e27d32 285 // wait 150ms to avoid bounce
mtkrtk 0:d0f130e27d32 286 wait_ms(150);
mtkrtk 0:d0f130e27d32 287
mtkrtk 0:d0f130e27d32 288 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
mtkrtk 0:d0f130e27d32 289 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
mtkrtk 0:d0f130e27d32 290 }
mtkrtk 0:d0f130e27d32 291
mtkrtk 0:d0f130e27d32 292 //Root device disconnected
mtkrtk 0:d0f130e27d32 293 else {
mtkrtk 0:d0f130e27d32 294
mtkrtk 0:d0f130e27d32 295 if (!(int_status & OR_INTR_STATUS_WDH)) {
mtkrtk 0:d0f130e27d32 296 usb_hcca->DoneHead = 0;
mtkrtk 0:d0f130e27d32 297 }
mtkrtk 0:d0f130e27d32 298
mtkrtk 0:d0f130e27d32 299 // wait 200ms to avoid bounce
mtkrtk 0:d0f130e27d32 300 wait_ms(200);
mtkrtk 0:d0f130e27d32 301
mtkrtk 0:d0f130e27d32 302 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
mtkrtk 0:d0f130e27d32 303
mtkrtk 0:d0f130e27d32 304 if (int_status & OR_INTR_STATUS_WDH) {
mtkrtk 0:d0f130e27d32 305 usb_hcca->DoneHead = 0;
mtkrtk 0:d0f130e27d32 306 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
mtkrtk 0:d0f130e27d32 307 }
mtkrtk 0:d0f130e27d32 308 }
mtkrtk 0:d0f130e27d32 309 }
mtkrtk 0:d0f130e27d32 310 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
mtkrtk 0:d0f130e27d32 311 }
mtkrtk 0:d0f130e27d32 312 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
mtkrtk 0:d0f130e27d32 313 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
mtkrtk 0:d0f130e27d32 314 }
mtkrtk 0:d0f130e27d32 315 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
mtkrtk 0:d0f130e27d32 316 }
mtkrtk 0:d0f130e27d32 317
mtkrtk 0:d0f130e27d32 318 // Writeback Done Head interrupt
mtkrtk 0:d0f130e27d32 319 if (int_status & OR_INTR_STATUS_WDH) {
mtkrtk 0:d0f130e27d32 320 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
mtkrtk 0:d0f130e27d32 321 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
mtkrtk 0:d0f130e27d32 322 }
mtkrtk 0:d0f130e27d32 323 }
mtkrtk 0:d0f130e27d32 324 }
mtkrtk 0:d0f130e27d32 325 #endif
mtkrtk 0:d0f130e27d32 326