Marcell Rausch / RF24

original

Fork of RF24 by Akash Vibhute

RF24.cpp@10:71acc66e27f8, 2016-10-17 (annotated)

Committer:
mrcrsch
Date:
Mon Oct 17 09:02:10 2016 +0000
Revision:
10:71acc66e27f8
Parent:
8:b70b1d82f1d7 
com

Who changed what in which revision?

UserRevisionLine numberNew contents of line
akashvibhute 0:bb74812ac6bb 1 /*
akashvibhute 0:bb74812ac6bb 2 Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
akashvibhute 0:bb74812ac6bb 3
akashvibhute 0:bb74812ac6bb 4 This program is free software; you can redistribute it and/or
akashvibhute 0:bb74812ac6bb 5 modify it under the terms of the GNU General Public License
akashvibhute 0:bb74812ac6bb 6 version 2 as published by the Free Software Foundation.
akashvibhute 0:bb74812ac6bb 7 */
akashvibhute 6:5cc7136648d1 8
akashvibhute 3:e94be00fd19e 9 /*
akashvibhute 3:e94be00fd19e 10 * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
akashvibhute 3:e94be00fd19e 11 * Porting completed on Nov/05/2015
akashvibhute 3:e94be00fd19e 12 *
akashvibhute 6:5cc7136648d1 13 * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
akashvibhute 6:5cc7136648d1 14 * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
akashvibhute 3:e94be00fd19e 15 *
akashvibhute 3:e94be00fd19e 16 */
akashvibhute 6:5cc7136648d1 17
akashvibhute 2:3bdf0d9bb71f 18 #include "nRF24L01.h"
akashvibhute 2:3bdf0d9bb71f 19 #include "RF24_config.h"
akashvibhute 0:bb74812ac6bb 20 #include "RF24.h"
akashvibhute 0:bb74812ac6bb 21
akashvibhute 0:bb74812ac6bb 22 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 23
akashvibhute 2:3bdf0d9bb71f 24 void RF24::csn(bool mode)
akashvibhute 0:bb74812ac6bb 25 {
akashvibhute 6:5cc7136648d1 26
akashvibhute 6:5cc7136648d1 27 csn_pin = mode;
akashvibhute 6:5cc7136648d1 28
akashvibhute 6:5cc7136648d1 29
akashvibhute 6:5cc7136648d1 30
akashvibhute 6:5cc7136648d1 31
akashvibhute 6:5cc7136648d1 32
akashvibhute 6:5cc7136648d1 33
akashvibhute 6:5cc7136648d1 34
akashvibhute 6:5cc7136648d1 35
akashvibhute 6:5cc7136648d1 36
akashvibhute 6:5cc7136648d1 37
akashvibhute 6:5cc7136648d1 38
akashvibhute 6:5cc7136648d1 39
akashvibhute 6:5cc7136648d1 40
akashvibhute 6:5cc7136648d1 41
akashvibhute 6:5cc7136648d1 42
akashvibhute 6:5cc7136648d1 43
akashvibhute 6:5cc7136648d1 44
akashvibhute 6:5cc7136648d1 45
akashvibhute 6:5cc7136648d1 46
akashvibhute 6:5cc7136648d1 47
akashvibhute 6:5cc7136648d1 48
akashvibhute 6:5cc7136648d1 49
akashvibhute 6:5cc7136648d1 50
akashvibhute 6:5cc7136648d1 51
akashvibhute 6:5cc7136648d1 52
akashvibhute 6:5cc7136648d1 53
akashvibhute 6:5cc7136648d1 54
akashvibhute 6:5cc7136648d1 55
akashvibhute 6:5cc7136648d1 56
akashvibhute 6:5cc7136648d1 57
akashvibhute 6:5cc7136648d1 58
akashvibhute 6:5cc7136648d1 59
akashvibhute 6:5cc7136648d1 60
akashvibhute 6:5cc7136648d1 61
akashvibhute 6:5cc7136648d1 62
akashvibhute 6:5cc7136648d1 63
akashvibhute 6:5cc7136648d1 64
akashvibhute 0:bb74812ac6bb 65 }
akashvibhute 0:bb74812ac6bb 66
akashvibhute 0:bb74812ac6bb 67 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 68
akashvibhute 2:3bdf0d9bb71f 69 void RF24::ce(bool level)
akashvibhute 0:bb74812ac6bb 70 {
akashvibhute 6:5cc7136648d1 71 ce_pin = level;
akashvibhute 6:5cc7136648d1 72
akashvibhute 0:bb74812ac6bb 73 }
akashvibhute 0:bb74812ac6bb 74
akashvibhute 0:bb74812ac6bb 75 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 76
akashvibhute 6:5cc7136648d1 77 inline void RF24::beginTransaction() {
akashvibhute 6:5cc7136648d1 78
akashvibhute 6:5cc7136648d1 79
akashvibhute 6:5cc7136648d1 80 csn(LOW);
akashvibhute 6:5cc7136648d1 81 }
akashvibhute 2:3bdf0d9bb71f 82
akashvibhute 2:3bdf0d9bb71f 83 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 84
akashvibhute 6:5cc7136648d1 85 inline void RF24::endTransaction() {
akashvibhute 6:5cc7136648d1 86 csn(HIGH);
akashvibhute 6:5cc7136648d1 87
akashvibhute 6:5cc7136648d1 88
akashvibhute 6:5cc7136648d1 89
akashvibhute 6:5cc7136648d1 90 }
akashvibhute 2:3bdf0d9bb71f 91
akashvibhute 2:3bdf0d9bb71f 92 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 93
akashvibhute 0:bb74812ac6bb 94 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
akashvibhute 0:bb74812ac6bb 95 {
akashvibhute 6:5cc7136648d1 96 uint8_t status;
akashvibhute 0:bb74812ac6bb 97
akashvibhute 6:5cc7136648d1 98
akashvibhute 6:5cc7136648d1 99
akashvibhute 6:5cc7136648d1 100
akashvibhute 6:5cc7136648d1 101
akashvibhute 6:5cc7136648d1 102
akashvibhute 6:5cc7136648d1 103
akashvibhute 6:5cc7136648d1 104
akashvibhute 6:5cc7136648d1 105
akashvibhute 6:5cc7136648d1 106
akashvibhute 6:5cc7136648d1 107
akashvibhute 6:5cc7136648d1 108
akashvibhute 6:5cc7136648d1 109
akashvibhute 6:5cc7136648d1 110
akashvibhute 6:5cc7136648d1 111
akashvibhute 6:5cc7136648d1 112
akashvibhute 6:5cc7136648d1 113
akashvibhute 6:5cc7136648d1 114
akashvibhute 6:5cc7136648d1 115
akashvibhute 6:5cc7136648d1 116
akashvibhute 6:5cc7136648d1 117
akashvibhute 3:e94be00fd19e 118
akashvibhute 6:5cc7136648d1 119 beginTransaction();
akashvibhute 6:5cc7136648d1 120 status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
akashvibhute 6:5cc7136648d1 121 while ( len-- ){
akashvibhute 6:5cc7136648d1 122 *buf++ = spi.write(0xff);
akashvibhute 6:5cc7136648d1 123 }
akashvibhute 6:5cc7136648d1 124 endTransaction();
akashvibhute 6:5cc7136648d1 125
akashvibhute 6:5cc7136648d1 126
akashvibhute 6:5cc7136648d1 127
akashvibhute 6:5cc7136648d1 128 return status;
akashvibhute 0:bb74812ac6bb 129 }
akashvibhute 0:bb74812ac6bb 130
akashvibhute 0:bb74812ac6bb 131 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 132
akashvibhute 0:bb74812ac6bb 133 uint8_t RF24::read_register(uint8_t reg)
akashvibhute 0:bb74812ac6bb 134 {
akashvibhute 6:5cc7136648d1 135 uint8_t result;
akashvibhute 6:5cc7136648d1 136
akashvibhute 6:5cc7136648d1 137
akashvibhute 6:5cc7136648d1 138
akashvibhute 6:5cc7136648d1 139
akashvibhute 6:5cc7136648d1 140
akashvibhute 6:5cc7136648d1 141
akashvibhute 6:5cc7136648d1 142
akashvibhute 6:5cc7136648d1 143
akashvibhute 6:5cc7136648d1 144
akashvibhute 6:5cc7136648d1 145
akashvibhute 6:5cc7136648d1 146
akashvibhute 6:5cc7136648d1 147
akashvibhute 6:5cc7136648d1 148
akashvibhute 6:5cc7136648d1 149
akashvibhute 6:5cc7136648d1 150
akashvibhute 0:bb74812ac6bb 151
akashvibhute 6:5cc7136648d1 152 beginTransaction();
akashvibhute 6:5cc7136648d1 153 spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
akashvibhute 6:5cc7136648d1 154 result = spi.write(0xff);
akashvibhute 6:5cc7136648d1 155 endTransaction();
akashvibhute 3:e94be00fd19e 156
akashvibhute 6:5cc7136648d1 157
akashvibhute 6:5cc7136648d1 158
akashvibhute 6:5cc7136648d1 159 return result;
akashvibhute 0:bb74812ac6bb 160 }
akashvibhute 0:bb74812ac6bb 161
akashvibhute 0:bb74812ac6bb 162 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 163
akashvibhute 0:bb74812ac6bb 164 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
akashvibhute 0:bb74812ac6bb 165 {
akashvibhute 6:5cc7136648d1 166 uint8_t status;
akashvibhute 0:bb74812ac6bb 167
akashvibhute 6:5cc7136648d1 168
akashvibhute 6:5cc7136648d1 169
akashvibhute 6:5cc7136648d1 170
akashvibhute 6:5cc7136648d1 171
akashvibhute 6:5cc7136648d1 172
akashvibhute 6:5cc7136648d1 173
akashvibhute 6:5cc7136648d1 174
akashvibhute 6:5cc7136648d1 175
akashvibhute 6:5cc7136648d1 176
akashvibhute 6:5cc7136648d1 177
akashvibhute 6:5cc7136648d1 178
akashvibhute 6:5cc7136648d1 179
akashvibhute 6:5cc7136648d1 180
akashvibhute 6:5cc7136648d1 181
akashvibhute 3:e94be00fd19e 182
akashvibhute 6:5cc7136648d1 183 beginTransaction();
akashvibhute 6:5cc7136648d1 184 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
akashvibhute 6:5cc7136648d1 185 while ( len-- )
akashvibhute 6:5cc7136648d1 186 spi.write(*buf++);
akashvibhute 6:5cc7136648d1 187 endTransaction();
akashvibhute 6:5cc7136648d1 188
akashvibhute 6:5cc7136648d1 189
akashvibhute 6:5cc7136648d1 190
akashvibhute 6:5cc7136648d1 191 return status;
akashvibhute 0:bb74812ac6bb 192 }
akashvibhute 0:bb74812ac6bb 193
akashvibhute 0:bb74812ac6bb 194 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 195
akashvibhute 0:bb74812ac6bb 196 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
akashvibhute 0:bb74812ac6bb 197 {
akashvibhute 6:5cc7136648d1 198 uint8_t status;
akashvibhute 2:3bdf0d9bb71f 199
akashvibhute 6:5cc7136648d1 200 IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
akashvibhute 2:3bdf0d9bb71f 201
akashvibhute 6:5cc7136648d1 202
akashvibhute 6:5cc7136648d1 203
akashvibhute 6:5cc7136648d1 204
akashvibhute 6:5cc7136648d1 205
akashvibhute 6:5cc7136648d1 206
akashvibhute 6:5cc7136648d1 207
akashvibhute 6:5cc7136648d1 208
akashvibhute 6:5cc7136648d1 209
akashvibhute 6:5cc7136648d1 210
akashvibhute 6:5cc7136648d1 211
akashvibhute 6:5cc7136648d1 212
akashvibhute 3:e94be00fd19e 213
akashvibhute 6:5cc7136648d1 214 beginTransaction();
akashvibhute 6:5cc7136648d1 215 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
akashvibhute 6:5cc7136648d1 216 spi.write(value);
akashvibhute 6:5cc7136648d1 217 endTransaction();
akashvibhute 6:5cc7136648d1 218
akashvibhute 6:5cc7136648d1 219
akashvibhute 6:5cc7136648d1 220
akashvibhute 6:5cc7136648d1 221 return status;
akashvibhute 2:3bdf0d9bb71f 222 }
akashvibhute 2:3bdf0d9bb71f 223
akashvibhute 2:3bdf0d9bb71f 224 /****************************************************************************/
akashvibhute 6:5cc7136648d1 225
akashvibhute 6:5cc7136648d1 226 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
akashvibhute 2:3bdf0d9bb71f 227 {
akashvibhute 6:5cc7136648d1 228 uint8_t status;
akashvibhute 6:5cc7136648d1 229 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
akashvibhute 2:3bdf0d9bb71f 230
akashvibhute 6:5cc7136648d1 231 data_len = rf24_min(data_len, payload_size);
akashvibhute 6:5cc7136648d1 232 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
akashvibhute 6:5cc7136648d1 233
akashvibhute 6:5cc7136648d1 234 //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
akashvibhute 6:5cc7136648d1 235 IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
akashvibhute 6:5cc7136648d1 236
akashvibhute 6:5cc7136648d1 237
akashvibhute 6:5cc7136648d1 238
akashvibhute 6:5cc7136648d1 239
akashvibhute 6:5cc7136648d1 240
akashvibhute 6:5cc7136648d1 241
akashvibhute 6:5cc7136648d1 242
akashvibhute 6:5cc7136648d1 243
akashvibhute 6:5cc7136648d1 244
akashvibhute 6:5cc7136648d1 245
akashvibhute 6:5cc7136648d1 246
akashvibhute 6:5cc7136648d1 247
akashvibhute 6:5cc7136648d1 248
akashvibhute 6:5cc7136648d1 249
akashvibhute 6:5cc7136648d1 250
akashvibhute 6:5cc7136648d1 251
akashvibhute 6:5cc7136648d1 252
akashvibhute 6:5cc7136648d1 253
akashvibhute 6:5cc7136648d1 254
akashvibhute 3:e94be00fd19e 255
akashvibhute 6:5cc7136648d1 256 beginTransaction();
akashvibhute 6:5cc7136648d1 257 status = spi.write( writeType );
akashvibhute 6:5cc7136648d1 258 while ( data_len-- ) {
akashvibhute 6:5cc7136648d1 259 spi.write(*current++);
akashvibhute 6:5cc7136648d1 260 }
akashvibhute 6:5cc7136648d1 261 while ( blank_len-- ) {
akashvibhute 6:5cc7136648d1 262 spi.write(0);
akashvibhute 6:5cc7136648d1 263 }
akashvibhute 6:5cc7136648d1 264 endTransaction();
akashvibhute 3:e94be00fd19e 265
akashvibhute 6:5cc7136648d1 266
akashvibhute 6:5cc7136648d1 267
akashvibhute 6:5cc7136648d1 268 return status;
akashvibhute 0:bb74812ac6bb 269 }
akashvibhute 0:bb74812ac6bb 270
akashvibhute 0:bb74812ac6bb 271 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 272
akashvibhute 2:3bdf0d9bb71f 273 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
akashvibhute 0:bb74812ac6bb 274 {
akashvibhute 6:5cc7136648d1 275 uint8_t status;
akashvibhute 6:5cc7136648d1 276 uint8_t* current = reinterpret_cast<uint8_t*>(buf);
akashvibhute 2:3bdf0d9bb71f 277
akashvibhute 6:5cc7136648d1 278 if(data_len > payload_size) data_len = payload_size;
akashvibhute 6:5cc7136648d1 279 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
akashvibhute 6:5cc7136648d1 280
akashvibhute 6:5cc7136648d1 281 //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
akashvibhute 0:bb74812ac6bb 282
akashvibhute 6:5cc7136648d1 283 IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
akashvibhute 6:5cc7136648d1 284
akashvibhute 6:5cc7136648d1 285
akashvibhute 6:5cc7136648d1 286
akashvibhute 6:5cc7136648d1 287
akashvibhute 6:5cc7136648d1 288
akashvibhute 6:5cc7136648d1 289
akashvibhute 6:5cc7136648d1 290
akashvibhute 6:5cc7136648d1 291
akashvibhute 6:5cc7136648d1 292
akashvibhute 6:5cc7136648d1 293
akashvibhute 6:5cc7136648d1 294
akashvibhute 6:5cc7136648d1 295
akashvibhute 6:5cc7136648d1 296
akashvibhute 6:5cc7136648d1 297
akashvibhute 6:5cc7136648d1 298
akashvibhute 6:5cc7136648d1 299
akashvibhute 6:5cc7136648d1 300
akashvibhute 6:5cc7136648d1 301
akashvibhute 6:5cc7136648d1 302
akashvibhute 6:5cc7136648d1 303
akashvibhute 6:5cc7136648d1 304
akashvibhute 6:5cc7136648d1 305
akashvibhute 6:5cc7136648d1 306
akashvibhute 6:5cc7136648d1 307
akashvibhute 6:5cc7136648d1 308
akashvibhute 6:5cc7136648d1 309
akashvibhute 3:e94be00fd19e 310
akashvibhute 6:5cc7136648d1 311 beginTransaction();
akashvibhute 6:5cc7136648d1 312 status = spi.write( R_RX_PAYLOAD );
akashvibhute 6:5cc7136648d1 313 while ( data_len-- ) {
akashvibhute 6:5cc7136648d1 314 *current++ = spi.write(0xFF);
akashvibhute 6:5cc7136648d1 315 }
akashvibhute 6:5cc7136648d1 316 while ( blank_len-- ) {
akashvibhute 6:5cc7136648d1 317 spi.write(0xff);
akashvibhute 6:5cc7136648d1 318 }
akashvibhute 6:5cc7136648d1 319 endTransaction();
akashvibhute 6:5cc7136648d1 320
akashvibhute 6:5cc7136648d1 321
akashvibhute 6:5cc7136648d1 322
akashvibhute 6:5cc7136648d1 323 return status;
akashvibhute 0:bb74812ac6bb 324 }
akashvibhute 0:bb74812ac6bb 325
akashvibhute 0:bb74812ac6bb 326 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 327
akashvibhute 0:bb74812ac6bb 328 uint8_t RF24::flush_rx(void)
akashvibhute 0:bb74812ac6bb 329 {
akashvibhute 6:5cc7136648d1 330 return spiTrans( FLUSH_RX );
akashvibhute 0:bb74812ac6bb 331 }
akashvibhute 0:bb74812ac6bb 332
akashvibhute 0:bb74812ac6bb 333 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 334
akashvibhute 0:bb74812ac6bb 335 uint8_t RF24::flush_tx(void)
akashvibhute 0:bb74812ac6bb 336 {
akashvibhute 6:5cc7136648d1 337 return spiTrans( FLUSH_TX );
akashvibhute 2:3bdf0d9bb71f 338 }
akashvibhute 2:3bdf0d9bb71f 339
akashvibhute 2:3bdf0d9bb71f 340 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 341
akashvibhute 6:5cc7136648d1 342 uint8_t RF24::spiTrans(uint8_t cmd){
akashvibhute 0:bb74812ac6bb 343
akashvibhute 6:5cc7136648d1 344 uint8_t status;
akashvibhute 6:5cc7136648d1 345
akashvibhute 6:5cc7136648d1 346 beginTransaction();
akashvibhute 6:5cc7136648d1 347 status = spi.write( cmd );
akashvibhute 6:5cc7136648d1 348 endTransaction();
akashvibhute 6:5cc7136648d1 349
akashvibhute 6:5cc7136648d1 350 return status;
akashvibhute 0:bb74812ac6bb 351 }
akashvibhute 0:bb74812ac6bb 352
akashvibhute 0:bb74812ac6bb 353 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 354
akashvibhute 0:bb74812ac6bb 355 uint8_t RF24::get_status(void)
akashvibhute 0:bb74812ac6bb 356 {
akashvibhute 6:5cc7136648d1 357 return spiTrans(NOP);
akashvibhute 0:bb74812ac6bb 358 }
akashvibhute 0:bb74812ac6bb 359
akashvibhute 0:bb74812ac6bb 360 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 361 #if !defined (MINIMAL)
akashvibhute 0:bb74812ac6bb 362
akashvibhute 0:bb74812ac6bb 363
akashvibhute 0:bb74812ac6bb 364 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 365
mrcrsch 10:71acc66e27f8 366
akashvibhute 0:bb74812ac6bb 367
akashvibhute 0:bb74812ac6bb 368 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 369
mrcrsch 10:71acc66e27f8 370
akashvibhute 0:bb74812ac6bb 371
mrcrsch 10:71acc66e27f8 372 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 373
akashvibhute 3:e94be00fd19e 374
akashvibhute 2:3bdf0d9bb71f 375 #endif
akashvibhute 2:3bdf0d9bb71f 376 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 377 RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin):
akashvibhute 6:5cc7136648d1 378 spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true),
akashvibhute 6:5cc7136648d1 379 payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
akashvibhute 2:3bdf0d9bb71f 380 {
akashvibhute 6:5cc7136648d1 381 pipe0_reading_address[0]=0;
akashvibhute 6:5cc7136648d1 382
akashvibhute 6:5cc7136648d1 383 //spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus
akashvibhute 6:5cc7136648d1 384 spi.frequency(10000000);
akashvibhute 6:5cc7136648d1 385 //spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
akashvibhute 6:5cc7136648d1 386 spi.format(8,0);
akashvibhute 6:5cc7136648d1 387 wait_ms(10);
akashvibhute 0:bb74812ac6bb 388 }
akashvibhute 0:bb74812ac6bb 389
akashvibhute 2:3bdf0d9bb71f 390
akashvibhute 2:3bdf0d9bb71f 391
akashvibhute 0:bb74812ac6bb 392
akashvibhute 2:3bdf0d9bb71f 393
akashvibhute 2:3bdf0d9bb71f 394
akashvibhute 2:3bdf0d9bb71f 395
akashvibhute 0:bb74812ac6bb 396
akashvibhute 0:bb74812ac6bb 397 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 398
akashvibhute 0:bb74812ac6bb 399 void RF24::setChannel(uint8_t channel)
akashvibhute 0:bb74812ac6bb 400 {
akashvibhute 6:5cc7136648d1 401 const uint8_t max_channel = 125;
akashvibhute 6:5cc7136648d1 402 write_register(RF_CH,rf24_min(channel,max_channel));
akashvibhute 0:bb74812ac6bb 403 }
akashvibhute 0:bb74812ac6bb 404
akashvibhute 2:3bdf0d9bb71f 405 uint8_t RF24::getChannel()
akashvibhute 2:3bdf0d9bb71f 406 {
akashvibhute 6:5cc7136648d1 407
akashvibhute 6:5cc7136648d1 408 return read_register(RF_CH);
akashvibhute 2:3bdf0d9bb71f 409 }
akashvibhute 0:bb74812ac6bb 410 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 411
akashvibhute 0:bb74812ac6bb 412 void RF24::setPayloadSize(uint8_t size)
akashvibhute 0:bb74812ac6bb 413 {
akashvibhute 6:5cc7136648d1 414 payload_size = rf24_min(size,32);
akashvibhute 0:bb74812ac6bb 415 }
akashvibhute 0:bb74812ac6bb 416
akashvibhute 0:bb74812ac6bb 417 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 418
akashvibhute 0:bb74812ac6bb 419 uint8_t RF24::getPayloadSize(void)
akashvibhute 0:bb74812ac6bb 420 {
akashvibhute 6:5cc7136648d1 421 return payload_size;
akashvibhute 0:bb74812ac6bb 422 }
akashvibhute 0:bb74812ac6bb 423
akashvibhute 0:bb74812ac6bb 424 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 425
akashvibhute 2:3bdf0d9bb71f 426 #if !defined (MINIMAL)
akashvibhute 2:3bdf0d9bb71f 427
akashvibhute 2:3bdf0d9bb71f 428 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
akashvibhute 2:3bdf0d9bb71f 429 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
akashvibhute 2:3bdf0d9bb71f 430 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
akashvibhute 2:3bdf0d9bb71f 431 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
akashvibhute 6:5cc7136648d1 432 rf24_datarate_e_str_0,
akashvibhute 6:5cc7136648d1 433 rf24_datarate_e_str_1,
akashvibhute 6:5cc7136648d1 434 rf24_datarate_e_str_2,
akashvibhute 0:bb74812ac6bb 435 };
akashvibhute 2:3bdf0d9bb71f 436 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
akashvibhute 2:3bdf0d9bb71f 437 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
akashvibhute 2:3bdf0d9bb71f 438 static const char * const rf24_model_e_str_P[] PROGMEM = {
akashvibhute 6:5cc7136648d1 439 rf24_model_e_str_0,
akashvibhute 6:5cc7136648d1 440 rf24_model_e_str_1,
akashvibhute 0:bb74812ac6bb 441 };
akashvibhute 2:3bdf0d9bb71f 442 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
akashvibhute 2:3bdf0d9bb71f 443 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
akashvibhute 2:3bdf0d9bb71f 444 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
akashvibhute 2:3bdf0d9bb71f 445 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
akashvibhute 6:5cc7136648d1 446 rf24_crclength_e_str_0,
akashvibhute 6:5cc7136648d1 447 rf24_crclength_e_str_1,
akashvibhute 6:5cc7136648d1 448 rf24_crclength_e_str_2,
akashvibhute 0:bb74812ac6bb 449 };
akashvibhute 2:3bdf0d9bb71f 450 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
akashvibhute 2:3bdf0d9bb71f 451 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
akashvibhute 2:3bdf0d9bb71f 452 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
akashvibhute 2:3bdf0d9bb71f 453 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
akashvibhute 2:3bdf0d9bb71f 454 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
akashvibhute 6:5cc7136648d1 455 rf24_pa_dbm_e_str_0,
akashvibhute 6:5cc7136648d1 456 rf24_pa_dbm_e_str_1,
akashvibhute 6:5cc7136648d1 457 rf24_pa_dbm_e_str_2,
akashvibhute 6:5cc7136648d1 458 rf24_pa_dbm_e_str_3,
akashvibhute 0:bb74812ac6bb 459 };
akashvibhute 0:bb74812ac6bb 460
akashvibhute 6:5cc7136648d1 461
akashvibhute 6:5cc7136648d1 462
akashvibhute 6:5cc7136648d1 463
akashvibhute 6:5cc7136648d1 464
akashvibhute 6:5cc7136648d1 465
akashvibhute 6:5cc7136648d1 466
akashvibhute 6:5cc7136648d1 467
akashvibhute 6:5cc7136648d1 468
akashvibhute 6:5cc7136648d1 469
akashvibhute 6:5cc7136648d1 470
akashvibhute 6:5cc7136648d1 471
akashvibhute 6:5cc7136648d1 472
akashvibhute 6:5cc7136648d1 473
akashvibhute 0:bb74812ac6bb 474 void RF24::printDetails(void)
akashvibhute 0:bb74812ac6bb 475 {
akashvibhute 6:5cc7136648d1 476
akashvibhute 0:bb74812ac6bb 477 }
akashvibhute 0:bb74812ac6bb 478
akashvibhute 2:3bdf0d9bb71f 479 #endif
akashvibhute 0:bb74812ac6bb 480 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 481
akashvibhute 2:3bdf0d9bb71f 482 bool RF24::begin(void)
akashvibhute 0:bb74812ac6bb 483 {
akashvibhute 6:5cc7136648d1 484
akashvibhute 6:5cc7136648d1 485 uint8_t setup=0;
akashvibhute 6:5cc7136648d1 486
akashvibhute 6:5cc7136648d1 487 mainTimer.start();
akashvibhute 6:5cc7136648d1 488
akashvibhute 6:5cc7136648d1 489 ce(LOW);
akashvibhute 6:5cc7136648d1 490 csn(HIGH);
akashvibhute 6:5cc7136648d1 491
akashvibhute 6:5cc7136648d1 492 wait_ms(100);
akashvibhute 6:5cc7136648d1 493
akashvibhute 6:5cc7136648d1 494
akashvibhute 6:5cc7136648d1 495
akashvibhute 6:5cc7136648d1 496
akashvibhute 2:3bdf0d9bb71f 497
akashvibhute 6:5cc7136648d1 498
akashvibhute 6:5cc7136648d1 499
akashvibhute 6:5cc7136648d1 500
akashvibhute 6:5cc7136648d1 501
akashvibhute 6:5cc7136648d1 502
akashvibhute 6:5cc7136648d1 503
akashvibhute 3:e94be00fd19e 504
akashvibhute 6:5cc7136648d1 505
akashvibhute 6:5cc7136648d1 506
akashvibhute 6:5cc7136648d1 507
akashvibhute 6:5cc7136648d1 508
akashvibhute 6:5cc7136648d1 509
akashvibhute 6:5cc7136648d1 510
akashvibhute 0:bb74812ac6bb 511
akashvibhute 6:5cc7136648d1 512
akashvibhute 6:5cc7136648d1 513
akashvibhute 6:5cc7136648d1 514
akashvibhute 6:5cc7136648d1 515
akashvibhute 6:5cc7136648d1 516
akashvibhute 6:5cc7136648d1 517
akashvibhute 6:5cc7136648d1 518
akashvibhute 6:5cc7136648d1 519
akashvibhute 6:5cc7136648d1 520
akashvibhute 6:5cc7136648d1 521
akashvibhute 6:5cc7136648d1 522
akashvibhute 6:5cc7136648d1 523
akashvibhute 6:5cc7136648d1 524
akashvibhute 3:e94be00fd19e 525
akashvibhute 6:5cc7136648d1 526
akashvibhute 6:5cc7136648d1 527
akashvibhute 6:5cc7136648d1 528
akashvibhute 6:5cc7136648d1 529
akashvibhute 6:5cc7136648d1 530
akashvibhute 6:5cc7136648d1 531
akashvibhute 3:e94be00fd19e 532
akashvibhute 6:5cc7136648d1 533 // Must allow the radio time to settle else configuration bits will not necessarily stick.
akashvibhute 6:5cc7136648d1 534 // This is actually only required following power up but some settling time also appears to
akashvibhute 6:5cc7136648d1 535 // be required after resets too. For full coverage, we'll always assume the worst.
akashvibhute 6:5cc7136648d1 536 // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
akashvibhute 6:5cc7136648d1 537 // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
akashvibhute 6:5cc7136648d1 538 // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
akashvibhute 6:5cc7136648d1 539 wait_ms( 5 ) ;
akashvibhute 0:bb74812ac6bb 540
akashvibhute 6:5cc7136648d1 541 // Reset NRF_CONFIG and enable 16-bit CRC.
akashvibhute 6:5cc7136648d1 542 write_register( NRF_CONFIG, 0b00001100 ) ;
akashvibhute 6:5cc7136648d1 543
akashvibhute 6:5cc7136648d1 544 // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
akashvibhute 6:5cc7136648d1 545 // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
akashvibhute 6:5cc7136648d1 546 // sizes must never be used. See documentation for a more complete explanation.
akashvibhute 6:5cc7136648d1 547 setRetries(5,15);
akashvibhute 6:5cc7136648d1 548
akashvibhute 6:5cc7136648d1 549 // Reset value is MAX
akashvibhute 6:5cc7136648d1 550 //setPALevel( RF24_PA_MAX ) ;
akashvibhute 0:bb74812ac6bb 551
akashvibhute 6:5cc7136648d1 552 // check for connected module and if this is a p nRF24l01 variant
akashvibhute 6:5cc7136648d1 553 //
akashvibhute 6:5cc7136648d1 554 if( setDataRate( RF24_250KBPS ) )
akashvibhute 6:5cc7136648d1 555 {
akashvibhute 6:5cc7136648d1 556 p_variant = true ;
akashvibhute 6:5cc7136648d1 557 }
akashvibhute 6:5cc7136648d1 558 setup = read_register(RF_SETUP);
akashvibhute 6:5cc7136648d1 559 /*if( setup == 0b00001110 ) // register default for nRF24L01P
akashvibhute 6:5cc7136648d1 560 {
akashvibhute 6:5cc7136648d1 561 p_variant = true ;
akashvibhute 6:5cc7136648d1 562 }*/
akashvibhute 6:5cc7136648d1 563
akashvibhute 6:5cc7136648d1 564 // Then set the data rate to the slowest (and most reliable) speed supported by all
akashvibhute 6:5cc7136648d1 565 // hardware.
akashvibhute 6:5cc7136648d1 566 //setDataRate( RF24_1MBPS ) ;
akashvibhute 6:5cc7136648d1 567 setDataRate( RF24_2MBPS ) ;
akashvibhute 0:bb74812ac6bb 568
akashvibhute 6:5cc7136648d1 569 // Initialize CRC and request 2-byte (16bit) CRC
akashvibhute 6:5cc7136648d1 570 //setCRCLength( RF24_CRC_16 ) ;
akashvibhute 2:3bdf0d9bb71f 571
akashvibhute 6:5cc7136648d1 572 // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
akashvibhute 6:5cc7136648d1 573 toggle_features();
akashvibhute 6:5cc7136648d1 574 write_register(FEATURE,0 );
akashvibhute 6:5cc7136648d1 575 write_register(DYNPD,0);
akashvibhute 6:5cc7136648d1 576
akashvibhute 6:5cc7136648d1 577 // Reset current status
akashvibhute 6:5cc7136648d1 578 // Notice reset and flush is the last thing we do
akashvibhute 6:5cc7136648d1 579 write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
akashvibhute 0:bb74812ac6bb 580
akashvibhute 6:5cc7136648d1 581 // Set up default configuration. Callers can always change it later.
akashvibhute 6:5cc7136648d1 582 // This channel should be universally safe and not bleed over into adjacent
akashvibhute 6:5cc7136648d1 583 // spectrum.
akashvibhute 6:5cc7136648d1 584 setChannel(76);
akashvibhute 0:bb74812ac6bb 585
akashvibhute 6:5cc7136648d1 586 // Flush buffers
akashvibhute 6:5cc7136648d1 587 flush_rx();
akashvibhute 6:5cc7136648d1 588 flush_tx();
akashvibhute 2:3bdf0d9bb71f 589
akashvibhute 6:5cc7136648d1 590 powerUp(); //Power up by default when begin() is called
akashvibhute 2:3bdf0d9bb71f 591
akashvibhute 6:5cc7136648d1 592 // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
akashvibhute 6:5cc7136648d1 593 // PTX should use only 22uA of power
akashvibhute 6:5cc7136648d1 594 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
akashvibhute 8:b70b1d82f1d7 595 //printDetails();
akashvibhute 6:5cc7136648d1 596 // if setup is 0 or ff then there was no response from module
akashvibhute 6:5cc7136648d1 597 return ( setup != 0 && setup != 0xff );
akashvibhute 0:bb74812ac6bb 598 }
akashvibhute 0:bb74812ac6bb 599
akashvibhute 0:bb74812ac6bb 600 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 601
akashvibhute 0:bb74812ac6bb 602 void RF24::startListening(void)
akashvibhute 0:bb74812ac6bb 603 {
akashvibhute 6:5cc7136648d1 604
akashvibhute 6:5cc7136648d1 605
akashvibhute 6:5cc7136648d1 606
akashvibhute 6:5cc7136648d1 607 write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
akashvibhute 6:5cc7136648d1 608 write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
akashvibhute 6:5cc7136648d1 609 ce(HIGH);
akashvibhute 6:5cc7136648d1 610 // Restore the pipe0 adddress, if exists
akashvibhute 6:5cc7136648d1 611 if (pipe0_reading_address[0] > 0){
akashvibhute 6:5cc7136648d1 612 write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
akashvibhute 6:5cc7136648d1 613 }else{
akashvibhute 6:5cc7136648d1 614 closeReadingPipe(0);
akashvibhute 6:5cc7136648d1 615 }
akashvibhute 0:bb74812ac6bb 616
akashvibhute 6:5cc7136648d1 617 // Flush buffers
akashvibhute 6:5cc7136648d1 618 //flush_rx();
akashvibhute 6:5cc7136648d1 619 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
akashvibhute 6:5cc7136648d1 620 flush_tx();
akashvibhute 6:5cc7136648d1 621 }
akashvibhute 0:bb74812ac6bb 622
akashvibhute 6:5cc7136648d1 623 // Go!
akashvibhute 6:5cc7136648d1 624 //delayMicroseconds(100);
akashvibhute 0:bb74812ac6bb 625 }
akashvibhute 0:bb74812ac6bb 626
akashvibhute 0:bb74812ac6bb 627 /****************************************************************************/
akashvibhute 6:5cc7136648d1 628 static const uint8_t child_pipe_enable[] PROGMEM =
akashvibhute 6:5cc7136648d1 629 {
akashvibhute 6:5cc7136648d1 630 ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
akashvibhute 2:3bdf0d9bb71f 631 };
akashvibhute 0:bb74812ac6bb 632
akashvibhute 0:bb74812ac6bb 633 void RF24::stopListening(void)
akashvibhute 6:5cc7136648d1 634 {
akashvibhute 6:5cc7136648d1 635 ce(LOW);
akashvibhute 2:3bdf0d9bb71f 636
akashvibhute 6:5cc7136648d1 637 wait_us(txRxDelay);
akashvibhute 6:5cc7136648d1 638
akashvibhute 6:5cc7136648d1 639 if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
akashvibhute 6:5cc7136648d1 640 wait_us(txRxDelay); //200
akashvibhute 6:5cc7136648d1 641 flush_tx();
akashvibhute 6:5cc7136648d1 642 }
akashvibhute 6:5cc7136648d1 643 //flush_rx();
akashvibhute 6:5cc7136648d1 644 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
akashvibhute 6:5cc7136648d1 645
akashvibhute 6:5cc7136648d1 646
akashvibhute 6:5cc7136648d1 647
akashvibhute 6:5cc7136648d1 648
akashvibhute 6:5cc7136648d1 649
akashvibhute 6:5cc7136648d1 650
akashvibhute 6:5cc7136648d1 651
akashvibhute 6:5cc7136648d1 652
akashvibhute 6:5cc7136648d1 653 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
akashvibhute 6:5cc7136648d1 654
akashvibhute 6:5cc7136648d1 655 //delayMicroseconds(100);
akashvibhute 2:3bdf0d9bb71f 656
akashvibhute 0:bb74812ac6bb 657 }
akashvibhute 0:bb74812ac6bb 658
akashvibhute 0:bb74812ac6bb 659 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 660
akashvibhute 0:bb74812ac6bb 661 void RF24::powerDown(void)
akashvibhute 0:bb74812ac6bb 662 {
akashvibhute 6:5cc7136648d1 663 ce(LOW); // Guarantee CE is low on powerDown
akashvibhute 6:5cc7136648d1 664 write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
akashvibhute 0:bb74812ac6bb 665 }
akashvibhute 0:bb74812ac6bb 666
akashvibhute 0:bb74812ac6bb 667 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 668
akashvibhute 2:3bdf0d9bb71f 669 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
akashvibhute 0:bb74812ac6bb 670 void RF24::powerUp(void)
akashvibhute 0:bb74812ac6bb 671 {
akashvibhute 6:5cc7136648d1 672 uint8_t cfg = read_register(NRF_CONFIG);
akashvibhute 2:3bdf0d9bb71f 673
akashvibhute 6:5cc7136648d1 674 // if not powered up then power up and wait for the radio to initialize
akashvibhute 6:5cc7136648d1 675 if (!(cfg & _BV(PWR_UP))){
akashvibhute 6:5cc7136648d1 676 write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
akashvibhute 2:3bdf0d9bb71f 677
akashvibhute 6:5cc7136648d1 678 // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
akashvibhute 6:5cc7136648d1 679 // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
akashvibhute 6:5cc7136648d1 680 // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
akashvibhute 6:5cc7136648d1 681 wait_ms(5);
akashvibhute 6:5cc7136648d1 682 }
akashvibhute 0:bb74812ac6bb 683 }
akashvibhute 0:bb74812ac6bb 684
akashvibhute 0:bb74812ac6bb 685 /******************************************************************/
akashvibhute 6:5cc7136648d1 686 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 687 void RF24::errNotify(){
akashvibhute 6:5cc7136648d1 688 #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 689 printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
akashvibhute 6:5cc7136648d1 690 #endif
akashvibhute 6:5cc7136648d1 691 #if defined (FAILURE_HANDLING)
akashvibhute 6:5cc7136648d1 692 failureDetected = 1;
akashvibhute 6:5cc7136648d1 693 #else
akashvibhute 6:5cc7136648d1 694 wait_ms(5000);
akashvibhute 6:5cc7136648d1 695 #endif
akashvibhute 2:3bdf0d9bb71f 696 }
akashvibhute 2:3bdf0d9bb71f 697 #endif
akashvibhute 2:3bdf0d9bb71f 698 /******************************************************************/
akashvibhute 0:bb74812ac6bb 699
akashvibhute 2:3bdf0d9bb71f 700 //Similar to the previous write, clears the interrupt flags
akashvibhute 2:3bdf0d9bb71f 701 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
akashvibhute 2:3bdf0d9bb71f 702 {
akashvibhute 6:5cc7136648d1 703 //Start Writing
akashvibhute 6:5cc7136648d1 704 startFastWrite(buf,len,multicast);
akashvibhute 3:e94be00fd19e 705
akashvibhute 6:5cc7136648d1 706 //Wait until complete or failed
akashvibhute 6:5cc7136648d1 707 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 708 uint32_t timer = mainTimer.read_ms();
akashvibhute 6:5cc7136648d1 709 #endif
akashvibhute 6:5cc7136648d1 710
akashvibhute 6:5cc7136648d1 711 while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
akashvibhute 6:5cc7136648d1 712 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 713 if(mainTimer.read_ms() - timer > 95){
akashvibhute 6:5cc7136648d1 714 errNotify();
akashvibhute 6:5cc7136648d1 715 #if defined (FAILURE_HANDLING)
akashvibhute 6:5cc7136648d1 716 return 0;
akashvibhute 6:5cc7136648d1 717 #else
akashvibhute 6:5cc7136648d1 718 wait_ms(100);
akashvibhute 6:5cc7136648d1 719 #endif
akashvibhute 6:5cc7136648d1 720 }
akashvibhute 6:5cc7136648d1 721 #endif
akashvibhute 6:5cc7136648d1 722 }
akashvibhute 6:5cc7136648d1 723
akashvibhute 6:5cc7136648d1 724 ce(LOW);
akashvibhute 3:e94be00fd19e 725
akashvibhute 6:5cc7136648d1 726 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
akashvibhute 0:bb74812ac6bb 727
akashvibhute 6:5cc7136648d1 728 //Max retries exceeded
akashvibhute 6:5cc7136648d1 729 if( status & _BV(MAX_RT)){
akashvibhute 6:5cc7136648d1 730 flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
akashvibhute 6:5cc7136648d1 731 return 0;
akashvibhute 6:5cc7136648d1 732 }
akashvibhute 6:5cc7136648d1 733 //TX OK 1 or 0
akashvibhute 6:5cc7136648d1 734 return 1;
akashvibhute 2:3bdf0d9bb71f 735 }
akashvibhute 0:bb74812ac6bb 736
akashvibhute 6:5cc7136648d1 737 bool RF24::write( const void* buf, uint8_t len ){
akashvibhute 6:5cc7136648d1 738 return write(buf,len,0);
akashvibhute 0:bb74812ac6bb 739 }
akashvibhute 0:bb74812ac6bb 740 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 741
akashvibhute 2:3bdf0d9bb71f 742 //For general use, the interrupt flags are not important to clear
akashvibhute 2:3bdf0d9bb71f 743 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
akashvibhute 2:3bdf0d9bb71f 744 {
akashvibhute 6:5cc7136648d1 745 //Block until the FIFO is NOT full.
akashvibhute 6:5cc7136648d1 746 //Keep track of the MAX retries and set auto-retry if seeing failures
akashvibhute 6:5cc7136648d1 747 //This way the FIFO will fill up and allow blocking until packets go through
akashvibhute 6:5cc7136648d1 748 //The radio will auto-clear everything in the FIFO as long as CE remains high
akashvibhute 2:3bdf0d9bb71f 749
akashvibhute 6:5cc7136648d1 750 uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started
akashvibhute 2:3bdf0d9bb71f 751
akashvibhute 6:5cc7136648d1 752 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
akashvibhute 2:3bdf0d9bb71f 753
akashvibhute 6:5cc7136648d1 754 if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached
akashvibhute 6:5cc7136648d1 755 reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
akashvibhute 6:5cc7136648d1 756 if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0
akashvibhute 6:5cc7136648d1 757 }
akashvibhute 6:5cc7136648d1 758 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 759 if(mainTimer.read_ms() - timer > (timeout+95) ){
akashvibhute 6:5cc7136648d1 760 errNotify();
akashvibhute 6:5cc7136648d1 761 #if defined (FAILURE_HANDLING)
akashvibhute 6:5cc7136648d1 762 return 0;
akashvibhute 6:5cc7136648d1 763 #endif
akashvibhute 6:5cc7136648d1 764 }
akashvibhute 6:5cc7136648d1 765 #endif
akashvibhute 2:3bdf0d9bb71f 766
akashvibhute 6:5cc7136648d1 767 }
akashvibhute 2:3bdf0d9bb71f 768
akashvibhute 6:5cc7136648d1 769 //Start Writing
akashvibhute 6:5cc7136648d1 770 startFastWrite(buf,len,0); //Write the payload if a buffer is clear
akashvibhute 6:5cc7136648d1 771
akashvibhute 6:5cc7136648d1 772 return 1; //Return 1 to indicate successful transmission
akashvibhute 2:3bdf0d9bb71f 773 }
akashvibhute 2:3bdf0d9bb71f 774
akashvibhute 2:3bdf0d9bb71f 775 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 776
akashvibhute 6:5cc7136648d1 777 void RF24::reUseTX(){
akashvibhute 6:5cc7136648d1 778 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
akashvibhute 6:5cc7136648d1 779 spiTrans( REUSE_TX_PL );
akashvibhute 6:5cc7136648d1 780 ce(LOW); //Re-Transfer packet
akashvibhute 6:5cc7136648d1 781 ce(HIGH);
akashvibhute 2:3bdf0d9bb71f 782 }
akashvibhute 2:3bdf0d9bb71f 783
akashvibhute 2:3bdf0d9bb71f 784 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 785
akashvibhute 2:3bdf0d9bb71f 786 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
akashvibhute 0:bb74812ac6bb 787 {
akashvibhute 6:5cc7136648d1 788 //Block until the FIFO is NOT full.
akashvibhute 6:5cc7136648d1 789 //Keep track of the MAX retries and set auto-retry if seeing failures
akashvibhute 6:5cc7136648d1 790 //Return 0 so the user can control the retrys and set a timer or failure counter if required
akashvibhute 6:5cc7136648d1 791 //The radio will auto-clear everything in the FIFO as long as CE remains high
akashvibhute 2:3bdf0d9bb71f 792
akashvibhute 6:5cc7136648d1 793 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 794 uint32_t timer = mainTimer.read_ms();
akashvibhute 6:5cc7136648d1 795 #endif
akashvibhute 6:5cc7136648d1 796
akashvibhute 6:5cc7136648d1 797 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
akashvibhute 2:3bdf0d9bb71f 798
akashvibhute 6:5cc7136648d1 799 if( get_status() & _BV(MAX_RT)){
akashvibhute 6:5cc7136648d1 800 //reUseTX(); //Set re-transmit
akashvibhute 6:5cc7136648d1 801 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
akashvibhute 6:5cc7136648d1 802 return 0; //Return 0. The previous payload has been retransmitted
akashvibhute 6:5cc7136648d1 803 //From the user perspective, if you get a 0, just keep trying to send the same payload
akashvibhute 6:5cc7136648d1 804 }
akashvibhute 6:5cc7136648d1 805 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 806 if(mainTimer.read_ms() - timer > 95 ){
akashvibhute 6:5cc7136648d1 807 errNotify();
akashvibhute 6:5cc7136648d1 808 #if defined (FAILURE_HANDLING)
akashvibhute 6:5cc7136648d1 809 return 0;
akashvibhute 6:5cc7136648d1 810 #endif
akashvibhute 6:5cc7136648d1 811 }
akashvibhute 6:5cc7136648d1 812 #endif
akashvibhute 6:5cc7136648d1 813 }
akashvibhute 6:5cc7136648d1 814 //Start Writing
akashvibhute 6:5cc7136648d1 815 startFastWrite(buf,len,multicast);
akashvibhute 2:3bdf0d9bb71f 816
akashvibhute 6:5cc7136648d1 817 return 1;
akashvibhute 2:3bdf0d9bb71f 818 }
akashvibhute 2:3bdf0d9bb71f 819
akashvibhute 6:5cc7136648d1 820 bool RF24::writeFast( const void* buf, uint8_t len ){
akashvibhute 6:5cc7136648d1 821 return writeFast(buf,len,0);
akashvibhute 2:3bdf0d9bb71f 822 }
akashvibhute 2:3bdf0d9bb71f 823
akashvibhute 2:3bdf0d9bb71f 824 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 825
akashvibhute 2:3bdf0d9bb71f 826 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
akashvibhute 2:3bdf0d9bb71f 827 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
akashvibhute 2:3bdf0d9bb71f 828 //Otherwise we enter Standby-II mode, which is still faster than standby mode
akashvibhute 2:3bdf0d9bb71f 829 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
akashvibhute 2:3bdf0d9bb71f 830
akashvibhute 6:5cc7136648d1 831 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
akashvibhute 2:3bdf0d9bb71f 832
akashvibhute 6:5cc7136648d1 833 //write_payload( buf,len);
akashvibhute 6:5cc7136648d1 834 write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
akashvibhute 6:5cc7136648d1 835 if(startTx){
akashvibhute 6:5cc7136648d1 836 ce(HIGH);
akashvibhute 6:5cc7136648d1 837 }
akashvibhute 6:5cc7136648d1 838
akashvibhute 2:3bdf0d9bb71f 839 }
akashvibhute 2:3bdf0d9bb71f 840
akashvibhute 2:3bdf0d9bb71f 841 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 842
akashvibhute 2:3bdf0d9bb71f 843 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
akashvibhute 2:3bdf0d9bb71f 844 //Allows the library to pass all tests
akashvibhute 6:5cc7136648d1 845 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
akashvibhute 2:3bdf0d9bb71f 846
akashvibhute 6:5cc7136648d1 847 // Send the payload
akashvibhute 2:3bdf0d9bb71f 848
akashvibhute 6:5cc7136648d1 849 //write_payload( buf, len );
akashvibhute 6:5cc7136648d1 850 write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
akashvibhute 6:5cc7136648d1 851 ce(HIGH);
akashvibhute 6:5cc7136648d1 852
akashvibhute 6:5cc7136648d1 853 wait_us(10);
akashvibhute 6:5cc7136648d1 854
akashvibhute 6:5cc7136648d1 855 ce(LOW);
akashvibhute 2:3bdf0d9bb71f 856
akashvibhute 2:3bdf0d9bb71f 857
akashvibhute 2:3bdf0d9bb71f 858 }
akashvibhute 2:3bdf0d9bb71f 859
akashvibhute 2:3bdf0d9bb71f 860 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 861
akashvibhute 6:5cc7136648d1 862 bool RF24::rxFifoFull(){
akashvibhute 6:5cc7136648d1 863 return read_register(FIFO_STATUS) & _BV(RX_FULL);
akashvibhute 6:5cc7136648d1 864 }
akashvibhute 6:5cc7136648d1 865 /****************************************************************************/
akashvibhute 6:5cc7136648d1 866
akashvibhute 6:5cc7136648d1 867 bool RF24::txStandBy(){
akashvibhute 6:5cc7136648d1 868
akashvibhute 6:5cc7136648d1 869 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 870 uint32_t timeout = mainTimer.read_ms();
akashvibhute 6:5cc7136648d1 871 #endif
akashvibhute 6:5cc7136648d1 872 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
akashvibhute 6:5cc7136648d1 873 if( get_status() & _BV(MAX_RT)){
akashvibhute 6:5cc7136648d1 874 write_register(NRF_STATUS,_BV(MAX_RT) );
akashvibhute 6:5cc7136648d1 875 ce(LOW);
akashvibhute 6:5cc7136648d1 876 flush_tx(); //Non blocking, flush the data
akashvibhute 6:5cc7136648d1 877 return 0;
akashvibhute 6:5cc7136648d1 878 }
akashvibhute 6:5cc7136648d1 879 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 880 if( mainTimer.read_ms() - timeout > 95){
akashvibhute 6:5cc7136648d1 881 errNotify();
akashvibhute 6:5cc7136648d1 882 #if defined (FAILURE_HANDLING)
akashvibhute 6:5cc7136648d1 883 return 0;
akashvibhute 6:5cc7136648d1 884 #endif
akashvibhute 6:5cc7136648d1 885 }
akashvibhute 6:5cc7136648d1 886 #endif
akashvibhute 6:5cc7136648d1 887 }
akashvibhute 6:5cc7136648d1 888
akashvibhute 6:5cc7136648d1 889 ce(LOW); //Set STANDBY-I mode
akashvibhute 6:5cc7136648d1 890 return 1;
akashvibhute 6:5cc7136648d1 891 }
akashvibhute 6:5cc7136648d1 892
akashvibhute 6:5cc7136648d1 893 /****************************************************************************/
akashvibhute 6:5cc7136648d1 894
akashvibhute 6:5cc7136648d1 895 bool RF24::txStandBy(uint32_t timeout, bool startTx){
akashvibhute 2:3bdf0d9bb71f 896
akashvibhute 6:5cc7136648d1 897 if(startTx){
akashvibhute 6:5cc7136648d1 898 stopListening();
akashvibhute 6:5cc7136648d1 899 ce(HIGH);
akashvibhute 6:5cc7136648d1 900 }
akashvibhute 6:5cc7136648d1 901 uint32_t start = mainTimer.read_ms();
akashvibhute 6:5cc7136648d1 902
akashvibhute 6:5cc7136648d1 903 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
akashvibhute 6:5cc7136648d1 904 if( get_status() & _BV(MAX_RT)){
akashvibhute 6:5cc7136648d1 905 write_register(NRF_STATUS,_BV(MAX_RT) );
akashvibhute 6:5cc7136648d1 906 ce(LOW); //Set re-transmit
akashvibhute 6:5cc7136648d1 907 ce(HIGH);
akashvibhute 6:5cc7136648d1 908 if(mainTimer.read_ms() - start >= timeout){
akashvibhute 6:5cc7136648d1 909 ce(LOW); flush_tx(); return 0;
akashvibhute 6:5cc7136648d1 910 }
akashvibhute 6:5cc7136648d1 911 }
akashvibhute 6:5cc7136648d1 912 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
akashvibhute 6:5cc7136648d1 913 if( mainTimer.read_ms() - start > (timeout+95)){
akashvibhute 6:5cc7136648d1 914 errNotify();
akashvibhute 6:5cc7136648d1 915 #if defined (FAILURE_HANDLING)
akashvibhute 6:5cc7136648d1 916 return 0;
akashvibhute 6:5cc7136648d1 917 #endif
akashvibhute 6:5cc7136648d1 918 }
akashvibhute 6:5cc7136648d1 919 #endif
akashvibhute 6:5cc7136648d1 920 }
akashvibhute 6:5cc7136648d1 921
akashvibhute 6:5cc7136648d1 922
akashvibhute 6:5cc7136648d1 923 ce(LOW); //Set STANDBY-I mode
akashvibhute 6:5cc7136648d1 924 return 1;
akashvibhute 6:5cc7136648d1 925
akashvibhute 6:5cc7136648d1 926 }
akashvibhute 6:5cc7136648d1 927
akashvibhute 6:5cc7136648d1 928 /****************************************************************************/
akashvibhute 6:5cc7136648d1 929
akashvibhute 6:5cc7136648d1 930 void RF24::maskIRQ(bool tx, bool fail, bool rx){
akashvibhute 6:5cc7136648d1 931
akashvibhute 6:5cc7136648d1 932 uint8_t config = read_register(NRF_CONFIG);
akashvibhute 6:5cc7136648d1 933 /* clear the interrupt flags */
akashvibhute 6:5cc7136648d1 934 config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
akashvibhute 6:5cc7136648d1 935 /* set the specified interrupt flags */
akashvibhute 6:5cc7136648d1 936 config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
akashvibhute 6:5cc7136648d1 937 write_register(NRF_CONFIG, config);
akashvibhute 0:bb74812ac6bb 938 }
akashvibhute 0:bb74812ac6bb 939
akashvibhute 0:bb74812ac6bb 940 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 941
akashvibhute 0:bb74812ac6bb 942 uint8_t RF24::getDynamicPayloadSize(void)
akashvibhute 0:bb74812ac6bb 943 {
akashvibhute 6:5cc7136648d1 944 uint8_t result = 0;
akashvibhute 0:bb74812ac6bb 945
akashvibhute 6:5cc7136648d1 946
akashvibhute 6:5cc7136648d1 947
akashvibhute 6:5cc7136648d1 948
akashvibhute 6:5cc7136648d1 949
akashvibhute 6:5cc7136648d1 950
akashvibhute 6:5cc7136648d1 951
akashvibhute 6:5cc7136648d1 952
akashvibhute 6:5cc7136648d1 953
akashvibhute 6:5cc7136648d1 954 beginTransaction();
akashvibhute 6:5cc7136648d1 955 spi.write( R_RX_PL_WID );
akashvibhute 6:5cc7136648d1 956 result = spi.write(0xff);
akashvibhute 6:5cc7136648d1 957 endTransaction();
akashvibhute 6:5cc7136648d1 958
akashvibhute 0:bb74812ac6bb 959
akashvibhute 6:5cc7136648d1 960 if(result > 32) { flush_rx(); wait_ms(2); return 0; }
akashvibhute 6:5cc7136648d1 961 return result;
akashvibhute 0:bb74812ac6bb 962 }
akashvibhute 0:bb74812ac6bb 963
akashvibhute 0:bb74812ac6bb 964 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 965
akashvibhute 0:bb74812ac6bb 966 bool RF24::available(void)
akashvibhute 0:bb74812ac6bb 967 {
akashvibhute 6:5cc7136648d1 968 return available(NULL);
akashvibhute 0:bb74812ac6bb 969 }
akashvibhute 0:bb74812ac6bb 970
akashvibhute 0:bb74812ac6bb 971 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 972
akashvibhute 0:bb74812ac6bb 973 bool RF24::available(uint8_t* pipe_num)
akashvibhute 0:bb74812ac6bb 974 {
akashvibhute 6:5cc7136648d1 975 if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
akashvibhute 0:bb74812ac6bb 976
akashvibhute 6:5cc7136648d1 977 // If the caller wants the pipe number, include that
akashvibhute 6:5cc7136648d1 978 if ( pipe_num ){
akashvibhute 6:5cc7136648d1 979 uint8_t status = get_status();
akashvibhute 6:5cc7136648d1 980 *pipe_num = ( status >> RX_P_NO ) & 0b111;
akashvibhute 6:5cc7136648d1 981 }
akashvibhute 6:5cc7136648d1 982 return 1;
akashvibhute 6:5cc7136648d1 983 }
akashvibhute 3:e94be00fd19e 984
akashvibhute 6:5cc7136648d1 985
akashvibhute 6:5cc7136648d1 986 return 0;
akashvibhute 6:5cc7136648d1 987
akashvibhute 6:5cc7136648d1 988
akashvibhute 0:bb74812ac6bb 989 }
akashvibhute 0:bb74812ac6bb 990
akashvibhute 0:bb74812ac6bb 991 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 992
akashvibhute 6:5cc7136648d1 993 void RF24::read( void* buf, uint8_t len ){
akashvibhute 2:3bdf0d9bb71f 994
akashvibhute 6:5cc7136648d1 995 // Fetch the payload
akashvibhute 6:5cc7136648d1 996 read_payload( buf, len );
akashvibhute 0:bb74812ac6bb 997
akashvibhute 6:5cc7136648d1 998 //Clear the two possible interrupt flags with one command
akashvibhute 6:5cc7136648d1 999 write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
akashvibhute 6:5cc7136648d1 1000
akashvibhute 0:bb74812ac6bb 1001 }
akashvibhute 0:bb74812ac6bb 1002
akashvibhute 0:bb74812ac6bb 1003 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1004
akashvibhute 0:bb74812ac6bb 1005 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
akashvibhute 0:bb74812ac6bb 1006 {
akashvibhute 6:5cc7136648d1 1007 // Read the status & reset the status in one easy call
akashvibhute 6:5cc7136648d1 1008 // Or is that such a good idea?
akashvibhute 6:5cc7136648d1 1009 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
akashvibhute 0:bb74812ac6bb 1010
akashvibhute 6:5cc7136648d1 1011 // Report to the user what happened
akashvibhute 6:5cc7136648d1 1012 tx_ok = status & _BV(TX_DS);
akashvibhute 6:5cc7136648d1 1013 tx_fail = status & _BV(MAX_RT);
akashvibhute 6:5cc7136648d1 1014 rx_ready = status & _BV(RX_DR);
akashvibhute 0:bb74812ac6bb 1015 }
akashvibhute 0:bb74812ac6bb 1016
akashvibhute 0:bb74812ac6bb 1017 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1018
akashvibhute 0:bb74812ac6bb 1019 void RF24::openWritingPipe(uint64_t value)
akashvibhute 0:bb74812ac6bb 1020 {
akashvibhute 6:5cc7136648d1 1021 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
akashvibhute 6:5cc7136648d1 1022 // expects it LSB first too, so we're good.
akashvibhute 0:bb74812ac6bb 1023
akashvibhute 6:5cc7136648d1 1024 write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
akashvibhute 6:5cc7136648d1 1025 write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
akashvibhute 6:5cc7136648d1 1026
akashvibhute 6:5cc7136648d1 1027
akashvibhute 6:5cc7136648d1 1028 //const uint8_t max_payload_size = 32;
akashvibhute 6:5cc7136648d1 1029 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
akashvibhute 6:5cc7136648d1 1030 write_register(RX_PW_P0,payload_size);
akashvibhute 0:bb74812ac6bb 1031 }
akashvibhute 0:bb74812ac6bb 1032
akashvibhute 0:bb74812ac6bb 1033 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 1034 void RF24::openWritingPipe(const uint8_t *address)
akashvibhute 2:3bdf0d9bb71f 1035 {
akashvibhute 6:5cc7136648d1 1036 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
akashvibhute 6:5cc7136648d1 1037 // expects it LSB first too, so we're good.
akashvibhute 0:bb74812ac6bb 1038
akashvibhute 6:5cc7136648d1 1039 write_register(RX_ADDR_P0,address, addr_width);
akashvibhute 6:5cc7136648d1 1040 write_register(TX_ADDR, address, addr_width);
akashvibhute 2:3bdf0d9bb71f 1041
akashvibhute 6:5cc7136648d1 1042 //const uint8_t max_payload_size = 32;
akashvibhute 6:5cc7136648d1 1043 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
akashvibhute 6:5cc7136648d1 1044 write_register(RX_PW_P0,payload_size);
akashvibhute 2:3bdf0d9bb71f 1045 }
akashvibhute 2:3bdf0d9bb71f 1046
akashvibhute 2:3bdf0d9bb71f 1047 /****************************************************************************/
akashvibhute 6:5cc7136648d1 1048 static const uint8_t child_pipe[] PROGMEM =
akashvibhute 6:5cc7136648d1 1049 {
akashvibhute 6:5cc7136648d1 1050 RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
akashvibhute 0:bb74812ac6bb 1051 };
akashvibhute 6:5cc7136648d1 1052 static const uint8_t child_payload_size[] PROGMEM =
akashvibhute 6:5cc7136648d1 1053 {
akashvibhute 6:5cc7136648d1 1054 RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
akashvibhute 0:bb74812ac6bb 1055 };
akashvibhute 2:3bdf0d9bb71f 1056
akashvibhute 0:bb74812ac6bb 1057
akashvibhute 0:bb74812ac6bb 1058 void RF24::openReadingPipe(uint8_t child, uint64_t address)
akashvibhute 0:bb74812ac6bb 1059 {
akashvibhute 6:5cc7136648d1 1060 // If this is pipe 0, cache the address. This is needed because
akashvibhute 6:5cc7136648d1 1061 // openWritingPipe() will overwrite the pipe 0 address, so
akashvibhute 6:5cc7136648d1 1062 // startListening() will have to restore it.
akashvibhute 6:5cc7136648d1 1063 if (child == 0){
akashvibhute 6:5cc7136648d1 1064 memcpy(pipe0_reading_address,&address,addr_width);
akashvibhute 6:5cc7136648d1 1065 }
akashvibhute 0:bb74812ac6bb 1066
akashvibhute 6:5cc7136648d1 1067 if (child <= 6)
akashvibhute 6:5cc7136648d1 1068 {
akashvibhute 6:5cc7136648d1 1069 // For pipes 2-5, only write the LSB
akashvibhute 6:5cc7136648d1 1070 if ( child < 2 )
akashvibhute 6:5cc7136648d1 1071 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
akashvibhute 6:5cc7136648d1 1072 else
akashvibhute 6:5cc7136648d1 1073 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
akashvibhute 0:bb74812ac6bb 1074
akashvibhute 6:5cc7136648d1 1075 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
akashvibhute 0:bb74812ac6bb 1076
akashvibhute 6:5cc7136648d1 1077 // Note it would be more efficient to set all of the bits for all open
akashvibhute 6:5cc7136648d1 1078 // pipes at once. However, I thought it would make the calling code
akashvibhute 6:5cc7136648d1 1079 // more simple to do it this way.
akashvibhute 6:5cc7136648d1 1080 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
akashvibhute 6:5cc7136648d1 1081 }
akashvibhute 2:3bdf0d9bb71f 1082 }
akashvibhute 2:3bdf0d9bb71f 1083
akashvibhute 2:3bdf0d9bb71f 1084 /****************************************************************************/
akashvibhute 6:5cc7136648d1 1085 void RF24::setAddressWidth(uint8_t a_width){
akashvibhute 2:3bdf0d9bb71f 1086
akashvibhute 6:5cc7136648d1 1087 if(a_width -= 2){
akashvibhute 6:5cc7136648d1 1088 write_register(SETUP_AW,a_width%4);
akashvibhute 6:5cc7136648d1 1089 addr_width = (a_width%4) + 2;
akashvibhute 6:5cc7136648d1 1090 }
akashvibhute 6:5cc7136648d1 1091
akashvibhute 2:3bdf0d9bb71f 1092 }
akashvibhute 2:3bdf0d9bb71f 1093
akashvibhute 2:3bdf0d9bb71f 1094 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 1095
akashvibhute 2:3bdf0d9bb71f 1096 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
akashvibhute 2:3bdf0d9bb71f 1097 {
akashvibhute 6:5cc7136648d1 1098 // If this is pipe 0, cache the address. This is needed because
akashvibhute 6:5cc7136648d1 1099 // openWritingPipe() will overwrite the pipe 0 address, so
akashvibhute 6:5cc7136648d1 1100 // startListening() will have to restore it.
akashvibhute 6:5cc7136648d1 1101 if (child == 0){
akashvibhute 6:5cc7136648d1 1102 memcpy(pipe0_reading_address,address,addr_width);
akashvibhute 6:5cc7136648d1 1103 }
akashvibhute 6:5cc7136648d1 1104 if (child <= 6)
akashvibhute 6:5cc7136648d1 1105 {
akashvibhute 6:5cc7136648d1 1106 // For pipes 2-5, only write the LSB
akashvibhute 6:5cc7136648d1 1107 if ( child < 2 ){
akashvibhute 6:5cc7136648d1 1108 write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
akashvibhute 6:5cc7136648d1 1109 }else{
akashvibhute 6:5cc7136648d1 1110 write_register(pgm_read_byte(&child_pipe[child]), address, 1);
akashvibhute 6:5cc7136648d1 1111 }
akashvibhute 6:5cc7136648d1 1112 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
akashvibhute 2:3bdf0d9bb71f 1113
akashvibhute 6:5cc7136648d1 1114 // Note it would be more efficient to set all of the bits for all open
akashvibhute 6:5cc7136648d1 1115 // pipes at once. However, I thought it would make the calling code
akashvibhute 6:5cc7136648d1 1116 // more simple to do it this way.
akashvibhute 6:5cc7136648d1 1117 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
akashvibhute 6:5cc7136648d1 1118
akashvibhute 6:5cc7136648d1 1119 }
akashvibhute 2:3bdf0d9bb71f 1120 }
akashvibhute 2:3bdf0d9bb71f 1121
akashvibhute 2:3bdf0d9bb71f 1122 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 1123
akashvibhute 2:3bdf0d9bb71f 1124 void RF24::closeReadingPipe( uint8_t pipe )
akashvibhute 2:3bdf0d9bb71f 1125 {
akashvibhute 6:5cc7136648d1 1126 write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
akashvibhute 0:bb74812ac6bb 1127 }
akashvibhute 0:bb74812ac6bb 1128
akashvibhute 0:bb74812ac6bb 1129 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1130
akashvibhute 0:bb74812ac6bb 1131 void RF24::toggle_features(void)
akashvibhute 0:bb74812ac6bb 1132 {
akashvibhute 2:3bdf0d9bb71f 1133 beginTransaction();
akashvibhute 6:5cc7136648d1 1134 spi.write( ACTIVATE );
akashvibhute 2:3bdf0d9bb71f 1135 spi.write( 0x73 );
akashvibhute 6:5cc7136648d1 1136 endTransaction();
akashvibhute 0:bb74812ac6bb 1137 }
akashvibhute 0:bb74812ac6bb 1138
akashvibhute 0:bb74812ac6bb 1139 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1140
akashvibhute 0:bb74812ac6bb 1141 void RF24::enableDynamicPayloads(void)
akashvibhute 0:bb74812ac6bb 1142 {
akashvibhute 6:5cc7136648d1 1143 // Enable dynamic payload throughout the system
akashvibhute 0:bb74812ac6bb 1144
akashvibhute 2:3bdf0d9bb71f 1145 //toggle_features();
akashvibhute 0:bb74812ac6bb 1146 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
akashvibhute 2:3bdf0d9bb71f 1147
akashvibhute 6:5cc7136648d1 1148
akashvibhute 6:5cc7136648d1 1149 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
akashvibhute 0:bb74812ac6bb 1150
akashvibhute 6:5cc7136648d1 1151 // Enable dynamic payload on all pipes
akashvibhute 6:5cc7136648d1 1152 //
akashvibhute 6:5cc7136648d1 1153 // Not sure the use case of only having dynamic payload on certain
akashvibhute 6:5cc7136648d1 1154 // pipes, so the library does not support it.
akashvibhute 6:5cc7136648d1 1155 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
akashvibhute 0:bb74812ac6bb 1156
akashvibhute 6:5cc7136648d1 1157 dynamic_payloads_enabled = true;
akashvibhute 0:bb74812ac6bb 1158 }
akashvibhute 0:bb74812ac6bb 1159
akashvibhute 0:bb74812ac6bb 1160 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1161
akashvibhute 0:bb74812ac6bb 1162 void RF24::enableAckPayload(void)
akashvibhute 0:bb74812ac6bb 1163 {
akashvibhute 6:5cc7136648d1 1164 //
akashvibhute 6:5cc7136648d1 1165 // enable ack payload and dynamic payload features
akashvibhute 6:5cc7136648d1 1166 //
akashvibhute 0:bb74812ac6bb 1167
akashvibhute 2:3bdf0d9bb71f 1168 //toggle_features();
akashvibhute 2:3bdf0d9bb71f 1169 write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
akashvibhute 0:bb74812ac6bb 1170
akashvibhute 6:5cc7136648d1 1171 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
akashvibhute 0:bb74812ac6bb 1172
akashvibhute 6:5cc7136648d1 1173 //
akashvibhute 6:5cc7136648d1 1174 // Enable dynamic payload on pipes 0 & 1
akashvibhute 6:5cc7136648d1 1175 //
akashvibhute 0:bb74812ac6bb 1176
akashvibhute 6:5cc7136648d1 1177 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
akashvibhute 6:5cc7136648d1 1178 dynamic_payloads_enabled = true;
akashvibhute 2:3bdf0d9bb71f 1179 }
akashvibhute 2:3bdf0d9bb71f 1180
akashvibhute 2:3bdf0d9bb71f 1181 /****************************************************************************/
akashvibhute 2:3bdf0d9bb71f 1182
akashvibhute 6:5cc7136648d1 1183 void RF24::enableDynamicAck(void){
akashvibhute 6:5cc7136648d1 1184 //
akashvibhute 6:5cc7136648d1 1185 // enable dynamic ack features
akashvibhute 6:5cc7136648d1 1186 //
akashvibhute 2:3bdf0d9bb71f 1187 //toggle_features();
akashvibhute 2:3bdf0d9bb71f 1188 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
akashvibhute 2:3bdf0d9bb71f 1189
akashvibhute 6:5cc7136648d1 1190 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
akashvibhute 2:3bdf0d9bb71f 1191
akashvibhute 2:3bdf0d9bb71f 1192
akashvibhute 0:bb74812ac6bb 1193 }
akashvibhute 0:bb74812ac6bb 1194
akashvibhute 0:bb74812ac6bb 1195 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1196
akashvibhute 0:bb74812ac6bb 1197 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
akashvibhute 0:bb74812ac6bb 1198 {
akashvibhute 6:5cc7136648d1 1199 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
akashvibhute 0:bb74812ac6bb 1200
akashvibhute 6:5cc7136648d1 1201 uint8_t data_len = rf24_min(len,32);
akashvibhute 2:3bdf0d9bb71f 1202
akashvibhute 6:5cc7136648d1 1203
akashvibhute 6:5cc7136648d1 1204
akashvibhute 6:5cc7136648d1 1205
akashvibhute 6:5cc7136648d1 1206
akashvibhute 6:5cc7136648d1 1207
akashvibhute 6:5cc7136648d1 1208
akashvibhute 6:5cc7136648d1 1209
akashvibhute 6:5cc7136648d1 1210
akashvibhute 6:5cc7136648d1 1211
akashvibhute 6:5cc7136648d1 1212
akashvibhute 6:5cc7136648d1 1213
akashvibhute 6:5cc7136648d1 1214
akashvibhute 6:5cc7136648d1 1215 beginTransaction();
akashvibhute 6:5cc7136648d1 1216 spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
akashvibhute 2:3bdf0d9bb71f 1217
akashvibhute 6:5cc7136648d1 1218 while ( data_len-- )
akashvibhute 6:5cc7136648d1 1219 spi.write(*current++);
akashvibhute 6:5cc7136648d1 1220 endTransaction();
akashvibhute 6:5cc7136648d1 1221
akashvibhute 6:5cc7136648d1 1222
akashvibhute 0:bb74812ac6bb 1223
akashvibhute 0:bb74812ac6bb 1224 }
akashvibhute 0:bb74812ac6bb 1225
akashvibhute 0:bb74812ac6bb 1226 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1227
akashvibhute 0:bb74812ac6bb 1228 bool RF24::isAckPayloadAvailable(void)
akashvibhute 0:bb74812ac6bb 1229 {
akashvibhute 6:5cc7136648d1 1230 return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
akashvibhute 0:bb74812ac6bb 1231 }
akashvibhute 0:bb74812ac6bb 1232
akashvibhute 0:bb74812ac6bb 1233 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1234
akashvibhute 0:bb74812ac6bb 1235 bool RF24::isPVariant(void)
akashvibhute 0:bb74812ac6bb 1236 {
akashvibhute 6:5cc7136648d1 1237 return p_variant ;
akashvibhute 0:bb74812ac6bb 1238 }
akashvibhute 0:bb74812ac6bb 1239
akashvibhute 0:bb74812ac6bb 1240 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1241
akashvibhute 0:bb74812ac6bb 1242 void RF24::setAutoAck(bool enable)
akashvibhute 0:bb74812ac6bb 1243 {
akashvibhute 6:5cc7136648d1 1244 if ( enable )
akashvibhute 6:5cc7136648d1 1245 write_register(EN_AA, 0b111111);
akashvibhute 6:5cc7136648d1 1246 else
akashvibhute 6:5cc7136648d1 1247 write_register(EN_AA, 0);
akashvibhute 0:bb74812ac6bb 1248 }
akashvibhute 0:bb74812ac6bb 1249
akashvibhute 0:bb74812ac6bb 1250 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1251
akashvibhute 0:bb74812ac6bb 1252 void RF24::setAutoAck( uint8_t pipe, bool enable )
akashvibhute 0:bb74812ac6bb 1253 {
akashvibhute 6:5cc7136648d1 1254 if ( pipe <= 6 )
akashvibhute 6:5cc7136648d1 1255 {
akashvibhute 6:5cc7136648d1 1256 uint8_t en_aa = read_register( EN_AA ) ;
akashvibhute 6:5cc7136648d1 1257 if( enable )
akashvibhute 6:5cc7136648d1 1258 {
akashvibhute 6:5cc7136648d1 1259 en_aa |= _BV(pipe) ;
akashvibhute 0:bb74812ac6bb 1260 }
akashvibhute 6:5cc7136648d1 1261 else
akashvibhute 6:5cc7136648d1 1262 {
akashvibhute 6:5cc7136648d1 1263 en_aa &= ~_BV(pipe) ;
akashvibhute 6:5cc7136648d1 1264 }
akashvibhute 6:5cc7136648d1 1265 write_register( EN_AA, en_aa ) ;
akashvibhute 6:5cc7136648d1 1266 }
akashvibhute 0:bb74812ac6bb 1267 }
akashvibhute 0:bb74812ac6bb 1268
akashvibhute 0:bb74812ac6bb 1269 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1270
akashvibhute 0:bb74812ac6bb 1271 bool RF24::testCarrier(void)
akashvibhute 0:bb74812ac6bb 1272 {
akashvibhute 6:5cc7136648d1 1273 return ( read_register(CD) & 1 );
akashvibhute 0:bb74812ac6bb 1274 }
akashvibhute 0:bb74812ac6bb 1275
akashvibhute 0:bb74812ac6bb 1276 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1277
akashvibhute 0:bb74812ac6bb 1278 bool RF24::testRPD(void)
akashvibhute 0:bb74812ac6bb 1279 {
akashvibhute 6:5cc7136648d1 1280 return ( read_register(RPD) & 1 ) ;
akashvibhute 0:bb74812ac6bb 1281 }
akashvibhute 0:bb74812ac6bb 1282
akashvibhute 0:bb74812ac6bb 1283 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1284
akashvibhute 2:3bdf0d9bb71f 1285 void RF24::setPALevel(uint8_t level)
akashvibhute 0:bb74812ac6bb 1286 {
akashvibhute 2:3bdf0d9bb71f 1287
akashvibhute 6:5cc7136648d1 1288 uint8_t setup = read_register(RF_SETUP) & 0b11111000;
akashvibhute 0:bb74812ac6bb 1289
akashvibhute 6:5cc7136648d1 1290 if(level > 3){ // If invalid level, go to max PA
akashvibhute 6:5cc7136648d1 1291 level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
akashvibhute 6:5cc7136648d1 1292 }else{
akashvibhute 6:5cc7136648d1 1293 level = (level << 1) + 1; // Else set level as requested
akashvibhute 6:5cc7136648d1 1294 }
akashvibhute 0:bb74812ac6bb 1295
akashvibhute 2:3bdf0d9bb71f 1296
akashvibhute 6:5cc7136648d1 1297 write_register( RF_SETUP, setup |= level ) ; // Write it to the chip
akashvibhute 0:bb74812ac6bb 1298 }
akashvibhute 0:bb74812ac6bb 1299
akashvibhute 0:bb74812ac6bb 1300 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1301
akashvibhute 2:3bdf0d9bb71f 1302 uint8_t RF24::getPALevel(void)
akashvibhute 0:bb74812ac6bb 1303 {
akashvibhute 0:bb74812ac6bb 1304
akashvibhute 6:5cc7136648d1 1305 return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
akashvibhute 0:bb74812ac6bb 1306 }
akashvibhute 0:bb74812ac6bb 1307
akashvibhute 0:bb74812ac6bb 1308 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1309
akashvibhute 0:bb74812ac6bb 1310 bool RF24::setDataRate(rf24_datarate_e speed)
akashvibhute 0:bb74812ac6bb 1311 {
akashvibhute 6:5cc7136648d1 1312 bool result = false;
akashvibhute 6:5cc7136648d1 1313 uint8_t setup = read_register(RF_SETUP) ;
akashvibhute 0:bb74812ac6bb 1314
akashvibhute 6:5cc7136648d1 1315 // HIGH and LOW '00' is 1Mbs - our default
akashvibhute 6:5cc7136648d1 1316 setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
akashvibhute 6:5cc7136648d1 1317
akashvibhute 6:5cc7136648d1 1318
akashvibhute 6:5cc7136648d1 1319
akashvibhute 6:5cc7136648d1 1320
akashvibhute 2:3bdf0d9bb71f 1321 txRxDelay=85;
akashvibhute 2:3bdf0d9bb71f 1322
akashvibhute 6:5cc7136648d1 1323 if( speed == RF24_250KBPS )
akashvibhute 6:5cc7136648d1 1324 {
akashvibhute 6:5cc7136648d1 1325 // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
akashvibhute 6:5cc7136648d1 1326 // Making it '10'.
akashvibhute 6:5cc7136648d1 1327 setup |= _BV( RF_DR_LOW ) ;
akashvibhute 6:5cc7136648d1 1328
akashvibhute 6:5cc7136648d1 1329
akashvibhute 6:5cc7136648d1 1330
akashvibhute 6:5cc7136648d1 1331 txRxDelay=155;
akashvibhute 6:5cc7136648d1 1332
akashvibhute 6:5cc7136648d1 1333 }
akashvibhute 6:5cc7136648d1 1334 else
akashvibhute 6:5cc7136648d1 1335 {
akashvibhute 6:5cc7136648d1 1336 // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
akashvibhute 6:5cc7136648d1 1337 // Making it '01'
akashvibhute 6:5cc7136648d1 1338 if ( speed == RF24_2MBPS )
akashvibhute 6:5cc7136648d1 1339 {
akashvibhute 6:5cc7136648d1 1340 setup |= _BV(RF_DR_HIGH);
akashvibhute 6:5cc7136648d1 1341
akashvibhute 6:5cc7136648d1 1342
akashvibhute 6:5cc7136648d1 1343 //txRxDelay=65;
akashvibhute 6:5cc7136648d1 1344 txRxDelay=15; //mbed works fine with this latency
akashvibhute 6:5cc7136648d1 1345
akashvibhute 0:bb74812ac6bb 1346 }
akashvibhute 6:5cc7136648d1 1347 }
akashvibhute 6:5cc7136648d1 1348 write_register(RF_SETUP,setup);
akashvibhute 0:bb74812ac6bb 1349
akashvibhute 6:5cc7136648d1 1350 // Verify our result
akashvibhute 6:5cc7136648d1 1351 if ( read_register(RF_SETUP) == setup )
akashvibhute 6:5cc7136648d1 1352 {
akashvibhute 6:5cc7136648d1 1353 result = true;
akashvibhute 6:5cc7136648d1 1354 }
akashvibhute 6:5cc7136648d1 1355 return result;
akashvibhute 0:bb74812ac6bb 1356 }
akashvibhute 0:bb74812ac6bb 1357
akashvibhute 0:bb74812ac6bb 1358 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1359
akashvibhute 0:bb74812ac6bb 1360 rf24_datarate_e RF24::getDataRate( void )
akashvibhute 0:bb74812ac6bb 1361 {
akashvibhute 6:5cc7136648d1 1362 rf24_datarate_e result ;
akashvibhute 6:5cc7136648d1 1363 uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
akashvibhute 2:3bdf0d9bb71f 1364
akashvibhute 6:5cc7136648d1 1365 // switch uses RAM (evil!)
akashvibhute 6:5cc7136648d1 1366 // Order matters in our case below
akashvibhute 6:5cc7136648d1 1367 if ( dr == _BV(RF_DR_LOW) )
akashvibhute 6:5cc7136648d1 1368 {
akashvibhute 6:5cc7136648d1 1369 // '10' = 250KBPS
akashvibhute 6:5cc7136648d1 1370 result = RF24_250KBPS ;
akashvibhute 6:5cc7136648d1 1371 }
akashvibhute 6:5cc7136648d1 1372 else if ( dr == _BV(RF_DR_HIGH) )
akashvibhute 6:5cc7136648d1 1373 {
akashvibhute 6:5cc7136648d1 1374 // '01' = 2MBPS
akashvibhute 6:5cc7136648d1 1375 result = RF24_2MBPS ;
akashvibhute 6:5cc7136648d1 1376 }
akashvibhute 6:5cc7136648d1 1377 else
akashvibhute 6:5cc7136648d1 1378 {
akashvibhute 6:5cc7136648d1 1379 // '00' = 1MBPS
akashvibhute 6:5cc7136648d1 1380 result = RF24_1MBPS ;
akashvibhute 6:5cc7136648d1 1381 }
akashvibhute 6:5cc7136648d1 1382 return result ;
akashvibhute 0:bb74812ac6bb 1383 }
akashvibhute 0:bb74812ac6bb 1384
akashvibhute 0:bb74812ac6bb 1385 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1386
akashvibhute 0:bb74812ac6bb 1387 void RF24::setCRCLength(rf24_crclength_e length)
akashvibhute 0:bb74812ac6bb 1388 {
akashvibhute 6:5cc7136648d1 1389 uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
akashvibhute 2:3bdf0d9bb71f 1390
akashvibhute 6:5cc7136648d1 1391 // switch uses RAM (evil!)
akashvibhute 6:5cc7136648d1 1392 if ( length == RF24_CRC_DISABLED )
akashvibhute 6:5cc7136648d1 1393 {
akashvibhute 6:5cc7136648d1 1394 // Do nothing, we turned it off above.
akashvibhute 6:5cc7136648d1 1395 }
akashvibhute 6:5cc7136648d1 1396 else if ( length == RF24_CRC_8 )
akashvibhute 6:5cc7136648d1 1397 {
akashvibhute 6:5cc7136648d1 1398 config |= _BV(EN_CRC);
akashvibhute 6:5cc7136648d1 1399 }
akashvibhute 6:5cc7136648d1 1400 else
akashvibhute 6:5cc7136648d1 1401 {
akashvibhute 6:5cc7136648d1 1402 config |= _BV(EN_CRC);
akashvibhute 6:5cc7136648d1 1403 config |= _BV( CRCO );
akashvibhute 6:5cc7136648d1 1404 }
akashvibhute 6:5cc7136648d1 1405 write_register( NRF_CONFIG, config ) ;
akashvibhute 0:bb74812ac6bb 1406 }
akashvibhute 0:bb74812ac6bb 1407
akashvibhute 0:bb74812ac6bb 1408 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1409
akashvibhute 0:bb74812ac6bb 1410 rf24_crclength_e RF24::getCRCLength(void)
akashvibhute 0:bb74812ac6bb 1411 {
akashvibhute 6:5cc7136648d1 1412 rf24_crclength_e result = RF24_CRC_DISABLED;
akashvibhute 6:5cc7136648d1 1413
akashvibhute 6:5cc7136648d1 1414 uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
akashvibhute 6:5cc7136648d1 1415 uint8_t AA = read_register(EN_AA);
akashvibhute 6:5cc7136648d1 1416
akashvibhute 6:5cc7136648d1 1417 if ( config & _BV(EN_CRC ) || AA)
akashvibhute 6:5cc7136648d1 1418 {
akashvibhute 6:5cc7136648d1 1419 if ( config & _BV(CRCO) )
akashvibhute 6:5cc7136648d1 1420 result = RF24_CRC_16;
akashvibhute 6:5cc7136648d1 1421 else
akashvibhute 6:5cc7136648d1 1422 result = RF24_CRC_8;
akashvibhute 6:5cc7136648d1 1423 }
akashvibhute 0:bb74812ac6bb 1424
akashvibhute 6:5cc7136648d1 1425 return result;
akashvibhute 0:bb74812ac6bb 1426 }
akashvibhute 0:bb74812ac6bb 1427
akashvibhute 0:bb74812ac6bb 1428 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1429
akashvibhute 0:bb74812ac6bb 1430 void RF24::disableCRC( void )
akashvibhute 0:bb74812ac6bb 1431 {
akashvibhute 6:5cc7136648d1 1432 uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
akashvibhute 6:5cc7136648d1 1433 write_register( NRF_CONFIG, disable ) ;
akashvibhute 0:bb74812ac6bb 1434 }
akashvibhute 0:bb74812ac6bb 1435
akashvibhute 0:bb74812ac6bb 1436 /****************************************************************************/
akashvibhute 0:bb74812ac6bb 1437 void RF24::setRetries(uint8_t delay, uint8_t count)
akashvibhute 0:bb74812ac6bb 1438 {
akashvibhute 6:5cc7136648d1 1439 write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
akashvibhute 0:bb74812ac6bb 1440 }
akashvibhute 6:5cc7136648d1 1441