Denis Nyzovets / FT810

Library for FT810 EVE chip

Fork of FT810 by Curtis Mattull

src/FT_GPU_Hal.cpp@12:74108436751e, 2018-01-24 (annotated)

Committer:
mozillain
Date:
Wed Jan 24 13:04:36 2018 +0000
Revision:
12:74108436751e
Parent:
11:435747a1f2ae 
Diff

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cpm219 0:2d0ef4830603 1 #include "FT_Platform.h"
cpm219 0:2d0ef4830603 2 #include "mbed.h"
cpm219 0:2d0ef4830603 3 #include "FT_LCD_Type.h"
cpm219 0:2d0ef4830603 4
cpm219 0:2d0ef4830603 5 FT800::FT800(PinName mosi,
cpm219 0:2d0ef4830603 6 PinName miso,
cpm219 0:2d0ef4830603 7 PinName sck,
cpm219 0:2d0ef4830603 8 PinName ss,
cpm219 0:2d0ef4830603 9 PinName intr,
cpm219 0:2d0ef4830603 10 PinName pd)
cpm219 0:2d0ef4830603 11 :
cpm219 5:506e2de9a9e6 12
cpm219 0:2d0ef4830603 13 _spi(mosi, miso, sck),
cpm219 0:2d0ef4830603 14 _ss(ss),
cpm219 0:2d0ef4830603 15 _pd(pd),
cpm219 0:2d0ef4830603 16 _f800_isr(InterruptIn(intr))
cpm219 0:2d0ef4830603 17 {
cpm219 0:2d0ef4830603 18 _spi.format(8,0); // 8 bit spi mode 0
cpm219 6:ce30c1530d71 19 _spi.frequency(1000000); // start with 10 Mhz SPI clock
cpm219 0:2d0ef4830603 20 _ss = 1; // cs high
cpm219 0:2d0ef4830603 21 _pd = 1; // PD high
cpm219 0:2d0ef4830603 22 Bootup();
cpm219 0:2d0ef4830603 23 }
cpm219 0:2d0ef4830603 24
cpm219 0:2d0ef4830603 25
cpm219 0:2d0ef4830603 26 ft_bool_t FT800::Bootup(void){
mozillain 10:4c10e6aeb239 27 //pc.printf("Bootup() entered\r\n");
cpm219 0:2d0ef4830603 28 Open();
cpm219 5:506e2de9a9e6 29
cpm219 0:2d0ef4830603 30 BootupConfig();
cpm219 0:2d0ef4830603 31
cpm219 0:2d0ef4830603 32 return(1);
cpm219 0:2d0ef4830603 33 }
cpm219 0:2d0ef4830603 34
cpm219 0:2d0ef4830603 35
cpm219 0:2d0ef4830603 36 ft_void_t FT800::BootupConfig(void){
cpm219 0:2d0ef4830603 37 ft_uint8_t chipid;
cpm219 0:2d0ef4830603 38 /* Do a power cycle for safer side */
cpm219 0:2d0ef4830603 39 Powercycle( FT_TRUE);
mozillain 12:74108436751e 40
mozillain 12:74108436751e 41 /* Set the clk to external clock */
mozillain 12:74108436751e 42 HostCommand( FT_GPU_EXTERNAL_OSC);
mozillain 12:74108436751e 43 Sleep(10);
mozillain 12:74108436751e 44
mozillain 12:74108436751e 45 /* Access address 0 to wake up the FT800 */
cpm219 0:2d0ef4830603 46 HostCommand( FT_GPU_ACTIVE_M);
mozillain 12:74108436751e 47 Sleep(500);
cpm219 0:2d0ef4830603 48
mozillain 12:74108436751e 49 /* Switch PLL output to 48MHz */
mozillain 12:74108436751e 50 // HostCommand( FT_GPU_PLL_48M);
mozillain 12:74108436751e 51 Sleep(10);
mozillain 12:74108436751e 52
mozillain 12:74108436751e 53 /* Do a core reset for safer side */
mozillain 12:74108436751e 54 HostCommand( FT_GPU_CORE_RESET);
mozillain 12:74108436751e 55 Sleep(500);
mozillain 12:74108436751e 56 //Read Register ID to check if FT800 is ready.
mozillain 12:74108436751e 57 chipid = Rd8( REG_ID);
cpm219 0:2d0ef4830603 58 while(chipid != 0x7C)
mozillain 10:4c10e6aeb239 59
mozillain 12:74108436751e 60 _spi.frequency(30000000); // 30 Mhz SPI clock DC
mozillain 12:74108436751e 61 // _spi.frequency(20000000); // 20 Mhz SPI clock DC
mozillain 12:74108436751e 62 // _spi.frequency(12000000); // 12 Mhz SPI clock
mozillain 12:74108436751e 63 /* Configuration of LCD display */
cpm219 0:2d0ef4830603 64 /* Configuration of LCD display */
cpm219 0:2d0ef4830603 65 DispHCycle = my_DispHCycle;
cpm219 0:2d0ef4830603 66 Wr16( REG_HCYCLE, DispHCycle);
cpm219 0:2d0ef4830603 67 DispHOffset = my_DispHOffset;
cpm219 0:2d0ef4830603 68 Wr16( REG_HOFFSET, DispHOffset);
cpm219 0:2d0ef4830603 69 DispWidth = my_DispWidth;
cpm219 0:2d0ef4830603 70 Wr16( REG_HSIZE, DispWidth);
cpm219 0:2d0ef4830603 71 DispHSync0 = my_DispHSync0;
cpm219 0:2d0ef4830603 72 Wr16( REG_HSYNC0, DispHSync0);
cpm219 0:2d0ef4830603 73 DispHSync1 = my_DispHSync1;
cpm219 0:2d0ef4830603 74 Wr16( REG_HSYNC1, DispHSync1);
cpm219 0:2d0ef4830603 75 DispVCycle = my_DispVCycle;
cpm219 0:2d0ef4830603 76 Wr16( REG_VCYCLE, DispVCycle);
cpm219 0:2d0ef4830603 77 DispVOffset = my_DispVOffset;
cpm219 0:2d0ef4830603 78 Wr16( REG_VOFFSET, DispVOffset);
cpm219 0:2d0ef4830603 79 DispHeight = my_DispHeight;
cpm219 0:2d0ef4830603 80 Wr16( REG_VSIZE, DispHeight);
cpm219 0:2d0ef4830603 81 DispVSync0 = my_DispVSync0;
cpm219 0:2d0ef4830603 82 Wr16( REG_VSYNC0, DispVSync0);
cpm219 0:2d0ef4830603 83 DispVSync1 = my_DispVSync1;
cpm219 0:2d0ef4830603 84 Wr16( REG_VSYNC1, DispVSync1);
cpm219 0:2d0ef4830603 85 DispSwizzle = my_DispSwizzle;
cpm219 0:2d0ef4830603 86 Wr8( REG_SWIZZLE, DispSwizzle);
cpm219 0:2d0ef4830603 87 DispPCLKPol = my_DispPCLKPol;
cpm219 0:2d0ef4830603 88 Wr8( REG_PCLK_POL, DispPCLKPol);
mozillain 10:4c10e6aeb239 89 Wr8( REG_CSPREAD, 0);
cpm219 0:2d0ef4830603 90 DispPCLK = my_DispPCLK;
cpm219 0:2d0ef4830603 91 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
mozillain 12:74108436751e 92
mozillain 12:74108436751e 93
mozillain 10:4c10e6aeb239 94 ft_uint8_t temp = Rd8(REG_PCLK);
mozillain 10:4c10e6aeb239 95 if (temp!=DispPCLK){DigitalOut led(LED1); led=1;}
mozillain 10:4c10e6aeb239 96 Serial pc(SERIAL_TX, SERIAL_RX);
mozillain 12:74108436751e 97 pc.printf("ID:%08X\n", Rd8(0x0C0000));
mozillain 11:435747a1f2ae 98
mozillain 12:74108436751e 99 Wr16(REG_PWM_HZ, 10000);
mozillain 12:74108436751e 100 pc.printf("PWM:%08X\n", Rd16(REG_PWM_HZ));
mozillain 12:74108436751e 101 Wr16(REG_PWM_DUTY, 127);
mozillain 12:74108436751e 102 Wr8(REG_GPIO_DIR,0x82);
mozillain 12:74108436751e 103 Wr8(REG_GPIO,0x82);
mozillain 12:74108436751e 104 pc.printf("GPIO:%08X\n", Rd8(REG_GPIO));
mozillain 12:74108436751e 105 Wr16(REG_GPIOX_DIR,0x8000);
mozillain 12:74108436751e 106 Wr16(REG_GPIOX,0x8000);
cpm219 0:2d0ef4830603 107
cpm219 0:2d0ef4830603 108 Wr32( RAM_DL, CLEAR(1,1,1));
cpm219 0:2d0ef4830603 109 Wr32( RAM_DL+4, DISPLAY());
cpm219 0:2d0ef4830603 110 Wr32( REG_DLSWAP,1);
cpm219 0:2d0ef4830603 111
cpm219 0:2d0ef4830603 112 Wr16( REG_PCLK, DispPCLK);
cpm219 0:2d0ef4830603 113
cpm219 0:2d0ef4830603 114 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
mozillain 10:4c10e6aeb239 115 Wr16( REG_TOUCH_RZTHRESH,1200);
cpm219 0:2d0ef4830603 116 }
cpm219 0:2d0ef4830603 117
cpm219 0:2d0ef4830603 118
cpm219 0:2d0ef4830603 119
cpm219 0:2d0ef4830603 120 /* API to initialize the SPI interface */
cpm219 0:2d0ef4830603 121 ft_bool_t FT800::Init()
cpm219 0:2d0ef4830603 122 {
cpm219 0:2d0ef4830603 123 // is done in constructor
cpm219 0:2d0ef4830603 124 return 1;
cpm219 0:2d0ef4830603 125 }
cpm219 0:2d0ef4830603 126
cpm219 0:2d0ef4830603 127
cpm219 0:2d0ef4830603 128 ft_bool_t FT800::Open()
cpm219 0:2d0ef4830603 129 {
cpm219 0:2d0ef4830603 130 cmd_fifo_wp = dl_buff_wp = 0;
cpm219 0:2d0ef4830603 131 status = OPENED;
cpm219 0:2d0ef4830603 132 return 1;
cpm219 0:2d0ef4830603 133 }
cpm219 0:2d0ef4830603 134
cpm219 0:2d0ef4830603 135 ft_void_t FT800::Close( )
cpm219 0:2d0ef4830603 136 {
cpm219 0:2d0ef4830603 137 status = CLOSED;
cpm219 0:2d0ef4830603 138 }
cpm219 0:2d0ef4830603 139
cpm219 0:2d0ef4830603 140 ft_void_t FT800::DeInit()
cpm219 0:2d0ef4830603 141 {
cpm219 0:2d0ef4830603 142
cpm219 0:2d0ef4830603 143 }
cpm219 0:2d0ef4830603 144
cpm219 0:2d0ef4830603 145 /*The APIs for reading/writing transfer continuously only with small buffer system*/
cpm219 0:2d0ef4830603 146 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
cpm219 0:2d0ef4830603 147 {
cpm219 0:2d0ef4830603 148 if (FT_GPU_READ == rw){
cpm219 0:2d0ef4830603 149 _ss = 0; // cs low
cpm219 0:2d0ef4830603 150 _spi.write(addr >> 16);
cpm219 0:2d0ef4830603 151 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 152 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 153 _spi.write(0); //Dummy Read Byte
cpm219 0:2d0ef4830603 154 status = READING;
cpm219 0:2d0ef4830603 155 }else{
cpm219 0:2d0ef4830603 156 _ss = 0; // cs low
cpm219 0:2d0ef4830603 157 _spi.write(0x80 | (addr >> 16));
cpm219 0:2d0ef4830603 158 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 159 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 160 status = WRITING;
cpm219 0:2d0ef4830603 161 }
cpm219 0:2d0ef4830603 162 }
cpm219 0:2d0ef4830603 163
cpm219 0:2d0ef4830603 164
cpm219 0:2d0ef4830603 165 /*The APIs for writing transfer continuously only*/
cpm219 0:2d0ef4830603 166 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
cpm219 0:2d0ef4830603 167 {
cpm219 0:2d0ef4830603 168 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
cpm219 0:2d0ef4830603 169 }
cpm219 0:2d0ef4830603 170
cpm219 0:2d0ef4830603 171 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
cpm219 0:2d0ef4830603 172 {
cpm219 0:2d0ef4830603 173 ft_uint16_t length = strlen(string);
cpm219 0:2d0ef4830603 174 while(length --){
cpm219 0:2d0ef4830603 175 Transfer8( *string);
cpm219 0:2d0ef4830603 176 string ++;
cpm219 0:2d0ef4830603 177 }
cpm219 0:2d0ef4830603 178 //Append one null as ending flag
cpm219 0:2d0ef4830603 179 Transfer8( 0);
cpm219 0:2d0ef4830603 180 return(1);
cpm219 0:2d0ef4830603 181 }
cpm219 0:2d0ef4830603 182
cpm219 0:2d0ef4830603 183
cpm219 0:2d0ef4830603 184 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
cpm219 0:2d0ef4830603 185 {
cpm219 0:2d0ef4830603 186 return _spi.write(value);
cpm219 0:2d0ef4830603 187 }
cpm219 0:2d0ef4830603 188
cpm219 0:2d0ef4830603 189
cpm219 0:2d0ef4830603 190 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
cpm219 0:2d0ef4830603 191 {
cpm219 0:2d0ef4830603 192 ft_uint16_t retVal = 0;
cpm219 0:2d0ef4830603 193
cpm219 0:2d0ef4830603 194 if (status == WRITING){
cpm219 0:2d0ef4830603 195 Transfer8( value & 0xFF);//LSB first
cpm219 0:2d0ef4830603 196 Transfer8( (value >> 8) & 0xFF);
cpm219 0:2d0ef4830603 197 }else{
cpm219 0:2d0ef4830603 198 retVal = Transfer8( 0);
cpm219 0:2d0ef4830603 199 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
cpm219 0:2d0ef4830603 200 }
cpm219 0:2d0ef4830603 201
cpm219 0:2d0ef4830603 202 return retVal;
cpm219 0:2d0ef4830603 203 }
cpm219 0:2d0ef4830603 204
cpm219 0:2d0ef4830603 205 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
cpm219 0:2d0ef4830603 206 {
cpm219 0:2d0ef4830603 207 ft_uint32_t retVal = 0;
cpm219 0:2d0ef4830603 208 if (status == WRITING){
cpm219 0:2d0ef4830603 209 Transfer16( value & 0xFFFF);//LSB first
cpm219 0:2d0ef4830603 210 Transfer16( (value >> 16) & 0xFFFF);
cpm219 0:2d0ef4830603 211 }else{
cpm219 0:2d0ef4830603 212 retVal = Transfer16( 0);
cpm219 0:2d0ef4830603 213 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
cpm219 0:2d0ef4830603 214 }
cpm219 0:2d0ef4830603 215 return retVal;
cpm219 0:2d0ef4830603 216 }
cpm219 0:2d0ef4830603 217
cpm219 0:2d0ef4830603 218 ft_void_t FT800::EndTransfer( )
cpm219 0:2d0ef4830603 219 {
cpm219 0:2d0ef4830603 220 _ss = 1;
cpm219 0:2d0ef4830603 221 status = OPENED;
cpm219 0:2d0ef4830603 222 }
cpm219 0:2d0ef4830603 223
cpm219 0:2d0ef4830603 224
cpm219 0:2d0ef4830603 225 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
cpm219 0:2d0ef4830603 226 {
cpm219 0:2d0ef4830603 227 ft_uint8_t value;
cpm219 0:2d0ef4830603 228 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 229 value = Transfer8( 0);
cpm219 0:2d0ef4830603 230 EndTransfer( );
cpm219 0:2d0ef4830603 231 return value;
cpm219 0:2d0ef4830603 232 }
cpm219 0:2d0ef4830603 233 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
cpm219 0:2d0ef4830603 234 {
cpm219 0:2d0ef4830603 235 ft_uint16_t value;
cpm219 0:2d0ef4830603 236 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 237 value = Transfer16( 0);
cpm219 0:2d0ef4830603 238 EndTransfer( );
cpm219 0:2d0ef4830603 239 return value;
cpm219 0:2d0ef4830603 240 }
cpm219 0:2d0ef4830603 241 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
cpm219 0:2d0ef4830603 242 {
cpm219 0:2d0ef4830603 243 ft_uint32_t value;
cpm219 0:2d0ef4830603 244 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 245 value = Transfer32( 0);
cpm219 0:2d0ef4830603 246 EndTransfer( );
cpm219 0:2d0ef4830603 247 return value;
cpm219 0:2d0ef4830603 248 }
cpm219 0:2d0ef4830603 249
cpm219 0:2d0ef4830603 250 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
cpm219 0:2d0ef4830603 251 {
cpm219 0:2d0ef4830603 252 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 253 Transfer8( v);
cpm219 0:2d0ef4830603 254 EndTransfer( );
cpm219 0:2d0ef4830603 255 }
cpm219 0:2d0ef4830603 256 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
cpm219 0:2d0ef4830603 257 {
cpm219 0:2d0ef4830603 258 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 259 Transfer16( v);
cpm219 0:2d0ef4830603 260 EndTransfer( );
cpm219 0:2d0ef4830603 261 }
cpm219 0:2d0ef4830603 262 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
cpm219 0:2d0ef4830603 263 {
cpm219 0:2d0ef4830603 264 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 265 Transfer32( v);
cpm219 0:2d0ef4830603 266 EndTransfer( );
cpm219 0:2d0ef4830603 267 }
cpm219 0:2d0ef4830603 268
cpm219 0:2d0ef4830603 269 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
cpm219 0:2d0ef4830603 270 {
cpm219 0:2d0ef4830603 271 _ss = 0;
cpm219 0:2d0ef4830603 272 _spi.write(cmd);
cpm219 0:2d0ef4830603 273 _spi.write(0);
cpm219 0:2d0ef4830603 274 _spi.write(0);
cpm219 0:2d0ef4830603 275 _ss = 1;
cpm219 0:2d0ef4830603 276 }
cpm219 0:2d0ef4830603 277
cpm219 0:2d0ef4830603 278 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
cpm219 0:2d0ef4830603 279 {
cpm219 0:2d0ef4830603 280 HostCommand( pllsource);
cpm219 0:2d0ef4830603 281 }
cpm219 0:2d0ef4830603 282
cpm219 0:2d0ef4830603 283 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
cpm219 0:2d0ef4830603 284 {
cpm219 0:2d0ef4830603 285 HostCommand( freq);
cpm219 0:2d0ef4830603 286 }
cpm219 0:2d0ef4830603 287
cpm219 0:2d0ef4830603 288 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
cpm219 0:2d0ef4830603 289 {
cpm219 0:2d0ef4830603 290 HostCommand( pwrmode);
cpm219 0:2d0ef4830603 291 }
cpm219 0:2d0ef4830603 292
cpm219 0:2d0ef4830603 293 ft_void_t FT800::CoreReset( )
cpm219 0:2d0ef4830603 294 {
cpm219 0:2d0ef4830603 295 HostCommand( 0x68);
cpm219 0:2d0ef4830603 296 }
cpm219 0:2d0ef4830603 297
cpm219 0:2d0ef4830603 298
cpm219 0:2d0ef4830603 299 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
cpm219 0:2d0ef4830603 300 {
cpm219 0:2d0ef4830603 301 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
cpm219 0:2d0ef4830603 302 //4 byte alignment
cpm219 0:2d0ef4830603 303 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
cpm219 0:2d0ef4830603 304 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
cpm219 0:2d0ef4830603 305 }
cpm219 0:2d0ef4830603 306
cpm219 0:2d0ef4830603 307
cpm219 0:2d0ef4830603 308 ft_uint16_t FT800::fifo_Freespace( )
cpm219 0:2d0ef4830603 309 {
cpm219 0:2d0ef4830603 310 ft_uint16_t fullness,retval;
cpm219 0:2d0ef4830603 311
cpm219 0:2d0ef4830603 312 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
cpm219 0:2d0ef4830603 313 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
cpm219 0:2d0ef4830603 314 return (retval);
cpm219 0:2d0ef4830603 315 }
cpm219 0:2d0ef4830603 316
cpm219 0:2d0ef4830603 317 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 318 {
cpm219 0:2d0ef4830603 319 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 320
cpm219 0:2d0ef4830603 321 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 322 do {
cpm219 0:2d0ef4830603 323 length = count;
cpm219 0:2d0ef4830603 324 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 325 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 326 }
cpm219 0:2d0ef4830603 327 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 328
cpm219 0:2d0ef4830603 329 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 330
cpm219 0:2d0ef4830603 331 SizeTransfered = 0;
cpm219 0:2d0ef4830603 332 while (length--) {
cpm219 0:2d0ef4830603 333 Transfer8( *buffer);
cpm219 0:2d0ef4830603 334 buffer++;
cpm219 0:2d0ef4830603 335 SizeTransfered ++;
cpm219 0:2d0ef4830603 336 }
cpm219 0:2d0ef4830603 337 length = SizeTransfered;
cpm219 0:2d0ef4830603 338
cpm219 0:2d0ef4830603 339 EndTransfer( );
cpm219 0:2d0ef4830603 340 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 341
cpm219 0:2d0ef4830603 342 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 343
cpm219 0:2d0ef4830603 344 count -= length;
cpm219 0:2d0ef4830603 345 }while (count > 0);
cpm219 0:2d0ef4830603 346 }
cpm219 0:2d0ef4830603 347
cpm219 0:2d0ef4830603 348
cpm219 0:2d0ef4830603 349 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 350 {
cpm219 0:2d0ef4830603 351 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 352
cpm219 0:2d0ef4830603 353 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 354 do {
cpm219 0:2d0ef4830603 355 length = count;
cpm219 0:2d0ef4830603 356 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 357 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 358 }
cpm219 0:2d0ef4830603 359 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 360
cpm219 0:2d0ef4830603 361 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 362
cpm219 0:2d0ef4830603 363
cpm219 0:2d0ef4830603 364 SizeTransfered = 0;
cpm219 0:2d0ef4830603 365 while (length--) {
cpm219 0:2d0ef4830603 366 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 367 buffer++;
cpm219 0:2d0ef4830603 368 SizeTransfered ++;
cpm219 0:2d0ef4830603 369 }
cpm219 0:2d0ef4830603 370 length = SizeTransfered;
cpm219 0:2d0ef4830603 371
cpm219 0:2d0ef4830603 372 EndTransfer( );
cpm219 0:2d0ef4830603 373 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 374
cpm219 0:2d0ef4830603 375 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 376
cpm219 0:2d0ef4830603 377 count -= length;
cpm219 0:2d0ef4830603 378 }while (count > 0);
cpm219 0:2d0ef4830603 379 }
cpm219 0:2d0ef4830603 380
cpm219 0:2d0ef4830603 381
cpm219 0:2d0ef4830603 382 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
cpm219 0:2d0ef4830603 383 {
cpm219 0:2d0ef4830603 384 ft_uint16_t getfreespace;
cpm219 0:2d0ef4830603 385 do{
cpm219 0:2d0ef4830603 386 getfreespace = fifo_Freespace( );
cpm219 0:2d0ef4830603 387 }while(getfreespace < count);
cpm219 0:2d0ef4830603 388 }
cpm219 0:2d0ef4830603 389
cpm219 0:2d0ef4830603 390 ft_void_t FT800::WaitCmdfifo_empty( )
cpm219 0:2d0ef4830603 391 {
cpm219 0:2d0ef4830603 392 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
cpm219 0:2d0ef4830603 393
cpm219 0:2d0ef4830603 394 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 395 }
cpm219 0:2d0ef4830603 396
cpm219 0:2d0ef4830603 397 ft_void_t FT800::WaitLogo_Finish( )
cpm219 0:2d0ef4830603 398 {
cpm219 0:2d0ef4830603 399 ft_int16_t cmdrdptr,cmdwrptr;
cpm219 0:2d0ef4830603 400
cpm219 0:2d0ef4830603 401 do{
cpm219 0:2d0ef4830603 402 cmdrdptr = Rd16( REG_CMD_READ);
cpm219 0:2d0ef4830603 403 cmdwrptr = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 404 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
cpm219 0:2d0ef4830603 405 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 406 }
cpm219 0:2d0ef4830603 407
cpm219 0:2d0ef4830603 408
cpm219 0:2d0ef4830603 409 ft_void_t FT800::ResetCmdFifo( )
cpm219 0:2d0ef4830603 410 {
cpm219 0:2d0ef4830603 411 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 412 }
cpm219 0:2d0ef4830603 413
cpm219 0:2d0ef4830603 414
cpm219 0:2d0ef4830603 415 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
cpm219 0:2d0ef4830603 416 {
cpm219 0:2d0ef4830603 417 CheckCmdBuffer( sizeof(cmd));
cpm219 0:2d0ef4830603 418
cpm219 0:2d0ef4830603 419 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
cpm219 0:2d0ef4830603 420
cpm219 0:2d0ef4830603 421 Updatecmdfifo( sizeof(cmd));
cpm219 0:2d0ef4830603 422 }
cpm219 0:2d0ef4830603 423
cpm219 0:2d0ef4830603 424
cpm219 0:2d0ef4830603 425 ft_void_t FT800::ResetDLBuffer( )
cpm219 0:2d0ef4830603 426 {
cpm219 0:2d0ef4830603 427 dl_buff_wp = 0;
cpm219 0:2d0ef4830603 428 }
cpm219 0:2d0ef4830603 429
cpm219 0:2d0ef4830603 430 /* Toggle PD_N pin of FT800 board for a power cycle*/
cpm219 0:2d0ef4830603 431 ft_void_t FT800::Powercycle( ft_bool_t up)
cpm219 0:2d0ef4830603 432 {
cpm219 0:2d0ef4830603 433 if (up)
cpm219 0:2d0ef4830603 434 {
cpm219 0:2d0ef4830603 435 //Toggle PD_N from low to high for power up switch
cpm219 0:2d0ef4830603 436 _pd = 0;
cpm219 0:2d0ef4830603 437 Sleep(20);
cpm219 0:2d0ef4830603 438
cpm219 0:2d0ef4830603 439 _pd = 1;
cpm219 0:2d0ef4830603 440 Sleep(20);
cpm219 0:2d0ef4830603 441 }else
cpm219 0:2d0ef4830603 442 {
cpm219 0:2d0ef4830603 443 //Toggle PD_N from high to low for power down switch
cpm219 0:2d0ef4830603 444 _pd = 1;
cpm219 0:2d0ef4830603 445 Sleep(20);
cpm219 0:2d0ef4830603 446
cpm219 0:2d0ef4830603 447 _pd = 0;
cpm219 0:2d0ef4830603 448 Sleep(20);
cpm219 0:2d0ef4830603 449 }
cpm219 0:2d0ef4830603 450 }
cpm219 0:2d0ef4830603 451
cpm219 0:2d0ef4830603 452 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 453 {
cpm219 0:2d0ef4830603 454 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 455
cpm219 0:2d0ef4830603 456 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 457
cpm219 0:2d0ef4830603 458 while (length--) {
cpm219 0:2d0ef4830603 459 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 460 buffer++;
cpm219 0:2d0ef4830603 461 }
cpm219 0:2d0ef4830603 462
cpm219 0:2d0ef4830603 463 EndTransfer( );
cpm219 0:2d0ef4830603 464 }
cpm219 0:2d0ef4830603 465
cpm219 0:2d0ef4830603 466 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 467 {
cpm219 0:2d0ef4830603 468 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 469
cpm219 0:2d0ef4830603 470 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 471
cpm219 0:2d0ef4830603 472 while (length--) {
cpm219 0:2d0ef4830603 473 Transfer8( *buffer);
cpm219 0:2d0ef4830603 474 buffer++;
cpm219 0:2d0ef4830603 475 }
cpm219 0:2d0ef4830603 476
cpm219 0:2d0ef4830603 477 EndTransfer( );
cpm219 0:2d0ef4830603 478 }
cpm219 0:2d0ef4830603 479
cpm219 0:2d0ef4830603 480
cpm219 0:2d0ef4830603 481 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 482 {
cpm219 0:2d0ef4830603 483 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 484
cpm219 0:2d0ef4830603 485 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 486
cpm219 0:2d0ef4830603 487 while (length--) {
cpm219 0:2d0ef4830603 488 *buffer = Transfer8( 0);
cpm219 0:2d0ef4830603 489 buffer++;
cpm219 0:2d0ef4830603 490 }
cpm219 0:2d0ef4830603 491
cpm219 0:2d0ef4830603 492 EndTransfer( );
cpm219 0:2d0ef4830603 493 }
cpm219 0:2d0ef4830603 494
cpm219 0:2d0ef4830603 495 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
cpm219 0:2d0ef4830603 496 {
cpm219 0:2d0ef4830603 497 ft_int16_t Length;
cpm219 0:2d0ef4830603 498 ft_char8_t *pdst,charval;
cpm219 0:2d0ef4830603 499 ft_int32_t CurrVal = value,tmpval,i;
cpm219 0:2d0ef4830603 500 ft_char8_t tmparray[16],idx = 0;
cpm219 0:2d0ef4830603 501
cpm219 0:2d0ef4830603 502 Length = strlen(pSrc);
cpm219 0:2d0ef4830603 503 pdst = pSrc + Length;
cpm219 0:2d0ef4830603 504
cpm219 0:2d0ef4830603 505 if(0 == value)
cpm219 0:2d0ef4830603 506 {
cpm219 0:2d0ef4830603 507 *pdst++ = '0';
cpm219 0:2d0ef4830603 508 *pdst++ = '\0';
cpm219 0:2d0ef4830603 509 return 0;
cpm219 0:2d0ef4830603 510 }
cpm219 0:2d0ef4830603 511
cpm219 0:2d0ef4830603 512 if(CurrVal < 0)
cpm219 0:2d0ef4830603 513 {
cpm219 0:2d0ef4830603 514 *pdst++ = '-';
cpm219 0:2d0ef4830603 515 CurrVal = - CurrVal;
cpm219 0:2d0ef4830603 516 }
cpm219 0:2d0ef4830603 517 /* insert the value */
cpm219 0:2d0ef4830603 518 while(CurrVal > 0){
cpm219 0:2d0ef4830603 519 tmpval = CurrVal;
cpm219 0:2d0ef4830603 520 CurrVal /= 10;
cpm219 0:2d0ef4830603 521 tmpval = tmpval - CurrVal*10;
cpm219 0:2d0ef4830603 522 charval = '0' + tmpval;
cpm219 0:2d0ef4830603 523 tmparray[idx++] = charval;
cpm219 0:2d0ef4830603 524 }
cpm219 0:2d0ef4830603 525
cpm219 0:2d0ef4830603 526 for(i=0;i<idx;i++)
cpm219 0:2d0ef4830603 527 {
cpm219 0:2d0ef4830603 528 *pdst++ = tmparray[idx - i - 1];
cpm219 0:2d0ef4830603 529 }
cpm219 0:2d0ef4830603 530 *pdst++ = '\0';
cpm219 0:2d0ef4830603 531
cpm219 0:2d0ef4830603 532 return 0;
cpm219 0:2d0ef4830603 533 }
cpm219 0:2d0ef4830603 534
cpm219 0:2d0ef4830603 535
cpm219 0:2d0ef4830603 536 ft_void_t FT800::Sleep(ft_uint16_t ms)
cpm219 0:2d0ef4830603 537 {
cpm219 0:2d0ef4830603 538 wait_ms(ms);
cpm219 0:2d0ef4830603 539 }
cpm219 0:2d0ef4830603 540
cpm219 0:2d0ef4830603 541 ft_void_t FT800::Sound_ON(){
cpm219 0:2d0ef4830603 542 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 543 }
cpm219 0:2d0ef4830603 544
cpm219 0:2d0ef4830603 545 ft_void_t FT800::Sound_OFF(){
cpm219 0:2d0ef4830603 546 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 547 }
cpm219 0:2d0ef4830603 548
cpm219 0:2d0ef4830603 549
cpm219 0:2d0ef4830603 550
cpm219 0:2d0ef4830603 551