Denis Nyzovets / FT810

Library for FT810 EVE chip

Fork of FT810 by Curtis Mattull

src/FT_GPU_Hal.cpp@10:4c10e6aeb239, 2017-09-16 (annotated)

Committer:
mozillain
Date:
Sat Sep 16 18:34:14 2017 +0000
Revision:
10:4c10e6aeb239
Parent:
8:b5a41d1581ad
Child:
11:435747a1f2ae
Temp

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cpm219 0:2d0ef4830603 1 #include "FT_Platform.h"
cpm219 0:2d0ef4830603 2 #include "mbed.h"
cpm219 0:2d0ef4830603 3 #include "FT_LCD_Type.h"
cpm219 0:2d0ef4830603 4
cpm219 0:2d0ef4830603 5 FT800::FT800(PinName mosi,
cpm219 0:2d0ef4830603 6 PinName miso,
cpm219 0:2d0ef4830603 7 PinName sck,
cpm219 0:2d0ef4830603 8 PinName ss,
cpm219 0:2d0ef4830603 9 PinName intr,
cpm219 0:2d0ef4830603 10 PinName pd)
cpm219 0:2d0ef4830603 11 :
cpm219 5:506e2de9a9e6 12
cpm219 0:2d0ef4830603 13 _spi(mosi, miso, sck),
cpm219 0:2d0ef4830603 14 _ss(ss),
cpm219 0:2d0ef4830603 15 _pd(pd),
cpm219 0:2d0ef4830603 16 _f800_isr(InterruptIn(intr))
cpm219 0:2d0ef4830603 17 {
cpm219 0:2d0ef4830603 18 _spi.format(8,0); // 8 bit spi mode 0
cpm219 6:ce30c1530d71 19 _spi.frequency(1000000); // start with 10 Mhz SPI clock
cpm219 0:2d0ef4830603 20 _ss = 1; // cs high
cpm219 0:2d0ef4830603 21 _pd = 1; // PD high
cpm219 0:2d0ef4830603 22 Bootup();
cpm219 0:2d0ef4830603 23 }
cpm219 0:2d0ef4830603 24
cpm219 0:2d0ef4830603 25
cpm219 0:2d0ef4830603 26 ft_bool_t FT800::Bootup(void){
mozillain 10:4c10e6aeb239 27 //pc.printf("Bootup() entered\r\n");
cpm219 0:2d0ef4830603 28 Open();
cpm219 5:506e2de9a9e6 29
cpm219 0:2d0ef4830603 30 BootupConfig();
cpm219 0:2d0ef4830603 31
cpm219 0:2d0ef4830603 32 return(1);
cpm219 0:2d0ef4830603 33 }
cpm219 0:2d0ef4830603 34
cpm219 0:2d0ef4830603 35
cpm219 0:2d0ef4830603 36 ft_void_t FT800::BootupConfig(void){
cpm219 0:2d0ef4830603 37 ft_uint8_t chipid;
cpm219 0:2d0ef4830603 38 /* Do a power cycle for safer side */
cpm219 0:2d0ef4830603 39 Powercycle( FT_TRUE);
cpm219 0:2d0ef4830603 40 /*
cpm219 0:2d0ef4830603 41 7/8/16: Curt added the sleep delay below...
cpm219 0:2d0ef4830603 42 */
cpm219 0:2d0ef4830603 43 // Sleep(30);
cpm219 0:2d0ef4830603 44
cpm219 0:2d0ef4830603 45 /* Set the clk to external clock */
cpm219 0:2d0ef4830603 46 HostCommand( FT_GPU_EXTERNAL_OSC);
cpm219 0:2d0ef4830603 47 Sleep(10);
cpm219 0:2d0ef4830603 48
cpm219 0:2d0ef4830603 49 /* Access address 0 to wake up the FT800 */
cpm219 0:2d0ef4830603 50 HostCommand( FT_GPU_ACTIVE_M);
cpm219 0:2d0ef4830603 51 Sleep(500);
cpm219 0:2d0ef4830603 52
cpm219 0:2d0ef4830603 53 /* Switch PLL output to 48MHz */
cpm219 0:2d0ef4830603 54 // HostCommand( FT_GPU_PLL_48M);
cpm219 0:2d0ef4830603 55 Sleep(10);
cpm219 0:2d0ef4830603 56
cpm219 0:2d0ef4830603 57 /* Do a core reset for safer side */
cpm219 0:2d0ef4830603 58 HostCommand( FT_GPU_CORE_RESET);
cpm219 0:2d0ef4830603 59 Sleep(500);
cpm219 0:2d0ef4830603 60 //Read Register ID to check if FT800 is ready.
cpm219 0:2d0ef4830603 61 chipid = Rd8( REG_ID);
cpm219 0:2d0ef4830603 62 while(chipid != 0x7C)
mozillain 10:4c10e6aeb239 63
cpm219 0:2d0ef4830603 64 // Speed up
cpm219 8:b5a41d1581ad 65 _spi.frequency(30000000); // 30 Mhz SPI clock DC
cpm219 5:506e2de9a9e6 66 // _spi.frequency(20000000); // 20 Mhz SPI clock DC
cpm219 8:b5a41d1581ad 67 // _spi.frequency(12000000); // 12 Mhz SPI clock
cpm219 0:2d0ef4830603 68 /* Configuration of LCD display */
cpm219 0:2d0ef4830603 69 DispHCycle = my_DispHCycle;
cpm219 0:2d0ef4830603 70 Wr16( REG_HCYCLE, DispHCycle);
cpm219 0:2d0ef4830603 71 DispHOffset = my_DispHOffset;
cpm219 0:2d0ef4830603 72 Wr16( REG_HOFFSET, DispHOffset);
cpm219 0:2d0ef4830603 73 DispWidth = my_DispWidth;
cpm219 0:2d0ef4830603 74 Wr16( REG_HSIZE, DispWidth);
cpm219 0:2d0ef4830603 75 DispHSync0 = my_DispHSync0;
cpm219 0:2d0ef4830603 76 Wr16( REG_HSYNC0, DispHSync0);
cpm219 0:2d0ef4830603 77 DispHSync1 = my_DispHSync1;
cpm219 0:2d0ef4830603 78 Wr16( REG_HSYNC1, DispHSync1);
cpm219 0:2d0ef4830603 79 DispVCycle = my_DispVCycle;
cpm219 0:2d0ef4830603 80 Wr16( REG_VCYCLE, DispVCycle);
cpm219 0:2d0ef4830603 81 DispVOffset = my_DispVOffset;
cpm219 0:2d0ef4830603 82 Wr16( REG_VOFFSET, DispVOffset);
cpm219 0:2d0ef4830603 83 DispHeight = my_DispHeight;
cpm219 0:2d0ef4830603 84 Wr16( REG_VSIZE, DispHeight);
cpm219 0:2d0ef4830603 85 DispVSync0 = my_DispVSync0;
cpm219 0:2d0ef4830603 86 Wr16( REG_VSYNC0, DispVSync0);
cpm219 0:2d0ef4830603 87 DispVSync1 = my_DispVSync1;
cpm219 0:2d0ef4830603 88 Wr16( REG_VSYNC1, DispVSync1);
cpm219 0:2d0ef4830603 89 DispSwizzle = my_DispSwizzle;
cpm219 0:2d0ef4830603 90 Wr8( REG_SWIZZLE, DispSwizzle);
cpm219 0:2d0ef4830603 91 DispPCLKPol = my_DispPCLKPol;
cpm219 0:2d0ef4830603 92 Wr8( REG_PCLK_POL, DispPCLKPol);
mozillain 10:4c10e6aeb239 93 Wr8( REG_CSPREAD, 0);
cpm219 0:2d0ef4830603 94 DispPCLK = my_DispPCLK;
cpm219 0:2d0ef4830603 95 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
mozillain 10:4c10e6aeb239 96
mozillain 10:4c10e6aeb239 97 ft_uint8_t temp = Rd8(REG_PCLK);
mozillain 10:4c10e6aeb239 98 if (temp!=DispPCLK){DigitalOut led(LED1); led=1;}
mozillain 10:4c10e6aeb239 99 Serial pc(SERIAL_TX, SERIAL_RX);
mozillain 10:4c10e6aeb239 100 ft_uint8_t chipid1 = Rd8(0x0C0000);
mozillain 10:4c10e6aeb239 101 pc.printf("ID:%08X\n", chipid1);
cpm219 0:2d0ef4830603 102
cpm219 4:03932ce8a04e 103 Wr16( REG_PWM_HZ, 10000);
mozillain 10:4c10e6aeb239 104 pc.printf("ID:%08X\n", Rd16(REG_PWM_HZ));
cpm219 4:03932ce8a04e 105 //#ifdef Inv_Backlite // turn on backlite
mozillain 10:4c10e6aeb239 106 //Wr16( REG_PWM_DUTY, 0);
cpm219 4:03932ce8a04e 107 //#else
cpm219 5:506e2de9a9e6 108 Wr16( REG_PWM_DUTY, 127);
cpm219 4:03932ce8a04e 109 //#endif
cpm219 0:2d0ef4830603 110 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
cpm219 0:2d0ef4830603 111 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 112
cpm219 0:2d0ef4830603 113 Wr32( RAM_DL, CLEAR(1,1,1));
cpm219 0:2d0ef4830603 114 Wr32( RAM_DL+4, DISPLAY());
cpm219 0:2d0ef4830603 115 Wr32( REG_DLSWAP,1);
cpm219 0:2d0ef4830603 116
cpm219 0:2d0ef4830603 117 Wr16( REG_PCLK, DispPCLK);
cpm219 0:2d0ef4830603 118
cpm219 0:2d0ef4830603 119 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
mozillain 10:4c10e6aeb239 120 Wr16( REG_TOUCH_RZTHRESH,1200);
mozillain 10:4c10e6aeb239 121 // Wr16( REG_TOUCH_RZTHRESH,0xFFFF);
cpm219 0:2d0ef4830603 122
cpm219 0:2d0ef4830603 123 }
cpm219 0:2d0ef4830603 124
cpm219 0:2d0ef4830603 125
cpm219 0:2d0ef4830603 126
cpm219 0:2d0ef4830603 127 /* API to initialize the SPI interface */
cpm219 0:2d0ef4830603 128 ft_bool_t FT800::Init()
cpm219 0:2d0ef4830603 129 {
cpm219 0:2d0ef4830603 130 // is done in constructor
cpm219 0:2d0ef4830603 131 return 1;
cpm219 0:2d0ef4830603 132 }
cpm219 0:2d0ef4830603 133
cpm219 0:2d0ef4830603 134
cpm219 0:2d0ef4830603 135 ft_bool_t FT800::Open()
cpm219 0:2d0ef4830603 136 {
cpm219 0:2d0ef4830603 137 cmd_fifo_wp = dl_buff_wp = 0;
cpm219 0:2d0ef4830603 138 status = OPENED;
cpm219 0:2d0ef4830603 139 return 1;
cpm219 0:2d0ef4830603 140 }
cpm219 0:2d0ef4830603 141
cpm219 0:2d0ef4830603 142 ft_void_t FT800::Close( )
cpm219 0:2d0ef4830603 143 {
cpm219 0:2d0ef4830603 144 status = CLOSED;
cpm219 0:2d0ef4830603 145 }
cpm219 0:2d0ef4830603 146
cpm219 0:2d0ef4830603 147 ft_void_t FT800::DeInit()
cpm219 0:2d0ef4830603 148 {
cpm219 0:2d0ef4830603 149
cpm219 0:2d0ef4830603 150 }
cpm219 0:2d0ef4830603 151
cpm219 0:2d0ef4830603 152 /*The APIs for reading/writing transfer continuously only with small buffer system*/
cpm219 0:2d0ef4830603 153 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
cpm219 0:2d0ef4830603 154 {
cpm219 0:2d0ef4830603 155 if (FT_GPU_READ == rw){
cpm219 0:2d0ef4830603 156 _ss = 0; // cs low
cpm219 0:2d0ef4830603 157 _spi.write(addr >> 16);
cpm219 0:2d0ef4830603 158 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 159 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 160 _spi.write(0); //Dummy Read Byte
cpm219 0:2d0ef4830603 161 status = READING;
cpm219 0:2d0ef4830603 162 }else{
cpm219 0:2d0ef4830603 163 _ss = 0; // cs low
cpm219 0:2d0ef4830603 164 _spi.write(0x80 | (addr >> 16));
cpm219 0:2d0ef4830603 165 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 166 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 167 status = WRITING;
cpm219 0:2d0ef4830603 168 }
cpm219 0:2d0ef4830603 169 }
cpm219 0:2d0ef4830603 170
cpm219 0:2d0ef4830603 171
cpm219 0:2d0ef4830603 172 /*The APIs for writing transfer continuously only*/
cpm219 0:2d0ef4830603 173 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
cpm219 0:2d0ef4830603 174 {
cpm219 0:2d0ef4830603 175 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
cpm219 0:2d0ef4830603 176 }
cpm219 0:2d0ef4830603 177
cpm219 0:2d0ef4830603 178 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
cpm219 0:2d0ef4830603 179 {
cpm219 0:2d0ef4830603 180 ft_uint16_t length = strlen(string);
cpm219 0:2d0ef4830603 181 while(length --){
cpm219 0:2d0ef4830603 182 Transfer8( *string);
cpm219 0:2d0ef4830603 183 string ++;
cpm219 0:2d0ef4830603 184 }
cpm219 0:2d0ef4830603 185 //Append one null as ending flag
cpm219 0:2d0ef4830603 186 Transfer8( 0);
cpm219 0:2d0ef4830603 187 return(1);
cpm219 0:2d0ef4830603 188 }
cpm219 0:2d0ef4830603 189
cpm219 0:2d0ef4830603 190
cpm219 0:2d0ef4830603 191 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
cpm219 0:2d0ef4830603 192 {
cpm219 0:2d0ef4830603 193 return _spi.write(value);
cpm219 0:2d0ef4830603 194 }
cpm219 0:2d0ef4830603 195
cpm219 0:2d0ef4830603 196
cpm219 0:2d0ef4830603 197 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
cpm219 0:2d0ef4830603 198 {
cpm219 0:2d0ef4830603 199 ft_uint16_t retVal = 0;
cpm219 0:2d0ef4830603 200
cpm219 0:2d0ef4830603 201 if (status == WRITING){
cpm219 0:2d0ef4830603 202 Transfer8( value & 0xFF);//LSB first
cpm219 0:2d0ef4830603 203 Transfer8( (value >> 8) & 0xFF);
cpm219 0:2d0ef4830603 204 }else{
cpm219 0:2d0ef4830603 205 retVal = Transfer8( 0);
cpm219 0:2d0ef4830603 206 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
cpm219 0:2d0ef4830603 207 }
cpm219 0:2d0ef4830603 208
cpm219 0:2d0ef4830603 209 return retVal;
cpm219 0:2d0ef4830603 210 }
cpm219 0:2d0ef4830603 211
cpm219 0:2d0ef4830603 212 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
cpm219 0:2d0ef4830603 213 {
cpm219 0:2d0ef4830603 214 ft_uint32_t retVal = 0;
cpm219 0:2d0ef4830603 215 if (status == WRITING){
cpm219 0:2d0ef4830603 216 Transfer16( value & 0xFFFF);//LSB first
cpm219 0:2d0ef4830603 217 Transfer16( (value >> 16) & 0xFFFF);
cpm219 0:2d0ef4830603 218 }else{
cpm219 0:2d0ef4830603 219 retVal = Transfer16( 0);
cpm219 0:2d0ef4830603 220 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
cpm219 0:2d0ef4830603 221 }
cpm219 0:2d0ef4830603 222 return retVal;
cpm219 0:2d0ef4830603 223 }
cpm219 0:2d0ef4830603 224
cpm219 0:2d0ef4830603 225 ft_void_t FT800::EndTransfer( )
cpm219 0:2d0ef4830603 226 {
cpm219 0:2d0ef4830603 227 _ss = 1;
cpm219 0:2d0ef4830603 228 status = OPENED;
cpm219 0:2d0ef4830603 229 }
cpm219 0:2d0ef4830603 230
cpm219 0:2d0ef4830603 231
cpm219 0:2d0ef4830603 232 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
cpm219 0:2d0ef4830603 233 {
cpm219 0:2d0ef4830603 234 ft_uint8_t value;
cpm219 0:2d0ef4830603 235 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 236 value = Transfer8( 0);
cpm219 0:2d0ef4830603 237 EndTransfer( );
cpm219 0:2d0ef4830603 238 return value;
cpm219 0:2d0ef4830603 239 }
cpm219 0:2d0ef4830603 240 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
cpm219 0:2d0ef4830603 241 {
cpm219 0:2d0ef4830603 242 ft_uint16_t value;
cpm219 0:2d0ef4830603 243 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 244 value = Transfer16( 0);
cpm219 0:2d0ef4830603 245 EndTransfer( );
cpm219 0:2d0ef4830603 246 return value;
cpm219 0:2d0ef4830603 247 }
cpm219 0:2d0ef4830603 248 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
cpm219 0:2d0ef4830603 249 {
cpm219 0:2d0ef4830603 250 ft_uint32_t value;
cpm219 0:2d0ef4830603 251 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 252 value = Transfer32( 0);
cpm219 0:2d0ef4830603 253 EndTransfer( );
cpm219 0:2d0ef4830603 254 return value;
cpm219 0:2d0ef4830603 255 }
cpm219 0:2d0ef4830603 256
cpm219 0:2d0ef4830603 257 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
cpm219 0:2d0ef4830603 258 {
cpm219 0:2d0ef4830603 259 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 260 Transfer8( v);
cpm219 0:2d0ef4830603 261 EndTransfer( );
cpm219 0:2d0ef4830603 262 }
cpm219 0:2d0ef4830603 263 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
cpm219 0:2d0ef4830603 264 {
cpm219 0:2d0ef4830603 265 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 266 Transfer16( v);
cpm219 0:2d0ef4830603 267 EndTransfer( );
cpm219 0:2d0ef4830603 268 }
cpm219 0:2d0ef4830603 269 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
cpm219 0:2d0ef4830603 270 {
cpm219 0:2d0ef4830603 271 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 272 Transfer32( v);
cpm219 0:2d0ef4830603 273 EndTransfer( );
cpm219 0:2d0ef4830603 274 }
cpm219 0:2d0ef4830603 275
cpm219 0:2d0ef4830603 276 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
cpm219 0:2d0ef4830603 277 {
cpm219 0:2d0ef4830603 278 _ss = 0;
cpm219 0:2d0ef4830603 279 _spi.write(cmd);
cpm219 0:2d0ef4830603 280 _spi.write(0);
cpm219 0:2d0ef4830603 281 _spi.write(0);
cpm219 0:2d0ef4830603 282 _ss = 1;
cpm219 0:2d0ef4830603 283 }
cpm219 0:2d0ef4830603 284
cpm219 0:2d0ef4830603 285 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
cpm219 0:2d0ef4830603 286 {
cpm219 0:2d0ef4830603 287 HostCommand( pllsource);
cpm219 0:2d0ef4830603 288 }
cpm219 0:2d0ef4830603 289
cpm219 0:2d0ef4830603 290 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
cpm219 0:2d0ef4830603 291 {
cpm219 0:2d0ef4830603 292 HostCommand( freq);
cpm219 0:2d0ef4830603 293 }
cpm219 0:2d0ef4830603 294
cpm219 0:2d0ef4830603 295 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
cpm219 0:2d0ef4830603 296 {
cpm219 0:2d0ef4830603 297 HostCommand( pwrmode);
cpm219 0:2d0ef4830603 298 }
cpm219 0:2d0ef4830603 299
cpm219 0:2d0ef4830603 300 ft_void_t FT800::CoreReset( )
cpm219 0:2d0ef4830603 301 {
cpm219 0:2d0ef4830603 302 HostCommand( 0x68);
cpm219 0:2d0ef4830603 303 }
cpm219 0:2d0ef4830603 304
cpm219 0:2d0ef4830603 305
cpm219 0:2d0ef4830603 306 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
cpm219 0:2d0ef4830603 307 {
cpm219 0:2d0ef4830603 308 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
cpm219 0:2d0ef4830603 309 //4 byte alignment
cpm219 0:2d0ef4830603 310 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
cpm219 0:2d0ef4830603 311 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
cpm219 0:2d0ef4830603 312 }
cpm219 0:2d0ef4830603 313
cpm219 0:2d0ef4830603 314
cpm219 0:2d0ef4830603 315 ft_uint16_t FT800::fifo_Freespace( )
cpm219 0:2d0ef4830603 316 {
cpm219 0:2d0ef4830603 317 ft_uint16_t fullness,retval;
cpm219 0:2d0ef4830603 318
cpm219 0:2d0ef4830603 319 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
cpm219 0:2d0ef4830603 320 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
cpm219 0:2d0ef4830603 321 return (retval);
cpm219 0:2d0ef4830603 322 }
cpm219 0:2d0ef4830603 323
cpm219 0:2d0ef4830603 324 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 325 {
cpm219 0:2d0ef4830603 326 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 327
cpm219 0:2d0ef4830603 328 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 329 do {
cpm219 0:2d0ef4830603 330 length = count;
cpm219 0:2d0ef4830603 331 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 332 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 333 }
cpm219 0:2d0ef4830603 334 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 335
cpm219 0:2d0ef4830603 336 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 337
cpm219 0:2d0ef4830603 338 SizeTransfered = 0;
cpm219 0:2d0ef4830603 339 while (length--) {
cpm219 0:2d0ef4830603 340 Transfer8( *buffer);
cpm219 0:2d0ef4830603 341 buffer++;
cpm219 0:2d0ef4830603 342 SizeTransfered ++;
cpm219 0:2d0ef4830603 343 }
cpm219 0:2d0ef4830603 344 length = SizeTransfered;
cpm219 0:2d0ef4830603 345
cpm219 0:2d0ef4830603 346 EndTransfer( );
cpm219 0:2d0ef4830603 347 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 348
cpm219 0:2d0ef4830603 349 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 350
cpm219 0:2d0ef4830603 351 count -= length;
cpm219 0:2d0ef4830603 352 }while (count > 0);
cpm219 0:2d0ef4830603 353 }
cpm219 0:2d0ef4830603 354
cpm219 0:2d0ef4830603 355
cpm219 0:2d0ef4830603 356 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 357 {
cpm219 0:2d0ef4830603 358 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 359
cpm219 0:2d0ef4830603 360 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 361 do {
cpm219 0:2d0ef4830603 362 length = count;
cpm219 0:2d0ef4830603 363 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 364 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 365 }
cpm219 0:2d0ef4830603 366 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 367
cpm219 0:2d0ef4830603 368 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 369
cpm219 0:2d0ef4830603 370
cpm219 0:2d0ef4830603 371 SizeTransfered = 0;
cpm219 0:2d0ef4830603 372 while (length--) {
cpm219 0:2d0ef4830603 373 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 374 buffer++;
cpm219 0:2d0ef4830603 375 SizeTransfered ++;
cpm219 0:2d0ef4830603 376 }
cpm219 0:2d0ef4830603 377 length = SizeTransfered;
cpm219 0:2d0ef4830603 378
cpm219 0:2d0ef4830603 379 EndTransfer( );
cpm219 0:2d0ef4830603 380 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 381
cpm219 0:2d0ef4830603 382 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 383
cpm219 0:2d0ef4830603 384 count -= length;
cpm219 0:2d0ef4830603 385 }while (count > 0);
cpm219 0:2d0ef4830603 386 }
cpm219 0:2d0ef4830603 387
cpm219 0:2d0ef4830603 388
cpm219 0:2d0ef4830603 389 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
cpm219 0:2d0ef4830603 390 {
cpm219 0:2d0ef4830603 391 ft_uint16_t getfreespace;
cpm219 0:2d0ef4830603 392 do{
cpm219 0:2d0ef4830603 393 getfreespace = fifo_Freespace( );
cpm219 0:2d0ef4830603 394 }while(getfreespace < count);
cpm219 0:2d0ef4830603 395 }
cpm219 0:2d0ef4830603 396
cpm219 0:2d0ef4830603 397 ft_void_t FT800::WaitCmdfifo_empty( )
cpm219 0:2d0ef4830603 398 {
cpm219 0:2d0ef4830603 399 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
cpm219 0:2d0ef4830603 400
cpm219 0:2d0ef4830603 401 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 402 }
cpm219 0:2d0ef4830603 403
cpm219 0:2d0ef4830603 404 ft_void_t FT800::WaitLogo_Finish( )
cpm219 0:2d0ef4830603 405 {
cpm219 0:2d0ef4830603 406 ft_int16_t cmdrdptr,cmdwrptr;
cpm219 0:2d0ef4830603 407
cpm219 0:2d0ef4830603 408 do{
cpm219 0:2d0ef4830603 409 cmdrdptr = Rd16( REG_CMD_READ);
cpm219 0:2d0ef4830603 410 cmdwrptr = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 411 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
cpm219 0:2d0ef4830603 412 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 413 }
cpm219 0:2d0ef4830603 414
cpm219 0:2d0ef4830603 415
cpm219 0:2d0ef4830603 416 ft_void_t FT800::ResetCmdFifo( )
cpm219 0:2d0ef4830603 417 {
cpm219 0:2d0ef4830603 418 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 419 }
cpm219 0:2d0ef4830603 420
cpm219 0:2d0ef4830603 421
cpm219 0:2d0ef4830603 422 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
cpm219 0:2d0ef4830603 423 {
cpm219 0:2d0ef4830603 424 CheckCmdBuffer( sizeof(cmd));
cpm219 0:2d0ef4830603 425
cpm219 0:2d0ef4830603 426 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
cpm219 0:2d0ef4830603 427
cpm219 0:2d0ef4830603 428 Updatecmdfifo( sizeof(cmd));
cpm219 0:2d0ef4830603 429 }
cpm219 0:2d0ef4830603 430
cpm219 0:2d0ef4830603 431
cpm219 0:2d0ef4830603 432 ft_void_t FT800::ResetDLBuffer( )
cpm219 0:2d0ef4830603 433 {
cpm219 0:2d0ef4830603 434 dl_buff_wp = 0;
cpm219 0:2d0ef4830603 435 }
cpm219 0:2d0ef4830603 436
cpm219 0:2d0ef4830603 437 /* Toggle PD_N pin of FT800 board for a power cycle*/
cpm219 0:2d0ef4830603 438 ft_void_t FT800::Powercycle( ft_bool_t up)
cpm219 0:2d0ef4830603 439 {
cpm219 0:2d0ef4830603 440 if (up)
cpm219 0:2d0ef4830603 441 {
cpm219 0:2d0ef4830603 442 //Toggle PD_N from low to high for power up switch
cpm219 0:2d0ef4830603 443 _pd = 0;
cpm219 0:2d0ef4830603 444 Sleep(20);
cpm219 0:2d0ef4830603 445
cpm219 0:2d0ef4830603 446 _pd = 1;
cpm219 0:2d0ef4830603 447 Sleep(20);
cpm219 0:2d0ef4830603 448 }else
cpm219 0:2d0ef4830603 449 {
cpm219 0:2d0ef4830603 450 //Toggle PD_N from high to low for power down switch
cpm219 0:2d0ef4830603 451 _pd = 1;
cpm219 0:2d0ef4830603 452 Sleep(20);
cpm219 0:2d0ef4830603 453
cpm219 0:2d0ef4830603 454 _pd = 0;
cpm219 0:2d0ef4830603 455 Sleep(20);
cpm219 0:2d0ef4830603 456 }
cpm219 0:2d0ef4830603 457 }
cpm219 0:2d0ef4830603 458
cpm219 0:2d0ef4830603 459 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 460 {
cpm219 0:2d0ef4830603 461 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 462
cpm219 0:2d0ef4830603 463 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 464
cpm219 0:2d0ef4830603 465 while (length--) {
cpm219 0:2d0ef4830603 466 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 467 buffer++;
cpm219 0:2d0ef4830603 468 }
cpm219 0:2d0ef4830603 469
cpm219 0:2d0ef4830603 470 EndTransfer( );
cpm219 0:2d0ef4830603 471 }
cpm219 0:2d0ef4830603 472
cpm219 0:2d0ef4830603 473 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 474 {
cpm219 0:2d0ef4830603 475 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 476
cpm219 0:2d0ef4830603 477 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 478
cpm219 0:2d0ef4830603 479 while (length--) {
cpm219 0:2d0ef4830603 480 Transfer8( *buffer);
cpm219 0:2d0ef4830603 481 buffer++;
cpm219 0:2d0ef4830603 482 }
cpm219 0:2d0ef4830603 483
cpm219 0:2d0ef4830603 484 EndTransfer( );
cpm219 0:2d0ef4830603 485 }
cpm219 0:2d0ef4830603 486
cpm219 0:2d0ef4830603 487
cpm219 0:2d0ef4830603 488 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 489 {
cpm219 0:2d0ef4830603 490 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 491
cpm219 0:2d0ef4830603 492 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 493
cpm219 0:2d0ef4830603 494 while (length--) {
cpm219 0:2d0ef4830603 495 *buffer = Transfer8( 0);
cpm219 0:2d0ef4830603 496 buffer++;
cpm219 0:2d0ef4830603 497 }
cpm219 0:2d0ef4830603 498
cpm219 0:2d0ef4830603 499 EndTransfer( );
cpm219 0:2d0ef4830603 500 }
cpm219 0:2d0ef4830603 501
cpm219 0:2d0ef4830603 502 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
cpm219 0:2d0ef4830603 503 {
cpm219 0:2d0ef4830603 504 ft_int16_t Length;
cpm219 0:2d0ef4830603 505 ft_char8_t *pdst,charval;
cpm219 0:2d0ef4830603 506 ft_int32_t CurrVal = value,tmpval,i;
cpm219 0:2d0ef4830603 507 ft_char8_t tmparray[16],idx = 0;
cpm219 0:2d0ef4830603 508
cpm219 0:2d0ef4830603 509 Length = strlen(pSrc);
cpm219 0:2d0ef4830603 510 pdst = pSrc + Length;
cpm219 0:2d0ef4830603 511
cpm219 0:2d0ef4830603 512 if(0 == value)
cpm219 0:2d0ef4830603 513 {
cpm219 0:2d0ef4830603 514 *pdst++ = '0';
cpm219 0:2d0ef4830603 515 *pdst++ = '\0';
cpm219 0:2d0ef4830603 516 return 0;
cpm219 0:2d0ef4830603 517 }
cpm219 0:2d0ef4830603 518
cpm219 0:2d0ef4830603 519 if(CurrVal < 0)
cpm219 0:2d0ef4830603 520 {
cpm219 0:2d0ef4830603 521 *pdst++ = '-';
cpm219 0:2d0ef4830603 522 CurrVal = - CurrVal;
cpm219 0:2d0ef4830603 523 }
cpm219 0:2d0ef4830603 524 /* insert the value */
cpm219 0:2d0ef4830603 525 while(CurrVal > 0){
cpm219 0:2d0ef4830603 526 tmpval = CurrVal;
cpm219 0:2d0ef4830603 527 CurrVal /= 10;
cpm219 0:2d0ef4830603 528 tmpval = tmpval - CurrVal*10;
cpm219 0:2d0ef4830603 529 charval = '0' + tmpval;
cpm219 0:2d0ef4830603 530 tmparray[idx++] = charval;
cpm219 0:2d0ef4830603 531 }
cpm219 0:2d0ef4830603 532
cpm219 0:2d0ef4830603 533 for(i=0;i<idx;i++)
cpm219 0:2d0ef4830603 534 {
cpm219 0:2d0ef4830603 535 *pdst++ = tmparray[idx - i - 1];
cpm219 0:2d0ef4830603 536 }
cpm219 0:2d0ef4830603 537 *pdst++ = '\0';
cpm219 0:2d0ef4830603 538
cpm219 0:2d0ef4830603 539 return 0;
cpm219 0:2d0ef4830603 540 }
cpm219 0:2d0ef4830603 541
cpm219 0:2d0ef4830603 542
cpm219 0:2d0ef4830603 543 ft_void_t FT800::Sleep(ft_uint16_t ms)
cpm219 0:2d0ef4830603 544 {
cpm219 0:2d0ef4830603 545 wait_ms(ms);
cpm219 0:2d0ef4830603 546 }
cpm219 0:2d0ef4830603 547
cpm219 0:2d0ef4830603 548 ft_void_t FT800::Sound_ON(){
cpm219 0:2d0ef4830603 549 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 550 }
cpm219 0:2d0ef4830603 551
cpm219 0:2d0ef4830603 552 ft_void_t FT800::Sound_OFF(){
cpm219 0:2d0ef4830603 553 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 554 }
cpm219 0:2d0ef4830603 555
cpm219 0:2d0ef4830603 556
cpm219 0:2d0ef4830603 557
cpm219 0:2d0ef4830603 558