test test test
snake-test/mbed/drivers/QSPI.h@0:e4c5e6ec922e, 2020-05-25 (annotated)
- Committer:
- mohamedmoawya
- Date:
- Mon May 25 19:06:11 2020 +0000
- Revision:
- 0:e4c5e6ec922e
snake game tteest
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mohamedmoawya | 0:e4c5e6ec922e | 1 | /* mbed Microcontroller Library |
mohamedmoawya | 0:e4c5e6ec922e | 2 | * Copyright (c) 2006-2018 ARM Limited |
mohamedmoawya | 0:e4c5e6ec922e | 3 | * |
mohamedmoawya | 0:e4c5e6ec922e | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mohamedmoawya | 0:e4c5e6ec922e | 5 | * you may not use this file except in compliance with the License. |
mohamedmoawya | 0:e4c5e6ec922e | 6 | * You may obtain a copy of the License at |
mohamedmoawya | 0:e4c5e6ec922e | 7 | * |
mohamedmoawya | 0:e4c5e6ec922e | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mohamedmoawya | 0:e4c5e6ec922e | 9 | * |
mohamedmoawya | 0:e4c5e6ec922e | 10 | * Unless required by applicable law or agreed to in writing, software |
mohamedmoawya | 0:e4c5e6ec922e | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mohamedmoawya | 0:e4c5e6ec922e | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mohamedmoawya | 0:e4c5e6ec922e | 13 | * See the License for the specific language governing permissions and |
mohamedmoawya | 0:e4c5e6ec922e | 14 | * limitations under the License. |
mohamedmoawya | 0:e4c5e6ec922e | 15 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 16 | #ifndef MBED_QSPI_H |
mohamedmoawya | 0:e4c5e6ec922e | 17 | #define MBED_QSPI_H |
mohamedmoawya | 0:e4c5e6ec922e | 18 | |
mohamedmoawya | 0:e4c5e6ec922e | 19 | #include "platform/platform.h" |
mohamedmoawya | 0:e4c5e6ec922e | 20 | |
mohamedmoawya | 0:e4c5e6ec922e | 21 | #if defined (DEVICE_QSPI) || defined(DOXYGEN_ONLY) |
mohamedmoawya | 0:e4c5e6ec922e | 22 | |
mohamedmoawya | 0:e4c5e6ec922e | 23 | #include "hal/qspi_api.h" |
mohamedmoawya | 0:e4c5e6ec922e | 24 | #include "platform/PlatformMutex.h" |
mohamedmoawya | 0:e4c5e6ec922e | 25 | #include "platform/SingletonPtr.h" |
mohamedmoawya | 0:e4c5e6ec922e | 26 | #include "platform/NonCopyable.h" |
mohamedmoawya | 0:e4c5e6ec922e | 27 | |
mohamedmoawya | 0:e4c5e6ec922e | 28 | #define ONE_MHZ 1000000 |
mohamedmoawya | 0:e4c5e6ec922e | 29 | |
mohamedmoawya | 0:e4c5e6ec922e | 30 | namespace mbed { |
mohamedmoawya | 0:e4c5e6ec922e | 31 | |
mohamedmoawya | 0:e4c5e6ec922e | 32 | /** \addtogroup drivers */ |
mohamedmoawya | 0:e4c5e6ec922e | 33 | |
mohamedmoawya | 0:e4c5e6ec922e | 34 | /** A QSPI Driver, used for communicating with QSPI slave devices |
mohamedmoawya | 0:e4c5e6ec922e | 35 | * |
mohamedmoawya | 0:e4c5e6ec922e | 36 | * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz |
mohamedmoawya | 0:e4c5e6ec922e | 37 | * Most QSPI devices will also require Chip Select which is indicated by ssel. |
mohamedmoawya | 0:e4c5e6ec922e | 38 | * |
mohamedmoawya | 0:e4c5e6ec922e | 39 | * @note Synchronization level: Thread safe |
mohamedmoawya | 0:e4c5e6ec922e | 40 | * |
mohamedmoawya | 0:e4c5e6ec922e | 41 | * Example: |
mohamedmoawya | 0:e4c5e6ec922e | 42 | * @code |
mohamedmoawya | 0:e4c5e6ec922e | 43 | * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined |
mohamedmoawya | 0:e4c5e6ec922e | 44 | * |
mohamedmoawya | 0:e4c5e6ec922e | 45 | * #include "mbed.h" |
mohamedmoawya | 0:e4c5e6ec922e | 46 | * |
mohamedmoawya | 0:e4c5e6ec922e | 47 | * #define CMD_WRITE 0x02 |
mohamedmoawya | 0:e4c5e6ec922e | 48 | * #define CMD_READ 0x03 |
mohamedmoawya | 0:e4c5e6ec922e | 49 | * #define ADDRESS 0x1000 |
mohamedmoawya | 0:e4c5e6ec922e | 50 | * |
mohamedmoawya | 0:e4c5e6ec922e | 51 | * // hardware ssel (where applicable) |
mohamedmoawya | 0:e4c5e6ec922e | 52 | * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel |
mohamedmoawya | 0:e4c5e6ec922e | 53 | * |
mohamedmoawya | 0:e4c5e6ec922e | 54 | * |
mohamedmoawya | 0:e4c5e6ec922e | 55 | * int main() { |
mohamedmoawya | 0:e4c5e6ec922e | 56 | * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 }; |
mohamedmoawya | 0:e4c5e6ec922e | 57 | * char rx_buf[4]; |
mohamedmoawya | 0:e4c5e6ec922e | 58 | * int buf_len = sizeof(tx_buf); |
mohamedmoawya | 0:e4c5e6ec922e | 59 | * |
mohamedmoawya | 0:e4c5e6ec922e | 60 | * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len); |
mohamedmoawya | 0:e4c5e6ec922e | 61 | * if (result != QSPI_STATUS_OK) { |
mohamedmoawya | 0:e4c5e6ec922e | 62 | * printf("Write failed"); |
mohamedmoawya | 0:e4c5e6ec922e | 63 | * } |
mohamedmoawya | 0:e4c5e6ec922e | 64 | * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len); |
mohamedmoawya | 0:e4c5e6ec922e | 65 | * if (result != QSPI_STATUS_OK) { |
mohamedmoawya | 0:e4c5e6ec922e | 66 | * printf("Read failed"); |
mohamedmoawya | 0:e4c5e6ec922e | 67 | * } |
mohamedmoawya | 0:e4c5e6ec922e | 68 | * |
mohamedmoawya | 0:e4c5e6ec922e | 69 | * } |
mohamedmoawya | 0:e4c5e6ec922e | 70 | * @endcode |
mohamedmoawya | 0:e4c5e6ec922e | 71 | * @ingroup drivers |
mohamedmoawya | 0:e4c5e6ec922e | 72 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 73 | class QSPI : private NonCopyable<QSPI> { |
mohamedmoawya | 0:e4c5e6ec922e | 74 | |
mohamedmoawya | 0:e4c5e6ec922e | 75 | public: |
mohamedmoawya | 0:e4c5e6ec922e | 76 | |
mohamedmoawya | 0:e4c5e6ec922e | 77 | /** Create a QSPI master connected to the specified pins |
mohamedmoawya | 0:e4c5e6ec922e | 78 | * |
mohamedmoawya | 0:e4c5e6ec922e | 79 | * io0-io3 is used to specify the Pins used for Quad SPI mode |
mohamedmoawya | 0:e4c5e6ec922e | 80 | * |
mohamedmoawya | 0:e4c5e6ec922e | 81 | * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction |
mohamedmoawya | 0:e4c5e6ec922e | 82 | * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction |
mohamedmoawya | 0:e4c5e6ec922e | 83 | * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction |
mohamedmoawya | 0:e4c5e6ec922e | 84 | * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction |
mohamedmoawya | 0:e4c5e6ec922e | 85 | * @param sclk QSPI Clock pin |
mohamedmoawya | 0:e4c5e6ec922e | 86 | * @param ssel QSPI chip select pin |
mohamedmoawya | 0:e4c5e6ec922e | 87 | * @param mode Clock polarity and phase mode (0 - 3) of SPI |
mohamedmoawya | 0:e4c5e6ec922e | 88 | * (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1) |
mohamedmoawya | 0:e4c5e6ec922e | 89 | * |
mohamedmoawya | 0:e4c5e6ec922e | 90 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 91 | QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0); |
mohamedmoawya | 0:e4c5e6ec922e | 92 | virtual ~QSPI() |
mohamedmoawya | 0:e4c5e6ec922e | 93 | { |
mohamedmoawya | 0:e4c5e6ec922e | 94 | } |
mohamedmoawya | 0:e4c5e6ec922e | 95 | |
mohamedmoawya | 0:e4c5e6ec922e | 96 | /** Configure the data transmission format |
mohamedmoawya | 0:e4c5e6ec922e | 97 | * |
mohamedmoawya | 0:e4c5e6ec922e | 98 | * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) |
mohamedmoawya | 0:e4c5e6ec922e | 99 | * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) |
mohamedmoawya | 0:e4c5e6ec922e | 100 | * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32) |
mohamedmoawya | 0:e4c5e6ec922e | 101 | * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) |
mohamedmoawya | 0:e4c5e6ec922e | 102 | * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32) |
mohamedmoawya | 0:e4c5e6ec922e | 103 | * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) |
mohamedmoawya | 0:e4c5e6ec922e | 104 | * @param dummy_cycles Number of dummy clock cycles to be used after alt phase |
mohamedmoawya | 0:e4c5e6ec922e | 105 | * |
mohamedmoawya | 0:e4c5e6ec922e | 106 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 107 | qspi_status_t configure_format(qspi_bus_width_t inst_width, |
mohamedmoawya | 0:e4c5e6ec922e | 108 | qspi_bus_width_t address_width, |
mohamedmoawya | 0:e4c5e6ec922e | 109 | qspi_address_size_t address_size, |
mohamedmoawya | 0:e4c5e6ec922e | 110 | qspi_bus_width_t alt_width, |
mohamedmoawya | 0:e4c5e6ec922e | 111 | qspi_alt_size_t alt_size, |
mohamedmoawya | 0:e4c5e6ec922e | 112 | qspi_bus_width_t data_width, |
mohamedmoawya | 0:e4c5e6ec922e | 113 | int dummy_cycles); |
mohamedmoawya | 0:e4c5e6ec922e | 114 | |
mohamedmoawya | 0:e4c5e6ec922e | 115 | /** Set the qspi bus clock frequency |
mohamedmoawya | 0:e4c5e6ec922e | 116 | * |
mohamedmoawya | 0:e4c5e6ec922e | 117 | * @param hz SCLK frequency in hz (default = 1MHz) |
mohamedmoawya | 0:e4c5e6ec922e | 118 | * @returns |
mohamedmoawya | 0:e4c5e6ec922e | 119 | * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed |
mohamedmoawya | 0:e4c5e6ec922e | 120 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 121 | qspi_status_t set_frequency(int hz = ONE_MHZ); |
mohamedmoawya | 0:e4c5e6ec922e | 122 | |
mohamedmoawya | 0:e4c5e6ec922e | 123 | /** Read from QSPI peripheral with the preset read_instruction and alt_value |
mohamedmoawya | 0:e4c5e6ec922e | 124 | * |
mohamedmoawya | 0:e4c5e6ec922e | 125 | * @param address Address to be accessed in QSPI peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 126 | * @param rx_buffer Buffer for data to be read from the peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 127 | * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read |
mohamedmoawya | 0:e4c5e6ec922e | 128 | * |
mohamedmoawya | 0:e4c5e6ec922e | 129 | * @returns |
mohamedmoawya | 0:e4c5e6ec922e | 130 | * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads. |
mohamedmoawya | 0:e4c5e6ec922e | 131 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 132 | qspi_status_t read(int address, char *rx_buffer, size_t *rx_length); |
mohamedmoawya | 0:e4c5e6ec922e | 133 | |
mohamedmoawya | 0:e4c5e6ec922e | 134 | /** Write to QSPI peripheral using custom write instruction |
mohamedmoawya | 0:e4c5e6ec922e | 135 | * |
mohamedmoawya | 0:e4c5e6ec922e | 136 | * @param address Address to be accessed in QSPI peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 137 | * @param tx_buffer Buffer containing data to be sent to peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 138 | * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written |
mohamedmoawya | 0:e4c5e6ec922e | 139 | * |
mohamedmoawya | 0:e4c5e6ec922e | 140 | * @returns |
mohamedmoawya | 0:e4c5e6ec922e | 141 | * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads. |
mohamedmoawya | 0:e4c5e6ec922e | 142 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 143 | qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length); |
mohamedmoawya | 0:e4c5e6ec922e | 144 | |
mohamedmoawya | 0:e4c5e6ec922e | 145 | /** Read from QSPI peripheral using custom read instruction, alt values |
mohamedmoawya | 0:e4c5e6ec922e | 146 | * |
mohamedmoawya | 0:e4c5e6ec922e | 147 | * @param instruction Instruction value to be used in instruction phase |
mohamedmoawya | 0:e4c5e6ec922e | 148 | * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase |
mohamedmoawya | 0:e4c5e6ec922e | 149 | * @param address Address to be accessed in QSPI peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 150 | * @param rx_buffer Buffer for data to be read from the peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 151 | * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read |
mohamedmoawya | 0:e4c5e6ec922e | 152 | * |
mohamedmoawya | 0:e4c5e6ec922e | 153 | * @returns |
mohamedmoawya | 0:e4c5e6ec922e | 154 | * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads. |
mohamedmoawya | 0:e4c5e6ec922e | 155 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 156 | qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length); |
mohamedmoawya | 0:e4c5e6ec922e | 157 | |
mohamedmoawya | 0:e4c5e6ec922e | 158 | /** Write to QSPI peripheral using custom write instruction, alt values |
mohamedmoawya | 0:e4c5e6ec922e | 159 | * |
mohamedmoawya | 0:e4c5e6ec922e | 160 | * @param instruction Instruction value to be used in instruction phase |
mohamedmoawya | 0:e4c5e6ec922e | 161 | * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase |
mohamedmoawya | 0:e4c5e6ec922e | 162 | * @param address Address to be accessed in QSPI peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 163 | * @param tx_buffer Buffer containing data to be sent to peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 164 | * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written |
mohamedmoawya | 0:e4c5e6ec922e | 165 | * |
mohamedmoawya | 0:e4c5e6ec922e | 166 | * @returns |
mohamedmoawya | 0:e4c5e6ec922e | 167 | * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads. |
mohamedmoawya | 0:e4c5e6ec922e | 168 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 169 | qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length); |
mohamedmoawya | 0:e4c5e6ec922e | 170 | |
mohamedmoawya | 0:e4c5e6ec922e | 171 | /** Perform a transaction to write to an address(a control register) and get the status results |
mohamedmoawya | 0:e4c5e6ec922e | 172 | * |
mohamedmoawya | 0:e4c5e6ec922e | 173 | * @param instruction Instruction value to be used in instruction phase |
mohamedmoawya | 0:e4c5e6ec922e | 174 | * @param address Some instruction might require address. Use -1 if no address |
mohamedmoawya | 0:e4c5e6ec922e | 175 | * @param tx_buffer Buffer containing data to be sent to peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 176 | * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written |
mohamedmoawya | 0:e4c5e6ec922e | 177 | * @param rx_buffer Buffer for data to be read from the peripheral |
mohamedmoawya | 0:e4c5e6ec922e | 178 | * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read |
mohamedmoawya | 0:e4c5e6ec922e | 179 | * |
mohamedmoawya | 0:e4c5e6ec922e | 180 | * @returns |
mohamedmoawya | 0:e4c5e6ec922e | 181 | * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads. |
mohamedmoawya | 0:e4c5e6ec922e | 182 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 183 | qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length); |
mohamedmoawya | 0:e4c5e6ec922e | 184 | |
mohamedmoawya | 0:e4c5e6ec922e | 185 | #if !defined(DOXYGEN_ONLY) |
mohamedmoawya | 0:e4c5e6ec922e | 186 | protected: |
mohamedmoawya | 0:e4c5e6ec922e | 187 | /** Acquire exclusive access to this SPI bus |
mohamedmoawya | 0:e4c5e6ec922e | 188 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 189 | virtual void lock(void); |
mohamedmoawya | 0:e4c5e6ec922e | 190 | |
mohamedmoawya | 0:e4c5e6ec922e | 191 | /** Release exclusive access to this SPI bus |
mohamedmoawya | 0:e4c5e6ec922e | 192 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 193 | virtual void unlock(void); |
mohamedmoawya | 0:e4c5e6ec922e | 194 | |
mohamedmoawya | 0:e4c5e6ec922e | 195 | qspi_t _qspi; |
mohamedmoawya | 0:e4c5e6ec922e | 196 | |
mohamedmoawya | 0:e4c5e6ec922e | 197 | bool acquire(void); |
mohamedmoawya | 0:e4c5e6ec922e | 198 | static QSPI *_owner; |
mohamedmoawya | 0:e4c5e6ec922e | 199 | static SingletonPtr<PlatformMutex> _mutex; |
mohamedmoawya | 0:e4c5e6ec922e | 200 | qspi_bus_width_t _inst_width; //Bus width for Instruction phase |
mohamedmoawya | 0:e4c5e6ec922e | 201 | qspi_bus_width_t _address_width; //Bus width for Address phase |
mohamedmoawya | 0:e4c5e6ec922e | 202 | qspi_address_size_t _address_size; |
mohamedmoawya | 0:e4c5e6ec922e | 203 | qspi_bus_width_t _alt_width; //Bus width for Alt phase |
mohamedmoawya | 0:e4c5e6ec922e | 204 | qspi_alt_size_t _alt_size; |
mohamedmoawya | 0:e4c5e6ec922e | 205 | qspi_bus_width_t _data_width; //Bus width for Data phase |
mohamedmoawya | 0:e4c5e6ec922e | 206 | qspi_command_t _qspi_command; //QSPI Hal command struct |
mohamedmoawya | 0:e4c5e6ec922e | 207 | unsigned int _num_dummy_cycles; //Number of dummy cycles to be used |
mohamedmoawya | 0:e4c5e6ec922e | 208 | int _hz; //Bus Frequency |
mohamedmoawya | 0:e4c5e6ec922e | 209 | int _mode; //SPI mode |
mohamedmoawya | 0:e4c5e6ec922e | 210 | bool _initialized; |
mohamedmoawya | 0:e4c5e6ec922e | 211 | PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select |
mohamedmoawya | 0:e4c5e6ec922e | 212 | |
mohamedmoawya | 0:e4c5e6ec922e | 213 | private: |
mohamedmoawya | 0:e4c5e6ec922e | 214 | /* Private acquire function without locking/unlocking |
mohamedmoawya | 0:e4c5e6ec922e | 215 | * Implemented in order to avoid duplicate locking and boost performance |
mohamedmoawya | 0:e4c5e6ec922e | 216 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 217 | bool _acquire(void); |
mohamedmoawya | 0:e4c5e6ec922e | 218 | bool _initialize(); |
mohamedmoawya | 0:e4c5e6ec922e | 219 | |
mohamedmoawya | 0:e4c5e6ec922e | 220 | /* |
mohamedmoawya | 0:e4c5e6ec922e | 221 | * This function builds the qspi command struct to be send to Hal |
mohamedmoawya | 0:e4c5e6ec922e | 222 | */ |
mohamedmoawya | 0:e4c5e6ec922e | 223 | inline void _build_qspi_command(int instruction, int address, int alt); |
mohamedmoawya | 0:e4c5e6ec922e | 224 | #endif |
mohamedmoawya | 0:e4c5e6ec922e | 225 | }; |
mohamedmoawya | 0:e4c5e6ec922e | 226 | |
mohamedmoawya | 0:e4c5e6ec922e | 227 | } // namespace mbed |
mohamedmoawya | 0:e4c5e6ec922e | 228 | |
mohamedmoawya | 0:e4c5e6ec922e | 229 | #endif |
mohamedmoawya | 0:e4c5e6ec922e | 230 | |
mohamedmoawya | 0:e4c5e6ec922e | 231 | #endif |