ADE120x Library Files
ADE120x.h@1:2eb9d6296ec3, 2019-10-03 (annotated)
- Committer:
- mlambe
- Date:
- Thu Oct 03 15:05:59 2019 +0000
- Revision:
- 1:2eb9d6296ec3
- Parent:
- 0:952a6272c495
- Child:
- 2:f9a986799375
Added comments
Who changed what in which revision?
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mlambe | 1:2eb9d6296ec3 | 1 | /** |
mlambe | 1:2eb9d6296ec3 | 2 | * @file ADE120x.h |
mlambe | 1:2eb9d6296ec3 | 3 | * @brief ADE120x library. This file contains all ADE120x library functions. |
mlambe | 1:2eb9d6296ec3 | 4 | * @version V0.0.1 |
mlambe | 1:2eb9d6296ec3 | 5 | * @author ADI |
mlambe | 1:2eb9d6296ec3 | 6 | * @date May 2019 |
mlambe | 1:2eb9d6296ec3 | 7 | * @par Revision History: |
mlambe | 1:2eb9d6296ec3 | 8 | * |
mlambe | 1:2eb9d6296ec3 | 9 | * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. |
mlambe | 1:2eb9d6296ec3 | 10 | * |
mlambe | 1:2eb9d6296ec3 | 11 | * This software is proprietary to Analog Devices, Inc. and its licensors. |
mlambe | 1:2eb9d6296ec3 | 12 | * By using this software you agree to the terms of the associated |
mlambe | 1:2eb9d6296ec3 | 13 | * Analog Devices Software License Agreement. |
mlambe | 1:2eb9d6296ec3 | 14 | **/ |
mlambe | 1:2eb9d6296ec3 | 15 | #ifndef _ADE120x_h_ |
mlambe | 1:2eb9d6296ec3 | 16 | #define _ADE120x_h_ |
mlambe | 1:2eb9d6296ec3 | 17 | |
mlambe | 1:2eb9d6296ec3 | 18 | #include "stdio.h" |
mlambe | 1:2eb9d6296ec3 | 19 | #include "math.h" |
mlambe | 1:2eb9d6296ec3 | 20 | #include "string.h" |
mlambe | 1:2eb9d6296ec3 | 21 | #include <stdint.h> |
mlambe | 1:2eb9d6296ec3 | 22 | |
mlambe | 1:2eb9d6296ec3 | 23 | #include "mbed.h" |
mlambe | 1:2eb9d6296ec3 | 24 | |
mlambe | 1:2eb9d6296ec3 | 25 | /** @addtogroup ADE120x_Library |
mlambe | 1:2eb9d6296ec3 | 26 | * @{ |
mlambe | 1:2eb9d6296ec3 | 27 | */ |
mlambe | 1:2eb9d6296ec3 | 28 | |
mlambe | 1:2eb9d6296ec3 | 29 | typedef struct threshold{ |
mlambe | 1:2eb9d6296ec3 | 30 | float BIN_HighThresh; |
mlambe | 1:2eb9d6296ec3 | 31 | float BIN_LowThresh; |
mlambe | 1:2eb9d6296ec3 | 32 | float WARNA_HighThresh; |
mlambe | 1:2eb9d6296ec3 | 33 | float WARNA_LowThresh; |
mlambe | 1:2eb9d6296ec3 | 34 | float WARNB_HighThresh; |
mlambe | 1:2eb9d6296ec3 | 35 | float WARNB_LowThresh; |
mlambe | 1:2eb9d6296ec3 | 36 | float WARNC_HighThresh; |
mlambe | 1:2eb9d6296ec3 | 37 | float WARNC_LowThresh; |
mlambe | 1:2eb9d6296ec3 | 38 | uint8_t BIN_Mode; |
mlambe | 1:2eb9d6296ec3 | 39 | uint8_t WARNA_Mode; |
mlambe | 1:2eb9d6296ec3 | 40 | uint8_t WARNB_Mode; |
mlambe | 1:2eb9d6296ec3 | 41 | uint8_t WARNC_Mode; |
mlambe | 1:2eb9d6296ec3 | 42 | uint8_t ADCPga; |
mlambe | 1:2eb9d6296ec3 | 43 | float VGain; |
mlambe | 1:2eb9d6296ec3 | 44 | }THRESHCfg_Type; |
mlambe | 1:2eb9d6296ec3 | 45 | |
mlambe | 1:2eb9d6296ec3 | 46 | typedef struct{ |
mlambe | 1:2eb9d6296ec3 | 47 | uint8_t enable; /** Enable PL */ |
mlambe | 1:2eb9d6296ec3 | 48 | uint8_t mode; /** Configure mode, HIGH_IDLE, LOW_IDLE */ |
mlambe | 1:2eb9d6296ec3 | 49 | float HighCurrent; /** High current in mA */ |
mlambe | 1:2eb9d6296ec3 | 50 | float LowCurrent; /** Low current in mA */ |
mlambe | 1:2eb9d6296ec3 | 51 | float HighTime; /** Duration of current pulse in us */ |
mlambe | 1:2eb9d6296ec3 | 52 | float VoltThresh; /** VOltage threshold to trigger programmable load */ |
mlambe | 1:2eb9d6296ec3 | 53 | uint8_t ADCPga; /** ADC PGA setting */ |
mlambe | 1:2eb9d6296ec3 | 54 | float VGain; /** Voltage gain set by external resister divider */ |
mlambe | 1:2eb9d6296ec3 | 55 | }PLOADCfg_Type; |
mlambe | 1:2eb9d6296ec3 | 56 | |
mlambe | 1:2eb9d6296ec3 | 57 | typedef struct{ |
mlambe | 1:2eb9d6296ec3 | 58 | uint8_t enable; /** Enable energy meter function */ |
mlambe | 1:2eb9d6296ec3 | 59 | float FET_Energy; /** SOA energy of exernal FET used */ |
mlambe | 1:2eb9d6296ec3 | 60 | float PulseMagnitude; /** AMplitude of current pulse in mA */ |
mlambe | 1:2eb9d6296ec3 | 61 | float PulseTime; /** Length of current pulse in ms */ |
mlambe | 1:2eb9d6296ec3 | 62 | float WorkingVoltage; /** Working voltage of system in V*/ |
mlambe | 1:2eb9d6296ec3 | 63 | uint32_t AvgADCCode; /** Average ADC code */ |
mlambe | 1:2eb9d6296ec3 | 64 | float SampleRate; /** Sample rate, 20us for ADE1202, 10us foe ADE1201 */ |
mlambe | 1:2eb9d6296ec3 | 65 | uint8_t Cooldown_TimeStep; |
mlambe | 1:2eb9d6296ec3 | 66 | uint8_t Cooldown_Decr; |
mlambe | 1:2eb9d6296ec3 | 67 | uint8_t Cooldown_Sec; |
mlambe | 1:2eb9d6296ec3 | 68 | uint8_t Ov_Scale; |
mlambe | 1:2eb9d6296ec3 | 69 | uint8_t ADCPga; /** ADC PGA setting */ |
mlambe | 1:2eb9d6296ec3 | 70 | float VGain; /** Voltage gain set by external resister divider */ |
mlambe | 1:2eb9d6296ec3 | 71 | }EnergyMtrCfg_Type; |
mlambe | 1:2eb9d6296ec3 | 72 | |
mlambe | 1:2eb9d6296ec3 | 73 | typedef struct{ |
mlambe | 1:2eb9d6296ec3 | 74 | uint16_t reg_addr; |
mlambe | 1:2eb9d6296ec3 | 75 | uint32_t reg_data; |
mlambe | 1:2eb9d6296ec3 | 76 | }RegisterData_Type; |
mlambe | 1:2eb9d6296ec3 | 77 | |
mlambe | 1:2eb9d6296ec3 | 78 | /******* REGISTER DEFINITION ***********/ |
mlambe | 1:2eb9d6296ec3 | 79 | |
mlambe | 1:2eb9d6296ec3 | 80 | #define REG_LOCK 0x000 |
mlambe | 1:2eb9d6296ec3 | 81 | #define REG_CTRL 0x001 |
mlambe | 1:2eb9d6296ec3 | 82 | #define REG_BIN_CTRL 0x002 |
mlambe | 1:2eb9d6296ec3 | 83 | #define REG_BIN_THR 0x003 |
mlambe | 1:2eb9d6296ec3 | 84 | #define REG_WARNA_THR 0x004 |
mlambe | 1:2eb9d6296ec3 | 85 | #define REG_WARNB_THR 0x005 |
mlambe | 1:2eb9d6296ec3 | 86 | #define REG_WARNC_THR 0x006 |
mlambe | 1:2eb9d6296ec3 | 87 | #define REG_BIN_FILTER 0x007 |
mlambe | 1:2eb9d6296ec3 | 88 | #define REG_WARNA_FILTER 0x008 |
mlambe | 1:2eb9d6296ec3 | 89 | #define REG_WARNB_FILTER 0x009 |
mlambe | 1:2eb9d6296ec3 | 90 | #define REG_WARNC_FILTER 0x00A |
mlambe | 1:2eb9d6296ec3 | 91 | #define REG_MASK 0x00B |
mlambe | 1:2eb9d6296ec3 | 92 | #define REG_INT_STATUS 0x00C |
mlambe | 1:2eb9d6296ec3 | 93 | #define REG_STATUS 0x00D |
mlambe | 1:2eb9d6296ec3 | 94 | #define REG_ADC 0x00E |
mlambe | 1:2eb9d6296ec3 | 95 | #define REG_ADCDEC 0x00F |
mlambe | 1:2eb9d6296ec3 | 96 | #define REG_PL_CTRL 0x010 |
mlambe | 1:2eb9d6296ec3 | 97 | #define REG_PL_RISE_THR 0x011 |
mlambe | 1:2eb9d6296ec3 | 98 | #define REG_PL_LOW_CODE 0x012 |
mlambe | 1:2eb9d6296ec3 | 99 | #define REG_PL_HIGH_CODE 0x013 |
mlambe | 1:2eb9d6296ec3 | 100 | #define REG_PL_HIGH_TIME 0x014 |
mlambe | 1:2eb9d6296ec3 | 101 | #define REG_EGY_MTR_CTRL 0x015 |
mlambe | 1:2eb9d6296ec3 | 102 | #define REG_EGY_MTR_THR 0x016 |
mlambe | 1:2eb9d6296ec3 | 103 | #define REG_EGY_MTR1 0x017 |
mlambe | 1:2eb9d6296ec3 | 104 | #define REG_PL_EN 0x200 |
mlambe | 1:2eb9d6296ec3 | 105 | #define REG_PGA_GAIN 0x201 |
mlambe | 1:2eb9d6296ec3 | 106 | |
mlambe | 1:2eb9d6296ec3 | 107 | /**************************************/ |
mlambe | 1:2eb9d6296ec3 | 108 | |
mlambe | 1:2eb9d6296ec3 | 109 | /******** BIT DEFINITION **************/ |
mlambe | 1:2eb9d6296ec3 | 110 | /** Config_LOCK **/ |
mlambe | 1:2eb9d6296ec3 | 111 | #define Dev_Unlock 0xADE0 |
mlambe | 1:2eb9d6296ec3 | 112 | #define Dev_Lock 0xADE1 |
mlambe | 1:2eb9d6296ec3 | 113 | |
mlambe | 1:2eb9d6296ec3 | 114 | /** CTRL **/ |
mlambe | 1:2eb9d6296ec3 | 115 | #define DEV_ADE1201 0x0 |
mlambe | 1:2eb9d6296ec3 | 116 | #define DEV_ADE1202 0x1000 |
mlambe | 1:2eb9d6296ec3 | 117 | #define SW_RST 0x10 |
mlambe | 1:2eb9d6296ec3 | 118 | #define ADDR_RELOAD 0x8 |
mlambe | 1:2eb9d6296ec3 | 119 | #define ADE1202_IRQ 0x4 |
mlambe | 1:2eb9d6296ec3 | 120 | #define CRC_EN 0x1 |
mlambe | 1:2eb9d6296ec3 | 121 | |
mlambe | 1:2eb9d6296ec3 | 122 | /** ADC **/ |
mlambe | 1:2eb9d6296ec3 | 123 | #define ADC_RAW 0 |
mlambe | 1:2eb9d6296ec3 | 124 | #define ADC_DECIMATOR 1 |
mlambe | 1:2eb9d6296ec3 | 125 | |
mlambe | 1:2eb9d6296ec3 | 126 | #define LOW_IDLE 0 |
mlambe | 1:2eb9d6296ec3 | 127 | #define HIGH_IDLE 1 |
mlambe | 1:2eb9d6296ec3 | 128 | |
mlambe | 1:2eb9d6296ec3 | 129 | #define OV_SCALE_1 0 |
mlambe | 1:2eb9d6296ec3 | 130 | #define OV_SCALE_4 1 |
mlambe | 1:2eb9d6296ec3 | 131 | #define OV_SCALE_8 2 |
mlambe | 1:2eb9d6296ec3 | 132 | #define OV_SCALE_16 3 |
mlambe | 1:2eb9d6296ec3 | 133 | |
mlambe | 1:2eb9d6296ec3 | 134 | /******** DEFAULT CONFIG **************/ |
mlambe | 1:2eb9d6296ec3 | 135 | #define BIN_FILTER_VAL 0x8003 |
mlambe | 1:2eb9d6296ec3 | 136 | |
mlambe | 1:2eb9d6296ec3 | 137 | typedef enum |
mlambe | 1:2eb9d6296ec3 | 138 | { |
mlambe | 1:2eb9d6296ec3 | 139 | COOLDOWN_TS_10us = 0, |
mlambe | 1:2eb9d6296ec3 | 140 | COOLDOWN_TS_20us = 1, |
mlambe | 1:2eb9d6296ec3 | 141 | COOLDOWN_TS_40us = 2, |
mlambe | 1:2eb9d6296ec3 | 142 | COOLDOWN_TS_80us = 3 |
mlambe | 1:2eb9d6296ec3 | 143 | }COOLDOWN_TIMESTAMP; |
mlambe | 1:2eb9d6296ec3 | 144 | |
mlambe | 1:2eb9d6296ec3 | 145 | #define CH1_Enable 1 |
mlambe | 1:2eb9d6296ec3 | 146 | #define CH2_Enable 2 |
mlambe | 1:2eb9d6296ec3 | 147 | #define CH1_CH2_Enable 3 |
mlambe | 1:2eb9d6296ec3 | 148 | #define CH1_Disable 0 |
mlambe | 1:2eb9d6296ec3 | 149 | #define CH2_disable 0 |
mlambe | 1:2eb9d6296ec3 | 150 | #define CH1_CH2_Disable 0 |
mlambe | 1:2eb9d6296ec3 | 151 | |
mlambe | 1:2eb9d6296ec3 | 152 | |
mlambe | 1:2eb9d6296ec3 | 153 | #define PL_CH2_ENABLE 1<<15 |
mlambe | 1:2eb9d6296ec3 | 154 | #define PL_CH1_ENABLE 1<<14 |
mlambe | 1:2eb9d6296ec3 | 155 | #define PL_CH2_DISABLE 0<<15 |
mlambe | 1:2eb9d6296ec3 | 156 | #define PL_CH1_DISABLE 0<<14 |
mlambe | 1:2eb9d6296ec3 | 157 | |
mlambe | 1:2eb9d6296ec3 | 158 | /** |
mlambe | 1:2eb9d6296ec3 | 159 | * @defgroup ADCPGA_Const |
mlambe | 1:2eb9d6296ec3 | 160 | * @brief ADC PGA Selection |
mlambe | 1:2eb9d6296ec3 | 161 | * @{ |
mlambe | 1:2eb9d6296ec3 | 162 | */ |
mlambe | 1:2eb9d6296ec3 | 163 | #define ADCPGA_1 1 |
mlambe | 1:2eb9d6296ec3 | 164 | #define ADCPGA_2 3 |
mlambe | 1:2eb9d6296ec3 | 165 | #define ADCPGA_5 7 |
mlambe | 1:2eb9d6296ec3 | 166 | #define ADCPGA_10 0xF |
mlambe | 1:2eb9d6296ec3 | 167 | |
mlambe | 1:2eb9d6296ec3 | 168 | |
mlambe | 1:2eb9d6296ec3 | 169 | #define DEV_UNLOCK 0xADE0 |
mlambe | 1:2eb9d6296ec3 | 170 | #define DEV_LOCK 0xADE1 |
mlambe | 1:2eb9d6296ec3 | 171 | /** |
mlambe | 1:2eb9d6296ec3 | 172 | * @defgroup AFEINTC_SRC_Const |
mlambe | 1:2eb9d6296ec3 | 173 | * @brief Interrupt source selection. These sources are defined as bit mask. They are available for register INT_STATUS and STATUS |
mlambe | 1:2eb9d6296ec3 | 174 | * @{ |
mlambe | 1:2eb9d6296ec3 | 175 | * */ |
mlambe | 1:2eb9d6296ec3 | 176 | #define INTSRC_DOUT1 0x0001 /**< Bit0, DOUT1 */ |
mlambe | 1:2eb9d6296ec3 | 177 | #define INTSRC_WARNA1 0x0002 /**< Bit1, Warning A from channel 1 */ |
mlambe | 1:2eb9d6296ec3 | 178 | #define INTSRC_WARNB1 0x0004 /**< Bit2, Warning B from channel 1 */ |
mlambe | 1:2eb9d6296ec3 | 179 | #define INTSRC_WARNC1 0x0008 /**< Bit3, Warning C from channel 1 */ |
mlambe | 1:2eb9d6296ec3 | 180 | #define INTSRC_DOUT2 0x0010 /**< Bit4, DOUT2 */ |
mlambe | 1:2eb9d6296ec3 | 181 | #define INTSRC_WARNA2 0x0020 /**< Bit5, Warning A from channel 2 */ |
mlambe | 1:2eb9d6296ec3 | 182 | #define INTSRC_WARNB2 0x0040 /**< Bit6, Warning B from channel 2 */ |
mlambe | 1:2eb9d6296ec3 | 183 | #define INTSRC_WARNC2 0x0080 /**< Bit7, Warning C from channel 2 */ |
mlambe | 1:2eb9d6296ec3 | 184 | #define INTSRC_MEMFLT 0x0100 /**< Bit8, Memory fault. After a memory fault is detected the user could reconfigure the device. */ |
mlambe | 1:2eb9d6296ec3 | 185 | #define INTSRC_COMFLT 0x0200 /**< Bit9, Communication fault */ |
mlambe | 1:2eb9d6296ec3 | 186 | #define INTSRC_TSD 0x0400 /**< Bit10, Thermal shutdown detected */ |
mlambe | 1:2eb9d6296ec3 | 187 | #define INTSRC_COOLDOWN1 0x0800 /**< Bit12, Channel 1 is in Cooldown mode */ |
mlambe | 1:2eb9d6296ec3 | 188 | #define INTSRC_COOLDOWN2 0x1000 /**< Bit13, Channel 2 is in Cooldown mode */ |
mlambe | 1:2eb9d6296ec3 | 189 | #define INTSRC_BUSY 0x2000 /**< Bit13, During busy assertion, internal communication is in progress. Once busy is deasserted, an irq can be triggered which indicates normal operation has resumed */ |
mlambe | 1:2eb9d6296ec3 | 190 | #define INTSRC_RSTDONE 0x4000 /**< Bit14, Indicates that the device has reset and is ready to be programmed or begin default normal operation */ |
mlambe | 1:2eb9d6296ec3 | 191 | #define INTSRC_ALL 0x7FFF /**< All bits. Used to clear all interrupt sources */ |
mlambe | 1:2eb9d6296ec3 | 192 | |
mlambe | 1:2eb9d6296ec3 | 193 | /** |
mlambe | 1:2eb9d6296ec3 | 194 | * @defgroup WARNx Mode Const |
mlambe | 1:2eb9d6296ec3 | 195 | * @brief Comparator modes |
mlambe | 1:2eb9d6296ec3 | 196 | * @details COnfigure mode for WARNx comparator modes |
mlambe | 1:2eb9d6296ec3 | 197 | * @{ |
mlambe | 1:2eb9d6296ec3 | 198 | */ |
mlambe | 1:2eb9d6296ec3 | 199 | #define Mode_Hysteretic 0 |
mlambe | 1:2eb9d6296ec3 | 200 | #define Mode_Inbetween 1 |
mlambe | 1:2eb9d6296ec3 | 201 | #define Mode_Greater 2 |
mlambe | 1:2eb9d6296ec3 | 202 | #define Mode_LessEqual 3 |
mlambe | 1:2eb9d6296ec3 | 203 | |
mlambe | 1:2eb9d6296ec3 | 204 | /** |
mlambe | 1:2eb9d6296ec3 | 205 | * Method to identify ADE120x |
mlambe | 1:2eb9d6296ec3 | 206 | * [15:14][13:12][11:9] [8:5] |
mlambe | 1:2eb9d6296ec3 | 207 | * [ RES ][MODEL][Addr][RevIf] |
mlambe | 1:2eb9d6296ec3 | 208 | * |
mlambe | 1:2eb9d6296ec3 | 209 | */ |
mlambe | 1:2eb9d6296ec3 | 210 | #define ADE120x_Model(data) ((((uint32_t)data)>>12)&0x3) /**< Return model. 0: ADE1201, 1:ADE1202 */ |
mlambe | 1:2eb9d6296ec3 | 211 | #define ADE120x_ChipAddr(data) ((((uint32_t)data)>>9)&0x7) /**< Return ECC of this FIFO result */ |
mlambe | 1:2eb9d6296ec3 | 212 | #define ADE120x_RevId(data) ((((uint32_t)data)>>5)&0xf) /**< Return Channel ID */ |
mlambe | 1:2eb9d6296ec3 | 213 | |
mlambe | 1:2eb9d6296ec3 | 214 | class ADE120x{ |
mlambe | 1:2eb9d6296ec3 | 215 | |
mlambe | 1:2eb9d6296ec3 | 216 | |
mlambe | 1:2eb9d6296ec3 | 217 | public: |
mlambe | 1:2eb9d6296ec3 | 218 | ADE120x(PinName mosi, PinName miso, PinName sclk, PinName cs); |
mlambe | 1:2eb9d6296ec3 | 219 | |
mlambe | 1:2eb9d6296ec3 | 220 | void WriteReg(uint8_t addr, uint32_t reg_addr, uint32_t data); |
mlambe | 1:2eb9d6296ec3 | 221 | uint32_t ReadReg(uint8_t addr, uint32_t reg_addr); |
mlambe | 1:2eb9d6296ec3 | 222 | |
mlambe | 1:2eb9d6296ec3 | 223 | |
mlambe | 1:2eb9d6296ec3 | 224 | uint8_t Reset(uint8_t addr); |
mlambe | 1:2eb9d6296ec3 | 225 | uint16_t GetDevID(uint8_t addr); |
mlambe | 1:2eb9d6296ec3 | 226 | void UnLock(uint8_t addr); |
mlambe | 1:2eb9d6296ec3 | 227 | void Lock(uint8_t addr); |
mlambe | 1:2eb9d6296ec3 | 228 | uint8_t DefaultConfig(uint8_t addr); |
mlambe | 1:2eb9d6296ec3 | 229 | |
mlambe | 1:2eb9d6296ec3 | 230 | void ClearIntStatus(uint8_t addr, uint16_t IntSrcSel); |
mlambe | 1:2eb9d6296ec3 | 231 | uint16_t GetIntStatus(uint8_t addr); |
mlambe | 1:2eb9d6296ec3 | 232 | void SetInt(uint8_t addr, uint16_t IntSrcSel); |
mlambe | 1:2eb9d6296ec3 | 233 | |
mlambe | 1:2eb9d6296ec3 | 234 | void SetBinaryThresh(uint8_t addr, uint16_t thresh); |
mlambe | 1:2eb9d6296ec3 | 235 | uint8_t CalculateThreshCode(float V_Thresh, uint8_t ADCPga, float V_Gain); |
mlambe | 1:2eb9d6296ec3 | 236 | uint8_t ThresholdCfg(uint8_t addr, THRESHCfg_Type *pCfg); |
mlambe | 1:2eb9d6296ec3 | 237 | uint8_t ProgrammableLoadCfg(uint8_t addr, PLOADCfg_Type *pCfg); |
mlambe | 1:2eb9d6296ec3 | 238 | uint8_t EnergyMtrCfg(uint8_t addr, EnergyMtrCfg_Type *pCfg); |
mlambe | 1:2eb9d6296ec3 | 239 | |
mlambe | 1:2eb9d6296ec3 | 240 | void SetPgaGain(uint8_t addr, uint16_t gain); |
mlambe | 1:2eb9d6296ec3 | 241 | uint8_t ReadADC(uint8_t addr, int8_t src); |
mlambe | 1:2eb9d6296ec3 | 242 | float ADCCode2Volt(uint32_t ADCCode, uint8_t ADCPga, float VOLTAGE_Gain); |
mlambe | 1:2eb9d6296ec3 | 243 | void GetRegisterData(uint8_t addr, RegisterData_Type *pBuff); |
mlambe | 1:2eb9d6296ec3 | 244 | private: |
mlambe | 1:2eb9d6296ec3 | 245 | SPI spi_; |
mlambe | 1:2eb9d6296ec3 | 246 | DigitalOut nCS_; |
mlambe | 1:2eb9d6296ec3 | 247 | |
mlambe | 1:2eb9d6296ec3 | 248 | }; |
mlambe | 1:2eb9d6296ec3 | 249 | |
mlambe | 1:2eb9d6296ec3 | 250 | #endif |