Junaid Ahmed / Mbed 2 deprecated 202A_HW1

Configuring sensors dynamically using serial bus from the host computer.

Dependencies:   MAG3110 mbed

SLCD/LCDconfig.h@0:1efeb3fc4ba6, 2014-02-12 (annotated)

Committer:
mja054
Date:
Wed Feb 12 22:23:22 2014 +0000
Revision:
0:1efeb3fc4ba6
Home work1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mja054 0:1efeb3fc4ba6 1 #include "FRDM-s401.h" // 4x7 segdisplay
mja054 0:1efeb3fc4ba6 2
mja054 0:1efeb3fc4ba6 3
mja054 0:1efeb3fc4ba6 4 #if 1 // VREF to VLL1
mja054 0:1efeb3fc4ba6 5 /* Following configuration is used for LCD default initialization */
mja054 0:1efeb3fc4ba6 6 #define _LCDRVEN (1) //
mja054 0:1efeb3fc4ba6 7 #define _LCDRVTRIM (8) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
mja054 0:1efeb3fc4ba6 8 #define _LCDCPSEL (1) // charge pump select 0 or 1
mja054 0:1efeb3fc4ba6 9 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
mja054 0:1efeb3fc4ba6 10 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
mja054 0:1efeb3fc4ba6 11 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
mja054 0:1efeb3fc4ba6 12
mja054 0:1efeb3fc4ba6 13 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
mja054 0:1efeb3fc4ba6 14 #define _LCDSUPPLY (1)
mja054 0:1efeb3fc4ba6 15 #define _LCDHREF (0) // 0 or 1
mja054 0:1efeb3fc4ba6 16 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
mja054 0:1efeb3fc4ba6 17 #define _LCDLCK (1) //Any number between 0 and 7
mja054 0:1efeb3fc4ba6 18 #define _LCDBLINKRATE (3) //Any number between 0 and 7
mja054 0:1efeb3fc4ba6 19
mja054 0:1efeb3fc4ba6 20
mja054 0:1efeb3fc4ba6 21 #else //VLL3 to VDD internally
mja054 0:1efeb3fc4ba6 22 /* Following configuration is used for LCD default initialization */
mja054 0:1efeb3fc4ba6 23 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
mja054 0:1efeb3fc4ba6 24 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
mja054 0:1efeb3fc4ba6 25 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
mja054 0:1efeb3fc4ba6 26 #define _LCDSUPPLY (0)
mja054 0:1efeb3fc4ba6 27 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
mja054 0:1efeb3fc4ba6 28 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
mja054 0:1efeb3fc4ba6 29 #define _LCDRVTRIM (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
mja054 0:1efeb3fc4ba6 30 #define _LCDHREF (0) // 0 or 1
mja054 0:1efeb3fc4ba6 31 #define _LCDCPSEL (1) // 0 or 1
mja054 0:1efeb3fc4ba6 32 #define _LCDRVEN (0) //
mja054 0:1efeb3fc4ba6 33 #define _LCDBLINKRATE (3) // Any number between 0 and 7
mja054 0:1efeb3fc4ba6 34 #define _LCDLCK (0) // Any number between 0 and 7
mja054 0:1efeb3fc4ba6 35
mja054 0:1efeb3fc4ba6 36 #endif
mja054 0:1efeb3fc4ba6 37
mja054 0:1efeb3fc4ba6 38
mja054 0:1efeb3fc4ba6 39
mja054 0:1efeb3fc4ba6 40
mja054 0:1efeb3fc4ba6 41 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 0 ~|~|~|~|~|~|~|~|~|~|~|~|~*/
mja054 0:1efeb3fc4ba6 42 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
mja054 0:1efeb3fc4ba6 43 #define _LCDINTENABLE (1)
mja054 0:1efeb3fc4ba6 44
mja054 0:1efeb3fc4ba6 45 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 1 ~|~|~|~|~|~|~|~|~|~|~|~|~|*/
mja054 0:1efeb3fc4ba6 46 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
mja054 0:1efeb3fc4ba6 47 #define _LCDFRAMEINTERRUPT (0) //0 Disable Frame Frequency Interrupt
mja054 0:1efeb3fc4ba6 48 //1 Enable an LCD interrupt that coincides with the LCD frame frequency
mja054 0:1efeb3fc4ba6 49 #define _LCDFULLCPLDIRIVE (0) // 0 GPIO shared with the LCD. Inputs levels and internal pullup reference to VDD
mja054 0:1efeb3fc4ba6 50 // 1 If VSUPPLY=11and RVEN=0. Inputs levels and internal pullup reference to VLL3
mja054 0:1efeb3fc4ba6 51 #define _LCDWAITMODE (0) // 0 Allows the LCD driver and charge pump to continue running during wait mode
mja054 0:1efeb3fc4ba6 52 // 1 Disable the LCD when the MCU goes into wait mode
mja054 0:1efeb3fc4ba6 53 #define _LCDSTOPMODE (0) // 0 Allows the LCD driver and charge pump to continue running during stop2 or stop3
mja054 0:1efeb3fc4ba6 54 // 1 Disable the LCD when and charge pump when the MCU goes into stop2 or stop3
mja054 0:1efeb3fc4ba6 55
mja054 0:1efeb3fc4ba6 56 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Voltage Supply Register ~|~|~|~|~|~|~|~|~|~|~|~*/
mja054 0:1efeb3fc4ba6 57 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
mja054 0:1efeb3fc4ba6 58 #define _LCDHIGHREF (0) //0 Divide input VIREG=1.0v
mja054 0:1efeb3fc4ba6 59 //1 Do not divide the input VIREG=1.67v
mja054 0:1efeb3fc4ba6 60 #define _LCDBBYPASS (0) //Determines whether the internal LCD op amp buffer is bypassed
mja054 0:1efeb3fc4ba6 61 //0 Buffered mode
mja054 0:1efeb3fc4ba6 62 //1 Unbuffered mode
mja054 0:1efeb3fc4ba6 63
mja054 0:1efeb3fc4ba6 64 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Regulated Voltage Control |~|~|~|~|~|~|~|~|~|~*/
mja054 0:1efeb3fc4ba6 65 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
mja054 0:1efeb3fc4ba6 66 #define _LCDCONTRAST (1) //Contrast by software 0 -- Disable 1-- Enable
mja054 0:1efeb3fc4ba6 67 #define _LVLCONTRAST (0) //Any number between 0 and 15, if the number is bigger the glass gets darker
mja054 0:1efeb3fc4ba6 68
mja054 0:1efeb3fc4ba6 69 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Blink Control Register ~|~|~|~|~|~|~|~|~|~|~|~*/
mja054 0:1efeb3fc4ba6 70 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
mja054 0:1efeb3fc4ba6 71 #define _LCDBLINKCONTROL (1) //0 Disable blink mode
mja054 0:1efeb3fc4ba6 72 //1 Enable blink mode
mja054 0:1efeb3fc4ba6 73 #define _LCDALTMODE (0) //0 Normal display
mja054 0:1efeb3fc4ba6 74 //1 Alternate display for 4 backplanes or less the LCD backplane sequencer changes to otuput an alternate display
mja054 0:1efeb3fc4ba6 75 #define _LCDBLANKDISP (0) //0 Do not blank display
mja054 0:1efeb3fc4ba6 76 //1 Blank display if you put it in 0 the text before blank is manteined
mja054 0:1efeb3fc4ba6 77 #define _LCDBLINKMODE (0) //0 Display blank during the blink period
mja054 0:1efeb3fc4ba6 78 //1 Display alternate displat during blink period (Ignored if duty is 5 or greater)
mja054 0:1efeb3fc4ba6 79
mja054 0:1efeb3fc4ba6 80
mja054 0:1efeb3fc4ba6 81 //Calculated values
mja054 0:1efeb3fc4ba6 82 #define _LCDUSEDPINS (_LCDFRONTPLANES + _LCDBACKPLANES)
mja054 0:1efeb3fc4ba6 83 #define _LCDDUTY (_LCDBACKPLANES-1) //Any number between 0 and 7
mja054 0:1efeb3fc4ba6 84 #define LCD_WF_BASE LCD->WF8B[0]
mja054 0:1efeb3fc4ba6 85
mja054 0:1efeb3fc4ba6 86 // General definitions used by the LCD library
mja054 0:1efeb3fc4ba6 87 #define LCD_WF(x) *((uint8 *)&LCD_WF_BASE + x)
mja054 0:1efeb3fc4ba6 88
mja054 0:1efeb3fc4ba6 89 /*LCD Fault Detections Consts*/
mja054 0:1efeb3fc4ba6 90 #define FP_TYPE 0x00 // pin is a Front Plane
mja054 0:1efeb3fc4ba6 91 #define BP_TYPE 0x80 // pin is Back Plane
mja054 0:1efeb3fc4ba6 92
mja054 0:1efeb3fc4ba6 93 // Fault Detect Preescaler Options
mja054 0:1efeb3fc4ba6 94 #define FDPRS_1 0
mja054 0:1efeb3fc4ba6 95 #define FDPRS_2 1
mja054 0:1efeb3fc4ba6 96 #define FDPRS_4 2
mja054 0:1efeb3fc4ba6 97 #define FDPRS_8 3
mja054 0:1efeb3fc4ba6 98 #define FDPRS_16 4
mja054 0:1efeb3fc4ba6 99 #define FDPRS_32 5
mja054 0:1efeb3fc4ba6 100 #define FDPRS_64 6
mja054 0:1efeb3fc4ba6 101 #define FDPRS_128 7
mja054 0:1efeb3fc4ba6 102
mja054 0:1efeb3fc4ba6 103 // Fault Detect Sample Window Width Values
mja054 0:1efeb3fc4ba6 104 #define FDSWW_4 0
mja054 0:1efeb3fc4ba6 105 #define FDSWW_8 1
mja054 0:1efeb3fc4ba6 106 #define FDSWW_16 2
mja054 0:1efeb3fc4ba6 107 #define FDSWW_32 3
mja054 0:1efeb3fc4ba6 108 #define FDSWW_64 4
mja054 0:1efeb3fc4ba6 109 #define FDSWW_128 5
mja054 0:1efeb3fc4ba6 110 #define FDSWW_256 6
mja054 0:1efeb3fc4ba6 111 #define FDSWW_512 7
mja054 0:1efeb3fc4ba6 112
mja054 0:1efeb3fc4ba6 113 /*
mja054 0:1efeb3fc4ba6 114 Mask Bit definitions used f
mja054 0:1efeb3fc4ba6 115 */
mja054 0:1efeb3fc4ba6 116 #define mBIT0 1
mja054 0:1efeb3fc4ba6 117 #define mBIT1 2
mja054 0:1efeb3fc4ba6 118 #define mBIT2 4
mja054 0:1efeb3fc4ba6 119 #define mBIT3 8
mja054 0:1efeb3fc4ba6 120 #define mBIT4 16
mja054 0:1efeb3fc4ba6 121 #define mBIT5 32
mja054 0:1efeb3fc4ba6 122 #define mBIT6 64
mja054 0:1efeb3fc4ba6 123 #define mBIT7 128
mja054 0:1efeb3fc4ba6 124 #define mBIT8 256
mja054 0:1efeb3fc4ba6 125 #define mBIT9 512
mja054 0:1efeb3fc4ba6 126 #define mBIT10 1024
mja054 0:1efeb3fc4ba6 127 #define mBIT11 2048
mja054 0:1efeb3fc4ba6 128 #define mBIT12 4096
mja054 0:1efeb3fc4ba6 129 #define mBIT13 8192
mja054 0:1efeb3fc4ba6 130 #define mBIT14 16384
mja054 0:1efeb3fc4ba6 131 #define mBIT15 32768
mja054 0:1efeb3fc4ba6 132 #define mBIT16 65536
mja054 0:1efeb3fc4ba6 133 #define mBIT17 131072
mja054 0:1efeb3fc4ba6 134 #define mBIT18 262144
mja054 0:1efeb3fc4ba6 135 #define mBIT19 524288
mja054 0:1efeb3fc4ba6 136 #define mBIT20 1048576
mja054 0:1efeb3fc4ba6 137 #define mBIT21 2097152
mja054 0:1efeb3fc4ba6 138 #define mBIT22 4194304
mja054 0:1efeb3fc4ba6 139 #define mBIT23 8388608
mja054 0:1efeb3fc4ba6 140 #define mBIT24 16777216
mja054 0:1efeb3fc4ba6 141 #define mBIT25 33554432
mja054 0:1efeb3fc4ba6 142 #define mBIT26 67108864
mja054 0:1efeb3fc4ba6 143 #define mBIT27 134217728
mja054 0:1efeb3fc4ba6 144 #define mBIT28 268435456
mja054 0:1efeb3fc4ba6 145 #define mBIT29 536870912
mja054 0:1efeb3fc4ba6 146 #define mBIT30 1073741824
mja054 0:1efeb3fc4ba6 147 #define mBIT31 2147483648
mja054 0:1efeb3fc4ba6 148
mja054 0:1efeb3fc4ba6 149 #define mBIT32 1
mja054 0:1efeb3fc4ba6 150 #define mBIT33 2
mja054 0:1efeb3fc4ba6 151 #define mBIT34 4
mja054 0:1efeb3fc4ba6 152 #define mBIT35 8
mja054 0:1efeb3fc4ba6 153 #define mBIT36 16
mja054 0:1efeb3fc4ba6 154 #define mBIT37 32
mja054 0:1efeb3fc4ba6 155 #define mBIT38 64
mja054 0:1efeb3fc4ba6 156 #define mBIT39 128
mja054 0:1efeb3fc4ba6 157 #define mBIT40 256
mja054 0:1efeb3fc4ba6 158 #define mBIT41 512
mja054 0:1efeb3fc4ba6 159 #define mBIT42 1024
mja054 0:1efeb3fc4ba6 160 #define mBIT43 2048
mja054 0:1efeb3fc4ba6 161 #define mBIT44 4096
mja054 0:1efeb3fc4ba6 162 #define mBIT45 8192
mja054 0:1efeb3fc4ba6 163 #define mBIT46 16384
mja054 0:1efeb3fc4ba6 164 #define mBIT47 32768
mja054 0:1efeb3fc4ba6 165 #define mBIT48 65536
mja054 0:1efeb3fc4ba6 166 #define mBIT49 131072
mja054 0:1efeb3fc4ba6 167 #define mBIT50 262144
mja054 0:1efeb3fc4ba6 168 #define mBIT51 524288
mja054 0:1efeb3fc4ba6 169 #define mBIT52 1048576
mja054 0:1efeb3fc4ba6 170 #define mBIT53 2097152
mja054 0:1efeb3fc4ba6 171 #define mBIT54 4194304
mja054 0:1efeb3fc4ba6 172 #define mBIT55 8388608
mja054 0:1efeb3fc4ba6 173 #define mBIT56 16777216
mja054 0:1efeb3fc4ba6 174 #define mBIT57 33554432
mja054 0:1efeb3fc4ba6 175 #define mBIT58 67108864
mja054 0:1efeb3fc4ba6 176 #define mBIT59 134217728
mja054 0:1efeb3fc4ba6 177 #define mBIT60 268435456
mja054 0:1efeb3fc4ba6 178 #define mBIT61 536870912
mja054 0:1efeb3fc4ba6 179 #define mBIT62 1073741824
mja054 0:1efeb3fc4ba6 180 #define mBIT63 2147483648
mja054 0:1efeb3fc4ba6 181
mja054 0:1efeb3fc4ba6 182
mja054 0:1efeb3fc4ba6 183