Diff: bq79606.cpp

Revision:

2:03a6da61d834

Parent:

1:d0662d4ffb8c

Child:

3:4dc457ed63d5

diff -r d0662d4ffb8c -r 03a6da61d834 bq79606.cpp
--- a/bq79606.cpp	Sun Dec 20 18:07:17 2020 +0000
+++ b/bq79606.cpp	Wed Dec 23 21:41:03 2020 +0000
@@ -15,8 +15,11 @@
 extern DigitalOut bmsWakeUp;
 
 void sendUART(int length, uint8_t * data){
-    for(int i = 0; i < length; i++)
+    pc1.printf("SENDING TO BOARD");
+    for(int i = 0; i < length; i++) {
+      //pc1.putc(data[i]);
       bms.putc(data[i]);
+      }
     //wait_ms(1);
 }
 
@@ -25,6 +28,7 @@
     wait_ms(50);
     bmsWakeUp = 0;
     wait_ms(10);
+    //bmsWakeUp = 1;
 }
 
 void AutoAddress()
@@ -32,7 +36,7 @@
     memset(response_frame2,0,sizeof(response_frame2)); //clear out the response frame buffer
 
     //dummy write to ECC_TEST (sync DLL)
-    WriteReg(0, ECC_TEST, 0x00, 1, FRMWRT_ALL_NR);
+    //WriteReg(0, ECC_TEST, 0x00, 1, FRMWRT_ALL_NR);
 
     //clear CONFIG in case it is set
     WriteReg(0, CONFIG, 0x00, 1, FRMWRT_ALL_NR);
@@ -47,30 +51,30 @@
     }
 
     //set all devices as a stack device
-    WriteReg(0, CONFIG, 0x02, 1, FRMWRT_ALL_NR);
+    //WriteReg(0, CONFIG, 0x02, 1, FRMWRT_ALL_NR);
 
     //if there's only 1 board, it's the base AND the top of stack, so change it to those
-    if(TOTALBOARDS==1)
-    {
+    //if(TOTALBOARDS==1)
+    //{
         WriteReg(0, CONFIG, 0x01, 1, FRMWRT_SGL_NR);
-    }
+    //}
     //otherwise set the base and top of stack individually
-    else
+    /*else
     {
         WriteReg(0, CONFIG, 0x00, 1, FRMWRT_SGL_NR);             //base
         WriteReg(TOTALBOARDS-1, CONFIG, 0x03, 1, FRMWRT_SGL_NR); //top of stack
-    }
+    }*/
 
     //dummy read from ECC_TEST (sync DLL)
-    ReadReg(TOTALBOARDS-1, ECC_TEST, response_frame2, 1, 0, FRMWRT_ALL_R);
+    //ReadReg(TOTALBOARDS-1, ECC_TEST, response_frame2, 1, 0, FRMWRT_ALL_R);
 
-//    //OPTIONAL: read back all device addresses
-//    WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Disable communication timeout because printf takes a long time
-//    for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) {
-//        memset(response_frame2, 0, sizeof(response_frame2));
-//        ReadReg(nCurrentBoard, DEVADD_USR, response_frame2, 1, 0, FRMWRT_SGL_R);
-//        printf("Board %d=%02x\n",nCurrentBoard,response_frame2[4]);
-//    }
+    //OPTIONAL: read back all device addresses
+    WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Disable communication timeout because printf takes a long time
+    for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) {
+        memset(response_frame2, 0, sizeof(response_frame2));
+        ReadReg(nCurrentBoard, DEVADD_USR, response_frame2, 1, 0, FRMWRT_SGL_R);
+        //printf("Board %d=%02x\n",nCurrentBoard,response_frame2[4]);
+    }
 }
 //**************************
 //END AUTO ADDRESS SEQUENCE
@@ -194,26 +198,35 @@
         //while(UART_RX_RDY == 0U && count>0) count--; /*wait*/
         //if(count == 0) printf("COUNT REACHED 0\n");
         //UART_RX_RDY = 0;
-        //bRes = bLen + 6;
-    } /*else if (bWriteType == FRMWRT_STK_R) {
+        bRes = bLen + 6;
+    /*else if (bWriteType == FRMWRT_STK_R) {
         bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType);
         memset(pData, 0, sizeof(pData));
         sciEnableNotification(scilinREG, SCI_RX_INT);
         sciReceive(scilinREG, (bLen + 6) * (TOTALBOARDS - 1), pData);
         while(UART_RX_RDY == 0U && count>0) count--; //wait
         UART_RX_RDY = 0;
-        bRes = (bLen + 6) * (TOTALBOARDS - 1);
+        bRes = (bLen + 6) * (TOTALBOARDS - 1);*/
     } else if (bWriteType == FRMWRT_ALL_R) {
         bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType);
-        memset(pData, 0, sizeof(pData));
+        /*memset(pData, 0, sizeof(pData));
         sciEnableNotification(scilinREG, SCI_RX_INT);
         sciReceive(scilinREG, (bLen + 6) * TOTALBOARDS, pData);
         while(UART_RX_RDY == 0U && count>0) count--; //wait
-        UART_RX_RDY = 0;
+        UART_RX_RDY = 0;*/
         bRes = (bLen + 6) * TOTALBOARDS;
     } else {
         bRes = 0;
-    }*/
+    }
+    /*int recBuff[256];
+    bRes = 1;
+    for(int i = 0; i < bRes; i++){
+            recBuff[i] = bms.getc();
+            //pc1.printf("rec = %d", recBuff[i]);
+        }
+        for(int i = 0; i < bRes; i++){
+            pc1.printf("rec = %d", recBuff[i]);
+        }*/
     return bRes;
 }
 
@@ -230,6 +243,8 @@
 
 void init(){
     
+   
+    
     /* mask all low level faults... user should unmask necessary faults */
     WriteReg(0, GPIO_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask GPIO faults
     //WriteReg(0, UV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UV faults
@@ -257,7 +272,7 @@
     WriteReg(0, OVUV_BIST_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); //mask ov/uv bist faults
     WriteReg(0, OTUT_BIST_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR);
     
-    WriteReg(0, CELL_ADC_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enables ADC for all 6 cell channels
+    WriteReg(0, CELL_ADC_CTRL, 0x07, 1, FRMWRT_ALL_NR); //enables ADC for all 6 cell channels
     WriteReg(0, OVUV_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable all cell ov/uv
     WriteReg(0, UV_THRESH, 0x53, 1, FRMWRT_ALL_NR); //sets cell UV to 2.8V
     WriteReg(0, OV_THRESH, 0x5B, 1, FRMWRT_ALL_NR); //sets cell OV to 4.3V
@@ -265,6 +280,7 @@
     WriteReg(0, AUX_ADC_CONF, 0x08, 1, FRMWRT_ALL_NR); //1MHz AUX sample rate,  128 decimation  ratio
     WriteReg(0, CELL_ADC_CONF1, 0x67, 1, FRMWRT_ALL_NR); //256 decimation ratio, 1MHz sample. 1.2 Hz LPF
     WriteReg(0, CELL_ADC_CONF2, 0x00, 1, FRMWRT_ALL_NR); //single conversion
+    WriteReg(0, CONTROL2, 0x01, 1, FRMWRT_ALL_NR);          //CELL_ADC_GO = 1
     ///enable continuous sampling. Otherwise, single conversions with CONTROL2[CELL_ADC_GO]
     //WriteReg(0,CELL_ADC_CONF2, 0x0A,1,FRMWRT_ALL_NR);//continuous sampling with 5ms interval
     //WriteReg(0, CONTROL2, 0x10, 1, FRMWRT_ALL_NR);// enable TSREF to give enough settling time