File content as of revision 20:c6a6e019922e:

#if defined(TARGET_STM32F4)
/*

This file is licensed under Apache 2.0 license.
(C) 2016 dinau

*/
#include "spi_dma.h"

#define DMAx_CLK_ENABLE()     __DMA2_CLK_ENABLE()    
#define SPIx_TX_DMA_STREAM    DMA2_Stream3
#define SPIx_RX_DMA_STREAM    DMA2_Stream2
#define SPIx_TX_DMA_CHANNEL   DMA_CHANNEL_3
#define SPIx_RX_DMA_CHANNEL   DMA_CHANNEL_3
#define SPIx_DMA_TX_IRQn      DMA2_Stream3_IRQn    
#define SPIx_DMA_RX_IRQn      DMA2_Stream2_IRQn    
#define DMAx_TX_IRQHandler    DMA2_Stream3_IRQHandler
#define DMAx_RX_IRQHandler    DMA2_Stream2_IRQHandler

#define readReg( reg, mask)  (  (reg) & (mask)  )    


void spi_dma_get_info( SPI_TypeDef *spi )
{
    SPI_HandleTypeDef *hspi;
    if( spi == SPI1 ){
        hspi = &Spi1Handle;
    } 
    #if 0
    else {
        hspi = &Spi2Handle;
    }
    #endif
    hspi->Instance               = spi;
    hspi->Init.Mode              = readReg(spi->CR1, SPI_MODE_MASTER); 
    hspi->Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
    hspi->Init.Direction         = readReg(spi->CR1, SPI_CR1_BIDIMODE); 
    hspi->Init.CLKPhase          = readReg(spi->CR1, SPI_CR1_CPHA);
    hspi->Init.CLKPolarity       = readReg(spi->CR1, SPI_CR1_CPOL);
    hspi->Init.CRCCalculation    = readReg(spi->CR1, SPI_CR1_CRCEN);
    hspi->Init.CRCPolynomial     = spi->CRCPR & 0xFFFF;
    hspi->Init.DataSize          = readReg(spi->CR1, SPI_CR1_DFF);
    hspi->Init.FirstBit          = SPI_FIRSTBIT_MSB;
    hspi->Init.NSS               = readReg(spi->CR1, SPI_CR1_SSM);
    hspi->Init.TIMode            = SPI_TIMODE_DISABLED;
    hspi->State                  = HAL_SPI_STATE_READY;
}

void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
{
    static uint8_t dma_handle_inited = 0;
    DMA_HandleTypeDef *hdma_tx, *hdma_rx;
    /* Peripheral DMA init*/
    if( spi == SPI1 ){ 
        hdma_tx = &hdma_spi1_tx;
        hdma_rx = &hdma_spi1_rx;
        /* TX: */
        if( !dma_handle_inited ){
            hdma_tx->Instance                 = SPIx_TX_DMA_STREAM;
            hdma_tx->Init.Channel             = SPIx_TX_DMA_CHANNEL; 
            hdma_tx->Init.Direction           = DMA_MEMORY_TO_PERIPH;
            hdma_tx->Init.PeriphInc           = DMA_PINC_DISABLE;
            hdma_tx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
            hdma_tx->Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
            hdma_tx->Init.Mode                = DMA_NORMAL;
            hdma_tx->Init.Priority            = DMA_PRIORITY_HIGH;
            /**/
            hdma_tx->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
            hdma_tx->Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
            hdma_tx->Init.MemBurst            = DMA_MBURST_SINGLE;
            hdma_tx->Init.PeriphBurst         = DMA_PBURST_SINGLE;
            /**/
        }
        hdma_tx->Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
        HAL_DMA_Init(&hdma_spi1_tx);
        __HAL_LINKDMA( &Spi1Handle,hdmatx,hdma_spi1_tx);

        /* RX: */
        if( !dma_handle_inited ){        
            hdma_rx->Instance                 = SPIx_RX_DMA_STREAM;
            hdma_rx->Init.Channel             = SPIx_RX_DMA_CHANNEL;
            hdma_rx->Init.Direction           = DMA_PERIPH_TO_MEMORY;
            hdma_rx->Init.PeriphInc           = DMA_PINC_DISABLE;
            hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
            hdma_rx->Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
            hdma_rx->Init.Mode                = DMA_NORMAL;
            hdma_rx->Init.Priority            = DMA_PRIORITY_LOW;
            /**/
            hdma_rx->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
            hdma_rx->Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
            hdma_rx->Init.MemBurst            = DMA_MBURST_SINGLE;
            hdma_rx->Init.PeriphBurst         = DMA_PBURST_SINGLE; 
            /**/
        }
        hdma_rx->Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
        HAL_DMA_Init(&hdma_spi1_rx);
        __HAL_LINKDMA( &Spi1Handle,hdmarx,hdma_spi1_rx);
    } 
    #if 0
    else if( spi == SPI2 ) {

    }
    #endif
    dma_handle_inited = 1;
}

void spi_dma_irq_setup( SPI_TypeDef *spi) 
{
    if( spi == SPI1 ) {
        /* DMA controller clock enable */
        DMAx_CLK_ENABLE();

        /* DMA interrupt init */
        HAL_NVIC_SetPriority(SPIx_DMA_TX_IRQn, 0, 1);
        HAL_NVIC_EnableIRQ(  SPIx_DMA_TX_IRQn);
        HAL_NVIC_SetPriority(SPIx_DMA_RX_IRQn, 0, 0);
        HAL_NVIC_EnableIRQ(  SPIx_DMA_RX_IRQn);
    }
#if 0
    else if ( spi == SPI2 ){ 

    }
#endif
}

void DMAx_TX_IRQHandler(void)
{
  HAL_DMA_IRQHandler(&hdma_spi1_tx);
}

void DMAx_RX_IRQHandler(void)
{
  HAL_DMA_IRQHandler(&hdma_spi1_rx);
}

#endif /* TARGET_STM32F4 */