mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

Diff: spi_dma/spi_dma_stm32f4.c

Revision:
20:c6a6e019922e
Parent:
18:1b1a0e68008a
Child:
21:41129109d6ab
--- a/spi_dma/spi_dma_stm32f4.c	Mon Feb 15 22:40:30 2016 +0900
+++ b/spi_dma/spi_dma_stm32f4.c	Mon Feb 15 22:40:41 2016 +0900
@@ -12,8 +12,8 @@
 #define SPIx_RX_DMA_STREAM    DMA2_Stream2
 #define SPIx_TX_DMA_CHANNEL   DMA_CHANNEL_3
 #define SPIx_RX_DMA_CHANNEL   DMA_CHANNEL_3
-#define SPIx_DMA_TX_IRQn      DMA2_Stream3_IRQn	
-#define SPIx_DMA_RX_IRQn      DMA2_Stream2_IRQn	
+#define SPIx_DMA_TX_IRQn      DMA2_Stream3_IRQn    
+#define SPIx_DMA_RX_IRQn      DMA2_Stream2_IRQn    
 #define DMAx_TX_IRQHandler    DMA2_Stream3_IRQHandler
 #define DMAx_RX_IRQHandler    DMA2_Stream2_IRQHandler
 
@@ -31,7 +31,7 @@
         hspi = &Spi2Handle;
     }
     #endif
-    hspi->Instance = spi;
+    hspi->Instance               = spi;
     hspi->Init.Mode              = readReg(spi->CR1, SPI_MODE_MASTER); 
     hspi->Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
     hspi->Init.Direction         = readReg(spi->CR1, SPI_CR1_BIDIMODE); 
@@ -43,53 +43,56 @@
     hspi->Init.FirstBit          = SPI_FIRSTBIT_MSB;
     hspi->Init.NSS               = readReg(spi->CR1, SPI_CR1_SSM);
     hspi->Init.TIMode            = SPI_TIMODE_DISABLED;
-    hspi->State                     = HAL_SPI_STATE_READY;
+    hspi->State                  = HAL_SPI_STATE_READY;
 }
 
 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
 {
     static uint8_t dma_handle_inited = 0;
+    DMA_HandleTypeDef *hdma_tx, *hdma_rx;
     /* Peripheral DMA init*/
     if( spi == SPI1 ){ 
+        hdma_tx = &hdma_spi1_tx;
+        hdma_rx = &hdma_spi1_rx;
         /* TX: */
-		if( !dma_handle_inited ){
-			hdma_spi1_tx.Instance                 = SPIx_TX_DMA_STREAM;
-			hdma_spi1_tx.Init.Channel             = SPIx_TX_DMA_CHANNEL; 
-			hdma_spi1_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
-			hdma_spi1_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
-			hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
-			hdma_spi1_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
-			hdma_spi1_tx.Init.Mode                = DMA_NORMAL;
-			hdma_spi1_tx.Init.Priority            = DMA_PRIORITY_HIGH;
-			/**/
-			hdma_spi1_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
-			hdma_spi1_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
-			hdma_spi1_tx.Init.MemBurst            = DMA_MBURST_SINGLE;
-			hdma_spi1_tx.Init.PeriphBurst         = DMA_PBURST_SINGLE;
-			/**/
-		}
-		hdma_spi1_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
+        if( !dma_handle_inited ){
+            hdma_tx->Instance                 = SPIx_TX_DMA_STREAM;
+            hdma_tx->Init.Channel             = SPIx_TX_DMA_CHANNEL; 
+            hdma_tx->Init.Direction           = DMA_MEMORY_TO_PERIPH;
+            hdma_tx->Init.PeriphInc           = DMA_PINC_DISABLE;
+            hdma_tx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+            hdma_tx->Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+            hdma_tx->Init.Mode                = DMA_NORMAL;
+            hdma_tx->Init.Priority            = DMA_PRIORITY_HIGH;
+            /**/
+            hdma_tx->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
+            hdma_tx->Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+            hdma_tx->Init.MemBurst            = DMA_MBURST_SINGLE;
+            hdma_tx->Init.PeriphBurst         = DMA_PBURST_SINGLE;
+            /**/
+        }
+        hdma_tx->Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
         HAL_DMA_Init(&hdma_spi1_tx);
         __HAL_LINKDMA( &Spi1Handle,hdmatx,hdma_spi1_tx);
 
         /* RX: */
-		if( !dma_handle_inited ){        
-			hdma_spi1_rx.Instance                 = SPIx_RX_DMA_STREAM;
-			hdma_spi1_rx.Init.Channel             = SPIx_RX_DMA_CHANNEL;
-			hdma_spi1_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
-			hdma_spi1_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
-			hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
-			hdma_spi1_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
-			hdma_spi1_rx.Init.Mode                = DMA_NORMAL;
-			hdma_spi1_rx.Init.Priority            = DMA_PRIORITY_LOW;
-			/**/
-			hdma_spi1_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
-			hdma_spi1_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
-			hdma_spi1_rx.Init.MemBurst            = DMA_MBURST_SINGLE;
-			hdma_spi1_rx.Init.PeriphBurst         = DMA_PBURST_SINGLE; 
-			/**/
-		}
-        hdma_spi1_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
+        if( !dma_handle_inited ){        
+            hdma_rx->Instance                 = SPIx_RX_DMA_STREAM;
+            hdma_rx->Init.Channel             = SPIx_RX_DMA_CHANNEL;
+            hdma_rx->Init.Direction           = DMA_PERIPH_TO_MEMORY;
+            hdma_rx->Init.PeriphInc           = DMA_PINC_DISABLE;
+            hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+            hdma_rx->Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+            hdma_rx->Init.Mode                = DMA_NORMAL;
+            hdma_rx->Init.Priority            = DMA_PRIORITY_LOW;
+            /**/
+            hdma_rx->Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
+            hdma_rx->Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+            hdma_rx->Init.MemBurst            = DMA_MBURST_SINGLE;
+            hdma_rx->Init.PeriphBurst         = DMA_PBURST_SINGLE; 
+            /**/
+        }
+        hdma_rx->Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
         HAL_DMA_Init(&hdma_spi1_rx);
         __HAL_LINKDMA( &Spi1Handle,hdmarx,hdma_spi1_rx);
     }