Michele Riccio / mbed-dsp_F767ZI

mbed-os 6.10 versione

cmsis_dsp/BasicMathFunctions/arm_shift_q15.c@5:ed60e5c5c2a8, 2021-06-21 (annotated)

Committer:
michelericcio
Date:
Mon Jun 21 10:16:02 2021 +0000
Revision:
5:ed60e5c5c2a8
Parent:
3:7a284390b0ce 
mbed-dsp working on ST Nucleo F767ZI and mbed-OS 6

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 3:7a284390b0ce 2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 3:7a284390b0ce 4 * $Date: 17. January 2013
mbed_official 3:7a284390b0ce 5 * $Revision: V1.4.1
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_shift_q15.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Shifts the elements of a Q15 vector by a specified number of bits.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @addtogroup shift
emilmont 1:fdd22bb7aa52 49 * @{
emilmont 1:fdd22bb7aa52 50 */
emilmont 1:fdd22bb7aa52 51
emilmont 1:fdd22bb7aa52 52 /**
emilmont 1:fdd22bb7aa52 53 * @brief Shifts the elements of a Q15 vector a specified number of bits.
emilmont 1:fdd22bb7aa52 54 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 55 * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
emilmont 1:fdd22bb7aa52 56 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 57 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 58 * @return none.
emilmont 1:fdd22bb7aa52 59 *
emilmont 1:fdd22bb7aa52 60 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 61 * \par
emilmont 1:fdd22bb7aa52 62 * The function uses saturating arithmetic.
emilmont 1:fdd22bb7aa52 63 * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
emilmont 1:fdd22bb7aa52 64 */
emilmont 1:fdd22bb7aa52 65
emilmont 1:fdd22bb7aa52 66 void arm_shift_q15(
emilmont 1:fdd22bb7aa52 67 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 68 int8_t shiftBits,
emilmont 1:fdd22bb7aa52 69 q15_t * pDst,
emilmont 1:fdd22bb7aa52 70 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 71 {
emilmont 1:fdd22bb7aa52 72 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 73 uint8_t sign; /* Sign of shiftBits */
emilmont 1:fdd22bb7aa52 74
mbed_official 3:7a284390b0ce 75 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 76
emilmont 1:fdd22bb7aa52 77 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 78
emilmont 1:fdd22bb7aa52 79 q15_t in1, in2; /* Temporary variables */
emilmont 1:fdd22bb7aa52 80
emilmont 1:fdd22bb7aa52 81
emilmont 1:fdd22bb7aa52 82 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 83 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 84
emilmont 1:fdd22bb7aa52 85 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 86 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 87
emilmont 1:fdd22bb7aa52 88 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 89 if(sign == 0u)
emilmont 1:fdd22bb7aa52 90 {
emilmont 1:fdd22bb7aa52 91 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 92 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 93 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 94 {
emilmont 1:fdd22bb7aa52 95 /* Read 2 inputs */
emilmont 1:fdd22bb7aa52 96 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 97 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 98 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 99 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 100 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 101
emilmont 1:fdd22bb7aa52 102 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 103 __SSAT((in2 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 104
emilmont 1:fdd22bb7aa52 105 #else
emilmont 1:fdd22bb7aa52 106
emilmont 1:fdd22bb7aa52 107 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 108 __SSAT((in1 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 109
emilmont 1:fdd22bb7aa52 110 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 111
emilmont 1:fdd22bb7aa52 112 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 113 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 114
emilmont 1:fdd22bb7aa52 115 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 116
emilmont 1:fdd22bb7aa52 117 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 118 __SSAT((in2 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 119
emilmont 1:fdd22bb7aa52 120 #else
emilmont 1:fdd22bb7aa52 121
emilmont 1:fdd22bb7aa52 122 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 123 __SSAT((in1 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 124
emilmont 1:fdd22bb7aa52 125 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 126
emilmont 1:fdd22bb7aa52 127 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 128 blkCnt--;
emilmont 1:fdd22bb7aa52 129 }
emilmont 1:fdd22bb7aa52 130
emilmont 1:fdd22bb7aa52 131 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 132 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 133 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 134
emilmont 1:fdd22bb7aa52 135 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 136 {
emilmont 1:fdd22bb7aa52 137 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 138 /* Shift and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 139 *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
emilmont 1:fdd22bb7aa52 140
emilmont 1:fdd22bb7aa52 141 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 142 blkCnt--;
emilmont 1:fdd22bb7aa52 143 }
emilmont 1:fdd22bb7aa52 144 }
emilmont 1:fdd22bb7aa52 145 else
emilmont 1:fdd22bb7aa52 146 {
emilmont 1:fdd22bb7aa52 147 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 148 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 149 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 150 {
emilmont 1:fdd22bb7aa52 151 /* Read 2 inputs */
emilmont 1:fdd22bb7aa52 152 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 153 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 154
emilmont 1:fdd22bb7aa52 155 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 156 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 157 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 158
emilmont 1:fdd22bb7aa52 159 *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
emilmont 1:fdd22bb7aa52 160 (in2 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 161
emilmont 1:fdd22bb7aa52 162 #else
emilmont 1:fdd22bb7aa52 163
emilmont 1:fdd22bb7aa52 164 *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
emilmont 1:fdd22bb7aa52 165 (in1 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 166
emilmont 1:fdd22bb7aa52 167 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 168
emilmont 1:fdd22bb7aa52 169 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 170 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 171
emilmont 1:fdd22bb7aa52 172 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 173
emilmont 1:fdd22bb7aa52 174 *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
emilmont 1:fdd22bb7aa52 175 (in2 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 176
emilmont 1:fdd22bb7aa52 177 #else
emilmont 1:fdd22bb7aa52 178
emilmont 1:fdd22bb7aa52 179 *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
emilmont 1:fdd22bb7aa52 180 (in1 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 181
emilmont 1:fdd22bb7aa52 182 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 183
emilmont 1:fdd22bb7aa52 184 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 185 blkCnt--;
emilmont 1:fdd22bb7aa52 186 }
emilmont 1:fdd22bb7aa52 187
emilmont 1:fdd22bb7aa52 188 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 189 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 190 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 191
emilmont 1:fdd22bb7aa52 192 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 193 {
emilmont 1:fdd22bb7aa52 194 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 195 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 196 *pDst++ = (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 197
emilmont 1:fdd22bb7aa52 198 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 199 blkCnt--;
emilmont 1:fdd22bb7aa52 200 }
emilmont 1:fdd22bb7aa52 201 }
emilmont 1:fdd22bb7aa52 202
emilmont 1:fdd22bb7aa52 203 #else
emilmont 1:fdd22bb7aa52 204
emilmont 1:fdd22bb7aa52 205 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 206
emilmont 1:fdd22bb7aa52 207 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 208 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 209
emilmont 1:fdd22bb7aa52 210 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 211 if(sign == 0u)
emilmont 1:fdd22bb7aa52 212 {
emilmont 1:fdd22bb7aa52 213 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 214 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 215
emilmont 1:fdd22bb7aa52 216 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 217 {
emilmont 1:fdd22bb7aa52 218 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 219 /* Shift and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 220 *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
emilmont 1:fdd22bb7aa52 221
emilmont 1:fdd22bb7aa52 222 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 223 blkCnt--;
emilmont 1:fdd22bb7aa52 224 }
emilmont 1:fdd22bb7aa52 225 }
emilmont 1:fdd22bb7aa52 226 else
emilmont 1:fdd22bb7aa52 227 {
emilmont 1:fdd22bb7aa52 228 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 229 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 230
emilmont 1:fdd22bb7aa52 231 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 232 {
emilmont 1:fdd22bb7aa52 233 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 234 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 235 *pDst++ = (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 236
emilmont 1:fdd22bb7aa52 237 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 238 blkCnt--;
emilmont 1:fdd22bb7aa52 239 }
emilmont 1:fdd22bb7aa52 240 }
emilmont 1:fdd22bb7aa52 241
mbed_official 3:7a284390b0ce 242 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 243
emilmont 1:fdd22bb7aa52 244 }
emilmont 1:fdd22bb7aa52 245
emilmont 1:fdd22bb7aa52 246 /**
emilmont 1:fdd22bb7aa52 247 * @} end of shift group
emilmont 1:fdd22bb7aa52 248 */