Michele Riccio / mbed-dsp_F767ZI

mbed-os 6.10 versione

cmsis_dsp/BasicMathFunctions/arm_shift_q15.c@1:fdd22bb7aa52, 2012-11-28 (annotated)

Committer:
emilmont
Date:
Wed Nov 28 12:30:09 2012 +0000
Revision:
1:fdd22bb7aa52
Child:
2:da51fb522205
DSP library code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
emilmont 1:fdd22bb7aa52 2 * Copyright (C) 2010 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
emilmont 1:fdd22bb7aa52 4 * $Date: 15. February 2012
emilmont 1:fdd22bb7aa52 5 * $Revision: V1.1.0
emilmont 1:fdd22bb7aa52 6 *
emilmont 1:fdd22bb7aa52 7 * Project: CMSIS DSP Library
emilmont 1:fdd22bb7aa52 8 * Title: arm_shift_q15.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 1:fdd22bb7aa52 10 * Description: Shifts the elements of a Q15 vector by a specified number of bits.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
emilmont 1:fdd22bb7aa52 14 * Version 1.1.0 2012/02/15
emilmont 1:fdd22bb7aa52 15 * Updated with more optimizations, bug fixes and minor API changes.
emilmont 1:fdd22bb7aa52 16 *
emilmont 1:fdd22bb7aa52 17 * Version 1.0.10 2011/7/15
emilmont 1:fdd22bb7aa52 18 * Big Endian support added and Merged M0 and M3/M4 Source code.
emilmont 1:fdd22bb7aa52 19 *
emilmont 1:fdd22bb7aa52 20 * Version 1.0.3 2010/11/29
emilmont 1:fdd22bb7aa52 21 * Re-organized the CMSIS folders and updated documentation.
emilmont 1:fdd22bb7aa52 22 *
emilmont 1:fdd22bb7aa52 23 * Version 1.0.2 2010/11/11
emilmont 1:fdd22bb7aa52 24 * Documentation updated.
emilmont 1:fdd22bb7aa52 25 *
emilmont 1:fdd22bb7aa52 26 * Version 1.0.1 2010/10/05
emilmont 1:fdd22bb7aa52 27 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 28 *
emilmont 1:fdd22bb7aa52 29 * Version 1.0.0 2010/09/20
emilmont 1:fdd22bb7aa52 30 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 31 *
emilmont 1:fdd22bb7aa52 32 * Version 0.0.7 2010/06/10
emilmont 1:fdd22bb7aa52 33 * Misra-C changes done
emilmont 1:fdd22bb7aa52 34 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 35
emilmont 1:fdd22bb7aa52 36 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 37
emilmont 1:fdd22bb7aa52 38 /**
emilmont 1:fdd22bb7aa52 39 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 40 */
emilmont 1:fdd22bb7aa52 41
emilmont 1:fdd22bb7aa52 42 /**
emilmont 1:fdd22bb7aa52 43 * @addtogroup shift
emilmont 1:fdd22bb7aa52 44 * @{
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @brief Shifts the elements of a Q15 vector a specified number of bits.
emilmont 1:fdd22bb7aa52 49 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 50 * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
emilmont 1:fdd22bb7aa52 51 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 52 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 53 * @return none.
emilmont 1:fdd22bb7aa52 54 *
emilmont 1:fdd22bb7aa52 55 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 56 * \par
emilmont 1:fdd22bb7aa52 57 * The function uses saturating arithmetic.
emilmont 1:fdd22bb7aa52 58 * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
emilmont 1:fdd22bb7aa52 59 */
emilmont 1:fdd22bb7aa52 60
emilmont 1:fdd22bb7aa52 61 void arm_shift_q15(
emilmont 1:fdd22bb7aa52 62 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 63 int8_t shiftBits,
emilmont 1:fdd22bb7aa52 64 q15_t * pDst,
emilmont 1:fdd22bb7aa52 65 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 66 {
emilmont 1:fdd22bb7aa52 67 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 68 uint8_t sign; /* Sign of shiftBits */
emilmont 1:fdd22bb7aa52 69
emilmont 1:fdd22bb7aa52 70 #ifndef ARM_MATH_CM0
emilmont 1:fdd22bb7aa52 71
emilmont 1:fdd22bb7aa52 72 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 73
emilmont 1:fdd22bb7aa52 74 q15_t in1, in2; /* Temporary variables */
emilmont 1:fdd22bb7aa52 75
emilmont 1:fdd22bb7aa52 76
emilmont 1:fdd22bb7aa52 77 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 78 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 79
emilmont 1:fdd22bb7aa52 80 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 81 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 84 if(sign == 0u)
emilmont 1:fdd22bb7aa52 85 {
emilmont 1:fdd22bb7aa52 86 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 87 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 88 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 89 {
emilmont 1:fdd22bb7aa52 90 /* Read 2 inputs */
emilmont 1:fdd22bb7aa52 91 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 92 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 93 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 94 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 95 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 96
emilmont 1:fdd22bb7aa52 97 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 98 __SSAT((in2 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 99
emilmont 1:fdd22bb7aa52 100 #else
emilmont 1:fdd22bb7aa52 101
emilmont 1:fdd22bb7aa52 102 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 103 __SSAT((in1 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 104
emilmont 1:fdd22bb7aa52 105 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 106
emilmont 1:fdd22bb7aa52 107 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 108 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 109
emilmont 1:fdd22bb7aa52 110 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 111
emilmont 1:fdd22bb7aa52 112 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 113 __SSAT((in2 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 114
emilmont 1:fdd22bb7aa52 115 #else
emilmont 1:fdd22bb7aa52 116
emilmont 1:fdd22bb7aa52 117 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
emilmont 1:fdd22bb7aa52 118 __SSAT((in1 << shiftBits), 16), 16);
emilmont 1:fdd22bb7aa52 119
emilmont 1:fdd22bb7aa52 120 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 121
emilmont 1:fdd22bb7aa52 122 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 123 blkCnt--;
emilmont 1:fdd22bb7aa52 124 }
emilmont 1:fdd22bb7aa52 125
emilmont 1:fdd22bb7aa52 126 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 127 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 128 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 129
emilmont 1:fdd22bb7aa52 130 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 131 {
emilmont 1:fdd22bb7aa52 132 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 133 /* Shift and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 134 *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
emilmont 1:fdd22bb7aa52 135
emilmont 1:fdd22bb7aa52 136 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 137 blkCnt--;
emilmont 1:fdd22bb7aa52 138 }
emilmont 1:fdd22bb7aa52 139 }
emilmont 1:fdd22bb7aa52 140 else
emilmont 1:fdd22bb7aa52 141 {
emilmont 1:fdd22bb7aa52 142 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 143 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 144 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 145 {
emilmont 1:fdd22bb7aa52 146 /* Read 2 inputs */
emilmont 1:fdd22bb7aa52 147 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 148 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 149
emilmont 1:fdd22bb7aa52 150 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 151 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 152 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 153
emilmont 1:fdd22bb7aa52 154 *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
emilmont 1:fdd22bb7aa52 155 (in2 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 156
emilmont 1:fdd22bb7aa52 157 #else
emilmont 1:fdd22bb7aa52 158
emilmont 1:fdd22bb7aa52 159 *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
emilmont 1:fdd22bb7aa52 160 (in1 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 161
emilmont 1:fdd22bb7aa52 162 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 163
emilmont 1:fdd22bb7aa52 164 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 165 in2 = *pSrc++;
emilmont 1:fdd22bb7aa52 166
emilmont 1:fdd22bb7aa52 167 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 168
emilmont 1:fdd22bb7aa52 169 *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
emilmont 1:fdd22bb7aa52 170 (in2 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 171
emilmont 1:fdd22bb7aa52 172 #else
emilmont 1:fdd22bb7aa52 173
emilmont 1:fdd22bb7aa52 174 *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
emilmont 1:fdd22bb7aa52 175 (in1 >> -shiftBits), 16);
emilmont 1:fdd22bb7aa52 176
emilmont 1:fdd22bb7aa52 177 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 178
emilmont 1:fdd22bb7aa52 179 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 180 blkCnt--;
emilmont 1:fdd22bb7aa52 181 }
emilmont 1:fdd22bb7aa52 182
emilmont 1:fdd22bb7aa52 183 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 184 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 185 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 186
emilmont 1:fdd22bb7aa52 187 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 188 {
emilmont 1:fdd22bb7aa52 189 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 190 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 191 *pDst++ = (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 192
emilmont 1:fdd22bb7aa52 193 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 194 blkCnt--;
emilmont 1:fdd22bb7aa52 195 }
emilmont 1:fdd22bb7aa52 196 }
emilmont 1:fdd22bb7aa52 197
emilmont 1:fdd22bb7aa52 198 #else
emilmont 1:fdd22bb7aa52 199
emilmont 1:fdd22bb7aa52 200 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 201
emilmont 1:fdd22bb7aa52 202 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 203 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 204
emilmont 1:fdd22bb7aa52 205 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 206 if(sign == 0u)
emilmont 1:fdd22bb7aa52 207 {
emilmont 1:fdd22bb7aa52 208 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 209 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 210
emilmont 1:fdd22bb7aa52 211 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 212 {
emilmont 1:fdd22bb7aa52 213 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 214 /* Shift and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 215 *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
emilmont 1:fdd22bb7aa52 216
emilmont 1:fdd22bb7aa52 217 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 218 blkCnt--;
emilmont 1:fdd22bb7aa52 219 }
emilmont 1:fdd22bb7aa52 220 }
emilmont 1:fdd22bb7aa52 221 else
emilmont 1:fdd22bb7aa52 222 {
emilmont 1:fdd22bb7aa52 223 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 224 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 225
emilmont 1:fdd22bb7aa52 226 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 227 {
emilmont 1:fdd22bb7aa52 228 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 229 /* Shift the inputs and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 230 *pDst++ = (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 231
emilmont 1:fdd22bb7aa52 232 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 233 blkCnt--;
emilmont 1:fdd22bb7aa52 234 }
emilmont 1:fdd22bb7aa52 235 }
emilmont 1:fdd22bb7aa52 236
emilmont 1:fdd22bb7aa52 237 #endif /* #ifndef ARM_MATH_CM0 */
emilmont 1:fdd22bb7aa52 238
emilmont 1:fdd22bb7aa52 239 }
emilmont 1:fdd22bb7aa52 240
emilmont 1:fdd22bb7aa52 241 /**
emilmont 1:fdd22bb7aa52 242 * @} end of shift group
emilmont 1:fdd22bb7aa52 243 */