Mike Fruge / OneWire

Implementation of 1-Wire with added Alarm Search Functionality

Dependents:   Max32630_One_Wire_Interface

OneWire_Masters/DS248x/ds248x.cpp@15:f6cb0d906fb6, 2016-03-16 (annotated)

Committer:
j3
Date:
Wed Mar 16 01:19:45 2016 +0000
Revision:
15:f6cb0d906fb6
Parent:
14:7b2886a50321
Child:
17:b646b1e3970b
Removed duplicated code between masters by providing 'OneWireMaster' class that implements common parts of OneWireInterface.  OneWireMaster is now the class inherited by individual master implementations.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 1:91e52f8ab8bf 1 /******************************************************************//**
j3 1:91e52f8ab8bf 2 * @file ds248x.cpp
j3 1:91e52f8ab8bf 3 *
j3 1:91e52f8ab8bf 4 * @author Justin Jordan
j3 1:91e52f8ab8bf 5 *
j3 1:91e52f8ab8bf 6 * @version 0.0.0
j3 1:91e52f8ab8bf 7 *
j3 1:91e52f8ab8bf 8 * Started: 30JAN16
j3 1:91e52f8ab8bf 9 *
j3 1:91e52f8ab8bf 10 * Updated:
j3 1:91e52f8ab8bf 11 *
j3 1:91e52f8ab8bf 12 * @brief Source file for Ds248x I2C to 1-wire master
j3 1:91e52f8ab8bf 13 ***********************************************************************
j3 1:91e52f8ab8bf 14 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 1:91e52f8ab8bf 15 *
j3 1:91e52f8ab8bf 16 * Permission is hereby granted, free of charge, to any person obtaining a
j3 1:91e52f8ab8bf 17 * copy of this software and associated documentation files (the "Software"),
j3 1:91e52f8ab8bf 18 * to deal in the Software without restriction, including without limitation
j3 1:91e52f8ab8bf 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 1:91e52f8ab8bf 20 * and/or sell copies of the Software, and to permit persons to whom the
j3 1:91e52f8ab8bf 21 * Software is furnished to do so, subject to the following conditions:
j3 1:91e52f8ab8bf 22 *
j3 1:91e52f8ab8bf 23 * The above copyright notice and this permission notice shall be included
j3 1:91e52f8ab8bf 24 * in all copies or substantial portions of the Software.
j3 1:91e52f8ab8bf 25 *
j3 1:91e52f8ab8bf 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 1:91e52f8ab8bf 27 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 1:91e52f8ab8bf 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 1:91e52f8ab8bf 29 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 1:91e52f8ab8bf 30 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 1:91e52f8ab8bf 31 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 1:91e52f8ab8bf 32 * OTHER DEALINGS IN THE SOFTWARE.
j3 1:91e52f8ab8bf 33 *
j3 1:91e52f8ab8bf 34 * Except as contained in this notice, the name of Maxim Integrated
j3 1:91e52f8ab8bf 35 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 1:91e52f8ab8bf 36 * Products, Inc. Branding Policy.
j3 1:91e52f8ab8bf 37 *
j3 1:91e52f8ab8bf 38 * The mere transfer of this software does not imply any licenses
j3 1:91e52f8ab8bf 39 * of trade secrets, proprietary technology, copyrights, patents,
j3 1:91e52f8ab8bf 40 * trademarks, maskwork rights, or any other form of intellectual
j3 1:91e52f8ab8bf 41 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 1:91e52f8ab8bf 42 * ownership rights.
j3 1:91e52f8ab8bf 43 **********************************************************************/
j3 1:91e52f8ab8bf 44
j3 1:91e52f8ab8bf 45
j3 1:91e52f8ab8bf 46 #include "ds248x.h"
j3 1:91e52f8ab8bf 47
j3 1:91e52f8ab8bf 48
j3 1:91e52f8ab8bf 49 //*********************************************************************
j3 5:ce108eeb878d 50 Ds248x::Ds248x(I2C &i2c_bus, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 51 :_p_i2c_bus(&i2c_bus), _i2c_owner(false)
j3 1:91e52f8ab8bf 52 {
j3 6:1faafa0b3cd7 53 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 54 }
j3 1:91e52f8ab8bf 55
j3 1:91e52f8ab8bf 56
j3 1:91e52f8ab8bf 57 //*********************************************************************
j3 5:ce108eeb878d 58 Ds248x::Ds248x(PinName sda, PinName scl, DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 59 :_p_i2c_bus(new I2C(sda, scl)), _i2c_owner(true)
j3 1:91e52f8ab8bf 60 {
j3 6:1faafa0b3cd7 61 set_i2c_adrs(adrs);
j3 1:91e52f8ab8bf 62 }
j3 1:91e52f8ab8bf 63
j3 1:91e52f8ab8bf 64
j3 1:91e52f8ab8bf 65 //*********************************************************************
j3 1:91e52f8ab8bf 66 Ds248x::~Ds248x()
j3 1:91e52f8ab8bf 67 {
j3 5:ce108eeb878d 68 if(_i2c_owner)
j3 1:91e52f8ab8bf 69 {
j3 1:91e52f8ab8bf 70 delete _p_i2c_bus;
j3 1:91e52f8ab8bf 71 }
j3 1:91e52f8ab8bf 72 }
j3 1:91e52f8ab8bf 73
j3 1:91e52f8ab8bf 74
j3 1:91e52f8ab8bf 75 //*********************************************************************
j3 14:7b2886a50321 76 bool Ds248x::OWInitMaster()
j3 14:7b2886a50321 77 {
j3 14:7b2886a50321 78 return(detect());
j3 14:7b2886a50321 79 }
j3 14:7b2886a50321 80
j3 14:7b2886a50321 81
j3 14:7b2886a50321 82 //*********************************************************************
j3 2:02d228c25fd4 83 bool Ds248x::detect(void)
j3 2:02d228c25fd4 84 {
j3 2:02d228c25fd4 85 bool rtn_val = false;
j3 2:02d228c25fd4 86
j3 2:02d228c25fd4 87 // reset the ds2484 ON selected address
j3 2:02d228c25fd4 88 if (!reset())
j3 2:02d228c25fd4 89 {
j3 2:02d228c25fd4 90 rtn_val = false;
j3 2:02d228c25fd4 91 }
j3 2:02d228c25fd4 92 else
j3 2:02d228c25fd4 93 {
j3 2:02d228c25fd4 94 // default configuration
j3 5:ce108eeb878d 95 _c1WS = false;
j3 5:ce108eeb878d 96 _cSPU = false;
j3 5:ce108eeb878d 97 _cPDN = false;
j3 5:ce108eeb878d 98 _cAPU = false;
j3 2:02d228c25fd4 99
j3 2:02d228c25fd4 100 // write the default configuration setup
j3 2:02d228c25fd4 101 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 102 {
j3 2:02d228c25fd4 103 rtn_val = false;
j3 2:02d228c25fd4 104 }
j3 2:02d228c25fd4 105 else
j3 2:02d228c25fd4 106 {
j3 2:02d228c25fd4 107 rtn_val = true;
j3 2:02d228c25fd4 108 }
j3 2:02d228c25fd4 109 }
j3 2:02d228c25fd4 110
j3 2:02d228c25fd4 111 return(rtn_val);
j3 2:02d228c25fd4 112 }
j3 2:02d228c25fd4 113
j3 2:02d228c25fd4 114
j3 2:02d228c25fd4 115 //*********************************************************************
j3 2:02d228c25fd4 116 bool Ds248x::reset(void)
j3 1:91e52f8ab8bf 117 {
j3 2:02d228c25fd4 118 char status;
j3 2:02d228c25fd4 119 char packet[] = {CMD_DRST};
j3 2:02d228c25fd4 120
j3 2:02d228c25fd4 121 // Device Reset
j3 2:02d228c25fd4 122 // S AD,0 [A] DRST [A] Sr AD,1 [A] [SS] A\ P
j3 2:02d228c25fd4 123 // [] indicates from slave
j3 2:02d228c25fd4 124 // SS status byte to read to verify state
j3 2:02d228c25fd4 125
j3 2:02d228c25fd4 126 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 127 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 128
j3 2:02d228c25fd4 129 return((status & 0xF7) == 0x10);
j3 2:02d228c25fd4 130 }
j3 2:02d228c25fd4 131
j3 2:02d228c25fd4 132
j3 2:02d228c25fd4 133 //*********************************************************************
j3 2:02d228c25fd4 134 bool Ds248x::write_config(uint8_t config)
j3 2:02d228c25fd4 135 {
j3 2:02d228c25fd4 136 bool rtn_val = false;
j3 2:02d228c25fd4 137 char read_config;
j3 2:02d228c25fd4 138 char packet [] = {CMD_WCFG, (config | (~config << 4))};
j3 2:02d228c25fd4 139
j3 2:02d228c25fd4 140 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 141 _p_i2c_bus->read(_r_adrs, &read_config, 1);
j3 2:02d228c25fd4 142
j3 2:02d228c25fd4 143 // check for failure due to incorrect read back
j3 2:02d228c25fd4 144 if (config != read_config)
j3 2:02d228c25fd4 145 {
j3 2:02d228c25fd4 146 // handle error
j3 2:02d228c25fd4 147 // ...
j3 2:02d228c25fd4 148 reset();
j3 2:02d228c25fd4 149 rtn_val = false;
j3 2:02d228c25fd4 150 }
j3 2:02d228c25fd4 151 else
j3 2:02d228c25fd4 152 {
j3 2:02d228c25fd4 153 rtn_val = true;
j3 2:02d228c25fd4 154 }
j3 2:02d228c25fd4 155
j3 1:91e52f8ab8bf 156 return(rtn_val);
j3 1:91e52f8ab8bf 157 }
j3 1:91e52f8ab8bf 158
j3 1:91e52f8ab8bf 159
j3 1:91e52f8ab8bf 160 //*********************************************************************
j3 2:02d228c25fd4 161 bool Ds248x::channel_select(uint8_t channel)
j3 1:91e52f8ab8bf 162 {
j3 2:02d228c25fd4 163
j3 2:02d228c25fd4 164 char ch, ch_read, check;
j3 2:02d228c25fd4 165 char packet [2];
j3 2:02d228c25fd4 166
j3 2:02d228c25fd4 167 packet[0] = CMD_CHSL;
j3 2:02d228c25fd4 168
j3 2:02d228c25fd4 169 // Channel Select (Case A)
j3 2:02d228c25fd4 170 // S AD,0 [A] CHSL [A] CC [A] Sr AD,1 [A] [RR] A\ P
j3 2:02d228c25fd4 171 // [] indicates from slave
j3 2:02d228c25fd4 172 // CC channel value
j3 2:02d228c25fd4 173 // RR channel read back
j3 2:02d228c25fd4 174
j3 2:02d228c25fd4 175 switch (channel)
j3 2:02d228c25fd4 176 {
j3 2:02d228c25fd4 177 default: case 0: ch = 0xF0; ch_read = 0xB8; break;
j3 2:02d228c25fd4 178 case 1: ch = 0xE1; ch_read = 0xB1; break;
j3 2:02d228c25fd4 179 case 2: ch = 0xD2; ch_read = 0xAA; break;
j3 2:02d228c25fd4 180 case 3: ch = 0xC3; ch_read = 0xA3; break;
j3 2:02d228c25fd4 181 case 4: ch = 0xB4; ch_read = 0x9C; break;
j3 2:02d228c25fd4 182 case 5: ch = 0xA5; ch_read = 0x95; break;
j3 2:02d228c25fd4 183 case 6: ch = 0x96; ch_read = 0x8E; break;
j3 2:02d228c25fd4 184 case 7: ch = 0x87; ch_read = 0x87; break;
j3 2:02d228c25fd4 185 };
j3 2:02d228c25fd4 186
j3 2:02d228c25fd4 187 packet[1] = ch;
j3 2:02d228c25fd4 188
j3 2:02d228c25fd4 189 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 190 _p_i2c_bus->read(_r_adrs, &check, 1);
j3 2:02d228c25fd4 191
j3 2:02d228c25fd4 192 // check for failure due to incorrect read back of channel
j3 2:02d228c25fd4 193 return (check == ch_read);
j3 2:02d228c25fd4 194 }
j3 2:02d228c25fd4 195
j3 2:02d228c25fd4 196
j3 2:02d228c25fd4 197 //*********************************************************************
j3 2:02d228c25fd4 198 bool Ds248x::adjust_timing(uint8_t param, uint8_t val)
j3 2:02d228c25fd4 199 {
j3 2:02d228c25fd4 200 bool rtn_val = false;
j3 2:02d228c25fd4 201 char read_port_config;
j3 2:02d228c25fd4 202 char control_byte;
j3 2:02d228c25fd4 203
j3 2:02d228c25fd4 204 control_byte = (((param & 0x0F) << 4) | (val & 0x0F));
j3 2:02d228c25fd4 205
j3 2:02d228c25fd4 206 char packet [] = {CMD_A1WP, control_byte};
j3 2:02d228c25fd4 207
j3 2:02d228c25fd4 208 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 209 _p_i2c_bus->read(_r_adrs, &read_port_config, 1);
j3 2:02d228c25fd4 210
j3 2:02d228c25fd4 211 // check for failure due to incorrect read back
j3 2:02d228c25fd4 212 if ((control_byte & 0x0F) != read_port_config)
j3 2:02d228c25fd4 213 {
j3 2:02d228c25fd4 214 // handle error
j3 2:02d228c25fd4 215 // ...
j3 2:02d228c25fd4 216 reset();
j3 2:02d228c25fd4 217
j3 2:02d228c25fd4 218 rtn_val = false;
j3 2:02d228c25fd4 219 }
j3 2:02d228c25fd4 220 else
j3 2:02d228c25fd4 221 {
j3 2:02d228c25fd4 222 rtn_val = true;
j3 2:02d228c25fd4 223 }
j3 2:02d228c25fd4 224
j3 2:02d228c25fd4 225 return(rtn_val);
j3 1:91e52f8ab8bf 226 }
j3 1:91e52f8ab8bf 227
j3 1:91e52f8ab8bf 228
j3 1:91e52f8ab8bf 229 //*********************************************************************
j3 2:02d228c25fd4 230 uint8_t Ds248x::search_triplet(uint8_t search_direction)
j3 1:91e52f8ab8bf 231 {
j3 2:02d228c25fd4 232 uint8_t rtn_val = 0;
j3 2:02d228c25fd4 233 uint8_t poll_count = 0;
j3 2:02d228c25fd4 234 char status;
j3 2:02d228c25fd4 235 char packet [] = {CMD_1WT, search_direction ? 0x80 : 0x00};
j3 2:02d228c25fd4 236
j3 2:02d228c25fd4 237 // 1-Wire Triplet (Case B)
j3 2:02d228c25fd4 238 // S AD,0 [A] 1WT [A] SS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 239 // \--------/
j3 2:02d228c25fd4 240 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 241 // [] indicates from slave
j3 2:02d228c25fd4 242 // SS indicates byte containing search direction bit value in msbit
j3 2:02d228c25fd4 243
j3 2:02d228c25fd4 244 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 245
j3 2:02d228c25fd4 246 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 247 // abort if poll limit reached
j3 2:02d228c25fd4 248 do
j3 2:02d228c25fd4 249 {
j3 2:02d228c25fd4 250 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 251 }
j3 2:02d228c25fd4 252 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 253
j3 2:02d228c25fd4 254 // check for failure due to poll limit reached
j3 2:02d228c25fd4 255 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 256 {
j3 2:02d228c25fd4 257 // handle error
j3 2:02d228c25fd4 258 // ...
j3 2:02d228c25fd4 259 reset();
j3 5:ce108eeb878d 260 rtn_val = false;
j3 2:02d228c25fd4 261 }
j3 2:02d228c25fd4 262 else
j3 2:02d228c25fd4 263 {
j3 2:02d228c25fd4 264 rtn_val = status;
j3 2:02d228c25fd4 265 }
j3 2:02d228c25fd4 266
j3 2:02d228c25fd4 267 return(rtn_val);
j3 1:91e52f8ab8bf 268 }
j3 1:91e52f8ab8bf 269
j3 1:91e52f8ab8bf 270
j3 1:91e52f8ab8bf 271 //*********************************************************************
j3 2:02d228c25fd4 272 bool Ds248x::OWReset()
j3 2:02d228c25fd4 273 {
j3 2:02d228c25fd4 274 bool rtn_val = false;
j3 2:02d228c25fd4 275
j3 2:02d228c25fd4 276 uint8_t poll_count = 0;
j3 2:02d228c25fd4 277 char status;
j3 2:02d228c25fd4 278 char packet [] = {CMD_1WRS};
j3 1:91e52f8ab8bf 279
j3 2:02d228c25fd4 280 // 1-Wire reset (Case B)
j3 2:02d228c25fd4 281 // S AD,0 [A] 1WRS [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 282 // \--------/
j3 2:02d228c25fd4 283 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 284 // [] indicates from slave
j3 2:02d228c25fd4 285
j3 2:02d228c25fd4 286 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 287
j3 2:02d228c25fd4 288 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 289 // abort if poll limit reached
j3 2:02d228c25fd4 290 do
j3 2:02d228c25fd4 291 {
j3 2:02d228c25fd4 292 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 293 }
j3 2:02d228c25fd4 294 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 1:91e52f8ab8bf 295
j3 2:02d228c25fd4 296 // check for failure due to poll limit reached
j3 2:02d228c25fd4 297 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 298 {
j3 2:02d228c25fd4 299 // handle error
j3 2:02d228c25fd4 300 // ...
j3 2:02d228c25fd4 301 reset();
j3 2:02d228c25fd4 302 rtn_val = false;
j3 2:02d228c25fd4 303 }
j3 2:02d228c25fd4 304 else
j3 2:02d228c25fd4 305 {
j3 2:02d228c25fd4 306 // check for short condition
j3 2:02d228c25fd4 307 if (status & STATUS_SD)
j3 2:02d228c25fd4 308 {
j3 5:ce108eeb878d 309 _short_detected = true;
j3 2:02d228c25fd4 310 }
j3 2:02d228c25fd4 311 else
j3 2:02d228c25fd4 312 {
j3 5:ce108eeb878d 313 _short_detected = false;
j3 2:02d228c25fd4 314 }
j3 2:02d228c25fd4 315
j3 2:02d228c25fd4 316 // check for presence detect
j3 2:02d228c25fd4 317 if (status & STATUS_PPD)
j3 2:02d228c25fd4 318 {
j3 2:02d228c25fd4 319 rtn_val = true;
j3 2:02d228c25fd4 320 }
j3 2:02d228c25fd4 321 else
j3 2:02d228c25fd4 322 {
j3 2:02d228c25fd4 323 rtn_val = false;
j3 2:02d228c25fd4 324 }
j3 2:02d228c25fd4 325 }
j3 2:02d228c25fd4 326
j3 1:91e52f8ab8bf 327 return(rtn_val);
j3 1:91e52f8ab8bf 328 }
j3 1:91e52f8ab8bf 329
j3 1:91e52f8ab8bf 330
j3 1:91e52f8ab8bf 331 //*********************************************************************
j3 1:91e52f8ab8bf 332 uint8_t Ds248x::OWTouchBit(uint8_t sendbit)
j3 1:91e52f8ab8bf 333 {
j3 1:91e52f8ab8bf 334 uint8_t rtn_val;
j3 2:02d228c25fd4 335 uint8_t poll_count = 0;
j3 2:02d228c25fd4 336 char status;
j3 2:02d228c25fd4 337 char packet[] = {CMD_1WSB, sendbit ? 0x80 : 0x00};
j3 2:02d228c25fd4 338
j3 2:02d228c25fd4 339 // 1-Wire bit (Case B)
j3 2:02d228c25fd4 340 // S AD,0 [A] 1WSB [A] BB [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 341 // \--------/
j3 2:02d228c25fd4 342 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 343 // [] indicates from slave
j3 2:02d228c25fd4 344 // BB indicates byte containing bit value in msbit
j3 2:02d228c25fd4 345
j3 2:02d228c25fd4 346 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 347
j3 2:02d228c25fd4 348 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 349 // abort if poll limit reached
j3 2:02d228c25fd4 350 do
j3 2:02d228c25fd4 351 {
j3 2:02d228c25fd4 352 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 353 }
j3 2:02d228c25fd4 354 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 355
j3 2:02d228c25fd4 356 // check for failure due to poll limit reached
j3 2:02d228c25fd4 357 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 358 {
j3 2:02d228c25fd4 359 // handle error
j3 2:02d228c25fd4 360 // ...
j3 2:02d228c25fd4 361 reset();
j3 2:02d228c25fd4 362 rtn_val = 0;
j3 2:02d228c25fd4 363 }
j3 2:02d228c25fd4 364 else
j3 2:02d228c25fd4 365 {
j3 2:02d228c25fd4 366 // return bit state
j3 2:02d228c25fd4 367 if (status & STATUS_SBR)
j3 2:02d228c25fd4 368 {
j3 2:02d228c25fd4 369 rtn_val = 1;
j3 2:02d228c25fd4 370 }
j3 2:02d228c25fd4 371 else
j3 2:02d228c25fd4 372 {
j3 2:02d228c25fd4 373 rtn_val = 0;
j3 2:02d228c25fd4 374 }
j3 2:02d228c25fd4 375 }
j3 2:02d228c25fd4 376
j3 2:02d228c25fd4 377 return(rtn_val);
j3 1:91e52f8ab8bf 378 }
j3 1:91e52f8ab8bf 379
j3 1:91e52f8ab8bf 380
j3 1:91e52f8ab8bf 381 //*********************************************************************
j3 2:02d228c25fd4 382 bool Ds248x::OWWriteByte(uint8_t sendbyte)
j3 1:91e52f8ab8bf 383 {
j3 2:02d228c25fd4 384 bool rtn_val = false;
j3 1:91e52f8ab8bf 385
j3 2:02d228c25fd4 386 uint8_t poll_count = 0;
j3 2:02d228c25fd4 387 char status;
j3 2:02d228c25fd4 388 char packet [] = {CMD_1WWB, sendbyte};
j3 2:02d228c25fd4 389
j3 2:02d228c25fd4 390 // 1-Wire Write Byte (Case B)
j3 2:02d228c25fd4 391 // S AD,0 [A] 1WWB [A] DD [A] Sr AD,1 [A] [Status] A [Status] A\ P
j3 2:02d228c25fd4 392 // \--------/
j3 2:02d228c25fd4 393 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 394 // [] indicates from slave
j3 2:02d228c25fd4 395 // DD data to write
j3 2:02d228c25fd4 396
j3 2:02d228c25fd4 397 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 398
j3 2:02d228c25fd4 399 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 400 // abort if poll limit reached
j3 2:02d228c25fd4 401 do
j3 2:02d228c25fd4 402 {
j3 2:02d228c25fd4 403 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 404 }
j3 2:02d228c25fd4 405 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 406
j3 2:02d228c25fd4 407 // check for failure due to poll limit reached
j3 2:02d228c25fd4 408 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 409 {
j3 2:02d228c25fd4 410 // handle error
j3 2:02d228c25fd4 411 // ...
j3 2:02d228c25fd4 412 reset();
j3 2:02d228c25fd4 413 rtn_val = false;
j3 2:02d228c25fd4 414 }
j3 2:02d228c25fd4 415 else
j3 2:02d228c25fd4 416 {
j3 2:02d228c25fd4 417 rtn_val = true;
j3 2:02d228c25fd4 418 }
j3 2:02d228c25fd4 419
j3 2:02d228c25fd4 420 return(rtn_val);
j3 1:91e52f8ab8bf 421 }
j3 1:91e52f8ab8bf 422
j3 1:91e52f8ab8bf 423
j3 1:91e52f8ab8bf 424 //*********************************************************************
j3 1:91e52f8ab8bf 425 uint8_t Ds248x::OWReadByte(void)
j3 1:91e52f8ab8bf 426 {
j3 1:91e52f8ab8bf 427 uint8_t rtn_val;
j3 2:02d228c25fd4 428
j3 2:02d228c25fd4 429 uint8_t poll_count = 0;
j3 2:02d228c25fd4 430 char data, status;
j3 2:02d228c25fd4 431 char packet[2] = {CMD_1WRB, 0};
j3 2:02d228c25fd4 432
j3 2:02d228c25fd4 433 // 1-Wire Read Bytes (Case C)
j3 2:02d228c25fd4 434 // S AD,0 [A] 1WRB [A] Sr AD,1 [A] [Status] A [Status] A\
j3 2:02d228c25fd4 435 // \--------/
j3 2:02d228c25fd4 436 // Repeat until 1WB bit has changed to 0
j3 2:02d228c25fd4 437 // Sr AD,0 [A] SRP [A] E1 [A] Sr AD,1 [A] DD A\ P
j3 2:02d228c25fd4 438 //
j3 2:02d228c25fd4 439 // [] indicates from slave
j3 2:02d228c25fd4 440 // DD data read
j3 2:02d228c25fd4 441
j3 2:02d228c25fd4 442 _p_i2c_bus->write(_w_adrs, packet, 1);
j3 2:02d228c25fd4 443
j3 2:02d228c25fd4 444 // loop checking 1WB bit for completion of 1-Wire operation
j3 2:02d228c25fd4 445 // abort if poll limit reached
j3 2:02d228c25fd4 446 do
j3 2:02d228c25fd4 447 {
j3 2:02d228c25fd4 448 _p_i2c_bus->read(_r_adrs, &status, 1);
j3 2:02d228c25fd4 449 }
j3 2:02d228c25fd4 450 while ((status & STATUS_1WB) && (poll_count++ < POLL_LIMIT));
j3 2:02d228c25fd4 451
j3 2:02d228c25fd4 452 // check for failure due to poll limit reached
j3 2:02d228c25fd4 453 if (poll_count >= POLL_LIMIT)
j3 2:02d228c25fd4 454 {
j3 2:02d228c25fd4 455 // handle error
j3 2:02d228c25fd4 456 // ...
j3 2:02d228c25fd4 457 reset();
j3 2:02d228c25fd4 458 rtn_val = 0;
j3 2:02d228c25fd4 459 }
j3 2:02d228c25fd4 460 else
j3 2:02d228c25fd4 461 {
j3 2:02d228c25fd4 462 packet[0] = CMD_SRP;
j3 2:02d228c25fd4 463 packet[1] = 0xE1;
j3 2:02d228c25fd4 464
j3 2:02d228c25fd4 465 _p_i2c_bus->write(_w_adrs, packet, 2);
j3 2:02d228c25fd4 466 _p_i2c_bus->read(_r_adrs, &data, 1);
j3 2:02d228c25fd4 467
j3 2:02d228c25fd4 468 rtn_val = data;
j3 2:02d228c25fd4 469 }
j3 2:02d228c25fd4 470
j3 1:91e52f8ab8bf 471 return(rtn_val);
j3 1:91e52f8ab8bf 472 }
j3 1:91e52f8ab8bf 473
j3 1:91e52f8ab8bf 474
j3 1:91e52f8ab8bf 475 //*********************************************************************
j3 2:02d228c25fd4 476 bool Ds248x::OWSearch(void)
j3 1:91e52f8ab8bf 477 {
j3 2:02d228c25fd4 478 uint8_t id_bit_number;
j3 2:02d228c25fd4 479 uint8_t last_zero, rom_byte_number, search_result;
j3 2:02d228c25fd4 480 uint8_t id_bit, cmp_id_bit;
j3 2:02d228c25fd4 481 uint8_t rom_byte_mask, search_direction, status;
j3 2:02d228c25fd4 482
j3 2:02d228c25fd4 483 // initialize for search
j3 2:02d228c25fd4 484 id_bit_number = 1;
j3 2:02d228c25fd4 485 last_zero = 0;
j3 2:02d228c25fd4 486 rom_byte_number = 0;
j3 2:02d228c25fd4 487 rom_byte_mask = 1;
j3 5:ce108eeb878d 488 search_result = false;
j3 2:02d228c25fd4 489 _crc8 = 0;
j3 2:02d228c25fd4 490
j3 2:02d228c25fd4 491 // if the last call was not the last one
j3 2:02d228c25fd4 492 if (!_last_device_flag)
j3 2:02d228c25fd4 493 {
j3 2:02d228c25fd4 494 // 1-Wire reset
j3 2:02d228c25fd4 495 if (!OWReset())
j3 2:02d228c25fd4 496 {
j3 2:02d228c25fd4 497 // reset the search
j3 2:02d228c25fd4 498 _last_discrepancy = 0;
j3 5:ce108eeb878d 499 _last_device_flag = false;
j3 2:02d228c25fd4 500 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 501 return false;
j3 2:02d228c25fd4 502 }
j3 2:02d228c25fd4 503
j3 2:02d228c25fd4 504 // issue the search command
j3 2:02d228c25fd4 505 OWWriteByte(SEARCH_ROM);
j3 2:02d228c25fd4 506
j3 2:02d228c25fd4 507 // loop to do the search
j3 2:02d228c25fd4 508 do
j3 2:02d228c25fd4 509 {
j3 2:02d228c25fd4 510 // if this discrepancy if before the Last Discrepancy
j3 2:02d228c25fd4 511 // on a previous next then pick the same as last time
j3 2:02d228c25fd4 512 if (id_bit_number < _last_discrepancy)
j3 2:02d228c25fd4 513 {
j3 2:02d228c25fd4 514 if ((_rom_number[rom_byte_number] & rom_byte_mask) > 0)
j3 2:02d228c25fd4 515 search_direction = 1;
j3 2:02d228c25fd4 516 else
j3 2:02d228c25fd4 517 search_direction = 0;
j3 2:02d228c25fd4 518 }
j3 2:02d228c25fd4 519 else
j3 2:02d228c25fd4 520 {
j3 2:02d228c25fd4 521 // if equal to last pick 1, if not then pick 0
j3 2:02d228c25fd4 522 if (id_bit_number == _last_discrepancy)
j3 2:02d228c25fd4 523 search_direction = 1;
j3 2:02d228c25fd4 524 else
j3 2:02d228c25fd4 525 search_direction = 0;
j3 2:02d228c25fd4 526 }
j3 2:02d228c25fd4 527
j3 2:02d228c25fd4 528 // Perform a triple operation on the ds2484 which will perform 2 read bits and 1 write bit
j3 2:02d228c25fd4 529 status = search_triplet(search_direction);
j3 2:02d228c25fd4 530
j3 2:02d228c25fd4 531 // check bit results in status byte
j3 2:02d228c25fd4 532 id_bit = ((status & STATUS_SBR) == STATUS_SBR);
j3 2:02d228c25fd4 533 cmp_id_bit = ((status & STATUS_TSB) == STATUS_TSB);
j3 2:02d228c25fd4 534 search_direction = ((status & STATUS_DIR) == STATUS_DIR) ? (unsigned char)1 : (unsigned char)0;
j3 2:02d228c25fd4 535
j3 2:02d228c25fd4 536 // check for no devices on 1-Wire
j3 2:02d228c25fd4 537 if ((id_bit) && (cmp_id_bit))
j3 2:02d228c25fd4 538 break;
j3 2:02d228c25fd4 539 else
j3 2:02d228c25fd4 540 {
j3 2:02d228c25fd4 541 if ((!id_bit) && (!cmp_id_bit) && (search_direction == 0))
j3 2:02d228c25fd4 542 {
j3 2:02d228c25fd4 543 last_zero = id_bit_number;
j3 2:02d228c25fd4 544
j3 2:02d228c25fd4 545 // check for Last discrepancy in family
j3 2:02d228c25fd4 546 if (last_zero < 9)
j3 2:02d228c25fd4 547 _last_family_discrepancy = last_zero;
j3 2:02d228c25fd4 548 }
j3 2:02d228c25fd4 549
j3 2:02d228c25fd4 550 // set or clear the bit in the ROM byte rom_byte_number
j3 2:02d228c25fd4 551 // with mask rom_byte_mask
j3 2:02d228c25fd4 552 if (search_direction == 1)
j3 2:02d228c25fd4 553 _rom_number[rom_byte_number] |= rom_byte_mask;
j3 2:02d228c25fd4 554 else
j3 2:02d228c25fd4 555 _rom_number[rom_byte_number] &= (unsigned char)~rom_byte_mask;
j3 2:02d228c25fd4 556
j3 2:02d228c25fd4 557 // increment the byte counter id_bit_number
j3 2:02d228c25fd4 558 // and shift the mask rom_byte_mask
j3 2:02d228c25fd4 559 id_bit_number++;
j3 2:02d228c25fd4 560 rom_byte_mask <<= 1;
j3 2:02d228c25fd4 561
j3 2:02d228c25fd4 562 // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
j3 2:02d228c25fd4 563 if (rom_byte_mask == 0)
j3 2:02d228c25fd4 564 {
j3 5:ce108eeb878d 565 _crc8 = OWCalc_crc8(_rom_number[rom_byte_number], _crc8); // accumulate the CRC
j3 2:02d228c25fd4 566 rom_byte_number++;
j3 2:02d228c25fd4 567 rom_byte_mask = 1;
j3 2:02d228c25fd4 568 }
j3 2:02d228c25fd4 569 }
j3 2:02d228c25fd4 570 }
j3 2:02d228c25fd4 571 while(rom_byte_number < 8); // loop until through all ROM bytes 0-7
j3 2:02d228c25fd4 572
j3 2:02d228c25fd4 573 // if the search was successful then
j3 2:02d228c25fd4 574 if (!((id_bit_number < 65) || (_crc8 != 0)))
j3 2:02d228c25fd4 575 {
j3 2:02d228c25fd4 576 // search successful so set LastDiscrepancy,LastDeviceFlag,search_result
j3 2:02d228c25fd4 577 _last_discrepancy = last_zero;
j3 2:02d228c25fd4 578
j3 2:02d228c25fd4 579 // check for last device
j3 2:02d228c25fd4 580 if (_last_discrepancy == 0)
j3 5:ce108eeb878d 581 _last_device_flag = true;
j3 2:02d228c25fd4 582
j3 5:ce108eeb878d 583 search_result = true;
j3 2:02d228c25fd4 584 }
j3 2:02d228c25fd4 585 }
j3 2:02d228c25fd4 586
j3 2:02d228c25fd4 587 // if no device found then reset counters so next 'search' will be like a first
j3 2:02d228c25fd4 588 if (!search_result || (_rom_number[0] == 0))
j3 2:02d228c25fd4 589 {
j3 2:02d228c25fd4 590 _last_discrepancy = 0;
j3 5:ce108eeb878d 591 _last_device_flag = false;
j3 2:02d228c25fd4 592 _last_family_discrepancy = 0;
j3 5:ce108eeb878d 593 search_result = false;
j3 2:02d228c25fd4 594 }
j3 2:02d228c25fd4 595
j3 2:02d228c25fd4 596 return search_result;
j3 1:91e52f8ab8bf 597 }
j3 1:91e52f8ab8bf 598
j3 1:91e52f8ab8bf 599
j3 1:91e52f8ab8bf 600 //*********************************************************************
j3 5:ce108eeb878d 601 uint8_t Ds248x::OWSpeed(OW_SPEED new_speed)
j3 1:91e52f8ab8bf 602 {
j3 2:02d228c25fd4 603 // set the speed
j3 5:ce108eeb878d 604 if (new_speed == SPEED_OVERDRIVE)
j3 2:02d228c25fd4 605 {
j3 2:02d228c25fd4 606 _c1WS = CONFIG_1WS;
j3 2:02d228c25fd4 607 }
j3 2:02d228c25fd4 608 else
j3 2:02d228c25fd4 609 {
j3 5:ce108eeb878d 610 _c1WS = false;
j3 2:02d228c25fd4 611 }
j3 2:02d228c25fd4 612
j3 2:02d228c25fd4 613 // write the new config
j3 2:02d228c25fd4 614 write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 2:02d228c25fd4 615
j3 2:02d228c25fd4 616 return(new_speed);
j3 1:91e52f8ab8bf 617 }
j3 1:91e52f8ab8bf 618
j3 1:91e52f8ab8bf 619
j3 1:91e52f8ab8bf 620 //*********************************************************************
j3 5:ce108eeb878d 621 uint8_t Ds248x::OWLevel(OW_LEVEL new_level)
j3 1:91e52f8ab8bf 622 {
j3 1:91e52f8ab8bf 623 uint8_t rtn_val;
j3 2:02d228c25fd4 624
j3 2:02d228c25fd4 625 // function only will turn back to non-strong pull-up
j3 5:ce108eeb878d 626 if (new_level != LEVEL_NORMAL)
j3 2:02d228c25fd4 627 {
j3 5:ce108eeb878d 628 rtn_val = LEVEL_STRONG;
j3 2:02d228c25fd4 629 }
j3 2:02d228c25fd4 630 else
j3 2:02d228c25fd4 631 {
j3 2:02d228c25fd4 632 // clear the strong pull-up bit in the global config state
j3 5:ce108eeb878d 633 _cSPU = false;
j3 2:02d228c25fd4 634 // write the new config
j3 2:02d228c25fd4 635 write_config(_c1WS | _cSPU | _cPDN | _cAPU);
j3 5:ce108eeb878d 636 rtn_val = LEVEL_NORMAL;
j3 2:02d228c25fd4 637 }
j3 2:02d228c25fd4 638
j3 1:91e52f8ab8bf 639 return(rtn_val);
j3 1:91e52f8ab8bf 640 }
j3 1:91e52f8ab8bf 641
j3 1:91e52f8ab8bf 642
j3 1:91e52f8ab8bf 643 //*********************************************************************
j3 2:02d228c25fd4 644 bool Ds248x::OWWriteBytePower(uint8_t sendbyte)
j3 1:91e52f8ab8bf 645 {
j3 2:02d228c25fd4 646 bool rtn_val = false;
j3 2:02d228c25fd4 647
j3 2:02d228c25fd4 648 // set strong pull-up enable
j3 2:02d228c25fd4 649 _cSPU = CONFIG_SPU;
j3 2:02d228c25fd4 650
j3 2:02d228c25fd4 651 // write the new config
j3 2:02d228c25fd4 652 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 653 {
j3 2:02d228c25fd4 654 rtn_val = false;
j3 2:02d228c25fd4 655 }
j3 2:02d228c25fd4 656 else
j3 2:02d228c25fd4 657 {
j3 2:02d228c25fd4 658 // perform write byte
j3 2:02d228c25fd4 659 OWWriteByte(sendbyte);
j3 2:02d228c25fd4 660 rtn_val = true;
j3 2:02d228c25fd4 661 }
j3 2:02d228c25fd4 662
j3 1:91e52f8ab8bf 663 return(rtn_val);
j3 1:91e52f8ab8bf 664 }
j3 1:91e52f8ab8bf 665
j3 1:91e52f8ab8bf 666
j3 1:91e52f8ab8bf 667 //*********************************************************************
j3 2:02d228c25fd4 668 bool Ds248x::OWReadBitPower(uint8_t applyPowerResponse)
j3 1:91e52f8ab8bf 669 {
j3 2:02d228c25fd4 670 bool rtn_val = false;
j3 2:02d228c25fd4 671
j3 2:02d228c25fd4 672 uint8_t rdbit;
j3 2:02d228c25fd4 673
j3 2:02d228c25fd4 674 // set strong pull-up enable
j3 2:02d228c25fd4 675 _cSPU = CONFIG_SPU;
j3 2:02d228c25fd4 676
j3 2:02d228c25fd4 677 // write the new config
j3 2:02d228c25fd4 678 if (!write_config(_c1WS | _cSPU | _cPDN | _cAPU))
j3 2:02d228c25fd4 679 {
j3 2:02d228c25fd4 680 rtn_val = false;
j3 2:02d228c25fd4 681 }
j3 2:02d228c25fd4 682 else
j3 2:02d228c25fd4 683 {
j3 2:02d228c25fd4 684 // perform read bit
j3 2:02d228c25fd4 685 rdbit = OWReadBit();
j3 2:02d228c25fd4 686
j3 2:02d228c25fd4 687 // check if response was correct, if not then turn off strong pull-up
j3 2:02d228c25fd4 688 if (rdbit != applyPowerResponse)
j3 2:02d228c25fd4 689 {
j3 5:ce108eeb878d 690 OWLevel(LEVEL_NORMAL);
j3 2:02d228c25fd4 691 rtn_val = false;
j3 2:02d228c25fd4 692 }
j3 2:02d228c25fd4 693
j3 2:02d228c25fd4 694 rtn_val = true;
j3 2:02d228c25fd4 695 }
j3 2:02d228c25fd4 696
j3 1:91e52f8ab8bf 697 return(rtn_val);
j3 1:91e52f8ab8bf 698 }
j3 1:91e52f8ab8bf 699
j3 1:91e52f8ab8bf 700
j3 1:91e52f8ab8bf 701 //*********************************************************************
j3 6:1faafa0b3cd7 702 void Ds248x::set_i2c_adrs(DS248X_I2C_ADRS adrs)
j3 6:1faafa0b3cd7 703 {
j3 6:1faafa0b3cd7 704 _w_adrs = (adrs << 1);
j3 6:1faafa0b3cd7 705 _r_adrs = (_w_adrs | 1);
j3 6:1faafa0b3cd7 706 }