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Dependents:   STM32F031_blink_LED_2

targets/cmsis/core_cm0plus.h@0:38ccae254a29, 2014-10-18 (annotated)

Committer:
mega64
Date:
Sat Oct 18 02:40:17 2014 +0000
Revision:
0:38ccae254a29
only for STM32F030F4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 0:38ccae254a29 1 /**************************************************************************//**
mega64 0:38ccae254a29 2 * @file core_cm0plus.h
mega64 0:38ccae254a29 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
mega64 0:38ccae254a29 4 * @version V3.20
mega64 0:38ccae254a29 5 * @date 25. February 2013
mega64 0:38ccae254a29 6 *
mega64 0:38ccae254a29 7 * @note
mega64 0:38ccae254a29 8 *
mega64 0:38ccae254a29 9 ******************************************************************************/
mega64 0:38ccae254a29 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mega64 0:38ccae254a29 11
mega64 0:38ccae254a29 12 All rights reserved.
mega64 0:38ccae254a29 13 Redistribution and use in source and binary forms, with or without
mega64 0:38ccae254a29 14 modification, are permitted provided that the following conditions are met:
mega64 0:38ccae254a29 15 - Redistributions of source code must retain the above copyright
mega64 0:38ccae254a29 16 notice, this list of conditions and the following disclaimer.
mega64 0:38ccae254a29 17 - Redistributions in binary form must reproduce the above copyright
mega64 0:38ccae254a29 18 notice, this list of conditions and the following disclaimer in the
mega64 0:38ccae254a29 19 documentation and/or other materials provided with the distribution.
mega64 0:38ccae254a29 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 0:38ccae254a29 21 to endorse or promote products derived from this software without
mega64 0:38ccae254a29 22 specific prior written permission.
mega64 0:38ccae254a29 23 *
mega64 0:38ccae254a29 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 0:38ccae254a29 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 0:38ccae254a29 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 0:38ccae254a29 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 0:38ccae254a29 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 0:38ccae254a29 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 0:38ccae254a29 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 0:38ccae254a29 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 0:38ccae254a29 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 0:38ccae254a29 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 0:38ccae254a29 34 POSSIBILITY OF SUCH DAMAGE.
mega64 0:38ccae254a29 35 ---------------------------------------------------------------------------*/
mega64 0:38ccae254a29 36
mega64 0:38ccae254a29 37
mega64 0:38ccae254a29 38 #if defined ( __ICCARM__ )
mega64 0:38ccae254a29 39 #pragma system_include /* treat file as system include file for MISRA check */
mega64 0:38ccae254a29 40 #endif
mega64 0:38ccae254a29 41
mega64 0:38ccae254a29 42 #ifdef __cplusplus
mega64 0:38ccae254a29 43 extern "C" {
mega64 0:38ccae254a29 44 #endif
mega64 0:38ccae254a29 45
mega64 0:38ccae254a29 46 #ifndef __CORE_CM0PLUS_H_GENERIC
mega64 0:38ccae254a29 47 #define __CORE_CM0PLUS_H_GENERIC
mega64 0:38ccae254a29 48
mega64 0:38ccae254a29 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mega64 0:38ccae254a29 50 CMSIS violates the following MISRA-C:2004 rules:
mega64 0:38ccae254a29 51
mega64 0:38ccae254a29 52 \li Required Rule 8.5, object/function definition in header file.<br>
mega64 0:38ccae254a29 53 Function definitions in header files are used to allow 'inlining'.
mega64 0:38ccae254a29 54
mega64 0:38ccae254a29 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mega64 0:38ccae254a29 56 Unions are used for effective representation of core registers.
mega64 0:38ccae254a29 57
mega64 0:38ccae254a29 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mega64 0:38ccae254a29 59 Function-like macros are used to allow more efficient code.
mega64 0:38ccae254a29 60 */
mega64 0:38ccae254a29 61
mega64 0:38ccae254a29 62
mega64 0:38ccae254a29 63 /*******************************************************************************
mega64 0:38ccae254a29 64 * CMSIS definitions
mega64 0:38ccae254a29 65 ******************************************************************************/
mega64 0:38ccae254a29 66 /** \ingroup Cortex-M0+
mega64 0:38ccae254a29 67 @{
mega64 0:38ccae254a29 68 */
mega64 0:38ccae254a29 69
mega64 0:38ccae254a29 70 /* CMSIS CM0P definitions */
mega64 0:38ccae254a29 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mega64 0:38ccae254a29 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mega64 0:38ccae254a29 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
mega64 0:38ccae254a29 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
mega64 0:38ccae254a29 75
mega64 0:38ccae254a29 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mega64 0:38ccae254a29 77
mega64 0:38ccae254a29 78
mega64 0:38ccae254a29 79 #if defined ( __CC_ARM )
mega64 0:38ccae254a29 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mega64 0:38ccae254a29 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mega64 0:38ccae254a29 82 #define __STATIC_INLINE static __inline
mega64 0:38ccae254a29 83
mega64 0:38ccae254a29 84 #elif defined ( __ICCARM__ )
mega64 0:38ccae254a29 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mega64 0:38ccae254a29 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mega64 0:38ccae254a29 87 #define __STATIC_INLINE static inline
mega64 0:38ccae254a29 88
mega64 0:38ccae254a29 89 #elif defined ( __GNUC__ )
mega64 0:38ccae254a29 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mega64 0:38ccae254a29 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mega64 0:38ccae254a29 92 #define __STATIC_INLINE static inline
mega64 0:38ccae254a29 93
mega64 0:38ccae254a29 94 #elif defined ( __TASKING__ )
mega64 0:38ccae254a29 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mega64 0:38ccae254a29 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mega64 0:38ccae254a29 97 #define __STATIC_INLINE static inline
mega64 0:38ccae254a29 98
mega64 0:38ccae254a29 99 #endif
mega64 0:38ccae254a29 100
mega64 0:38ccae254a29 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
mega64 0:38ccae254a29 102 */
mega64 0:38ccae254a29 103 #define __FPU_USED 0
mega64 0:38ccae254a29 104
mega64 0:38ccae254a29 105 #if defined ( __CC_ARM )
mega64 0:38ccae254a29 106 #if defined __TARGET_FPU_VFP
mega64 0:38ccae254a29 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 0:38ccae254a29 108 #endif
mega64 0:38ccae254a29 109
mega64 0:38ccae254a29 110 #elif defined ( __ICCARM__ )
mega64 0:38ccae254a29 111 #if defined __ARMVFP__
mega64 0:38ccae254a29 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 0:38ccae254a29 113 #endif
mega64 0:38ccae254a29 114
mega64 0:38ccae254a29 115 #elif defined ( __GNUC__ )
mega64 0:38ccae254a29 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mega64 0:38ccae254a29 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 0:38ccae254a29 118 #endif
mega64 0:38ccae254a29 119
mega64 0:38ccae254a29 120 #elif defined ( __TASKING__ )
mega64 0:38ccae254a29 121 #if defined __FPU_VFP__
mega64 0:38ccae254a29 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 0:38ccae254a29 123 #endif
mega64 0:38ccae254a29 124 #endif
mega64 0:38ccae254a29 125
mega64 0:38ccae254a29 126 #include <stdint.h> /* standard types definitions */
mega64 0:38ccae254a29 127 #include <core_cmInstr.h> /* Core Instruction Access */
mega64 0:38ccae254a29 128 #include <core_cmFunc.h> /* Core Function Access */
mega64 0:38ccae254a29 129
mega64 0:38ccae254a29 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
mega64 0:38ccae254a29 131
mega64 0:38ccae254a29 132 #ifndef __CMSIS_GENERIC
mega64 0:38ccae254a29 133
mega64 0:38ccae254a29 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
mega64 0:38ccae254a29 135 #define __CORE_CM0PLUS_H_DEPENDANT
mega64 0:38ccae254a29 136
mega64 0:38ccae254a29 137 /* check device defines and use defaults */
mega64 0:38ccae254a29 138 #if defined __CHECK_DEVICE_DEFINES
mega64 0:38ccae254a29 139 #ifndef __CM0PLUS_REV
mega64 0:38ccae254a29 140 #define __CM0PLUS_REV 0x0000
mega64 0:38ccae254a29 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
mega64 0:38ccae254a29 142 #endif
mega64 0:38ccae254a29 143
mega64 0:38ccae254a29 144 #ifndef __MPU_PRESENT
mega64 0:38ccae254a29 145 #define __MPU_PRESENT 0
mega64 0:38ccae254a29 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
mega64 0:38ccae254a29 147 #endif
mega64 0:38ccae254a29 148
mega64 0:38ccae254a29 149 #ifndef __VTOR_PRESENT
mega64 0:38ccae254a29 150 #define __VTOR_PRESENT 0
mega64 0:38ccae254a29 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
mega64 0:38ccae254a29 152 #endif
mega64 0:38ccae254a29 153
mega64 0:38ccae254a29 154 #ifndef __NVIC_PRIO_BITS
mega64 0:38ccae254a29 155 #define __NVIC_PRIO_BITS 2
mega64 0:38ccae254a29 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mega64 0:38ccae254a29 157 #endif
mega64 0:38ccae254a29 158
mega64 0:38ccae254a29 159 #ifndef __Vendor_SysTickConfig
mega64 0:38ccae254a29 160 #define __Vendor_SysTickConfig 0
mega64 0:38ccae254a29 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mega64 0:38ccae254a29 162 #endif
mega64 0:38ccae254a29 163 #endif
mega64 0:38ccae254a29 164
mega64 0:38ccae254a29 165 /* IO definitions (access restrictions to peripheral registers) */
mega64 0:38ccae254a29 166 /**
mega64 0:38ccae254a29 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
mega64 0:38ccae254a29 168
mega64 0:38ccae254a29 169 <strong>IO Type Qualifiers</strong> are used
mega64 0:38ccae254a29 170 \li to specify the access to peripheral variables.
mega64 0:38ccae254a29 171 \li for automatic generation of peripheral register debug information.
mega64 0:38ccae254a29 172 */
mega64 0:38ccae254a29 173 #ifdef __cplusplus
mega64 0:38ccae254a29 174 #define __I volatile /*!< Defines 'read only' permissions */
mega64 0:38ccae254a29 175 #else
mega64 0:38ccae254a29 176 #define __I volatile const /*!< Defines 'read only' permissions */
mega64 0:38ccae254a29 177 #endif
mega64 0:38ccae254a29 178 #define __O volatile /*!< Defines 'write only' permissions */
mega64 0:38ccae254a29 179 #define __IO volatile /*!< Defines 'read / write' permissions */
mega64 0:38ccae254a29 180
mega64 0:38ccae254a29 181 /*@} end of group Cortex-M0+ */
mega64 0:38ccae254a29 182
mega64 0:38ccae254a29 183
mega64 0:38ccae254a29 184
mega64 0:38ccae254a29 185 /*******************************************************************************
mega64 0:38ccae254a29 186 * Register Abstraction
mega64 0:38ccae254a29 187 Core Register contain:
mega64 0:38ccae254a29 188 - Core Register
mega64 0:38ccae254a29 189 - Core NVIC Register
mega64 0:38ccae254a29 190 - Core SCB Register
mega64 0:38ccae254a29 191 - Core SysTick Register
mega64 0:38ccae254a29 192 - Core MPU Register
mega64 0:38ccae254a29 193 ******************************************************************************/
mega64 0:38ccae254a29 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
mega64 0:38ccae254a29 195 \brief Type definitions and defines for Cortex-M processor based devices.
mega64 0:38ccae254a29 196 */
mega64 0:38ccae254a29 197
mega64 0:38ccae254a29 198 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 199 \defgroup CMSIS_CORE Status and Control Registers
mega64 0:38ccae254a29 200 \brief Core Register type definitions.
mega64 0:38ccae254a29 201 @{
mega64 0:38ccae254a29 202 */
mega64 0:38ccae254a29 203
mega64 0:38ccae254a29 204 /** \brief Union type to access the Application Program Status Register (APSR).
mega64 0:38ccae254a29 205 */
mega64 0:38ccae254a29 206 typedef union
mega64 0:38ccae254a29 207 {
mega64 0:38ccae254a29 208 struct
mega64 0:38ccae254a29 209 {
mega64 0:38ccae254a29 210 #if (__CORTEX_M != 0x04)
mega64 0:38ccae254a29 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mega64 0:38ccae254a29 212 #else
mega64 0:38ccae254a29 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mega64 0:38ccae254a29 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mega64 0:38ccae254a29 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mega64 0:38ccae254a29 216 #endif
mega64 0:38ccae254a29 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mega64 0:38ccae254a29 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mega64 0:38ccae254a29 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mega64 0:38ccae254a29 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mega64 0:38ccae254a29 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mega64 0:38ccae254a29 222 } b; /*!< Structure used for bit access */
mega64 0:38ccae254a29 223 uint32_t w; /*!< Type used for word access */
mega64 0:38ccae254a29 224 } APSR_Type;
mega64 0:38ccae254a29 225
mega64 0:38ccae254a29 226
mega64 0:38ccae254a29 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mega64 0:38ccae254a29 228 */
mega64 0:38ccae254a29 229 typedef union
mega64 0:38ccae254a29 230 {
mega64 0:38ccae254a29 231 struct
mega64 0:38ccae254a29 232 {
mega64 0:38ccae254a29 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mega64 0:38ccae254a29 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mega64 0:38ccae254a29 235 } b; /*!< Structure used for bit access */
mega64 0:38ccae254a29 236 uint32_t w; /*!< Type used for word access */
mega64 0:38ccae254a29 237 } IPSR_Type;
mega64 0:38ccae254a29 238
mega64 0:38ccae254a29 239
mega64 0:38ccae254a29 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mega64 0:38ccae254a29 241 */
mega64 0:38ccae254a29 242 typedef union
mega64 0:38ccae254a29 243 {
mega64 0:38ccae254a29 244 struct
mega64 0:38ccae254a29 245 {
mega64 0:38ccae254a29 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mega64 0:38ccae254a29 247 #if (__CORTEX_M != 0x04)
mega64 0:38ccae254a29 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mega64 0:38ccae254a29 249 #else
mega64 0:38ccae254a29 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mega64 0:38ccae254a29 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mega64 0:38ccae254a29 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mega64 0:38ccae254a29 253 #endif
mega64 0:38ccae254a29 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mega64 0:38ccae254a29 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mega64 0:38ccae254a29 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mega64 0:38ccae254a29 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mega64 0:38ccae254a29 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mega64 0:38ccae254a29 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mega64 0:38ccae254a29 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mega64 0:38ccae254a29 261 } b; /*!< Structure used for bit access */
mega64 0:38ccae254a29 262 uint32_t w; /*!< Type used for word access */
mega64 0:38ccae254a29 263 } xPSR_Type;
mega64 0:38ccae254a29 264
mega64 0:38ccae254a29 265
mega64 0:38ccae254a29 266 /** \brief Union type to access the Control Registers (CONTROL).
mega64 0:38ccae254a29 267 */
mega64 0:38ccae254a29 268 typedef union
mega64 0:38ccae254a29 269 {
mega64 0:38ccae254a29 270 struct
mega64 0:38ccae254a29 271 {
mega64 0:38ccae254a29 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mega64 0:38ccae254a29 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mega64 0:38ccae254a29 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mega64 0:38ccae254a29 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mega64 0:38ccae254a29 276 } b; /*!< Structure used for bit access */
mega64 0:38ccae254a29 277 uint32_t w; /*!< Type used for word access */
mega64 0:38ccae254a29 278 } CONTROL_Type;
mega64 0:38ccae254a29 279
mega64 0:38ccae254a29 280 /*@} end of group CMSIS_CORE */
mega64 0:38ccae254a29 281
mega64 0:38ccae254a29 282
mega64 0:38ccae254a29 283 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mega64 0:38ccae254a29 285 \brief Type definitions for the NVIC Registers
mega64 0:38ccae254a29 286 @{
mega64 0:38ccae254a29 287 */
mega64 0:38ccae254a29 288
mega64 0:38ccae254a29 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mega64 0:38ccae254a29 290 */
mega64 0:38ccae254a29 291 typedef struct
mega64 0:38ccae254a29 292 {
mega64 0:38ccae254a29 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mega64 0:38ccae254a29 294 uint32_t RESERVED0[31];
mega64 0:38ccae254a29 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mega64 0:38ccae254a29 296 uint32_t RSERVED1[31];
mega64 0:38ccae254a29 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mega64 0:38ccae254a29 298 uint32_t RESERVED2[31];
mega64 0:38ccae254a29 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mega64 0:38ccae254a29 300 uint32_t RESERVED3[31];
mega64 0:38ccae254a29 301 uint32_t RESERVED4[64];
mega64 0:38ccae254a29 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mega64 0:38ccae254a29 303 } NVIC_Type;
mega64 0:38ccae254a29 304
mega64 0:38ccae254a29 305 /*@} end of group CMSIS_NVIC */
mega64 0:38ccae254a29 306
mega64 0:38ccae254a29 307
mega64 0:38ccae254a29 308 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 309 \defgroup CMSIS_SCB System Control Block (SCB)
mega64 0:38ccae254a29 310 \brief Type definitions for the System Control Block Registers
mega64 0:38ccae254a29 311 @{
mega64 0:38ccae254a29 312 */
mega64 0:38ccae254a29 313
mega64 0:38ccae254a29 314 /** \brief Structure type to access the System Control Block (SCB).
mega64 0:38ccae254a29 315 */
mega64 0:38ccae254a29 316 typedef struct
mega64 0:38ccae254a29 317 {
mega64 0:38ccae254a29 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mega64 0:38ccae254a29 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mega64 0:38ccae254a29 320 #if (__VTOR_PRESENT == 1)
mega64 0:38ccae254a29 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mega64 0:38ccae254a29 322 #else
mega64 0:38ccae254a29 323 uint32_t RESERVED0;
mega64 0:38ccae254a29 324 #endif
mega64 0:38ccae254a29 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mega64 0:38ccae254a29 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mega64 0:38ccae254a29 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mega64 0:38ccae254a29 328 uint32_t RESERVED1;
mega64 0:38ccae254a29 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mega64 0:38ccae254a29 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mega64 0:38ccae254a29 331 } SCB_Type;
mega64 0:38ccae254a29 332
mega64 0:38ccae254a29 333 /* SCB CPUID Register Definitions */
mega64 0:38ccae254a29 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mega64 0:38ccae254a29 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mega64 0:38ccae254a29 336
mega64 0:38ccae254a29 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mega64 0:38ccae254a29 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mega64 0:38ccae254a29 339
mega64 0:38ccae254a29 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mega64 0:38ccae254a29 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mega64 0:38ccae254a29 342
mega64 0:38ccae254a29 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mega64 0:38ccae254a29 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mega64 0:38ccae254a29 345
mega64 0:38ccae254a29 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mega64 0:38ccae254a29 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mega64 0:38ccae254a29 348
mega64 0:38ccae254a29 349 /* SCB Interrupt Control State Register Definitions */
mega64 0:38ccae254a29 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mega64 0:38ccae254a29 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mega64 0:38ccae254a29 352
mega64 0:38ccae254a29 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mega64 0:38ccae254a29 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mega64 0:38ccae254a29 355
mega64 0:38ccae254a29 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mega64 0:38ccae254a29 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mega64 0:38ccae254a29 358
mega64 0:38ccae254a29 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mega64 0:38ccae254a29 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mega64 0:38ccae254a29 361
mega64 0:38ccae254a29 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mega64 0:38ccae254a29 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mega64 0:38ccae254a29 364
mega64 0:38ccae254a29 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mega64 0:38ccae254a29 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mega64 0:38ccae254a29 367
mega64 0:38ccae254a29 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mega64 0:38ccae254a29 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mega64 0:38ccae254a29 370
mega64 0:38ccae254a29 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mega64 0:38ccae254a29 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mega64 0:38ccae254a29 373
mega64 0:38ccae254a29 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mega64 0:38ccae254a29 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mega64 0:38ccae254a29 376
mega64 0:38ccae254a29 377 #if (__VTOR_PRESENT == 1)
mega64 0:38ccae254a29 378 /* SCB Interrupt Control State Register Definitions */
mega64 0:38ccae254a29 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
mega64 0:38ccae254a29 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mega64 0:38ccae254a29 381 #endif
mega64 0:38ccae254a29 382
mega64 0:38ccae254a29 383 /* SCB Application Interrupt and Reset Control Register Definitions */
mega64 0:38ccae254a29 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mega64 0:38ccae254a29 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mega64 0:38ccae254a29 386
mega64 0:38ccae254a29 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mega64 0:38ccae254a29 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mega64 0:38ccae254a29 389
mega64 0:38ccae254a29 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mega64 0:38ccae254a29 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mega64 0:38ccae254a29 392
mega64 0:38ccae254a29 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mega64 0:38ccae254a29 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mega64 0:38ccae254a29 395
mega64 0:38ccae254a29 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mega64 0:38ccae254a29 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mega64 0:38ccae254a29 398
mega64 0:38ccae254a29 399 /* SCB System Control Register Definitions */
mega64 0:38ccae254a29 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mega64 0:38ccae254a29 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mega64 0:38ccae254a29 402
mega64 0:38ccae254a29 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mega64 0:38ccae254a29 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mega64 0:38ccae254a29 405
mega64 0:38ccae254a29 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mega64 0:38ccae254a29 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mega64 0:38ccae254a29 408
mega64 0:38ccae254a29 409 /* SCB Configuration Control Register Definitions */
mega64 0:38ccae254a29 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mega64 0:38ccae254a29 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mega64 0:38ccae254a29 412
mega64 0:38ccae254a29 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mega64 0:38ccae254a29 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mega64 0:38ccae254a29 415
mega64 0:38ccae254a29 416 /* SCB System Handler Control and State Register Definitions */
mega64 0:38ccae254a29 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mega64 0:38ccae254a29 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mega64 0:38ccae254a29 419
mega64 0:38ccae254a29 420 /*@} end of group CMSIS_SCB */
mega64 0:38ccae254a29 421
mega64 0:38ccae254a29 422
mega64 0:38ccae254a29 423 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mega64 0:38ccae254a29 425 \brief Type definitions for the System Timer Registers.
mega64 0:38ccae254a29 426 @{
mega64 0:38ccae254a29 427 */
mega64 0:38ccae254a29 428
mega64 0:38ccae254a29 429 /** \brief Structure type to access the System Timer (SysTick).
mega64 0:38ccae254a29 430 */
mega64 0:38ccae254a29 431 typedef struct
mega64 0:38ccae254a29 432 {
mega64 0:38ccae254a29 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mega64 0:38ccae254a29 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mega64 0:38ccae254a29 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mega64 0:38ccae254a29 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mega64 0:38ccae254a29 437 } SysTick_Type;
mega64 0:38ccae254a29 438
mega64 0:38ccae254a29 439 /* SysTick Control / Status Register Definitions */
mega64 0:38ccae254a29 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mega64 0:38ccae254a29 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mega64 0:38ccae254a29 442
mega64 0:38ccae254a29 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mega64 0:38ccae254a29 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mega64 0:38ccae254a29 445
mega64 0:38ccae254a29 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mega64 0:38ccae254a29 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mega64 0:38ccae254a29 448
mega64 0:38ccae254a29 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mega64 0:38ccae254a29 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mega64 0:38ccae254a29 451
mega64 0:38ccae254a29 452 /* SysTick Reload Register Definitions */
mega64 0:38ccae254a29 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mega64 0:38ccae254a29 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mega64 0:38ccae254a29 455
mega64 0:38ccae254a29 456 /* SysTick Current Register Definitions */
mega64 0:38ccae254a29 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mega64 0:38ccae254a29 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mega64 0:38ccae254a29 459
mega64 0:38ccae254a29 460 /* SysTick Calibration Register Definitions */
mega64 0:38ccae254a29 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mega64 0:38ccae254a29 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mega64 0:38ccae254a29 463
mega64 0:38ccae254a29 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mega64 0:38ccae254a29 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mega64 0:38ccae254a29 466
mega64 0:38ccae254a29 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mega64 0:38ccae254a29 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mega64 0:38ccae254a29 469
mega64 0:38ccae254a29 470 /*@} end of group CMSIS_SysTick */
mega64 0:38ccae254a29 471
mega64 0:38ccae254a29 472 #if (__MPU_PRESENT == 1)
mega64 0:38ccae254a29 473 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mega64 0:38ccae254a29 475 \brief Type definitions for the Memory Protection Unit (MPU)
mega64 0:38ccae254a29 476 @{
mega64 0:38ccae254a29 477 */
mega64 0:38ccae254a29 478
mega64 0:38ccae254a29 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
mega64 0:38ccae254a29 480 */
mega64 0:38ccae254a29 481 typedef struct
mega64 0:38ccae254a29 482 {
mega64 0:38ccae254a29 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mega64 0:38ccae254a29 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mega64 0:38ccae254a29 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mega64 0:38ccae254a29 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mega64 0:38ccae254a29 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mega64 0:38ccae254a29 488 } MPU_Type;
mega64 0:38ccae254a29 489
mega64 0:38ccae254a29 490 /* MPU Type Register */
mega64 0:38ccae254a29 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mega64 0:38ccae254a29 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mega64 0:38ccae254a29 493
mega64 0:38ccae254a29 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mega64 0:38ccae254a29 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mega64 0:38ccae254a29 496
mega64 0:38ccae254a29 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mega64 0:38ccae254a29 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
mega64 0:38ccae254a29 499
mega64 0:38ccae254a29 500 /* MPU Control Register */
mega64 0:38ccae254a29 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mega64 0:38ccae254a29 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mega64 0:38ccae254a29 503
mega64 0:38ccae254a29 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mega64 0:38ccae254a29 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mega64 0:38ccae254a29 506
mega64 0:38ccae254a29 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mega64 0:38ccae254a29 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
mega64 0:38ccae254a29 509
mega64 0:38ccae254a29 510 /* MPU Region Number Register */
mega64 0:38ccae254a29 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mega64 0:38ccae254a29 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
mega64 0:38ccae254a29 513
mega64 0:38ccae254a29 514 /* MPU Region Base Address Register */
mega64 0:38ccae254a29 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
mega64 0:38ccae254a29 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mega64 0:38ccae254a29 517
mega64 0:38ccae254a29 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mega64 0:38ccae254a29 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mega64 0:38ccae254a29 520
mega64 0:38ccae254a29 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mega64 0:38ccae254a29 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
mega64 0:38ccae254a29 523
mega64 0:38ccae254a29 524 /* MPU Region Attribute and Size Register */
mega64 0:38ccae254a29 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mega64 0:38ccae254a29 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mega64 0:38ccae254a29 527
mega64 0:38ccae254a29 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mega64 0:38ccae254a29 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mega64 0:38ccae254a29 530
mega64 0:38ccae254a29 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mega64 0:38ccae254a29 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mega64 0:38ccae254a29 533
mega64 0:38ccae254a29 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mega64 0:38ccae254a29 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mega64 0:38ccae254a29 536
mega64 0:38ccae254a29 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mega64 0:38ccae254a29 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mega64 0:38ccae254a29 539
mega64 0:38ccae254a29 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mega64 0:38ccae254a29 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mega64 0:38ccae254a29 542
mega64 0:38ccae254a29 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mega64 0:38ccae254a29 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mega64 0:38ccae254a29 545
mega64 0:38ccae254a29 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mega64 0:38ccae254a29 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mega64 0:38ccae254a29 548
mega64 0:38ccae254a29 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mega64 0:38ccae254a29 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mega64 0:38ccae254a29 551
mega64 0:38ccae254a29 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mega64 0:38ccae254a29 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
mega64 0:38ccae254a29 554
mega64 0:38ccae254a29 555 /*@} end of group CMSIS_MPU */
mega64 0:38ccae254a29 556 #endif
mega64 0:38ccae254a29 557
mega64 0:38ccae254a29 558
mega64 0:38ccae254a29 559 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mega64 0:38ccae254a29 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
mega64 0:38ccae254a29 562 are only accessible over DAP and not via processor. Therefore
mega64 0:38ccae254a29 563 they are not covered by the Cortex-M0 header file.
mega64 0:38ccae254a29 564 @{
mega64 0:38ccae254a29 565 */
mega64 0:38ccae254a29 566 /*@} end of group CMSIS_CoreDebug */
mega64 0:38ccae254a29 567
mega64 0:38ccae254a29 568
mega64 0:38ccae254a29 569 /** \ingroup CMSIS_core_register
mega64 0:38ccae254a29 570 \defgroup CMSIS_core_base Core Definitions
mega64 0:38ccae254a29 571 \brief Definitions for base addresses, unions, and structures.
mega64 0:38ccae254a29 572 @{
mega64 0:38ccae254a29 573 */
mega64 0:38ccae254a29 574
mega64 0:38ccae254a29 575 /* Memory mapping of Cortex-M0+ Hardware */
mega64 0:38ccae254a29 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mega64 0:38ccae254a29 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mega64 0:38ccae254a29 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mega64 0:38ccae254a29 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mega64 0:38ccae254a29 580
mega64 0:38ccae254a29 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mega64 0:38ccae254a29 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mega64 0:38ccae254a29 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mega64 0:38ccae254a29 584
mega64 0:38ccae254a29 585 #if (__MPU_PRESENT == 1)
mega64 0:38ccae254a29 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mega64 0:38ccae254a29 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mega64 0:38ccae254a29 588 #endif
mega64 0:38ccae254a29 589
mega64 0:38ccae254a29 590 /*@} */
mega64 0:38ccae254a29 591
mega64 0:38ccae254a29 592
mega64 0:38ccae254a29 593
mega64 0:38ccae254a29 594 /*******************************************************************************
mega64 0:38ccae254a29 595 * Hardware Abstraction Layer
mega64 0:38ccae254a29 596 Core Function Interface contains:
mega64 0:38ccae254a29 597 - Core NVIC Functions
mega64 0:38ccae254a29 598 - Core SysTick Functions
mega64 0:38ccae254a29 599 - Core Register Access Functions
mega64 0:38ccae254a29 600 ******************************************************************************/
mega64 0:38ccae254a29 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mega64 0:38ccae254a29 602 */
mega64 0:38ccae254a29 603
mega64 0:38ccae254a29 604
mega64 0:38ccae254a29 605
mega64 0:38ccae254a29 606 /* ########################## NVIC functions #################################### */
mega64 0:38ccae254a29 607 /** \ingroup CMSIS_Core_FunctionInterface
mega64 0:38ccae254a29 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mega64 0:38ccae254a29 609 \brief Functions that manage interrupts and exceptions via the NVIC.
mega64 0:38ccae254a29 610 @{
mega64 0:38ccae254a29 611 */
mega64 0:38ccae254a29 612
mega64 0:38ccae254a29 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mega64 0:38ccae254a29 614 /* The following MACROS handle generation of the register offset and byte masks */
mega64 0:38ccae254a29 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
mega64 0:38ccae254a29 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
mega64 0:38ccae254a29 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
mega64 0:38ccae254a29 618
mega64 0:38ccae254a29 619
mega64 0:38ccae254a29 620 /** \brief Enable External Interrupt
mega64 0:38ccae254a29 621
mega64 0:38ccae254a29 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
mega64 0:38ccae254a29 623
mega64 0:38ccae254a29 624 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 0:38ccae254a29 625 */
mega64 0:38ccae254a29 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mega64 0:38ccae254a29 627 {
mega64 0:38ccae254a29 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mega64 0:38ccae254a29 629 }
mega64 0:38ccae254a29 630
mega64 0:38ccae254a29 631
mega64 0:38ccae254a29 632 /** \brief Disable External Interrupt
mega64 0:38ccae254a29 633
mega64 0:38ccae254a29 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
mega64 0:38ccae254a29 635
mega64 0:38ccae254a29 636 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 0:38ccae254a29 637 */
mega64 0:38ccae254a29 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mega64 0:38ccae254a29 639 {
mega64 0:38ccae254a29 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mega64 0:38ccae254a29 641 }
mega64 0:38ccae254a29 642
mega64 0:38ccae254a29 643
mega64 0:38ccae254a29 644 /** \brief Get Pending Interrupt
mega64 0:38ccae254a29 645
mega64 0:38ccae254a29 646 The function reads the pending register in the NVIC and returns the pending bit
mega64 0:38ccae254a29 647 for the specified interrupt.
mega64 0:38ccae254a29 648
mega64 0:38ccae254a29 649 \param [in] IRQn Interrupt number.
mega64 0:38ccae254a29 650
mega64 0:38ccae254a29 651 \return 0 Interrupt status is not pending.
mega64 0:38ccae254a29 652 \return 1 Interrupt status is pending.
mega64 0:38ccae254a29 653 */
mega64 0:38ccae254a29 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mega64 0:38ccae254a29 655 {
mega64 0:38ccae254a29 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
mega64 0:38ccae254a29 657 }
mega64 0:38ccae254a29 658
mega64 0:38ccae254a29 659
mega64 0:38ccae254a29 660 /** \brief Set Pending Interrupt
mega64 0:38ccae254a29 661
mega64 0:38ccae254a29 662 The function sets the pending bit of an external interrupt.
mega64 0:38ccae254a29 663
mega64 0:38ccae254a29 664 \param [in] IRQn Interrupt number. Value cannot be negative.
mega64 0:38ccae254a29 665 */
mega64 0:38ccae254a29 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mega64 0:38ccae254a29 667 {
mega64 0:38ccae254a29 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mega64 0:38ccae254a29 669 }
mega64 0:38ccae254a29 670
mega64 0:38ccae254a29 671
mega64 0:38ccae254a29 672 /** \brief Clear Pending Interrupt
mega64 0:38ccae254a29 673
mega64 0:38ccae254a29 674 The function clears the pending bit of an external interrupt.
mega64 0:38ccae254a29 675
mega64 0:38ccae254a29 676 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 0:38ccae254a29 677 */
mega64 0:38ccae254a29 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mega64 0:38ccae254a29 679 {
mega64 0:38ccae254a29 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mega64 0:38ccae254a29 681 }
mega64 0:38ccae254a29 682
mega64 0:38ccae254a29 683
mega64 0:38ccae254a29 684 /** \brief Set Interrupt Priority
mega64 0:38ccae254a29 685
mega64 0:38ccae254a29 686 The function sets the priority of an interrupt.
mega64 0:38ccae254a29 687
mega64 0:38ccae254a29 688 \note The priority cannot be set for every core interrupt.
mega64 0:38ccae254a29 689
mega64 0:38ccae254a29 690 \param [in] IRQn Interrupt number.
mega64 0:38ccae254a29 691 \param [in] priority Priority to set.
mega64 0:38ccae254a29 692 */
mega64 0:38ccae254a29 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mega64 0:38ccae254a29 694 {
mega64 0:38ccae254a29 695 if(IRQn < 0) {
mega64 0:38ccae254a29 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mega64 0:38ccae254a29 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mega64 0:38ccae254a29 698 else {
mega64 0:38ccae254a29 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mega64 0:38ccae254a29 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mega64 0:38ccae254a29 701 }
mega64 0:38ccae254a29 702
mega64 0:38ccae254a29 703
mega64 0:38ccae254a29 704 /** \brief Get Interrupt Priority
mega64 0:38ccae254a29 705
mega64 0:38ccae254a29 706 The function reads the priority of an interrupt. The interrupt
mega64 0:38ccae254a29 707 number can be positive to specify an external (device specific)
mega64 0:38ccae254a29 708 interrupt, or negative to specify an internal (core) interrupt.
mega64 0:38ccae254a29 709
mega64 0:38ccae254a29 710
mega64 0:38ccae254a29 711 \param [in] IRQn Interrupt number.
mega64 0:38ccae254a29 712 \return Interrupt Priority. Value is aligned automatically to the implemented
mega64 0:38ccae254a29 713 priority bits of the microcontroller.
mega64 0:38ccae254a29 714 */
mega64 0:38ccae254a29 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mega64 0:38ccae254a29 716 {
mega64 0:38ccae254a29 717
mega64 0:38ccae254a29 718 if(IRQn < 0) {
mega64 0:38ccae254a29 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
mega64 0:38ccae254a29 720 else {
mega64 0:38ccae254a29 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mega64 0:38ccae254a29 722 }
mega64 0:38ccae254a29 723
mega64 0:38ccae254a29 724
mega64 0:38ccae254a29 725 /** \brief System Reset
mega64 0:38ccae254a29 726
mega64 0:38ccae254a29 727 The function initiates a system reset request to reset the MCU.
mega64 0:38ccae254a29 728 */
mega64 0:38ccae254a29 729 __STATIC_INLINE void NVIC_SystemReset(void)
mega64 0:38ccae254a29 730 {
mega64 0:38ccae254a29 731 __DSB(); /* Ensure all outstanding memory accesses included
mega64 0:38ccae254a29 732 buffered write are completed before reset */
mega64 0:38ccae254a29 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mega64 0:38ccae254a29 734 SCB_AIRCR_SYSRESETREQ_Msk);
mega64 0:38ccae254a29 735 __DSB(); /* Ensure completion of memory access */
mega64 0:38ccae254a29 736 while(1); /* wait until reset */
mega64 0:38ccae254a29 737 }
mega64 0:38ccae254a29 738
mega64 0:38ccae254a29 739 /*@} end of CMSIS_Core_NVICFunctions */
mega64 0:38ccae254a29 740
mega64 0:38ccae254a29 741
mega64 0:38ccae254a29 742
mega64 0:38ccae254a29 743 /* ################################## SysTick function ############################################ */
mega64 0:38ccae254a29 744 /** \ingroup CMSIS_Core_FunctionInterface
mega64 0:38ccae254a29 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mega64 0:38ccae254a29 746 \brief Functions that configure the System.
mega64 0:38ccae254a29 747 @{
mega64 0:38ccae254a29 748 */
mega64 0:38ccae254a29 749
mega64 0:38ccae254a29 750 #if (__Vendor_SysTickConfig == 0)
mega64 0:38ccae254a29 751
mega64 0:38ccae254a29 752 /** \brief System Tick Configuration
mega64 0:38ccae254a29 753
mega64 0:38ccae254a29 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mega64 0:38ccae254a29 755 Counter is in free running mode to generate periodic interrupts.
mega64 0:38ccae254a29 756
mega64 0:38ccae254a29 757 \param [in] ticks Number of ticks between two interrupts.
mega64 0:38ccae254a29 758
mega64 0:38ccae254a29 759 \return 0 Function succeeded.
mega64 0:38ccae254a29 760 \return 1 Function failed.
mega64 0:38ccae254a29 761
mega64 0:38ccae254a29 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mega64 0:38ccae254a29 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mega64 0:38ccae254a29 764 must contain a vendor-specific implementation of this function.
mega64 0:38ccae254a29 765
mega64 0:38ccae254a29 766 */
mega64 0:38ccae254a29 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mega64 0:38ccae254a29 768 {
mega64 0:38ccae254a29 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mega64 0:38ccae254a29 770
mega64 0:38ccae254a29 771 SysTick->LOAD = ticks - 1; /* set reload register */
mega64 0:38ccae254a29 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mega64 0:38ccae254a29 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mega64 0:38ccae254a29 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mega64 0:38ccae254a29 775 SysTick_CTRL_TICKINT_Msk |
mega64 0:38ccae254a29 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mega64 0:38ccae254a29 777 return (0); /* Function successful */
mega64 0:38ccae254a29 778 }
mega64 0:38ccae254a29 779
mega64 0:38ccae254a29 780 #endif
mega64 0:38ccae254a29 781
mega64 0:38ccae254a29 782 /*@} end of CMSIS_Core_SysTickFunctions */
mega64 0:38ccae254a29 783
mega64 0:38ccae254a29 784
mega64 0:38ccae254a29 785
mega64 0:38ccae254a29 786
mega64 0:38ccae254a29 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
mega64 0:38ccae254a29 788
mega64 0:38ccae254a29 789 #endif /* __CMSIS_GENERIC */
mega64 0:38ccae254a29 790
mega64 0:38ccae254a29 791 #ifdef __cplusplus
mega64 0:38ccae254a29 792 }
mega64 0:38ccae254a29 793 #endif