MC3635 - 3-Axis Accelerometer

Users » mcm » Code » MC3635

3-Axis Accelerometer

MC3635.h@3:d8cf2591cab6, 2018-05-30 (annotated)

Committer:: mcm
Date:: Wed May 30 15:09:33 2018 +0000
Revision:: 3:d8cf2591cab6
Parent:: 2:292a5265228e

MC3635 driver was completed and tested, it works as expected ( it was tested using a NUCLEO-L152RE )

Who changed what in which revision?

User	Revision	Line number	New contents of line
mcm	1:d4b35641a624	1	/**
mcm	1:d4b35641a624	2	* @brief MC3635.h
mcm	1:d4b35641a624	3	* @details 3-Axis Accelerometer.
mcm	1:d4b35641a624	4	* Header file.
mcm	1:d4b35641a624	5	*
mcm	1:d4b35641a624	6	*
mcm	1:d4b35641a624	7	* @return N/A
mcm	1:d4b35641a624	8	*
mcm	1:d4b35641a624	9	* @author Manuel Caballero
mcm	1:d4b35641a624	10	* @date 30/May/2018
mcm	1:d4b35641a624	11	* @version 30/May/2018 The ORIGIN
mcm	1:d4b35641a624	12	* @pre N/A.
mcm	1:d4b35641a624	13	* @warning N/A
mcm	1:d4b35641a624	14	* @pre This code belongs to Nimbus Centre ( http://www.nimbus.cit.ie ).
mcm	1:d4b35641a624	15	*/
mcm	1:d4b35641a624	16	#ifndef MC3635_H
mcm	1:d4b35641a624	17	#define MC3635_H
mcm	1:d4b35641a624	18
mcm	1:d4b35641a624	19	#include "mbed.h"
mcm	1:d4b35641a624	20	/**
mcm	1:d4b35641a624	21	Example:
mcm	1:d4b35641a624	22
mcm	1:d4b35641a624	23	@code
mcm	3:d8cf2591cab6	24	#include "mbed.h"
mcm	3:d8cf2591cab6	25	#include "MC3635.h"
mcm	3:d8cf2591cab6	26
mcm	3:d8cf2591cab6	27	MC3635 myMC3635 ( I2C_SDA, I2C_SCL, MC3635::MC3635_ADDRESS_LOW, 100000 );
mcm	3:d8cf2591cab6	28	Serial pc ( USBTX, USBRX );
mcm	3:d8cf2591cab6	29
mcm	3:d8cf2591cab6	30	DigitalOut myled ( LED1 );
mcm	3:d8cf2591cab6	31	Ticker newReading;
mcm	3:d8cf2591cab6	32
mcm	3:d8cf2591cab6	33	MC3635::MC3635_status_t aux;
mcm	3:d8cf2591cab6	34	MC3635::MC3635_data_t myMC3635_data;
mcm	3:d8cf2591cab6	35	uint32_t myState = 0;
mcm	3:d8cf2591cab6	36
mcm	3:d8cf2591cab6	37
mcm	3:d8cf2591cab6	38	void changeDATA ( void )
mcm	3:d8cf2591cab6	39	{
mcm	3:d8cf2591cab6	40	myState = 1;
mcm	3:d8cf2591cab6	41	}
mcm	3:d8cf2591cab6	42
mcm	3:d8cf2591cab6	43
mcm	3:d8cf2591cab6	44	int main()
mcm	3:d8cf2591cab6	45	{
mcm	3:d8cf2591cab6	46	pc.baud ( 115200 );
mcm	3:d8cf2591cab6	47
mcm	3:d8cf2591cab6	48	myled = 1;
mcm	3:d8cf2591cab6	49	wait(3);
mcm	3:d8cf2591cab6	50	myled = 0;
mcm	3:d8cf2591cab6	51
mcm	3:d8cf2591cab6	52
mcm	3:d8cf2591cab6	53	// MC3635 CONFIGURATION
mcm	3:d8cf2591cab6	54	// MC3635 Software Reset
mcm	3:d8cf2591cab6	55	aux = myMC3635.MC3635_SetSoftwareReset ();
mcm	3:d8cf2591cab6	56
mcm	3:d8cf2591cab6	57	// MC3635 in Standby mode
mcm	3:d8cf2591cab6	58	aux = myMC3635.MC3635_SetStandbyMode ();
mcm	3:d8cf2591cab6	59
mcm	3:d8cf2591cab6	60	// MC3635 initialization sequence
mcm	3:d8cf2591cab6	61	aux = myMC3635.MC3635_InitializationSequence ();
mcm	3:d8cf2591cab6	62
mcm	3:d8cf2591cab6	63	// MC3635 Get the offset for all the axis
mcm	3:d8cf2591cab6	64	aux = myMC3635.MC3635_GetOffset ( MC3635::X_AXIS, &myMC3635_data );
mcm	3:d8cf2591cab6	65	aux = myMC3635.MC3635_GetOffset ( MC3635::Y_AXIS, &myMC3635_data );
mcm	3:d8cf2591cab6	66	aux = myMC3635.MC3635_GetOffset ( MC3635::Z_AXIS, &myMC3635_data );
mcm	3:d8cf2591cab6	67	pc.printf( "XOFFSET: %d \| YOFFSET: %d \| ZOFFSET: %d\r\n", myMC3635_data.XOffset, myMC3635_data.YOffset, myMC3635_data.ZOffset );
mcm	3:d8cf2591cab6	68
mcm	3:d8cf2591cab6	69	// MC3635 Get the gain for all the axis
mcm	3:d8cf2591cab6	70	aux = myMC3635.MC3635_GetGain ( MC3635::X_AXIS, &myMC3635_data );
mcm	3:d8cf2591cab6	71	aux = myMC3635.MC3635_GetGain ( MC3635::Y_AXIS, &myMC3635_data );
mcm	3:d8cf2591cab6	72	aux = myMC3635.MC3635_GetGain ( MC3635::Z_AXIS, &myMC3635_data );
mcm	3:d8cf2591cab6	73	pc.printf( "XGAIN: %d \| YGAIN: %d \| ZGAIN: %d\r\n", myMC3635_data.XGAIN, myMC3635_data.YGAIN, myMC3635_data.ZGAIN );
mcm	3:d8cf2591cab6	74
mcm	3:d8cf2591cab6	75	// MC3635 Check Scratch register
mcm	3:d8cf2591cab6	76	myMC3635_data.scratch = 0x23;
mcm	3:d8cf2591cab6	77	aux = myMC3635.MC3635_WriteScratchpadRegister ( myMC3635_data );
mcm	3:d8cf2591cab6	78
mcm	3:d8cf2591cab6	79	myMC3635_data.scratch = 0;
mcm	3:d8cf2591cab6	80	aux = myMC3635.MC3635_ReadScratchpadRegister ( &myMC3635_data );
mcm	3:d8cf2591cab6	81	pc.printf( "Scratchpad Register: %x ( 0x23 )\r\n", myMC3635_data.scratch );
mcm	3:d8cf2591cab6	82
mcm	3:d8cf2591cab6	83	// MC3635 FIFO disabled
mcm	3:d8cf2591cab6	84	aux = myMC3635.MC3635_EnableFIFO ( MC3635::FIFO_C_FIFO_EN_DISABLED );
mcm	3:d8cf2591cab6	85
mcm	3:d8cf2591cab6	86	// MC3635 All interrupts DISABLED
mcm	3:d8cf2591cab6	87	aux = myMC3635.MC3635_Set_INTN ( MC3635::INTR_C_INT_WAKE_DISABLED, MC3635::INTR_C_INT_ACQ_DISABLED, MC3635::INTR_C_INT_FIFO_EMPTY_DISABLED,
mcm	3:d8cf2591cab6	88	MC3635::INTR_C_INT_FIFO_FULL_DISABLED, MC3635::INTR_C_INT_FIFO_THRESH_DISABLED, MC3635::INTR_C_INT_SWAKE_DISABLED );
mcm	3:d8cf2591cab6	89
mcm	3:d8cf2591cab6	90	// MC3635 14-bits resolution ( FIFO not in use)
mcm	3:d8cf2591cab6	91	aux = myMC3635.MC3635_SetResolution ( MC3635::RANGE_C_RES_14_BITS );
mcm	3:d8cf2591cab6	92
mcm	3:d8cf2591cab6	93	// MC3635 16g range
mcm	3:d8cf2591cab6	94	aux = myMC3635.MC3635_SetRange ( MC3635::RANGE_C_RANGE_16G );
mcm	3:d8cf2591cab6	95
mcm	3:d8cf2591cab6	96	// MC3635 X/Y/Z axis enabled
mcm	3:d8cf2591cab6	97	aux = myMC3635.MC3635_EnableAxis ( MC3635::MODE_C_X_AXIS_PD_ENABLED, MC3635::MODE_C_Y_AXIS_PD_ENABLED, MC3635::MODE_C_Z_AXIS_PD_ENABLED );
mcm	3:d8cf2591cab6	98
mcm	3:d8cf2591cab6	99	// MC3635 CWAKE mode in Low Power enabled and ODR is 54Hz
mcm	3:d8cf2591cab6	100	aux = myMC3635.MC3635_SetMode ( MC3635::MODE_C_MCTRL_CWAKE, MC3635::LOW_POWER_MODE, MC3635::ODR_7 );
mcm	3:d8cf2591cab6	101	// END MC3635 CONFIGURATION
mcm	3:d8cf2591cab6	102
mcm	3:d8cf2591cab6	103
mcm	3:d8cf2591cab6	104	newReading.attach( &changeDATA, 1 ); // the address of the function to be attached ( changeDATA ) and the interval ( 1s )
mcm	3:d8cf2591cab6	105
mcm	3:d8cf2591cab6	106	// Let the callbacks take care of everything
mcm	3:d8cf2591cab6	107	while(1) {
mcm	3:d8cf2591cab6	108	sleep();
mcm	3:d8cf2591cab6	109
mcm	3:d8cf2591cab6	110	myled = 1;
mcm	3:d8cf2591cab6	111
mcm	3:d8cf2591cab6	112	if ( myState == 1 ) {
mcm	3:d8cf2591cab6	113	// Wait until a new data is available
mcm	3:d8cf2591cab6	114	do{
mcm	3:d8cf2591cab6	115	// MC3635 Read register Status1
mcm	3:d8cf2591cab6	116	aux = myMC3635.MC3635_ReadStatusRegister1 ( &myMC3635_data );
mcm	3:d8cf2591cab6	117	}while( ( myMC3635_data.status_1 & MC3635::STATUS_1_NEW_DATA_MASK ) == MC3635::STATUS_1_NEW_DATA_FALSE ); // [TODO] Dangerous!!! The uC may get stuck here if something goes wrong!
mcm	3:d8cf2591cab6	118	// [WORKAROUND] Insert a counter.
mcm	3:d8cf2591cab6	119
mcm	3:d8cf2591cab6	120	// MC3635 Read the data
mcm	3:d8cf2591cab6	121	aux = myMC3635.MC3635_ReadRawData ( &myMC3635_data );
mcm	3:d8cf2591cab6	122
mcm	3:d8cf2591cab6	123
mcm	3:d8cf2591cab6	124	// Send data through the UART
mcm	3:d8cf2591cab6	125	pc.printf( "X: %d \| Y: %d \| Z: %d\r\n", myMC3635_data.XAxis_mg, myMC3635_data.YAxis_mg, myMC3635_data.ZAxis_mg );
mcm	3:d8cf2591cab6	126	myState = 0; // Reset the variable
mcm	3:d8cf2591cab6	127	}
mcm	3:d8cf2591cab6	128
mcm	3:d8cf2591cab6	129	myled = 0;
mcm	3:d8cf2591cab6	130	}
mcm	3:d8cf2591cab6	131	}
mcm	1:d4b35641a624	132	@endcode
mcm	1:d4b35641a624	133
mcm	1:d4b35641a624	134	*/
mcm	1:d4b35641a624	135
mcm	1:d4b35641a624	136
mcm	1:d4b35641a624	137	/*!
mcm	1:d4b35641a624	138	Library for the MC3635 3-Axis Accelerometer.
mcm	1:d4b35641a624	139	*/
mcm	1:d4b35641a624	140	class MC3635
mcm	1:d4b35641a624	141	{
mcm	1:d4b35641a624	142	public:
mcm	1:d4b35641a624	143	/**
mcm	1:d4b35641a624	144	* @brief DEFAULT ADDRESSES
mcm	1:d4b35641a624	145	*/
mcm	1:d4b35641a624	146	typedef enum {
mcm	1:d4b35641a624	147	MC3635_ADDRESS_LOW = ( 0x4C << 1 ), /!< DOUT_A1 = GND /
mcm	1:d4b35641a624	148	MC3635_ADDRESS_HIGH = ( 0x6C << 1 ) /!< DOUT_A1 = VDD /
mcm	1:d4b35641a624	149	} MC3635_address_t;
mcm	1:d4b35641a624	150
mcm	1:d4b35641a624	151
mcm	1:d4b35641a624	152	/**
mcm	1:d4b35641a624	153	* @brief REGISTER SUMMARY
mcm	1:d4b35641a624	154	*/
mcm	1:d4b35641a624	155	typedef enum {
mcm	1:d4b35641a624	156	EXT_STAT_1 = 0x00, /!< Extended Status 1 /
mcm	1:d4b35641a624	157	EXT_STAT_2 = 0x01, /!< Extended Status 2 /
mcm	1:d4b35641a624	158	XOUT_LSB = 0x02, /!< XOUT_LSB /
mcm	1:d4b35641a624	159	XOUT_MSB = 0x03, /!< XOUT_MSB /
mcm	1:d4b35641a624	160	YOUT_LSB = 0x04, /!< YOUT_LSB /
mcm	1:d4b35641a624	161	YOUT_MSB = 0x05, /!< YOUT_MSB /
mcm	1:d4b35641a624	162	ZOUT_LSB = 0x06, /!< ZOUT_LSB /
mcm	1:d4b35641a624	163	ZOUT_MSB = 0x07, /!< ZOUT_MSB /
mcm	1:d4b35641a624	164	STATUS_1 = 0x08, /!< Status 1 /
mcm	1:d4b35641a624	165	STATUS_2 = 0x09, /!< Status 2 /
mcm	1:d4b35641a624	166
mcm	1:d4b35641a624	167	FREG_1 = 0x0D, /!< Feature 1 /
mcm	1:d4b35641a624	168	FREG_2 = 0x0E, /!< Feature 2 /
mcm	1:d4b35641a624	169	INIT_1 = 0x0F, /!< Initialization Register 1 /
mcm	1:d4b35641a624	170	MODE_C = 0x10, /!< Mode Control /
mcm	1:d4b35641a624	171	RATE_1 = 0x11, /!< Rate 1 /
mcm	1:d4b35641a624	172	SNIFF_C = 0x12, /!< Sniff Control /
mcm	1:d4b35641a624	173	SNIFFTH_C = 0x13, /!< Sniff Threshold Control /
mcm	1:d4b35641a624	174	SNIFFCF_C = 0x14, /!< Sniff Configuration /
mcm	1:d4b35641a624	175	RANGE_C = 0x15, /!< Range Resolution Control /
mcm	1:d4b35641a624	176	FIFO_C = 0x16, /!< FIFO Control /
mcm	1:d4b35641a624	177	INTR_C = 0x17, /!< Interrupt Control /
mcm	1:d4b35641a624	178
mcm	1:d4b35641a624	179	INIT_3 = 0x1A, /!< Initialization Register 3 /
mcm	1:d4b35641a624	180	SCRATCH = 0x1B, /!< Scratchpad /
mcm	1:d4b35641a624	181	PMCR = 0x1C, /!< Power Mode Control /
mcm	1:d4b35641a624	182
mcm	1:d4b35641a624	183	DMX = 0x20, /!< Drive Motion X /
mcm	1:d4b35641a624	184	DMY = 0x21, /!< Drive Motion Y /
mcm	1:d4b35641a624	185	DMZ = 0x22, /!< Drive Motion Z /
mcm	1:d4b35641a624	186
mcm	1:d4b35641a624	187	RESET = 0x24, /!< Reset /
mcm	1:d4b35641a624	188
mcm	1:d4b35641a624	189	INIT_2 = 0x28, /!< Initialization Register 2 /
mcm	1:d4b35641a624	190	TRIGC = 0x29, /!< Trigger Count /
mcm	1:d4b35641a624	191	XOFFL = 0x2A, /!< X-Offset LSB /
mcm	1:d4b35641a624	192	XOFFH = 0x2B, /!< X-Offset MSB /
mcm	1:d4b35641a624	193	YOFFL = 0x2C, /!< Y-Offset LSB /
mcm	1:d4b35641a624	194	YOFFH = 0x2D, /!< Y-Offset MSB /
mcm	1:d4b35641a624	195	ZOFFL = 0x2E, /!< Z-Offset LSB /
mcm	1:d4b35641a624	196	ZOFFH = 0x2F, /!< Z-Offset MSB /
mcm	1:d4b35641a624	197	XGAIN = 0x30, /!< X Gain /
mcm	1:d4b35641a624	198	YGAIN = 0x31, /!< Y Gain /
mcm	1:d4b35641a624	199	ZGAIN = 0x32 /!< Z Gain /
mcm	1:d4b35641a624	200	} MC3635_register_summary_t;
mcm	1:d4b35641a624	201
mcm	1:d4b35641a624	202
mcm	1:d4b35641a624	203
mcm	1:d4b35641a624	204	/* Commands Registers */
mcm	1:d4b35641a624	205	/**
mcm	1:d4b35641a624	206	* @brief EXTENDED STATUS REGISTER 1
mcm	1:d4b35641a624	207	*/
mcm	1:d4b35641a624	208	/* Bit 3 : This register contains status for the I2C address of the device. */
mcm	1:d4b35641a624	209	typedef enum {
mcm	1:d4b35641a624	210	EXT_STAT_1_I2C_AD0_BIT_MASK = ( 1 << 3 ), /!< I2C_AD0_BIT Mask /
mcm	1:d4b35641a624	211	EXT_STAT_1_I2C_AD0_BIT_0X4C = ( 0 << 3 ), /!< I2C Address 0x4C ( DOUT_A1 = LOW ) /
mcm	1:d4b35641a624	212	EXT_STAT_1_I2C_AD0_BIT_0X6C = ( 1 << 3 ) /!< I2C Address 0x6C ( DOUT_A1 = HIGH ) /
mcm	1:d4b35641a624	213	} MC3635_ext_stat_1_i2c_ad0_bit_t;
mcm	1:d4b35641a624	214
mcm	1:d4b35641a624	215
mcm	1:d4b35641a624	216
mcm	1:d4b35641a624	217	/**
mcm	1:d4b35641a624	218	* @brief EXTENDED STATUS REGISTER 2
mcm	1:d4b35641a624	219	*
mcm	1:d4b35641a624	220	* The device status register reports various conditions of the device data, clock and sniff
mcm	1:d4b35641a624	221	* circuitry.
mcm	1:d4b35641a624	222	*/
mcm	1:d4b35641a624	223	/* Bit 0 : OVR_DATA. */
mcm	1:d4b35641a624	224	typedef enum {
mcm	1:d4b35641a624	225	EXT_STAT_2_OVR_DATA_MASK = ( 1 << 0 ), /!< OVR_DATA Mask /
mcm	1:d4b35641a624	226	EXT_STAT_2_OVR_DATA_SAMPLE_OVERWRITTEN = ( 1 << 0 ), /!< Previous acceleration sample was not read by host and has been overwritten /
mcm	1:d4b35641a624	227	EXT_STAT_2_OVR_DATA_SAMPLE_NOT_OVERWRITTEN = ( 0 << 0 ) /!< Previous acceleration sample has not been overwritten before read by host /
mcm	1:d4b35641a624	228	} MC3635_ext_stat_2_ovr_data_t;
mcm	1:d4b35641a624	229
mcm	1:d4b35641a624	230
mcm	1:d4b35641a624	231	/* Bit 1 : PD_CLK_STAT. */
mcm	1:d4b35641a624	232	typedef enum {
mcm	1:d4b35641a624	233	EXT_STAT_2_PD_CLK_STAT_MASK = ( 1 << 1 ), /!< PD_CLK_STAT Mask /
mcm	1:d4b35641a624	234	EXT_STAT_2_PD_CLK_STAT_CLOCKS_ENABLED = ( 0 << 1 ), /!< Clocks are enabled /
mcm	1:d4b35641a624	235	EXT_STAT_2_PD_CLK_STAT_CLOCKS_DISABLED = ( 1 << 1 ) /!< Clocks are disabled /
mcm	1:d4b35641a624	236	} MC3635_ext_stat_2_pd_clk_stat_t;
mcm	1:d4b35641a624	237
mcm	1:d4b35641a624	238
mcm	1:d4b35641a624	239	/* Bit 5 : OTP_BUSY. */
mcm	1:d4b35641a624	240	typedef enum {
mcm	1:d4b35641a624	241	EXT_STAT_2_OTP_BUSY_MASK = ( 1 << 5 ), /!< OTP_BUSY Mask /
mcm	1:d4b35641a624	242	EXT_STAT_2_OTP_BUSY_OTP_POWER_DOWN = ( 0 << 5 ), /!< OTP_VDD supply is not enabled, OTP is powered down /
mcm	1:d4b35641a624	243	EXT_STAT_2_OTP_BUSY_OTP_POWERED = ( 1 << 5 ) /!< OTP_VDD supply is enabled, OTP is powered /
mcm	1:d4b35641a624	244	} MC3635_ext_stat_2_otp_busy_t;
mcm	1:d4b35641a624	245
mcm	1:d4b35641a624	246
mcm	1:d4b35641a624	247	/* Bit 6 : SNIFF_EN. */
mcm	1:d4b35641a624	248	typedef enum {
mcm	1:d4b35641a624	249	EXT_STAT_2_SNIFF_EN_MASK = ( 1 << 6 ), /!< SNIFF_EN Mask /
mcm	1:d4b35641a624	250	EXT_STAT_2_SNIFF_EN_DISABLED = ( 0 << 6 ), /!< SNIFF mode is not active /
mcm	1:d4b35641a624	251	EXT_STAT_2_SNIFF_EN_ENABLED = ( 1 << 6 ) /!< SNIFF mode is active /
mcm	1:d4b35641a624	252	} MC3635_ext_stat_2_sniff_en_t;
mcm	1:d4b35641a624	253
mcm	1:d4b35641a624	254
mcm	1:d4b35641a624	255	/* Bit 7 : SNIFF_DETECT. */
mcm	1:d4b35641a624	256	typedef enum {
mcm	1:d4b35641a624	257	EXT_STAT_2_SNIFF_DETECT_MASK = ( 1 << 7 ), /!< SNIFF_DETECT Mask /
mcm	1:d4b35641a624	258	EXT_STAT_2_SNIFF_DETECT_NOT_EVENT = ( 0 << 7 ), /!< No sniff event detected /
mcm	1:d4b35641a624	259	EXT_STAT_2_SNIFF_DETECT_EVENT = ( 1 << 7 ) /!< Sniff event detected, move to CWAKE mode /
mcm	1:d4b35641a624	260	} MC3635_ext_stat_2_sniff_detect_t;
mcm	1:d4b35641a624	261
mcm	1:d4b35641a624	262
mcm	1:d4b35641a624	263
mcm	1:d4b35641a624	264	/**
mcm	1:d4b35641a624	265	* @brief STATUS REGISTER 1
mcm	1:d4b35641a624	266	*
mcm	1:d4b35641a624	267	* This register reports the operational mode of the device. Note that the lower 3-bits, the
mcm	1:d4b35641a624	268	* MODE[2:0] field, do not immediately change once a command is written to the MODE register,
mcm	1:d4b35641a624	269	* but may take up to 3 transitions of the heartbeat clock.
mcm	1:d4b35641a624	270	*/
mcm	1:d4b35641a624	271	/* Bits 2:0 : MODE. */
mcm	1:d4b35641a624	272	typedef enum {
mcm	1:d4b35641a624	273	STATUS_1_MODE_MASK = ( 0b111 << 0 ), /!< MODE Mask /
mcm	1:d4b35641a624	274	STATUS_1_MODE_SLEEP = ( 0b000 << 0 ), /!< Lowest power mode, regulators on, no clock activity, partial chip power-down /
mcm	1:d4b35641a624	275	STATUS_1_MODE_STANDBY = ( 0b001 << 0 ), /!< Low power mode, no sampling, clocks active /
mcm	1:d4b35641a624	276	STATUS_1_MODE_SNIFF = ( 0b010 << 0 ), /!< Sniff activity detection mode, sniff enabled, sniff sampling, no FIFO operations, automatically transition to CWAKE mode upon activity detection /
mcm	1:d4b35641a624	277	STATUS_1_MODE_CWAKE = ( 0b101 << 0 ), /!< Continuous wake. Active XYZ sampling. Sniff circuitry not active /
mcm	1:d4b35641a624	278	STATUS_1_MODE_SWAKE = ( 0b110 << 0 ), /!< Use Sniff logic, main XYZ pipeline and optional FIFO at the same time; highest power consumption /
mcm	1:d4b35641a624	279	STATUS_1_MODE_TRIG = ( 0b111 << 0 ) /!< Trigger mode, 1 to 254 samples or continuous, return to sleep upon completion /
mcm	1:d4b35641a624	280	} MC3635_status_1_mode_t;
mcm	1:d4b35641a624	281
mcm	1:d4b35641a624	282
mcm	1:d4b35641a624	283	/* Bit 3 : NEW_DATA. */
mcm	1:d4b35641a624	284	typedef enum {
mcm	1:d4b35641a624	285	STATUS_1_NEW_DATA_MASK = ( 1 << 3 ), /!< NEW_DATA Mask /
mcm	1:d4b35641a624	286	STATUS_1_NEW_DATA_FALSE = ( 0 << 3 ), /!< No new sample data has arrived since last read /
mcm	1:d4b35641a624	287	STATUS_1_NEW_DATA_TRUE = ( 1 << 3 ) /!< New sample data has arrived and has been written to FIFO/registers. This bit is always enabled and valid, regardless of the settings of any interrupt enable bits /
mcm	1:d4b35641a624	288	} MC3635_status_1_new_data_t;
mcm	1:d4b35641a624	289
mcm	1:d4b35641a624	290
mcm	1:d4b35641a624	291	/* Bit 4 : FIFO_EMPTY. */
mcm	1:d4b35641a624	292	typedef enum {
mcm	1:d4b35641a624	293	STATUS_1_FIFO_EMPTY_MASK = ( 1 << 4 ), /!< FIFO_EMPTY Mask /
mcm	1:d4b35641a624	294	STATUS_1_FIFO_EMPTY_FALSE = ( 0 << 4 ), /!< FIFO has one or more samples in storage (level) /
mcm	1:d4b35641a624	295	STATUS_1_FIFO_EMPTY_TRUE = ( 1 << 4 ) /!< FIFO is empty (level) (default). This bit is set to 1 immediately after device power-up or device reset /
mcm	1:d4b35641a624	296	} MC3635_status_1_fifo_empty_t;
mcm	1:d4b35641a624	297
mcm	1:d4b35641a624	298
mcm	1:d4b35641a624	299	/* Bit 5 : FIFO_FULL. */
mcm	1:d4b35641a624	300	typedef enum {
mcm	1:d4b35641a624	301	STATUS_1_FIFO_FULL_MASK = ( 1 << 5 ), /!< FIFO_FULL Mask /
mcm	1:d4b35641a624	302	STATUS_1_FIFO_FULL_FALSE = ( 0 << 5 ), /!< FIFO has space or 1 or more samples (up to 32) (level) /
mcm	1:d4b35641a624	303	STATUS_1_FIFO_FULL_TRUE = ( 1 << 5 ) /!< FIFO is full, all 32 samples are used (level) /
mcm	1:d4b35641a624	304	} MC3635_status_1_fifo_full_t;
mcm	1:d4b35641a624	305
mcm	1:d4b35641a624	306
mcm	1:d4b35641a624	307	/* Bit 6 : FIFO_THRESH. */
mcm	1:d4b35641a624	308	typedef enum {
mcm	1:d4b35641a624	309	STATUS_1_FIFO_THRESH_MASK = ( 1 << 6 ), /!< FIFO_THRESH Mask /
mcm	1:d4b35641a624	310	STATUS_1_FIFO_THRESH_LESS = ( 0 << 6 ), /!< Amount of data in FIFO is less than the threshold (level) /
mcm	1:d4b35641a624	311	STATUS_1_FIFO_THRESH_EQUAL_GREATER = ( 1 << 6 ) /!< Amount of data in FIFO is equal to or greater than the threshold (level) /
mcm	1:d4b35641a624	312	} MC3635_status_1_fifo_thresh_t;
mcm	1:d4b35641a624	313
mcm	1:d4b35641a624	314
mcm	1:d4b35641a624	315	/* Bit 7 : INT_PEND. */
mcm	1:d4b35641a624	316	typedef enum {
mcm	1:d4b35641a624	317	STATUS_1_INT_PEND_MASK = ( 1 << 7 ), /!< INT_PEND Mask /
mcm	1:d4b35641a624	318	STATUS_1_INT_PEND_FALSE = ( 0 << 7 ), /!< No interrupt flags are pending in register 0x09 (level) /
mcm	1:d4b35641a624	319	STATUS_1_INT_PEND_TRUE = ( 1 << 7 ) /!< One or more interrupt flags are pending in register 0x09 (logical OR) (level) /
mcm	1:d4b35641a624	320	} MC3635_status_1_int_pend_t;
mcm	1:d4b35641a624	321
mcm	1:d4b35641a624	322
mcm	1:d4b35641a624	323
mcm	1:d4b35641a624	324	/**
mcm	1:d4b35641a624	325	* @brief STATUS REGISTER 2
mcm	1:d4b35641a624	326	*
mcm	1:d4b35641a624	327	* This register reports the state of the interrupts ('0' means not pending; '1' means pending). A
mcm	1:d4b35641a624	328	* bit in this register will only be set if the corresponding interrupt enable is set to '1' in (0x17)
mcm	1:d4b35641a624	329	* Interrupt Control Register.
mcm	1:d4b35641a624	330	*/
mcm	1:d4b35641a624	331	/* Bit 2 : INT_WAKE. */
mcm	1:d4b35641a624	332	typedef enum {
mcm	1:d4b35641a624	333	STATUS_2_INT_WAKE_MASK = ( 1 << 2 ), /!< INT_WAKE Mask /
mcm	1:d4b35641a624	334	STATUS_2_INT_WAKE_FALSE = ( 0 << 2 ), /!< INT_WAKE not triggered /
mcm	1:d4b35641a624	335	STATUS_2_INT_WAKE_TRUE = ( 1 << 2 ) /!< INT_WAKE triggered /
mcm	1:d4b35641a624	336	} MC3635_status_2_int_wake_t;
mcm	1:d4b35641a624	337
mcm	1:d4b35641a624	338
mcm	1:d4b35641a624	339	/* Bit 3 : INT_ACQ. */
mcm	1:d4b35641a624	340	typedef enum {
mcm	1:d4b35641a624	341	STATUS_2_INT_ACQ_MASK = ( 1 << 3 ), /!< INT_ACQ Mask /
mcm	1:d4b35641a624	342	STATUS_2_INT_ACQ_FALSE = ( 0 << 3 ), /!< INT_ACQ not triggered /
mcm	1:d4b35641a624	343	STATUS_2_INT_ACQ_TRUE = ( 1 << 3 ) /!< INT_ACQ triggered /
mcm	1:d4b35641a624	344	} MC3635_status_2_int_acq_t;
mcm	1:d4b35641a624	345
mcm	1:d4b35641a624	346
mcm	1:d4b35641a624	347	/* Bit 4 : INT_FIFO_EMPTY. */
mcm	1:d4b35641a624	348	typedef enum {
mcm	1:d4b35641a624	349	STATUS_2_INT_FIFO_EMPTY_MASK = ( 1 << 4 ), /!< INT_FIFO_EMPTY Mask /
mcm	1:d4b35641a624	350	STATUS_2_INT_FIFO_EMPTY_FALSE = ( 0 << 4 ), /!< INT_FIFO_EMPTY not triggered /
mcm	1:d4b35641a624	351	STATUS_2_INT_FIFO_EMPTY_TRUE = ( 1 << 4 ) /!< INT_FIFO_EMPTY triggered /
mcm	1:d4b35641a624	352	} MC3635_status_2_int_fifo_empty_t;
mcm	1:d4b35641a624	353
mcm	1:d4b35641a624	354
mcm	1:d4b35641a624	355	/* Bit 5 : INT_FIFO_FULL. */
mcm	1:d4b35641a624	356	typedef enum {
mcm	1:d4b35641a624	357	STATUS_2_INT_FIFO_FULL_MASK = ( 1 << 5 ), /!< INT_FIFO_FULL Mask /
mcm	1:d4b35641a624	358	STATUS_2_INT_FIFO_FULL_FALSE = ( 0 << 5 ), /!< INT_FIFO_FULL not triggered /
mcm	1:d4b35641a624	359	STATUS_2_INT_FIFO_FULL_TRUE = ( 1 << 5 ) /!< INT_FIFO_FULL triggered /
mcm	1:d4b35641a624	360	} MC3635_status_2_int_fifo_full_t;
mcm	1:d4b35641a624	361
mcm	1:d4b35641a624	362
mcm	1:d4b35641a624	363	/* Bit 6 : INT_FIFO_THRESH. */
mcm	1:d4b35641a624	364	typedef enum {
mcm	1:d4b35641a624	365	STATUS_2_INT_FIFO_THRESH_MASK = ( 1 << 6 ), /!< INT_FIFO_THRESH Mask /
mcm	1:d4b35641a624	366	STATUS_2_INT_FIFO_THRESH_FALSE = ( 0 << 6 ), /!< INT_FIFO_THRESH not triggered /
mcm	1:d4b35641a624	367	STATUS_2_INT_FIFO_THRESH_TRUE = ( 1 << 6 ) /!< INT_FIFO_THRESH triggered /
mcm	1:d4b35641a624	368	} MC3635_status_2_int_fifo_thresh_t;
mcm	1:d4b35641a624	369
mcm	1:d4b35641a624	370
mcm	1:d4b35641a624	371	/* Bit 7 : INT_SWAKE. */
mcm	1:d4b35641a624	372	typedef enum {
mcm	1:d4b35641a624	373	STATUS_2_INT_SWAKE_MASK = ( 1 << 7 ), /!< INT_SWAKE Mask /
mcm	1:d4b35641a624	374	STATUS_2_INT_SWAKE_FALSE = ( 0 << 7 ), /!< INT_SWAKE not triggered /
mcm	1:d4b35641a624	375	STATUS_2_INT_SWAKE_TRUE = ( 1 << 7 ) /!< INT_SWAKE triggered /
mcm	1:d4b35641a624	376	} MC3635_status_2_int_swake_t;
mcm	1:d4b35641a624	377
mcm	1:d4b35641a624	378
mcm	1:d4b35641a624	379
mcm	1:d4b35641a624	380	/**
mcm	1:d4b35641a624	381	* @brief FEATURE REGISTER 1
mcm	1:d4b35641a624	382	*
mcm	1:d4b35641a624	383	* This register is used to select the interface mode as well as the operation style of the FIFO and
mcm	1:d4b35641a624	384	* interrupt in SWAKE mode.
mcm	1:d4b35641a624	385	*/
mcm	1:d4b35641a624	386	/* Bit 3 : FREEZE. */
mcm	1:d4b35641a624	387	typedef enum {
mcm	1:d4b35641a624	388	FREG_1_FREEZE_MASK = ( 1 << 3 ), /!< FREEZE Mask /
mcm	1:d4b35641a624	389	FREG_1_FREEZE_FIFO_STANDARD_MODE = ( 0 << 3 ), /!< FIFO operates in standard mode, does not stop capturing data in SWAKE interrupt (default) /
mcm	1:d4b35641a624	390	FREG_1_FREEZE_FIFO_STOP_SWAKE = ( 1 << 3 ) /!< FIFO stops capturing on SWAKE interrupt, software can examine the conditions which generated the SWAKE event /
mcm	1:d4b35641a624	391	} MC3635_freg_1_freeze_t;
mcm	1:d4b35641a624	392
mcm	1:d4b35641a624	393
mcm	1:d4b35641a624	394	/* Bit 4 : INTSC_EN. */
mcm	1:d4b35641a624	395	typedef enum {
mcm	1:d4b35641a624	396	FREG_1_INTSC_EN_MASK = ( 1 << 4 ), /!< INTSC_EN Mask /
mcm	1:d4b35641a624	397	FREG_1_INTSC_EN_DISABLED = ( 0 << 4 ), /!< Do not re-arm SNIFF block following a SWAKE event (requires the SNIFF block to be reset by exiting SWAKE mode). (default) /
mcm	1:d4b35641a624	398	FREG_1_INTSC_EN_ENABLED = ( 1 << 4 ) /!< Clearing the SWAKE interrupt clears and rearms the SNIFF block for subsequent detections (device may stay in SWAKE mode and continuing processing subsequent SWAKE events once interrupt is cleared) /
mcm	1:d4b35641a624	399	} MC3635_freg_1_intsc_en_t;
mcm	1:d4b35641a624	400
mcm	1:d4b35641a624	401
mcm	1:d4b35641a624	402	/* Bit 5 : SPI3_EN. */
mcm	1:d4b35641a624	403	typedef enum {
mcm	1:d4b35641a624	404	FREG_1_SPI3_EN_MASK = ( 1 << 5 ), /!< SPI3_EN Mask /
mcm	1:d4b35641a624	405	FREG_1_SPI3_EN_DISABLED = ( 0 << 5 ), /!< SPI interface is 4-wire /
mcm	1:d4b35641a624	406	FREG_1_SPI3_EN_ENABLED = ( 1 << 5 ) /!< SPI interface is 3-wire (DOUT_A1 is the bidirectional pin) /
mcm	1:d4b35641a624	407	} MC3635_freg_1_spi3_en_t;
mcm	1:d4b35641a624	408
mcm	1:d4b35641a624	409
mcm	1:d4b35641a624	410	/* Bit 6 : I2C_EN. */
mcm	1:d4b35641a624	411	typedef enum {
mcm	1:d4b35641a624	412	FREG_1_I2C_EN_MASK = ( 1 << 6 ), /!< I2C_EN Mask /
mcm	1:d4b35641a624	413	FREG_1_I2C_EN_DISABLED = ( 0 << 6 ), /!< Device interface is still defined as it was at power-up but no data will appear in XOUT, YOUT and ZOUT registers if both this bit and SPI_EN are set to 0 (default). /
mcm	1:d4b35641a624	414	FREG_1_I2C_EN_ENABLED = ( 1 << 6 ) /!< Disables any SPI communications /
mcm	1:d4b35641a624	415	} MC3635_freg_1_i2c_en_t;
mcm	1:d4b35641a624	416
mcm	1:d4b35641a624	417
mcm	1:d4b35641a624	418	/* Bit 7 : SPI_EN. */
mcm	1:d4b35641a624	419	typedef enum {
mcm	1:d4b35641a624	420	FREG_1_SPI_EN_MASK = ( 1 << 7 ), /!< SPI_EN Mask /
mcm	1:d4b35641a624	421	FREG_1_SPI_EN_DISABLED = ( 0 << 7 ), /!< Device interface is still defined as it was at power-up but no data will appear in XOUT, YOUT and ZOUT registers if both this bit and I2C_EN are set to 0 (default). /
mcm	1:d4b35641a624	422	FREG_1_SPI_EN_ENABLED = ( 1 << 7 ) /!< Disables any I2C communications /
mcm	1:d4b35641a624	423	} MC3635_freg_1_spi_en_t;
mcm	1:d4b35641a624	424
mcm	1:d4b35641a624	425
mcm	1:d4b35641a624	426
mcm	1:d4b35641a624	427	/**
mcm	1:d4b35641a624	428	* @brief FEATURE REGISTER 2
mcm	1:d4b35641a624	429	*
mcm	1:d4b35641a624	430	* This register allows selection of various features for the FIFO, external trigger input, method of interrupt clearing and burst address wrapping.
mcm	1:d4b35641a624	431	*/
mcm	1:d4b35641a624	432	/* Bit 0 : WRAPA. */
mcm	1:d4b35641a624	433	typedef enum {
mcm	1:d4b35641a624	434	FREG_2_WRAPA_MASK = ( 1 << 0 ), /!< WRAPA Mask /
mcm	1:d4b35641a624	435	FREG_2_WRAPA_ADDRESS_0X07 = ( 0 << 0 ), /!< Burst read cycle address wrap address is 0x07, counter automatically returns to 0x02. (default) /
mcm	1:d4b35641a624	436	FREG_2_WRAPA_ADDRESS_0X09 = ( 1 << 0 ) /!< Burst read cycle address wrap address is 0x09, counter automatically returns to 0x02. This setting allows for status registers 0x08 and 0x09 to be included in the burst read /
mcm	1:d4b35641a624	437	} MC3635_freg_2_wrapa_t;
mcm	1:d4b35641a624	438
mcm	1:d4b35641a624	439
mcm	1:d4b35641a624	440	/* Bit 1 : FIFO_BURST. */
mcm	1:d4b35641a624	441	typedef enum {
mcm	1:d4b35641a624	442	FREG_2_FIFO_BURST_MASK = ( 1 << 1 ), /!< FIFO_BURST Mask /
mcm	1:d4b35641a624	443	FREG_2_FIFO_BURST_DISABLED = ( 0 << 1 ), /!< FIFO burst read cycles are 6-bytes in length, 0x02 to 0x07 per read cycle transaction (default) /
mcm	1:d4b35641a624	444	FREG_2_FIFO_BURST_ENABLED = ( 1 << 1 ) /!< FIFO burst read cycle can be any number of 6-byte reads, up to 32 x 6 bytes (i.e. the entire FIFO contents can be read). /
mcm	1:d4b35641a624	445	} MC3635_freg_2_fifo_burst_t;
mcm	1:d4b35641a624	446
mcm	1:d4b35641a624	447
mcm	1:d4b35641a624	448	/* Bit 2 : SPI_STAT_EN. */
mcm	1:d4b35641a624	449	typedef enum {
mcm	1:d4b35641a624	450	FREG_2_SPI_STAT_EN_MASK = ( 1 << 2 ), /!< SPI_STAT_EN Mask /
mcm	1:d4b35641a624	451	FREG_2_SPI_STAT_EN_SPI_FLAGS_DISABLED= ( 0 << 2 ), /!< No SPI status flags are shifted out (default) /
mcm	1:d4b35641a624	452	FREG_2_SPI_STAT_EN_SPI_FLAGS_ENABLED = ( 1 << 2 ) /!< SPI status flags are shifted out on the first byte of all 4-wire SPI transactions (SPI 3-wire and I2C modes are not supported, so no effect will be seen in those modes)./
mcm	1:d4b35641a624	453	} MC3635_freg_2_spi_stat_en_t;
mcm	1:d4b35641a624	454
mcm	1:d4b35641a624	455
mcm	1:d4b35641a624	456	/* Bit 3 : FIFO_STAT_EN. */
mcm	1:d4b35641a624	457	typedef enum {
mcm	1:d4b35641a624	458	FREG_2_FIFO_STAT_EN_MASK = ( 1 << 3 ), /!< FIFO_STAT_EN Mask /
mcm	1:d4b35641a624	459	FREG_2_FIFO_STAT_EN_DISABLED = ( 0 << 3 ), /!< FIFO status feature is disabled, Z channel FIFO data is not overwritten with FIFO status information. (default) /
mcm	1:d4b35641a624	460	FREG_2_FIFO_STAT_EN_ENABLED = ( 1 << 3 ) /!< FIFO status feature is enabled. When the resolution is less than 14-bits, the top 4-bits of 16-bit Z channel FIFO data are replaced with FIFO status information /
mcm	1:d4b35641a624	461	} MC3635_freg_2_fifo_stat_en_t;
mcm	1:d4b35641a624	462
mcm	1:d4b35641a624	463
mcm	1:d4b35641a624	464	/* Bit 4 : I2CINT_WRCLRE. */
mcm	1:d4b35641a624	465	typedef enum {
mcm	1:d4b35641a624	466	FREG_2_I2CINT_WRCLRE_MASK = ( 1 << 4 ), /!< I2CINT_WRCLRE Mask /
mcm	1:d4b35641a624	467	FREG_2_I2CINT_WRCLRE_DISABLED = ( 0 << 4 ), /!< In I2C mode, interrupts are cleared when reading register 0x09 (default) /
mcm	1:d4b35641a624	468	FREG_2_I2CINT_WRCLRE_ENABLED = ( 1 << 4 ) /!< if I2C_EN is '1', then interrupts are cleared when writing to register 0x09. Otherwise I2C reads to register 0x09 will still clear pending interrupts /
mcm	1:d4b35641a624	469	} MC3635_freg_2_i2cint_wrclre_t;
mcm	1:d4b35641a624	470
mcm	1:d4b35641a624	471
mcm	1:d4b35641a624	472	/* Bit 5 : FIFO_STREAM. */
mcm	1:d4b35641a624	473	typedef enum {
mcm	1:d4b35641a624	474	FREG_2_FIFO_STREAM_MASK = ( 1 << 5 ), /!< FIFO_STREAM Mask /
mcm	1:d4b35641a624	475	FREG_2_FIFO_STREAM_DISABLED = ( 0 << 5 ), /!< FIFO steam mode is disabled, FIFO stops accepting new data when FULL (default) /
mcm	1:d4b35641a624	476	FREG_2_FIFO_STREAM_ENABLED = ( 1 << 5 ) /!< FIFO stream mode is enabled, FIFO discards oldest samples once new data arrives /
mcm	1:d4b35641a624	477	} MC3635_freg_2_fifo_stream_t;
mcm	1:d4b35641a624	478
mcm	1:d4b35641a624	479
mcm	1:d4b35641a624	480	/* Bit 6 : EXT_TRIG_POL. */
mcm	1:d4b35641a624	481	typedef enum {
mcm	1:d4b35641a624	482	FREG_2_EXT_TRIG_POL_MASK = ( 1 << 6 ), /!< EXT_TRIG_POL Mask /
mcm	1:d4b35641a624	483	FREG_2_EXT_TRIG_POL_NEGATIVE_EDGE = ( 0 << 6 ), /!< Trigger polarity is negative edge triggered (default) /
mcm	1:d4b35641a624	484	FREG_2_EXT_TRIG_POL_POSITIVE_EDGE = ( 1 << 6 ) /!< Trigger polarity is positive edge triggered /
mcm	1:d4b35641a624	485	} MC3635_freg_2_ext_trig_pol_t;
mcm	1:d4b35641a624	486
mcm	1:d4b35641a624	487
mcm	1:d4b35641a624	488	/* Bit 7 : EXT_TRIG_EN. */
mcm	1:d4b35641a624	489	typedef enum {
mcm	1:d4b35641a624	490	FREG_2_EXT_TRIG_EN_MASK = ( 1 << 7 ), /!< EXT_TRIG_EN Mask /
mcm	1:d4b35641a624	491	FREG_2_EXT_TRIG_EN_DISABLED = ( 0 << 7 ), /!< External trigger mode is not enabled (default) /
mcm	1:d4b35641a624	492	FREG_2_EXT_TRIG_EN_ENABLED = ( 1 << 7 ) /!< External trigger mode is enabled, use INTN pin as the external trigger input. /
mcm	1:d4b35641a624	493	} MC3635_freg_2_ext_trig_en_t;
mcm	1:d4b35641a624	494
mcm	1:d4b35641a624	495
mcm	1:d4b35641a624	496
mcm	1:d4b35641a624	497	/**
mcm	1:d4b35641a624	498	* @brief INITIALIZATION REGISTER 1
mcm	1:d4b35641a624	499	*
mcm	1:d4b35641a624	500	* Software must write a fixed value to this register immediately after power-up or reset. This register will not typically read-back the value which was written.
mcm	1:d4b35641a624	501	*/
mcm	1:d4b35641a624	502	/* Bits 7:0 : INIT_1. */
mcm	1:d4b35641a624	503	typedef enum {
mcm	1:d4b35641a624	504	INIT_1_INIT_1_FIXED_VALUE = 0x42 /!< INIT_1 fix value /
mcm	1:d4b35641a624	505	} MC3635_init_1_init_1_t;
mcm	1:d4b35641a624	506
mcm	1:d4b35641a624	507
mcm	1:d4b35641a624	508
mcm	1:d4b35641a624	509	/**
mcm	1:d4b35641a624	510	* @brief MODE CONTROL REGISTER
mcm	1:d4b35641a624	511	*
mcm	1:d4b35641a624	512	* This register is the primary control register for the accelerometer. The operational mode of the device, X/Y/Z axis enables, and the TRIG one-shot
mcm	1:d4b35641a624	513	* mode can be written through this register. The mode transitions controlled by this register may take up to 3 transitions of the heartbeat clock.
mcm	1:d4b35641a624	514	* Depending on the operation, the lower 3-bits (MCTRL[2:0]) may be automatically set or cleared by hardware if auto-triggered events are executed.
mcm	1:d4b35641a624	515	* In general, when software sets an operational mode using the MCTRL [2:0] bits, there might be a delay time of 2 to 10 mSec before the operational mode
mcm	1:d4b35641a624	516	* is reflected by the MODE[2:0] bits in Status Register 1.
mcm	1:d4b35641a624	517	*/
mcm	1:d4b35641a624	518	/* Bits 2:0 : MCTRL. */
mcm	1:d4b35641a624	519	typedef enum {
mcm	1:d4b35641a624	520	MODE_C_MCTRL_MASK = ( 0b111 << 0 ), /!< MCTRL Mask /
mcm	1:d4b35641a624	521	MODE_C_MCTRL_SLEEP = ( 0b000 << 0 ), /!< Lowest power mode, regulators on, no clock activity, partial chip power-down /
mcm	1:d4b35641a624	522	MODE_C_MCTRL_STANDBY = ( 0b001 << 0 ), /!< Low power mode, no sampling, clocks active /
mcm	1:d4b35641a624	523	MODE_C_MCTRL_SNIFF = ( 0b010 << 0 ), /!< Sniff activity detection mode, sniff enabled, no sampling, no FIFO operations, automatically transition to CWAKE mode upon activity detection /
mcm	1:d4b35641a624	524	MODE_C_MCTRL_CWAKE = ( 0b101 << 0 ), /!< Continuous wake. Active XYZ sampling. Sniff circuitry not active /
mcm	1:d4b35641a624	525	MODE_C_MCTRL_SWAKE = ( 0b110 << 0 ), /!< Use Sniff logic, main XYZ pipeline and optional FIFO at the same time; highest power consumption /
mcm	1:d4b35641a624	526	MODE_C_MCTRL_TRIG = ( 0b111 << 0 ) /!< Trigger mode, 1 to 254 samples or continuous, return to sleep upon completion /
mcm	1:d4b35641a624	527	} MC3635_mode_c_mctrl_t;
mcm	1:d4b35641a624	528
mcm	1:d4b35641a624	529
mcm	1:d4b35641a624	530	/* Bit 4 : X_AXIS_PD. */
mcm	1:d4b35641a624	531	typedef enum {
mcm	1:d4b35641a624	532	MODE_C_X_AXIS_PD_MASK = ( 1 << 4 ), /!< X_AXIS_PD Mask /
mcm	1:d4b35641a624	533	MODE_C_X_AXIS_PD_ENABLED = ( 0 << 4 ), /!< X-axis is enabled /
mcm	1:d4b35641a624	534	MODE_C_X_AXIS_PD_DISABLED = ( 1 << 4 ) /!< X-axis is disabled /
mcm	1:d4b35641a624	535	} MC3635_mode_c_x_axis_pd_t;
mcm	1:d4b35641a624	536
mcm	1:d4b35641a624	537
mcm	1:d4b35641a624	538	/* Bit 5 : Y_AXIS_PD. */
mcm	1:d4b35641a624	539	typedef enum {
mcm	1:d4b35641a624	540	MODE_C_Y_AXIS_PD_MASK = ( 1 << 5 ), /!< Y_AXIS_PD Mask /
mcm	1:d4b35641a624	541	MODE_C_Y_AXIS_PD_ENABLED = ( 0 << 5 ), /!< Y-axis is enabled /
mcm	1:d4b35641a624	542	MODE_C_Y_AXIS_PD_DISABLED = ( 1 << 5 ) /!< Y-axis is disabled /
mcm	1:d4b35641a624	543	} MC3635_mode_c_y_axis_pd_t;
mcm	1:d4b35641a624	544
mcm	1:d4b35641a624	545
mcm	1:d4b35641a624	546	/* Bit 6 : Z_AXIS_PD. */
mcm	1:d4b35641a624	547	typedef enum {
mcm	1:d4b35641a624	548	MODE_C_Z_AXIS_PD_MASK = ( 1 << 6 ), /!< Z_AXIS_PD Mask /
mcm	1:d4b35641a624	549	MODE_C_Z_AXIS_PD_ENABLED = ( 0 << 6 ), /!< Z-axis is enabled /
mcm	1:d4b35641a624	550	MODE_C_Z_AXIS_PD_DISABLED = ( 1 << 6 ) /!< Z-axis is disabled /
mcm	1:d4b35641a624	551	} MC3635_mode_c_z_axis_pd_t;
mcm	1:d4b35641a624	552
mcm	1:d4b35641a624	553
mcm	1:d4b35641a624	554	/* Bit 7 : TRIG_CMD. */
mcm	1:d4b35641a624	555	typedef enum {
mcm	1:d4b35641a624	556	MODE_C_TRIG_CMD_MASK = ( 1 << 7 ), /!< TRIG_CMD Mask /
mcm	1:d4b35641a624	557	MODE_C_TRIG_CMD_DISABLED = ( 0 << 7 ),
mcm	1:d4b35641a624	558	MODE_C_TRIG_CMD_ENABLED = ( 1 << 7 )
mcm	1:d4b35641a624	559	} MC3635_mode_c_trig_cmd_t;
mcm	1:d4b35641a624	560
mcm	1:d4b35641a624	561
mcm	1:d4b35641a624	562	/**
mcm	1:d4b35641a624	563	* @brief RATE REGISTER 1
mcm	1:d4b35641a624	564	*
mcm	1:d4b35641a624	565	* This register configures the sample rates for wake modes. The rates also depend upon the value in register 0x1C.
mcm	1:d4b35641a624	566	* The device has several power modes which can be adjusted to achieve a desired power consumption at a certain ODR.
mcm	1:d4b35641a624	567	* The trade-off for lower power is either higher noise or lower ODR.
mcm	1:d4b35641a624	568	*/
mcm	1:d4b35641a624	569	/* Bits 3:0 : RR. */
mcm	1:d4b35641a624	570	typedef enum {
mcm	1:d4b35641a624	571	RATE_1_RR_MASK = ( 0b1111 << 0 ), /!< RR Mask /
mcm	1:d4b35641a624	572	RATE_1_RR_0X05 = ( 0x05 << 0 ), /!< RR value: 0x05 /
mcm	1:d4b35641a624	573	RATE_1_RR_0X06 = ( 0x06 << 0 ), /!< RR value: 0x06 /
mcm	1:d4b35641a624	574	RATE_1_RR_0X07 = ( 0x07 << 0 ), /!< RR value: 0x07 /
mcm	1:d4b35641a624	575	RATE_1_RR_0X08 = ( 0x08 << 0 ), /!< RR value: 0x08 /
mcm	1:d4b35641a624	576	RATE_1_RR_0X09 = ( 0x09 << 0 ), /!< RR value: 0x09 /
mcm	1:d4b35641a624	577	RATE_1_RR_0X0A = ( 0x0A << 0 ), /!< RR value: 0x0A /
mcm	1:d4b35641a624	578	RATE_1_RR_0X0B = ( 0x0B << 0 ), /!< RR value: 0x0B /
mcm	1:d4b35641a624	579	RATE_1_RR_0X0C = ( 0x0C << 0 ), /!< RR value: 0x0C /
mcm	1:d4b35641a624	580	RATE_1_RR_0X0F = ( 0x0F << 0 ) /!< RR value: 0x0F /
mcm	1:d4b35641a624	581	} MC3635_rate_1_rr_t;
mcm	1:d4b35641a624	582
mcm	1:d4b35641a624	583
mcm	1:d4b35641a624	584	/**
mcm	1:d4b35641a624	585	* @brief SNIFF CONTROL REGISTER
mcm	1:d4b35641a624	586	*
mcm	1:d4b35641a624	587	* This register selects the sample rate for SNIFF mode and the clock rate for STANDBY mode.
mcm	1:d4b35641a624	588	*/
mcm	1:d4b35641a624	589	/* Bits 3:0 : SNIFF_SR. */
mcm	1:d4b35641a624	590	typedef enum {
mcm	1:d4b35641a624	591	SNIFF_C_SNIFF_SR_MASK = ( 0b1111 << 0 ), /!< SNIFF_SR Mask /
mcm	1:d4b35641a624	592	SNIFF_C_SNIFF_SR_0 = ( 0b0000 << 0 ),
mcm	1:d4b35641a624	593	SNIFF_C_SNIFF_SR_1 = ( 0b0001 << 0 ),
mcm	1:d4b35641a624	594	SNIFF_C_SNIFF_SR_2 = ( 0b0010 << 0 ),
mcm	1:d4b35641a624	595	SNIFF_C_SNIFF_SR_3 = ( 0b0011 << 0 ),
mcm	1:d4b35641a624	596	SNIFF_C_SNIFF_SR_4 = ( 0b0100 << 0 ),
mcm	1:d4b35641a624	597	SNIFF_C_SNIFF_SR_5 = ( 0b0101 << 0 ),
mcm	1:d4b35641a624	598	SNIFF_C_SNIFF_SR_6 = ( 0b0110 << 0 ),
mcm	1:d4b35641a624	599	SNIFF_C_SNIFF_SR_7 = ( 0b0111 << 0 ),
mcm	1:d4b35641a624	600	SNIFF_C_SNIFF_SR_8 = ( 0b1000 << 0 ),
mcm	1:d4b35641a624	601	SNIFF_C_SNIFF_SR_9 = ( 0b1001 << 0 ),
mcm	1:d4b35641a624	602	SNIFF_C_SNIFF_SR_10 = ( 0b1010 << 0 ),
mcm	1:d4b35641a624	603	SNIFF_C_SNIFF_SR_11 = ( 0b1011 << 0 ),
mcm	1:d4b35641a624	604	SNIFF_C_SNIFF_SR_12 = ( 0b1100 << 0 ),
mcm	1:d4b35641a624	605	SNIFF_C_SNIFF_SR_13 = ( 0b1101 << 0 ),
mcm	1:d4b35641a624	606	SNIFF_C_SNIFF_SR_14 = ( 0b1110 << 0 ),
mcm	1:d4b35641a624	607	SNIFF_C_SNIFF_SR_15 = ( 0b1111 << 0 )
mcm	1:d4b35641a624	608	} MC3635_sniff_c_sniff_sr_t;
mcm	1:d4b35641a624	609
mcm	1:d4b35641a624	610
mcm	1:d4b35641a624	611	/* Bits 7:5 : STB_RATE. */
mcm	1:d4b35641a624	612	typedef enum {
mcm	1:d4b35641a624	613	SNIFF_C_STB_RATE_MASK = ( 0b111 << 5 ), /!< STB_RATE Mask /
mcm	1:d4b35641a624	614	SNIFF_C_STB_RATE_0 = ( 0b000 << 5 ),
mcm	1:d4b35641a624	615	SNIFF_C_STB_RATE_1 = ( 0b001 << 5 ),
mcm	1:d4b35641a624	616	SNIFF_C_STB_RATE_2 = ( 0b010 << 5 ),
mcm	1:d4b35641a624	617	SNIFF_C_STB_RATE_3 = ( 0b011 << 5 ),
mcm	1:d4b35641a624	618	SNIFF_C_STB_RATE_4 = ( 0b100 << 5 ),
mcm	1:d4b35641a624	619	SNIFF_C_STB_RATE_5 = ( 0b101 << 5 ),
mcm	1:d4b35641a624	620	SNIFF_C_STB_RATE_6 = ( 0b110 << 5 ),
mcm	1:d4b35641a624	621	SNIFF_C_STB_RATE_7 = ( 0b111 << 5 )
mcm	1:d4b35641a624	622	} MC3635_sniff_c_stb_rate_t;
mcm	1:d4b35641a624	623
mcm	1:d4b35641a624	624
mcm	1:d4b35641a624	625
mcm	1:d4b35641a624	626	/**
mcm	1:d4b35641a624	627	* @brief SNIFF THRESHOLD CONTROL REGISTER
mcm	1:d4b35641a624	628	*
mcm	1:d4b35641a624	629	* This register sets the threshold values used by the SNIFF logic for activity detection. For each axis,
mcm	1:d4b35641a624	630	* a delta count is generated and compared to the threshold. When the delta count is greater than the threshold,
mcm	1:d4b35641a624	631	* a SNIFF wakeup event occurs. There is a unique sniff threshold for each axis, and an optional 'false detection count'
mcm	1:d4b35641a624	632	* which requires multiple sniff detection events to occur before a wakeup condition is declared. These features are set by
mcm	1:d4b35641a624	633	* six shadow registers accessed by register 0x13[5:0] and register 0x14 bits [2:0].
mcm	1:d4b35641a624	634	*/
mcm	1:d4b35641a624	635	/* Bits 5:0 : SNIFF_TH. */
mcm	1:d4b35641a624	636	typedef enum {
mcm	1:d4b35641a624	637	SNIFFTH_C_SNIFF_TH_MASK = ( 0b111111 << 0 ) /!< SNIFF_TH Mask /
mcm	1:d4b35641a624	638	} MC3635_sniffth_c_sniff_th_t;
mcm	1:d4b35641a624	639
mcm	1:d4b35641a624	640
mcm	1:d4b35641a624	641	/* Bits 6 : SNIFF_AND_OR. */
mcm	1:d4b35641a624	642	typedef enum {
mcm	1:d4b35641a624	643	SNIFFTH_C_SNIFF_AND_OR_MASK = ( 1 << 6 ), /!< SNIFF_AND_OR Mask /
mcm	1:d4b35641a624	644	SNIFFTH_C_SNIFF_AND_OR_OR_ENABLED = ( 0 << 6 ), /!< OR - SNIFF wakeup/interrupt is triggered when any of the active channels have met detection threshold and count requirements (default) /
mcm	1:d4b35641a624	645	SNIFFTH_C_SNIFF_AND_OR_AND_ENABLED = ( 1 << 6 ) /!< AND - SNIFF wakeup/interrupt is triggered when all active channels have met detection threshold and count requirements /
mcm	1:d4b35641a624	646	} MC3635_sniffth_c_sniff_and_or_t;
mcm	1:d4b35641a624	647
mcm	1:d4b35641a624	648
mcm	1:d4b35641a624	649	/* Bits 7 : SNIFF_MODE. */
mcm	1:d4b35641a624	650	typedef enum {
mcm	1:d4b35641a624	651	SNIFFTH_C_SNIFF_MODE_MASK = ( 1 << 7 ), /!< SNIFF_MODE Mask /
mcm	1:d4b35641a624	652	SNIFFTH_C_SNIFF_MODE_C2P_ENABLED = ( 0 << 7 ), /!< C2P Mode (Current to Previous): The delta count between current and previous samples is a moving window. The SNIFF logic uses the current sample and the immediate previous sample to compute a delta (default) /
mcm	1:d4b35641a624	653	SNIFFTH_C_SNIFF_MODE_C2B_ENABLED = ( 1 << 7 ) /!< C2B Mode (Current to Baseline): The delta count is generated from subtracting the current sample from the first sample stored when entering SNIFF mode /
mcm	1:d4b35641a624	654	} MC3635_sniffth_c_sniff_mode_t;
mcm	1:d4b35641a624	655
mcm	1:d4b35641a624	656
mcm	1:d4b35641a624	657
mcm	1:d4b35641a624	658	/**
mcm	1:d4b35641a624	659	* @brief SNIFF CONFIGURATION REGISTER
mcm	1:d4b35641a624	660	*
mcm	1:d4b35641a624	661	* This register selects which of the six shadow registers is being accessed in register 0x13, and controls settings of the SNIFF hardware.
mcm	1:d4b35641a624	662	*/
mcm	1:d4b35641a624	663	/* Bits 2:0 : SNIFF_THADR. */
mcm	1:d4b35641a624	664	typedef enum {
mcm	1:d4b35641a624	665	SNIFFCF_C_SNIFF_THADR_MASK = ( 0b111 << 0 ), /!< SNIFF_THADR Mask /
mcm	1:d4b35641a624	666	SNIFFCF_C_SNIFF_THADR_NONE = ( 0b000 << 0 ), /!< None /
mcm	1:d4b35641a624	667	SNIFFCF_C_SNIFF_THADR_SNIFF_THRESHOLD_X_AXIS = ( 0b001 << 0 ), /!< SNIFF Threshold, X-axis /
mcm	1:d4b35641a624	668	SNIFFCF_C_SNIFF_THADR_SNIFF_THRESHOLD_Y_AXIS = ( 0b010 << 0 ), /!< SNIFF Threshold, X-axis /
mcm	1:d4b35641a624	669	SNIFFCF_C_SNIFF_THADR_SNIFF_THRESHOLD_Z_AXIS = ( 0b011 << 0 ), /!< SNIFF Threshold, X-axis /
mcm	1:d4b35641a624	670	//SNIFFCF_C_SNIFF_THADR_NONE = ( 0b100 << 0 ), /!< None /
mcm	1:d4b35641a624	671	SNIFFCF_C_SNIFF_THADR_SNIFF_DETECTION_X_AXIS = ( 0b101 << 0 ), /!< SNIFF Detection Count, X-axis /
mcm	1:d4b35641a624	672	SNIFFCF_C_SNIFF_THADR_SNIFF_DETECTION_Y_AXIS = ( 0b110 << 0 ), /!< SNIFF Detection Count, X-axis /
mcm	1:d4b35641a624	673	SNIFFCF_C_SNIFF_THADR_SNIFF_DETECTION_Z_AXIS = ( 0b111 << 0 ) /!< SNIFF Detection Count, X-axis /
mcm	1:d4b35641a624	674	} MC3635_sniffcf_c_sniff_thadr_t;
mcm	1:d4b35641a624	675
mcm	1:d4b35641a624	676
mcm	1:d4b35641a624	677	/* Bits 3 : SNIFF_CNTEN. */
mcm	1:d4b35641a624	678	typedef enum {
mcm	1:d4b35641a624	679	SNIFFCF_C_SNIFF_CNTEN_MASK = ( 1 << 3 ), /!< SNIFF_CNTEN Mask /
mcm	1:d4b35641a624	680	SNIFFCF_C_SNIFF_CNTEN_DISABLED = ( 0 << 3 ), /!< Do not use SNIFF detection counters. (default) /
mcm	1:d4b35641a624	681	SNIFFCF_C_SNIFF_CNTEN_ENABLED = ( 1 << 3 ) /!< Enable SNIFF detection counts, required for valid SNIFF wakeup /
mcm	1:d4b35641a624	682	} MC3635_sniffcf_c_sniff_cnten_t;
mcm	1:d4b35641a624	683
mcm	1:d4b35641a624	684
mcm	1:d4b35641a624	685	/* Bits 6:4 : SNIFF_MUX. */
mcm	1:d4b35641a624	686	typedef enum {
mcm	1:d4b35641a624	687	SNIFFCF_C_SNIFF_MUX_MASK = ( 0b111 << 4 ), /!< SNIFF_MUX Mask /
mcm	1:d4b35641a624	688	SNIFFCF_C_SNIFF_MUX_DELTA_5_0 = ( 0b000 << 4 ), /!< DELTA[5:0] /
mcm	1:d4b35641a624	689	SNIFFCF_C_SNIFF_MUX_DELTA_6_1 = ( 0b001 << 4 ), /!< DELTA[6:1] /
mcm	1:d4b35641a624	690	SNIFFCF_C_SNIFF_MUX_DELTA_7_2 = ( 0b010 << 4 ), /!< DELTA[7:2] /
mcm	1:d4b35641a624	691	SNIFFCF_C_SNIFF_MUX_DELTA_8_3 = ( 0b011 << 4 ), /!< DELTA[8:3] /
mcm	1:d4b35641a624	692	SNIFFCF_C_SNIFF_MUX_DELTA_9_4 = ( 0b100 << 4 ), /!< DELTA[9:4] /
mcm	1:d4b35641a624	693	SNIFFCF_C_SNIFF_MUX_DELTA_10_5 = ( 0b101 << 4 ) /!< DELTA[10:5] /
mcm	1:d4b35641a624	694	} MC3635_sniffcf_c_sniff_mux_t;
mcm	1:d4b35641a624	695
mcm	1:d4b35641a624	696
mcm	1:d4b35641a624	697	/* Bits 7 : SNIFF_RESET. */
mcm	1:d4b35641a624	698	typedef enum {
mcm	1:d4b35641a624	699	SNIFFCF_C_SNIFF_RESET_MASK = ( 1 << 7 ), /!< SNIFF_RESET Mask /
mcm	1:d4b35641a624	700	SNIFFCF_C_SNIFF_RESET_NOT_APPLIED = ( 0 << 7 ), /!< SNIFF block reset is not applied (default). /
mcm	1:d4b35641a624	701	SNIFFCF_C_SNIFF_RESET_APPLIED = ( 1 << 7 ) /!< SNIFF block reset is applied /
mcm	1:d4b35641a624	702	} MC3635_sniffcf_c_sniff_reset_t;
mcm	1:d4b35641a624	703
mcm	1:d4b35641a624	704
mcm	1:d4b35641a624	705
mcm	1:d4b35641a624	706	/**
mcm	1:d4b35641a624	707	* @brief RANGE AND RESOLUTION CONTROL REGISTER
mcm	1:d4b35641a624	708	*
mcm	1:d4b35641a624	709	* The RANGE register sets the resolution and range options for the accelerometer. All numbers are sign-extended, 2's complement format.
mcm	1:d4b35641a624	710	* All results are reported in registers 0x02 to 0x07. When the FIFO is enabled, only 6 to 12-bit resolutions are supported due to the
mcm	1:d4b35641a624	711	* 12-bit width of the FIFO.
mcm	1:d4b35641a624	712	*/
mcm	1:d4b35641a624	713	/* Bits 2:0 : RES. */
mcm	1:d4b35641a624	714	typedef enum {
mcm	1:d4b35641a624	715	RANGE_C_RES_MASK = ( 0b111 << 0 ), /!< RES Mask /
mcm	1:d4b35641a624	716	RANGE_C_RES_6_BITS = ( 0b000 << 0 ), /!< 6 bits /
mcm	1:d4b35641a624	717	RANGE_C_RES_7_BITS = ( 0b001 << 0 ), /!< 7 bits /
mcm	1:d4b35641a624	718	RANGE_C_RES_8_BITS = ( 0b010 << 0 ), /!< 8 bits /
mcm	1:d4b35641a624	719	RANGE_C_RES_10_BITS = ( 0b011 << 0 ), /!< 10 bits /
mcm	1:d4b35641a624	720	RANGE_C_RES_12_BITS = ( 0b100 << 0 ), /!< 12 bits /
mcm	1:d4b35641a624	721	RANGE_C_RES_14_BITS = ( 0b101 << 0 ) /!< 14 bits (only 12-bits if FIFO enabled) /
mcm	1:d4b35641a624	722	} MC3635_range_c_res_t;
mcm	1:d4b35641a624	723
mcm	1:d4b35641a624	724
mcm	1:d4b35641a624	725	/* Bits 6:4 : RANGE. */
mcm	1:d4b35641a624	726	typedef enum {
mcm	1:d4b35641a624	727	RANGE_C_RANGE_MASK = ( 0b111 << 4 ), /!< RANGE Mask /
mcm	1:d4b35641a624	728	RANGE_C_RANGE_2G = ( 0b000 << 4 ), /!< ±2g /
mcm	1:d4b35641a624	729	RANGE_C_RANGE_4G = ( 0b001 << 4 ), /!< ±4g /
mcm	1:d4b35641a624	730	RANGE_C_RANGE_8G = ( 0b010 << 4 ), /!< ±8g /
mcm	1:d4b35641a624	731	RANGE_C_RANGE_16G = ( 0b011 << 4 ), /!< ±16g /
mcm	1:d4b35641a624	732	RANGE_C_RANGE_12G = ( 0b100 << 4 ) /!< ±12g /
mcm	1:d4b35641a624	733	} MC3635_range_c_range_t;
mcm	1:d4b35641a624	734
mcm	1:d4b35641a624	735
mcm	1:d4b35641a624	736
mcm	1:d4b35641a624	737	/**
mcm	1:d4b35641a624	738	* @brief FIFO CONTROL REGISTER
mcm	1:d4b35641a624	739	*
mcm	1:d4b35641a624	740	* This register selects the FIFO threshold level, operation mode, FIFO reset and enable. With the exception of FIFO_RESET,
mcm	1:d4b35641a624	741	* the FIFO_EN bit must be '1' for any FIFO interrupts, thresholds, or modes to be enabled. The FIFO flags in register 0x08 will
mcm	1:d4b35641a624	742	* continue to report FIFO defaults even if the FIFO_EN is '0'.
mcm	1:d4b35641a624	743	*/
mcm	1:d4b35641a624	744	/* Bits 4:0 : FIFO_TH. */
mcm	1:d4b35641a624	745	typedef enum {
mcm	1:d4b35641a624	746	FIFO_C_FIFO_TH_MASK = ( 0b11111 << 0 ) /!< The FIFO threshold level selects the number of samples in the FIFO for different FIFO events. The threshold value may be 1 to 31 (00001 to 11111) /
mcm	1:d4b35641a624	747	} MC3635_fifo_c_fifo_th_t;
mcm	1:d4b35641a624	748
mcm	1:d4b35641a624	749
mcm	1:d4b35641a624	750	/* Bit 5 : FIFO_MODE. */
mcm	1:d4b35641a624	751	typedef enum {
mcm	1:d4b35641a624	752	FIFO_C_FIFO_MODE_MASK = ( 1 << 5 ), /!< FIFO_MODE Mask /
mcm	1:d4b35641a624	753	FIFO_C_FIFO_MODE_NORMAL = ( 0 << 5 ), /!< Normal operation, the FIFO continues to accept new sample data as long as there is space remaining (default) /
mcm	1:d4b35641a624	754	FIFO_C_FIFO_MODE_WATERMARK = ( 1 << 5 ) /!< Watermark, once the amount of samples in the FIFO reaches or exceeds the threshold level, the FIFO stops accepting new sample data. Any additional sample data is 'dropped' /
mcm	1:d4b35641a624	755	} MC3635_fifo_c_fifo_mode_t;
mcm	1:d4b35641a624	756
mcm	1:d4b35641a624	757
mcm	1:d4b35641a624	758	/* Bit 6 : FIFO_EN. */
mcm	1:d4b35641a624	759	typedef enum {
mcm	1:d4b35641a624	760	FIFO_C_FIFO_EN_MASK = ( 1 << 6 ), /!< FIFO_EN Mask /
mcm	1:d4b35641a624	761	FIFO_C_FIFO_EN_DISABLED = ( 0 << 6 ), /!< No FIFO operation, sample data written directly to output registers /
mcm	1:d4b35641a624	762	FIFO_C_FIFO_EN_ENABLED = ( 1 << 6 ) /!< FIFO enabled, all sample data written to FIFO write port if there is room. The FIFO write clock is controlled by this enable, resulting in higher dynamic power /
mcm	1:d4b35641a624	763	} MC3635_fifo_c_fifo_en_t;
mcm	1:d4b35641a624	764
mcm	1:d4b35641a624	765
mcm	1:d4b35641a624	766	/* Bit 7 : FIFO_RESET. */
mcm	1:d4b35641a624	767	typedef enum {
mcm	1:d4b35641a624	768	FIFO_C_FIFO_RESET_MASK = ( 1 << 7 ), /!< FIFO_RESET Mask /
mcm	1:d4b35641a624	769	FIFO_C_FIFO_RESET_DISABLED = ( 0 << 7 ), /!< FIFO reset is disabled, normal operation (default) /
mcm	1:d4b35641a624	770	FIFO_C_FIFO_RESET_ENABLED = ( 1 << 7 ) /!< FIFO read and write pointers are cleared, FIFO contents returned to 0 /
mcm	1:d4b35641a624	771	} MC3635_fifo_c_fifo_reset_t;
mcm	1:d4b35641a624	772
mcm	1:d4b35641a624	773
mcm	1:d4b35641a624	774
mcm	1:d4b35641a624	775	/**
mcm	1:d4b35641a624	776	* @brief INTERRUPT CONTROL REGISTER
mcm	1:d4b35641a624	777	*
mcm	1:d4b35641a624	778	*/
mcm	1:d4b35641a624	779	/* Bit 0 : IPP. */
mcm	1:d4b35641a624	780	typedef enum {
mcm	1:d4b35641a624	781	INTR_C_IPP_MASK = ( 1 << 0 ), /!< IPP Mask /
mcm	1:d4b35641a624	782	INTR_C_IPP_OPEN_DRAIN_MODE = ( 0 << 0 ), /!< INTN pin is configured for open-drain mode (external pull-up to VDDIO required) (default) /
mcm	1:d4b35641a624	783	INTR_C_IPP_PUSH_PULL_MODE = ( 1 << 0 ) /!< INTN pin is configured for active drive or 'push-pull' mode. Drive level is to VDDIO /
mcm	1:d4b35641a624	784	} MC3635_intr_c_ipp_t;
mcm	1:d4b35641a624	785
mcm	1:d4b35641a624	786
mcm	1:d4b35641a624	787	/* Bit 1 : IAH. */
mcm	1:d4b35641a624	788	typedef enum {
mcm	1:d4b35641a624	789	INTR_C_IAH_MASK = ( 1 << 1 ), /!< IAH Mask /
mcm	1:d4b35641a624	790	INTR_C_IAH_ACTIVE_LOW = ( 0 << 1 ), /!< Interrupt request is active low (default). /
mcm	1:d4b35641a624	791	INTR_C_IAH_ACTIVE_HIGH = ( 1 << 1 ) /!< Interrupt request is active high /
mcm	1:d4b35641a624	792	} MC3635_intr_c_iah_t;
mcm	1:d4b35641a624	793
mcm	1:d4b35641a624	794
mcm	1:d4b35641a624	795	/* Bit 2 : INT_WAKE. */
mcm	1:d4b35641a624	796	typedef enum {
mcm	1:d4b35641a624	797	INTR_C_INT_WAKE_MASK = ( 1 << 2 ), /!< INT_WAKE Mask /
mcm	1:d4b35641a624	798	INTR_C_INT_WAKE_DISABLED = ( 0 << 2 ), /!< No interrupt is generated when SNIFF activity is detected and the device auto-transitions to CWAKE mode (default) /
mcm	1:d4b35641a624	799	INTR_C_INT_WAKE_ENABLED = ( 1 << 2 ) /!< Generate an interrupt when activity is detected in SNIFF mode and the device auto-transitions to CWAKE mode. /
mcm	1:d4b35641a624	800	} MC3635_intr_c_int_wake_t;
mcm	1:d4b35641a624	801
mcm	1:d4b35641a624	802
mcm	1:d4b35641a624	803	/* Bit 3 : INT_ACQ. */
mcm	1:d4b35641a624	804	typedef enum {
mcm	1:d4b35641a624	805	INTR_C_INT_ACQ_MASK = ( 1 << 3 ), /!< INT_ACQ Mask /
mcm	1:d4b35641a624	806	INTR_C_INT_ACQ_DISABLED = ( 0 << 3 ), /!< No interrupt generated when new sample data is acquired (default) /
mcm	1:d4b35641a624	807	INTR_C_INT_ACQ_ENABLED = ( 1 << 3 ) /!< Generate an interrupt when new sample data is acquired (applies to new data written to output registers or FIFO). This enable is paired with the NEW_DATA flag in register 0x08 /
mcm	1:d4b35641a624	808	} MC3635_intr_c_int_acq_t;
mcm	1:d4b35641a624	809
mcm	1:d4b35641a624	810
mcm	1:d4b35641a624	811	/* Bit 4 : INT_FIFO_EMPTY. */
mcm	1:d4b35641a624	812	typedef enum {
mcm	1:d4b35641a624	813	INTR_C_INT_FIFO_EMPTY_MASK = ( 1 << 4 ), /!< INT_FIFO_EMPTY Mask /
mcm	1:d4b35641a624	814	INTR_C_INT_FIFO_EMPTY_DISABLED = ( 0 << 4 ), /!< No interrupt is generated when the FIFO is empty or completely drained of sample data (default) /
mcm	1:d4b35641a624	815	INTR_C_INT_FIFO_EMPTY_ENABLED = ( 1 << 4 ) /!< Generate an interrupt when the FIFO is empty. This interrupt is paired with the FIFO_EMPTY flag in register 0x08. Note that this interrupt is independent of the FIFO threshold level, and will only activate when the FIFO sample count has reached a value of 0 /
mcm	1:d4b35641a624	816	} MC3635_intr_c_int_fifo_empty_t;
mcm	1:d4b35641a624	817
mcm	1:d4b35641a624	818
mcm	1:d4b35641a624	819	/* Bit 5 : INT_FIFO_FULL. */
mcm	1:d4b35641a624	820	typedef enum {
mcm	1:d4b35641a624	821	INTR_C_INT_FIFO_FULL_MASK = ( 1 << 5 ), /!< INT_FIFO_FULL Mask /
mcm	1:d4b35641a624	822	INTR_C_INT_FIFO_FULL_DISABLED = ( 0 << 5 ), /!< No interrupt is generated when the FIFO is empty or completely filled of sample data (default) /
mcm	1:d4b35641a624	823	INTR_C_INT_FIFO_FULL_ENABLED = ( 1 << 5 ) /!< Generate an interrupt when the FIFO is full. This interrupt is paired with the FIFO_FULL flag in register 0x08. Note that this interrupt is independent of the FIFO threshold level, and will only activate when the FIFO sample count has reached a value of 32 /
mcm	1:d4b35641a624	824	} MC3635_intr_c_int_fifo_full_t;
mcm	1:d4b35641a624	825
mcm	1:d4b35641a624	826
mcm	1:d4b35641a624	827	/* Bit 6 : INT_FIFO_THRESH. */
mcm	1:d4b35641a624	828	typedef enum {
mcm	1:d4b35641a624	829	INTR_C_INT_FIFO_THRESH_MASK = ( 1 << 6 ), /!< INT_FIFO_THRESH Mask /
mcm	1:d4b35641a624	830	INTR_C_INT_FIFO_THRESH_DISABLED = ( 0 << 6 ), /!< No interrupt is generated when the FIFO threshold level is reached (default) /
mcm	1:d4b35641a624	831	INTR_C_INT_FIFO_THRESH_ENABLED = ( 1 << 6 ) /!< Generate an interrupt when the FIFO threshold level is reached /
mcm	1:d4b35641a624	832	} MC3635_intr_c_int_fifo_thresh_t;
mcm	1:d4b35641a624	833
mcm	1:d4b35641a624	834
mcm	1:d4b35641a624	835	/* Bit 7 : INT_SWAKE. */
mcm	1:d4b35641a624	836	typedef enum {
mcm	1:d4b35641a624	837	INTR_C_INT_SWAKE_MASK = ( 1 << 7 ), /!< INT_SWAKE Mask /
mcm	1:d4b35641a624	838	INTR_C_INT_SWAKE_DISABLED = ( 0 << 7 ), /!< No interrupt generated when SNIFF activity is detected (default) /
mcm	1:d4b35641a624	839	INTR_C_INT_SWAKE_ENABLED = ( 1 << 7 ) /!< Generate an interrupt when SNIFF activity is detected /
mcm	1:d4b35641a624	840	} MC3635_intr_c_int_fifo_swake_t;
mcm	1:d4b35641a624	841
mcm	1:d4b35641a624	842
mcm	1:d4b35641a624	843
mcm	1:d4b35641a624	844	/**
mcm	1:d4b35641a624	845	* @brief INITIALIZATION REGISTER 3
mcm	1:d4b35641a624	846	*
mcm	1:d4b35641a624	847	* Software must write a fixed value to this register immediately after power-up or reset
mcm	1:d4b35641a624	848	*/
mcm	1:d4b35641a624	849	/* Bits 7:0 : INIT_3. */
mcm	1:d4b35641a624	850	typedef enum {
mcm	1:d4b35641a624	851	INIT_3_INT_3_FIXED_VALUE = 0 /!< INIT_3 fixed value /
mcm	1:d4b35641a624	852	} MC3635_init_3_int_3t;
mcm	1:d4b35641a624	853
mcm	1:d4b35641a624	854
mcm	1:d4b35641a624	855
mcm	1:d4b35641a624	856	/**
mcm	1:d4b35641a624	857	* @brief POWER MODE CONTROL REGISTER
mcm	1:d4b35641a624	858	*
mcm	1:d4b35641a624	859	* This register selects the power setting for CWAKE, SWAKE and SNIFF modes.
mcm	1:d4b35641a624	860	*/
mcm	1:d4b35641a624	861	/* Bits 2:0 : CSPM. */
mcm	1:d4b35641a624	862	typedef enum {
mcm	1:d4b35641a624	863	PMCR_CSPM_MASK = ( 0b111 << 0 ), /!< CSPM Mask /
mcm	1:d4b35641a624	864	PMCR_CSPM_LOW_POWER_MODE = ( 0b000 << 0 ), /!< Low Power Mode (nominal noise levels) (default) /
mcm	1:d4b35641a624	865	PMCR_CSPM_ULTRA_LOW_POWER_MODE = ( 0b011 << 0 ), /!< Ultra-Low Power Mode (highest noise levels) /
mcm	1:d4b35641a624	866	PMCR_CSPM_PRECISION_MODE = ( 0b100 << 0 ) /!< Precision Mode (lowest noise levels) /
mcm	1:d4b35641a624	867	} MC3635_pmcr_cspm_t;
mcm	1:d4b35641a624	868
mcm	1:d4b35641a624	869
mcm	1:d4b35641a624	870	/* Bits 6:4 : SPM. */
mcm	1:d4b35641a624	871	typedef enum {
mcm	1:d4b35641a624	872	PMCR_SPM_MASK = ( 0b111 << 4 ), /!< SPM Mask /
mcm	1:d4b35641a624	873	PMCR_SPM_LOW_POWER_MODE = ( 0b000 << 4 ), /!< Low Power Mode (nominal noise levels) (default) /
mcm	1:d4b35641a624	874	PMCR_SPM_ULTRA_LOW_POWER_MODE = ( 0b011 << 4 ), /!< Ultra-Low Power Mode (highest noise levels) /
mcm	1:d4b35641a624	875	PMCR_SPM_PRECISION_MODE = ( 0b100 << 4 ) /!< Precision Mode (lowest noise levels) /
mcm	1:d4b35641a624	876	} MC3635_pmcr_spm_t;
mcm	1:d4b35641a624	877
mcm	1:d4b35641a624	878
mcm	1:d4b35641a624	879	/* Bit 7 : SPI_HS_EN. */
mcm	1:d4b35641a624	880	typedef enum {
mcm	1:d4b35641a624	881	PMCR_SPI_HS_EN_MASK = ( 1 << 7 ), /!< SPI_HS_EN Mask /
mcm	1:d4b35641a624	882	PMCR_SPI_HS_EN_DISABLED = ( 0 << 7 ), /!< This bit will always return a '0' when read. Software must keep track of the state of this bit /
mcm	1:d4b35641a624	883	PMCR_SPI_HS_EN_ENABLED = ( 1 << 7 ) /!< SPI High-Speed Enable /
mcm	1:d4b35641a624	884	} MC3635_pmcr_spi_hs_en_t;
mcm	1:d4b35641a624	885
mcm	1:d4b35641a624	886
mcm	1:d4b35641a624	887
mcm	1:d4b35641a624	888	/**
mcm	1:d4b35641a624	889	* @brief DRIVE MOTION X REGISTER
mcm	1:d4b35641a624	890	*
mcm	1:d4b35641a624	891	* This register controls the test mode which moves the sensor in the X axis direction and initializes specific hardware bits.
mcm	1:d4b35641a624	892	*/
mcm	1:d4b35641a624	893	/* Bit 2 : DPX. */
mcm	1:d4b35641a624	894	typedef enum {
mcm	1:d4b35641a624	895	DMX_DPX_MASK = ( 1 << 2 ), /!< DPX Mask /
mcm	1:d4b35641a624	896	DMX_DPX_DISABLED = ( 0 << 2 ), /!< Disabled (default) /
mcm	1:d4b35641a624	897	DMX_DPX_ENABLED = ( 1 << 2 ) /!< Move the sensor in X Positive direction /
mcm	1:d4b35641a624	898	} MC3635_dmx_dpx_t;
mcm	1:d4b35641a624	899
mcm	1:d4b35641a624	900
mcm	1:d4b35641a624	901	/* Bit 3 : DNX. */
mcm	1:d4b35641a624	902	typedef enum {
mcm	1:d4b35641a624	903	DMX_DNX_MASK = ( 1 << 3 ), /!< DNX Mask /
mcm	1:d4b35641a624	904	DMX_DNX_DISABLED = ( 0 << 3 ), /!< Disabled (default) /
mcm	1:d4b35641a624	905	DMX_DNX_ENABLED = ( 1 << 3 ) /!< Move the sensor in X Negative direction /
mcm	1:d4b35641a624	906	} MC3635_dmx_dpnx_t;
mcm	1:d4b35641a624	907
mcm	1:d4b35641a624	908
mcm	1:d4b35641a624	909
mcm	1:d4b35641a624	910	/**
mcm	1:d4b35641a624	911	* @brief DRIVE MOTION Y REGISTER
mcm	1:d4b35641a624	912	*
mcm	1:d4b35641a624	913	* This register controls the test mode which moves the sensor in the Y axis direction and initializes specific hardware bits.
mcm	1:d4b35641a624	914	*/
mcm	1:d4b35641a624	915	/* Bit 2 : DPY. */
mcm	1:d4b35641a624	916	typedef enum {
mcm	1:d4b35641a624	917	DMY_DPX_MASK = ( 1 << 2 ), /!< DPY Mask /
mcm	1:d4b35641a624	918	DMY_DPX_DISABLED = ( 0 << 2 ), /!< Disabled (default) /
mcm	1:d4b35641a624	919	DMY_DPX_ENABLED = ( 1 << 2 ) /!< Move the sensor in Y Positive direction /
mcm	1:d4b35641a624	920	} MC3635_dmy_dpy_t;
mcm	1:d4b35641a624	921
mcm	1:d4b35641a624	922
mcm	1:d4b35641a624	923	/* Bit 3 : DNY. */
mcm	1:d4b35641a624	924	typedef enum {
mcm	1:d4b35641a624	925	DMY_DNY_MASK = ( 1 << 3 ), /!< DNY Mask /
mcm	1:d4b35641a624	926	DMY_DNY_DISABLED = ( 0 << 3 ), /!< Disabled (default) /
mcm	1:d4b35641a624	927	DMY_DNY_ENABLED = ( 1 << 3 ) /!< Move the sensor in Y Negative direction /
mcm	1:d4b35641a624	928	} MC3635_dmy_dpny_t;
mcm	1:d4b35641a624	929
mcm	1:d4b35641a624	930
mcm	1:d4b35641a624	931
mcm	1:d4b35641a624	932	/**
mcm	1:d4b35641a624	933	* @brief DRIVE MOTION Z REGISTER
mcm	1:d4b35641a624	934	*
mcm	1:d4b35641a624	935	* This register controls the test mode which moves the sensor in the Z axis direction.
mcm	1:d4b35641a624	936	*/
mcm	1:d4b35641a624	937	/* Bit 2 : DPZ. */
mcm	1:d4b35641a624	938	typedef enum {
mcm	1:d4b35641a624	939	DMZ_DPZ_MASK = ( 1 << 2 ), /!< DPZ Mask /
mcm	1:d4b35641a624	940	DMZ_DPZ_DISABLED = ( 0 << 2 ), /!< Disabled (default) /
mcm	1:d4b35641a624	941	DMZ_DPZ_ENABLED = ( 1 << 2 ) /!< Move the sensor in Z Positive direction /
mcm	1:d4b35641a624	942	} MC3635_dmz_dpz_t;
mcm	1:d4b35641a624	943
mcm	1:d4b35641a624	944
mcm	1:d4b35641a624	945	/* Bit 3 : DNZ. */
mcm	1:d4b35641a624	946	typedef enum {
mcm	1:d4b35641a624	947	DMZ_DNZ_MASK = ( 1 << 3 ), /!< DNZ Mask /
mcm	1:d4b35641a624	948	DMZ_DNZ_DISABLED = ( 0 << 3 ), /!< Disabled (default) /
mcm	1:d4b35641a624	949	DMZ_DNZ_ENABLED = ( 1 << 3 ) /!< Move the sensor in Z Negative direction /
mcm	1:d4b35641a624	950	} MC3635_dmz_dpnz_t;
mcm	1:d4b35641a624	951
mcm	1:d4b35641a624	952
mcm	1:d4b35641a624	953
mcm	1:d4b35641a624	954	/**
mcm	1:d4b35641a624	955	* @brief RESET REGISTER
mcm	1:d4b35641a624	956	*
mcm	1:d4b35641a624	957	* This register can be used to reset the device. Anytime there is a reset to the device, a POR event, or a
mcm	1:d4b35641a624	958	* power cycle the SPI 3-wire configuration will reset to 4-wire mode.
mcm	1:d4b35641a624	959	*/
mcm	1:d4b35641a624	960	/* Bit 6 : RESET. */
mcm	1:d4b35641a624	961	typedef enum {
mcm	1:d4b35641a624	962	RESET_RESET_MASK = ( 1 << 6 ), /!< RESET Mask /
mcm	1:d4b35641a624	963	RESET_RESET_NORMAL_OPERATION = ( 0 << 6 ), /!< Normal operation (default) /
mcm	1:d4b35641a624	964	RESET_RESET_FORCE_POWER_ON_RESET = ( 1 << 6 ) /!< Force a power-on-reset (POR) sequence /
mcm	1:d4b35641a624	965	} MC3635_reset_reset_t;
mcm	1:d4b35641a624	966
mcm	1:d4b35641a624	967
mcm	1:d4b35641a624	968	/* Bit 7 : RELOAD. */
mcm	1:d4b35641a624	969	typedef enum {
mcm	1:d4b35641a624	970	RESET_RELOAD_MASK = ( 1 << 7 ), /!< RELOAD Mask /
mcm	1:d4b35641a624	971	RESET_RELOAD_NORMAL_OPERATION = ( 0 << 7 ), /!< Normal operation (default) /
mcm	1:d4b35641a624	972	RESET_RELOAD_RELOAD_REGISTER_FROM_OTP = ( 1 << 7 ) /!< Reloads the registers from OTP /
mcm	1:d4b35641a624	973	} MC3635_reset_reload_t;
mcm	1:d4b35641a624	974
mcm	1:d4b35641a624	975
mcm	1:d4b35641a624	976
mcm	1:d4b35641a624	977	/**
mcm	1:d4b35641a624	978	* @brief INITIALIZATION REGISTER 2
mcm	1:d4b35641a624	979	*
mcm	1:d4b35641a624	980	* Software must write a fixed value to this register immediately after power-up or reset
mcm	1:d4b35641a624	981	*/
mcm	1:d4b35641a624	982	/* Bits 7:0 : INIT_2. */
mcm	1:d4b35641a624	983	typedef enum {
mcm	1:d4b35641a624	984	INIT_2_INT_2_FIXED_VALUE = 0 /!< INIT_2 fixed value /
mcm	1:d4b35641a624	985	} MC3635_init_2_int_2_t;
mcm	1:d4b35641a624	986
mcm	1:d4b35641a624	987
mcm	1:d4b35641a624	988
mcm	1:d4b35641a624	989	/**
mcm	1:d4b35641a624	990	* @brief TRIGGER COUNT REGISTER
mcm	1:d4b35641a624	991	*
mcm	1:d4b35641a624	992	* This register selects the number of samples to be taken after the one-shot trigger is started
mcm	1:d4b35641a624	993	*/
mcm	1:d4b35641a624	994	/* Bits 7:0 : TRIGC. */
mcm	1:d4b35641a624	995	typedef enum {
mcm	1:d4b35641a624	996	TRIGC_MASK = 0xFF /!< TRIGC Mask /
mcm	1:d4b35641a624	997	} MC3635_trigc_t;
mcm	1:d4b35641a624	998
mcm	1:d4b35641a624	999
mcm	1:d4b35641a624	1000
mcm	1:d4b35641a624	1001
mcm	1:d4b35641a624	1002	/**
mcm	1:d4b35641a624	1003	* @brief X-AXIS OFFSET REGISTERS
mcm	1:d4b35641a624	1004	*
mcm	1:d4b35641a624	1005	* This register contains a signed 2's complement 15-bit value applied as an offset adjustment to the output
mcm	1:d4b35641a624	1006	* of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each
mcm	1:d4b35641a624	1007	* chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software.
mcm	1:d4b35641a624	1008	*/
mcm	1:d4b35641a624	1009	/* Bits 7:0 : XOFFL. */
mcm	1:d4b35641a624	1010	typedef enum {
mcm	1:d4b35641a624	1011	XOFFL_MASK = 0xFF /!< XOFFL Mask /
mcm	1:d4b35641a624	1012	} MC3635_x_axis_offset_xoffl_t;
mcm	1:d4b35641a624	1013
mcm	1:d4b35641a624	1014
mcm	1:d4b35641a624	1015	/* Bits 7:0 : XOFFH. */
mcm	1:d4b35641a624	1016	typedef enum {
mcm	1:d4b35641a624	1017	XOFFH_MASK = ( 0b01111111 << 0 ) /!< XOFFH Mask /
mcm	1:d4b35641a624	1018	} MC3635_x_axis_offset_xoffh_t;
mcm	1:d4b35641a624	1019
mcm	1:d4b35641a624	1020
mcm	1:d4b35641a624	1021
mcm	1:d4b35641a624	1022	/**
mcm	1:d4b35641a624	1023	* @brief Y-AXIS OFFSET REGISTERS
mcm	1:d4b35641a624	1024	*
mcm	1:d4b35641a624	1025	* This register contains a signed 2's complement 15-bit value applied as an offset adjustment to the output
mcm	1:d4b35641a624	1026	* of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each
mcm	1:d4b35641a624	1027	* chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software.
mcm	1:d4b35641a624	1028	*/
mcm	1:d4b35641a624	1029	/* Bits 7:0 : YOFFL. */
mcm	1:d4b35641a624	1030	typedef enum {
mcm	1:d4b35641a624	1031	YOFFL_MASK = 0xFF /!< YOFFL Mask /
mcm	1:d4b35641a624	1032	} MC3635_y_axis_offset_yoffl_t;
mcm	1:d4b35641a624	1033
mcm	1:d4b35641a624	1034
mcm	1:d4b35641a624	1035	/* Bits 7:0 : YOFFH. */
mcm	1:d4b35641a624	1036	typedef enum {
mcm	1:d4b35641a624	1037	YOFFH_MASK = ( 0b01111111 << 0 ) /!< YOFFH Mask /
mcm	1:d4b35641a624	1038	} MC3635_y_axis_offset_yoffh_t;
mcm	1:d4b35641a624	1039
mcm	1:d4b35641a624	1040
mcm	1:d4b35641a624	1041
mcm	1:d4b35641a624	1042	/**
mcm	1:d4b35641a624	1043	* @brief Z-AXIS OFFSET REGISTERS
mcm	1:d4b35641a624	1044	*
mcm	1:d4b35641a624	1045	* This register contains a signed 2's complement 15-bit value applied as an offset adjustment to the output
mcm	1:d4b35641a624	1046	* of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each
mcm	1:d4b35641a624	1047	* chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software.
mcm	1:d4b35641a624	1048	*/
mcm	1:d4b35641a624	1049	/* Bits 7:0 : ZOFFL. */
mcm	1:d4b35641a624	1050	typedef enum {
mcm	1:d4b35641a624	1051	ZOFFL_MASL = 0xFF /!< ZOFFL Mask /
mcm	1:d4b35641a624	1052	} MC3635_z_axis_offset_zoffl_t;
mcm	1:d4b35641a624	1053
mcm	1:d4b35641a624	1054
mcm	1:d4b35641a624	1055	/* Bits 7:0 : ZOFFH. */
mcm	1:d4b35641a624	1056	typedef enum {
mcm	1:d4b35641a624	1057	ZOFFH_MASK = ( 0b01111111 << 0 ) /!< ZOFFH Mask /
mcm	1:d4b35641a624	1058	} MC3635_z_axis_offset_zoffh_t;
mcm	1:d4b35641a624	1059
mcm	1:d4b35641a624	1060
mcm	1:d4b35641a624	1061
mcm	1:d4b35641a624	1062	/**
mcm	1:d4b35641a624	1063	* @brief X-AXIS GAIN REGISTERS
mcm	1:d4b35641a624	1064	*
mcm	1:d4b35641a624	1065	* The gain value is an unsigned 9-bit number.
mcm	1:d4b35641a624	1066	*/
mcm	1:d4b35641a624	1067	/* Bits 7:0 : GAIN LSB. */
mcm	1:d4b35641a624	1068	typedef enum {
mcm	1:d4b35641a624	1069	XGAINL_GAIN_MASK = 0xFF /!< XGAINL GAIN Mask /
mcm	1:d4b35641a624	1070	} MC3635_x_axis_xgainl_t;
mcm	1:d4b35641a624	1071
mcm	1:d4b35641a624	1072
mcm	1:d4b35641a624	1073	/* Bits 7:0 : GAIN HSB. */
mcm	1:d4b35641a624	1074	typedef enum {
mcm	1:d4b35641a624	1075	XGAINH_GAIN_MASK = ( 1 << 7 ) /!< XGAINH GAIN Mask /
mcm	1:d4b35641a624	1076	} MC3635_x_axis_xgainh_t;
mcm	1:d4b35641a624	1077
mcm	1:d4b35641a624	1078
mcm	1:d4b35641a624	1079
mcm	1:d4b35641a624	1080	/**
mcm	1:d4b35641a624	1081	* @brief Y-AXIS GAIN REGISTERS
mcm	1:d4b35641a624	1082	*
mcm	1:d4b35641a624	1083	* The gain value is an unsigned 9-bit number.
mcm	1:d4b35641a624	1084	*/
mcm	1:d4b35641a624	1085	/* Bits 7:0 : GAIN LSB. */
mcm	1:d4b35641a624	1086	typedef enum {
mcm	1:d4b35641a624	1087	YGAINL_GAIN_MASK = 0xFF /!< YGAINL GAIN Mask /
mcm	1:d4b35641a624	1088	} MC3635_y_axis_ygainl_t;
mcm	1:d4b35641a624	1089
mcm	1:d4b35641a624	1090
mcm	1:d4b35641a624	1091	/* Bits 7:0 : GAIN HSB. */
mcm	1:d4b35641a624	1092	typedef enum {
mcm	1:d4b35641a624	1093	YGAINH_GAIN_MASK = ( 1 << 7 ) /!< YGAINH GAIN Mask /
mcm	1:d4b35641a624	1094	} MC3635_y_axis_ygainh_t;
mcm	1:d4b35641a624	1095
mcm	1:d4b35641a624	1096
mcm	1:d4b35641a624	1097
mcm	1:d4b35641a624	1098	/**
mcm	1:d4b35641a624	1099	* @brief Z-AXIS GAIN REGISTERS
mcm	1:d4b35641a624	1100	*
mcm	1:d4b35641a624	1101	* The gain value is an unsigned 9-bit number.
mcm	1:d4b35641a624	1102	*/
mcm	1:d4b35641a624	1103	/* Bits 7:0 : GAIN LSB. */
mcm	1:d4b35641a624	1104	typedef enum {
mcm	1:d4b35641a624	1105	ZGAINL_GAIN_MASK = 0xFF /!< ZGAINL GAIN Mask /
mcm	1:d4b35641a624	1106	} MC3635_z_axis_zgainl_t;
mcm	1:d4b35641a624	1107
mcm	1:d4b35641a624	1108
mcm	1:d4b35641a624	1109	/* Bits 7:0 : GAIN HSB. */
mcm	1:d4b35641a624	1110	typedef enum {
mcm	1:d4b35641a624	1111	ZGAINH_GAIN_MASK = ( 1 << 7 ) /!< ZGAINH GAIN Mask /
mcm	1:d4b35641a624	1112	} MC3635_z_axis_zgainh_t;
mcm	1:d4b35641a624	1113
mcm	1:d4b35641a624	1114
mcm	1:d4b35641a624	1115
mcm	1:d4b35641a624	1116
mcm	1:d4b35641a624	1117
mcm	1:d4b35641a624	1118	/**
mcm	1:d4b35641a624	1119	* @brief POWER MODE FOR SNIFF, CWAKE and SWAKE
mcm	1:d4b35641a624	1120	*
mcm	1:d4b35641a624	1121	*/
mcm	1:d4b35641a624	1122	typedef enum {
mcm	1:d4b35641a624	1123	ULTRA_LOW_POWER_MODE = 0b011, /!< MODE: ULTRA-LOW POWER MODE /
mcm	1:d4b35641a624	1124	LOW_POWER_MODE = 0b000, /!< MODE: LOW POWER MODE /
mcm	1:d4b35641a624	1125	PRECISION = 0b100 /!< MODE: PRECISION /
mcm	1:d4b35641a624	1126	} MC3635_power_mode_t;
mcm	1:d4b35641a624	1127
mcm	1:d4b35641a624	1128
mcm	1:d4b35641a624	1129	/**
mcm	1:d4b35641a624	1130	* @brief SAMPLE RATE FOR SNIFF, CWAKE and SWAKE
mcm	1:d4b35641a624	1131	*
mcm	1:d4b35641a624	1132	*/
mcm	1:d4b35641a624	1133	typedef enum {
mcm	1:d4b35641a624	1134	ODR_0 = 0b0000, /!< ODR: 0b0000 /
mcm	1:d4b35641a624	1135	ODR_1 = 0b0001, /!< ODR: 0b0001 /
mcm	1:d4b35641a624	1136	ODR_2 = 0b0010, /!< ODR: 0b0010 /
mcm	1:d4b35641a624	1137	ODR_3 = 0b0011, /!< ODR: 0b0011 /
mcm	1:d4b35641a624	1138	ODR_4 = 0b0100, /!< ODR: 0b0100 /
mcm	1:d4b35641a624	1139	ODR_5 = 0b0101, /!< ODR: 0b0101 /
mcm	1:d4b35641a624	1140	ODR_6 = 0b0110, /!< ODR: 0b0110 /
mcm	1:d4b35641a624	1141	ODR_7 = 0b0111, /!< ODR: 0b0111 /
mcm	1:d4b35641a624	1142	ODR_8 = 0b1000, /!< ODR: 0b1000 /
mcm	1:d4b35641a624	1143	ODR_9 = 0b1001, /!< ODR: 0b1001 /
mcm	1:d4b35641a624	1144	ODR_10 = 0b1010, /!< ODR: 0b1010 /
mcm	1:d4b35641a624	1145	ODR_11 = 0b1011, /!< ODR: 0b1011 /
mcm	1:d4b35641a624	1146	ODR_12 = 0b1100, /!< ODR: 0b1100 /
mcm	1:d4b35641a624	1147	ODR_13 = 0b1101, /!< ODR: 0b1101 /
mcm	1:d4b35641a624	1148	ODR_14 = 0b1110, /!< ODR: 0b1110 /
mcm	1:d4b35641a624	1149	ODR_15 = 0b1111 /!< ODR: 0b1111 /
mcm	1:d4b35641a624	1150	} MC3635_sample_rate_t;
mcm	1:d4b35641a624	1151
mcm	1:d4b35641a624	1152
mcm	1:d4b35641a624	1153
mcm	1:d4b35641a624	1154	/**
mcm	1:d4b35641a624	1155	* @brief AXIS
mcm	1:d4b35641a624	1156	*
mcm	1:d4b35641a624	1157	*/
mcm	1:d4b35641a624	1158	typedef enum {
mcm	1:d4b35641a624	1159	X_AXIS = 0, /!< X-Axis chosen /
mcm	1:d4b35641a624	1160	Y_AXIS = 1, /!< Y-Axis chosen /
mcm	1:d4b35641a624	1161	Z_AXIS = 2 /!< Z-Axis chosen /
mcm	1:d4b35641a624	1162	} MC3635_axis_t;
mcm	1:d4b35641a624	1163
mcm	1:d4b35641a624	1164
mcm	1:d4b35641a624	1165
mcm	1:d4b35641a624	1166
mcm	1:d4b35641a624	1167	#ifndef MC3635_VECTOR_STRUCT_H
mcm	1:d4b35641a624	1168	#define MC3635_VECTOR_STRUCT_H
mcm	1:d4b35641a624	1169	typedef struct {
mcm	1:d4b35641a624	1170	int16_t XAxis_mg; /!< X Axis raw data in mg /
mcm	1:d4b35641a624	1171	int16_t YAxis_mg; /!< Y Axis raw data in mg /
mcm	1:d4b35641a624	1172	int16_t ZAxis_mg; /!< Z Axis raw data in mg /
mcm	1:d4b35641a624	1173
mcm	1:d4b35641a624	1174	uint8_t scratch; /!< Any value can be written and read-back /
mcm	1:d4b35641a624	1175	uint8_t ext_stat_2; /!< It contains the value for the Extended Status Register 2 /
mcm	1:d4b35641a624	1176	uint8_t status_1; /!< It contains the value for the Status Register 1 /
mcm	1:d4b35641a624	1177	uint8_t status_2; /!< It contains the value for the Status Register 2 /
mcm	1:d4b35641a624	1178	uint8_t FeatureRegister1; /!< It contains the value for the Feature Register 1 /
mcm	1:d4b35641a624	1179	uint8_t FeatureRegister2; /!< It contains the value for the Feature Register 2 /
mcm	1:d4b35641a624	1180
mcm	1:d4b35641a624	1181	MC3635_range_c_res_t resolution; /!< It contains the accelerometer resolution /
mcm	1:d4b35641a624	1182	MC3635_range_c_range_t range; /!< It contains the accelerometer range /
mcm	1:d4b35641a624	1183
mcm	1:d4b35641a624	1184	uint16_t XGAIN; /!< It contains the value for X-Axis gain /
mcm	1:d4b35641a624	1185	uint16_t YGAIN; /!< It contains the value for Y-Axis gain /
mcm	1:d4b35641a624	1186	uint16_t ZGAIN; /!< It contains the value for Z-Axis gain /
mcm	1:d4b35641a624	1187
mcm	1:d4b35641a624	1188	int16_t XOffset; /!< It contains the value for X-Axis offset /
mcm	1:d4b35641a624	1189	int16_t YOffset; /!< It contains the value for Y-Axis offset /
mcm	1:d4b35641a624	1190	int16_t ZOffset; /!< It contains the value for Z-Axis offset /
mcm	1:d4b35641a624	1191	} MC3635_data_t;
mcm	1:d4b35641a624	1192	#endif
mcm	1:d4b35641a624	1193
mcm	1:d4b35641a624	1194
mcm	1:d4b35641a624	1195
mcm	1:d4b35641a624	1196	/**
mcm	1:d4b35641a624	1197	* @brief INTERNAL CONSTANTS
mcm	1:d4b35641a624	1198	*/
mcm	1:d4b35641a624	1199	typedef enum {
mcm	1:d4b35641a624	1200	MC3635_SUCCESS = 0,
mcm	1:d4b35641a624	1201	MC3635_FAILURE = 1,
mcm	1:d4b35641a624	1202	I2C_SUCCESS = 1
mcm	1:d4b35641a624	1203	} MC3635_status_t;
mcm	1:d4b35641a624	1204
mcm	1:d4b35641a624	1205
mcm	1:d4b35641a624	1206
mcm	1:d4b35641a624	1207
mcm	1:d4b35641a624	1208	/** Create an MC3635 object connected to the specified SPI pins.
mcm	1:d4b35641a624	1209	*
mcm	1:d4b35641a624	1210	* @param sda I2C data pin
mcm	1:d4b35641a624	1211	* @param scl I2C clock pin
mcm	1:d4b35641a624	1212	* @param addr I2C slave address
mcm	1:d4b35641a624	1213	* @param freq I2C frequency in Hz.
mcm	1:d4b35641a624	1214	*/
mcm	1:d4b35641a624	1215	MC3635 ( PinName sda, PinName scl, uint32_t addr, uint32_t freq );
mcm	1:d4b35641a624	1216
mcm	1:d4b35641a624	1217	/** Delete MC3635 object.
mcm	1:d4b35641a624	1218	*/
mcm	1:d4b35641a624	1219	~MC3635();
mcm	1:d4b35641a624	1220
mcm	1:d4b35641a624	1221	/** It starts an initialization sequence.
mcm	1:d4b35641a624	1222	*/
mcm	1:d4b35641a624	1223	MC3635_status_t MC3635_InitializationSequence ( void );
mcm	1:d4b35641a624	1224
mcm	1:d4b35641a624	1225	/** It writes into the scratch pad register.
mcm	1:d4b35641a624	1226	*/
mcm	1:d4b35641a624	1227	MC3635_status_t MC3635_WriteScratchpadRegister ( MC3635_data_t myScratchpadRegister );
mcm	1:d4b35641a624	1228
mcm	1:d4b35641a624	1229	/** It reads the scratch pad register.
mcm	1:d4b35641a624	1230	*/
mcm	1:d4b35641a624	1231	MC3635_status_t MC3635_ReadScratchpadRegister ( MC3635_data_t* myScratchpadRegister );
mcm	1:d4b35641a624	1232
mcm	1:d4b35641a624	1233	/** It performs a software reset.
mcm	1:d4b35641a624	1234	*/
mcm	1:d4b35641a624	1235	MC3635_status_t MC3635_SetSoftwareReset ( void );
mcm	1:d4b35641a624	1236
mcm	1:d4b35641a624	1237	/** It performs a reload.
mcm	1:d4b35641a624	1238	*/
mcm	1:d4b35641a624	1239	MC3635_status_t MC3635_SetReload ( void );
mcm	1:d4b35641a624	1240
mcm	1:d4b35641a624	1241	/** It reads the Extended Status Register 2.
mcm	1:d4b35641a624	1242	*/
mcm	1:d4b35641a624	1243	MC3635_status_t MC3635_ReadExtendedStatusRegister2 ( MC3635_data_t* myExt_stat_2 );
mcm	1:d4b35641a624	1244
mcm	1:d4b35641a624	1245	/** It reads X, Y and Z raw data output.
mcm	1:d4b35641a624	1246	*/
mcm	1:d4b35641a624	1247	MC3635_status_t MC3635_ReadRawData ( MC3635_data_t* myRawData );
mcm	1:d4b35641a624	1248
mcm	1:d4b35641a624	1249	/** It reads the Status Register 1.
mcm	1:d4b35641a624	1250	*/
mcm	1:d4b35641a624	1251	MC3635_status_t MC3635_ReadStatusRegister1 ( MC3635_data_t* myStatus_1 );
mcm	1:d4b35641a624	1252
mcm	1:d4b35641a624	1253	/** It reads the Status Register 2.
mcm	1:d4b35641a624	1254	*/
mcm	1:d4b35641a624	1255	MC3635_status_t MC3635_ReadStatusRegister2 ( MC3635_data_t* myStatus_2 );
mcm	1:d4b35641a624	1256
mcm	1:d4b35641a624	1257	/** It reads the Feature Register 1.
mcm	1:d4b35641a624	1258	*/
mcm	1:d4b35641a624	1259	MC3635_status_t MC3635_ReadFeatureRegister1 ( MC3635_data_t* myFeatureRegister1 );
mcm	1:d4b35641a624	1260
mcm	1:d4b35641a624	1261	/** It reads the Feature Register 2.
mcm	1:d4b35641a624	1262	*/
mcm	1:d4b35641a624	1263	MC3635_status_t MC3635_ReadFeatureRegister2 ( MC3635_data_t* myFeatureRegister2 );
mcm	1:d4b35641a624	1264
mcm	1:d4b35641a624	1265	/** It enables/disables X/Y/Z Axis.
mcm	1:d4b35641a624	1266	*/
mcm	1:d4b35641a624	1267	MC3635_status_t MC3635_EnableAxis ( MC3635_mode_c_x_axis_pd_t myXAxis, MC3635_mode_c_y_axis_pd_t myYAxis, MC3635_mode_c_z_axis_pd_t myZAxis );
mcm	1:d4b35641a624	1268
mcm	1:d4b35641a624	1269	/** It sets the clock rate for STANDBY mode.
mcm	1:d4b35641a624	1270	*/
mcm	1:d4b35641a624	1271	MC3635_status_t MC3635_SetStandbyClockRate ( MC3635_sniff_c_stb_rate_t myStandbyCloclRate );
mcm	1:d4b35641a624	1272
mcm	1:d4b35641a624	1273	/** It sets the accelerometer resolution.
mcm	1:d4b35641a624	1274	*/
mcm	1:d4b35641a624	1275	MC3635_status_t MC3635_SetResolution ( MC3635_range_c_res_t myResolution );
mcm	1:d4b35641a624	1276
mcm	1:d4b35641a624	1277	/** It reads the accelerometer resolution.
mcm	1:d4b35641a624	1278	*/
mcm	1:d4b35641a624	1279	MC3635_status_t MC3635_GetResolution ( MC3635_data_t* myResolution );
mcm	1:d4b35641a624	1280
mcm	1:d4b35641a624	1281	/** It sets the accelerometer range.
mcm	1:d4b35641a624	1282	*/
mcm	1:d4b35641a624	1283	MC3635_status_t MC3635_SetRange ( MC3635_range_c_range_t myRange );
mcm	1:d4b35641a624	1284
mcm	1:d4b35641a624	1285	/** It reads the accelerometer range.
mcm	1:d4b35641a624	1286	*/
mcm	1:d4b35641a624	1287	MC3635_status_t MC3635_GetRange ( MC3635_data_t* myRange );
mcm	1:d4b35641a624	1288
mcm	1:d4b35641a624	1289	/** It sets the FIFO behavior.
mcm	1:d4b35641a624	1290	*/
mcm	1:d4b35641a624	1291	MC3635_status_t MC3635_SetFIFO ( uint8_t myNumberOfSamples, MC3635_fifo_c_fifo_mode_t myFIFO_Mode );
mcm	1:d4b35641a624	1292
mcm	1:d4b35641a624	1293	/** It enables/disables the FIFO.
mcm	1:d4b35641a624	1294	*/
mcm	1:d4b35641a624	1295	MC3635_status_t MC3635_EnableFIFO ( MC3635_fifo_c_fifo_en_t myFIFO_Enable );
mcm	1:d4b35641a624	1296
mcm	1:d4b35641a624	1297	/** It resets the FIFO pointers.
mcm	1:d4b35641a624	1298	*/
mcm	1:d4b35641a624	1299	MC3635_status_t MC3635_ResetFIFO ( void );
mcm	1:d4b35641a624	1300
mcm	1:d4b35641a624	1301	/** It configures the interrupt pin mode and level control.
mcm	1:d4b35641a624	1302	*/
mcm	1:d4b35641a624	1303	MC3635_status_t MC3635_Conf_INTN ( MC3635_intr_c_ipp_t myINTN_ModeControl, MC3635_intr_c_iah_t myINTN_LevelControl );
mcm	1:d4b35641a624	1304
mcm	1:d4b35641a624	1305	/** It activates the interrupts on INTN pin.
mcm	1:d4b35641a624	1306	*/
mcm	1:d4b35641a624	1307	MC3635_status_t MC3635_Set_INTN ( MC3635_intr_c_int_wake_t myINT_WakeMode, MC3635_intr_c_int_acq_t myINT_ACQMode,
mcm	1:d4b35641a624	1308	MC3635_intr_c_int_fifo_empty_t myINT_FIFO_EmptyMode, MC3635_intr_c_int_fifo_full_t myINT_FIFO_FullMode,
mcm	1:d4b35641a624	1309	MC3635_intr_c_int_fifo_thresh_t myINT_FIFO_ThreshMode, MC3635_intr_c_int_fifo_swake_t myINT_SwakeMode );
mcm	1:d4b35641a624	1310	/** It sets the device mode, power mode and the ODR.
mcm	1:d4b35641a624	1311	*/
mcm	1:d4b35641a624	1312	MC3635_status_t MC3635_SetMode ( MC3635_mode_c_mctrl_t myMode, MC3635_power_mode_t myPowerMode, MC3635_sample_rate_t myODR );
mcm	1:d4b35641a624	1313
mcm	1:d4b35641a624	1314	/** It configures the parameters for the SNIFF mode.
mcm	1:d4b35641a624	1315	*/
mcm	1:d4b35641a624	1316	MC3635_status_t MC3635_ConfSniffMode ( MC3635_sniffcf_c_sniff_thadr_t mySniffADR, uint8_t mySniffThreshold,
mcm	1:d4b35641a624	1317	MC3635_sniffth_c_sniff_and_or_t mySniffLogicalMode, MC3635_sniffth_c_sniff_mode_t mySniffDeltaCount,
mcm	1:d4b35641a624	1318	MC3635_sniffcf_c_sniff_cnten_t mySniffEnableDetectionCount, MC3635_sniffcf_c_sniff_mux_t mySniffMux );
mcm	1:d4b35641a624	1319	/** It is a manual reset for the Sniff block.
mcm	1:d4b35641a624	1320	*/
mcm	1:d4b35641a624	1321	MC3635_status_t MC3635_ManualSniffReset ( MC3635_sniffcf_c_sniff_reset_t mySniffResetBit );
mcm	2:292a5265228e	1322
mcm	1:d4b35641a624	1323	/** It sets the TRIGGER mode.
mcm	1:d4b35641a624	1324	*/
mcm	1:d4b35641a624	1325	MC3635_status_t MC3635_SetTriggerMode ( MC3635_mode_c_trig_cmd_t myTriggerEnable, uint8_t myTriggerSamples, MC3635_sniff_c_stb_rate_t mySTANDBY_ClockRate );
mcm	1:d4b35641a624	1326
mcm	1:d4b35641a624	1327	/** It sets the device into the STANDBY mode.
mcm	1:d4b35641a624	1328	*/
mcm	1:d4b35641a624	1329	MC3635_status_t MC3635_SetStandbyMode ( void );
mcm	1:d4b35641a624	1330
mcm	1:d4b35641a624	1331	/** It sets the device into the SLEEP mode.
mcm	1:d4b35641a624	1332	*/
mcm	1:d4b35641a624	1333	MC3635_status_t MC3635_SetSleepMode ( void );
mcm	1:d4b35641a624	1334
mcm	1:d4b35641a624	1335	/** It gets the gain for a certain axis.
mcm	1:d4b35641a624	1336	*/
mcm	1:d4b35641a624	1337	MC3635_status_t MC3635_GetGain ( MC3635_axis_t myChosenAxis, MC3635_data_t* myGain );
mcm	1:d4b35641a624	1338
mcm	1:d4b35641a624	1339	/** It gets the offset for a certain axis.
mcm	1:d4b35641a624	1340	*/
mcm	1:d4b35641a624	1341	MC3635_status_t MC3635_GetOffset ( MC3635_axis_t myChosenAxis, MC3635_data_t* myOffset );
mcm	1:d4b35641a624	1342
mcm	1:d4b35641a624	1343
mcm	1:d4b35641a624	1344	private:
mcm	1:d4b35641a624	1345	I2C _i2c;
mcm	1:d4b35641a624	1346	uint32_t _MC3635_Addr;
mcm	1:d4b35641a624	1347	};
mcm	1:d4b35641a624	1348
mcm	1:d4b35641a624	1349	#endif

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	30 May 2018
Imports:	8
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	0
Followers:	1

MC3635.h@3:d8cf2591cab6, 2018-05-30 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning