Manuel Caballero / MC3635

3-Axis Accelerometer

MC3635.h@1:d4b35641a624, 2018-05-30 (annotated)

Committer:
mcm
Date:
Wed May 30 11:50:20 2018 +0000
Revision:
1:d4b35641a624
Parent:
0:fb11c9db05cc
Child:
2:292a5265228e
The header file is ready to be tested.

Who changed what in which revision?

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mcm 1:d4b35641a624 1 /**
mcm 1:d4b35641a624 2 * @brief MC3635.h
mcm 1:d4b35641a624 3 * @details 3-Axis Accelerometer.
mcm 1:d4b35641a624 4 * Header file.
mcm 1:d4b35641a624 5 *
mcm 1:d4b35641a624 6 *
mcm 1:d4b35641a624 7 * @return N/A
mcm 1:d4b35641a624 8 *
mcm 1:d4b35641a624 9 * @author Manuel Caballero
mcm 1:d4b35641a624 10 * @date 30/May/2018
mcm 1:d4b35641a624 11 * @version 30/May/2018 The ORIGIN
mcm 1:d4b35641a624 12 * @pre N/A.
mcm 1:d4b35641a624 13 * @warning N/A
mcm 1:d4b35641a624 14 * @pre This code belongs to Nimbus Centre ( http://www.nimbus.cit.ie ).
mcm 1:d4b35641a624 15 */
mcm 1:d4b35641a624 16 #ifndef MC3635_H
mcm 1:d4b35641a624 17 #define MC3635_H
mcm 1:d4b35641a624 18
mcm 1:d4b35641a624 19 #include "mbed.h"
mcm 1:d4b35641a624 20 /**
mcm 1:d4b35641a624 21 Example:
mcm 1:d4b35641a624 22
mcm 1:d4b35641a624 23 @code
mcm 1:d4b35641a624 24 [TODO]
mcm 1:d4b35641a624 25 @endcode
mcm 1:d4b35641a624 26
mcm 1:d4b35641a624 27 */
mcm 1:d4b35641a624 28
mcm 1:d4b35641a624 29
mcm 1:d4b35641a624 30 /*!
mcm 1:d4b35641a624 31 Library for the MC3635 3-Axis Accelerometer.
mcm 1:d4b35641a624 32 */
mcm 1:d4b35641a624 33 class MC3635
mcm 1:d4b35641a624 34 {
mcm 1:d4b35641a624 35 public:
mcm 1:d4b35641a624 36 /**
mcm 1:d4b35641a624 37 * @brief DEFAULT ADDRESSES
mcm 1:d4b35641a624 38 */
mcm 1:d4b35641a624 39 typedef enum {
mcm 1:d4b35641a624 40 MC3635_ADDRESS_LOW = ( 0x4C << 1 ), /*!< DOUT_A1 = GND */
mcm 1:d4b35641a624 41 MC3635_ADDRESS_HIGH = ( 0x6C << 1 ) /*!< DOUT_A1 = VDD */
mcm 1:d4b35641a624 42 } MC3635_address_t;
mcm 1:d4b35641a624 43
mcm 1:d4b35641a624 44
mcm 1:d4b35641a624 45 /**
mcm 1:d4b35641a624 46 * @brief REGISTER SUMMARY
mcm 1:d4b35641a624 47 */
mcm 1:d4b35641a624 48 typedef enum {
mcm 1:d4b35641a624 49 EXT_STAT_1 = 0x00, /*!< Extended Status 1 */
mcm 1:d4b35641a624 50 EXT_STAT_2 = 0x01, /*!< Extended Status 2 */
mcm 1:d4b35641a624 51 XOUT_LSB = 0x02, /*!< XOUT_LSB */
mcm 1:d4b35641a624 52 XOUT_MSB = 0x03, /*!< XOUT_MSB */
mcm 1:d4b35641a624 53 YOUT_LSB = 0x04, /*!< YOUT_LSB */
mcm 1:d4b35641a624 54 YOUT_MSB = 0x05, /*!< YOUT_MSB */
mcm 1:d4b35641a624 55 ZOUT_LSB = 0x06, /*!< ZOUT_LSB */
mcm 1:d4b35641a624 56 ZOUT_MSB = 0x07, /*!< ZOUT_MSB */
mcm 1:d4b35641a624 57 STATUS_1 = 0x08, /*!< Status 1 */
mcm 1:d4b35641a624 58 STATUS_2 = 0x09, /*!< Status 2 */
mcm 1:d4b35641a624 59
mcm 1:d4b35641a624 60 FREG_1 = 0x0D, /*!< Feature 1 */
mcm 1:d4b35641a624 61 FREG_2 = 0x0E, /*!< Feature 2 */
mcm 1:d4b35641a624 62 INIT_1 = 0x0F, /*!< Initialization Register 1 */
mcm 1:d4b35641a624 63 MODE_C = 0x10, /*!< Mode Control */
mcm 1:d4b35641a624 64 RATE_1 = 0x11, /*!< Rate 1 */
mcm 1:d4b35641a624 65 SNIFF_C = 0x12, /*!< Sniff Control */
mcm 1:d4b35641a624 66 SNIFFTH_C = 0x13, /*!< Sniff Threshold Control */
mcm 1:d4b35641a624 67 SNIFFCF_C = 0x14, /*!< Sniff Configuration */
mcm 1:d4b35641a624 68 RANGE_C = 0x15, /*!< Range Resolution Control */
mcm 1:d4b35641a624 69 FIFO_C = 0x16, /*!< FIFO Control */
mcm 1:d4b35641a624 70 INTR_C = 0x17, /*!< Interrupt Control */
mcm 1:d4b35641a624 71
mcm 1:d4b35641a624 72 INIT_3 = 0x1A, /*!< Initialization Register 3 */
mcm 1:d4b35641a624 73 SCRATCH = 0x1B, /*!< Scratchpad */
mcm 1:d4b35641a624 74 PMCR = 0x1C, /*!< Power Mode Control */
mcm 1:d4b35641a624 75
mcm 1:d4b35641a624 76 DMX = 0x20, /*!< Drive Motion X */
mcm 1:d4b35641a624 77 DMY = 0x21, /*!< Drive Motion Y */
mcm 1:d4b35641a624 78 DMZ = 0x22, /*!< Drive Motion Z */
mcm 1:d4b35641a624 79
mcm 1:d4b35641a624 80 RESET = 0x24, /*!< Reset */
mcm 1:d4b35641a624 81
mcm 1:d4b35641a624 82 INIT_2 = 0x28, /*!< Initialization Register 2 */
mcm 1:d4b35641a624 83 TRIGC = 0x29, /*!< Trigger Count */
mcm 1:d4b35641a624 84 XOFFL = 0x2A, /*!< X-Offset LSB */
mcm 1:d4b35641a624 85 XOFFH = 0x2B, /*!< X-Offset MSB */
mcm 1:d4b35641a624 86 YOFFL = 0x2C, /*!< Y-Offset LSB */
mcm 1:d4b35641a624 87 YOFFH = 0x2D, /*!< Y-Offset MSB */
mcm 1:d4b35641a624 88 ZOFFL = 0x2E, /*!< Z-Offset LSB */
mcm 1:d4b35641a624 89 ZOFFH = 0x2F, /*!< Z-Offset MSB */
mcm 1:d4b35641a624 90 XGAIN = 0x30, /*!< X Gain */
mcm 1:d4b35641a624 91 YGAIN = 0x31, /*!< Y Gain */
mcm 1:d4b35641a624 92 ZGAIN = 0x32 /*!< Z Gain */
mcm 1:d4b35641a624 93 } MC3635_register_summary_t;
mcm 1:d4b35641a624 94
mcm 1:d4b35641a624 95
mcm 1:d4b35641a624 96
mcm 1:d4b35641a624 97 /* Commands Registers */
mcm 1:d4b35641a624 98 /**
mcm 1:d4b35641a624 99 * @brief EXTENDED STATUS REGISTER 1
mcm 1:d4b35641a624 100 */
mcm 1:d4b35641a624 101 /* Bit 3 : This register contains status for the I2C address of the device. */
mcm 1:d4b35641a624 102 typedef enum {
mcm 1:d4b35641a624 103 EXT_STAT_1_I2C_AD0_BIT_MASK = ( 1 << 3 ), /*!< I2C_AD0_BIT Mask */
mcm 1:d4b35641a624 104 EXT_STAT_1_I2C_AD0_BIT_0X4C = ( 0 << 3 ), /*!< I2C Address 0x4C ( DOUT_A1 = LOW ) */
mcm 1:d4b35641a624 105 EXT_STAT_1_I2C_AD0_BIT_0X6C = ( 1 << 3 ) /*!< I2C Address 0x6C ( DOUT_A1 = HIGH ) */
mcm 1:d4b35641a624 106 } MC3635_ext_stat_1_i2c_ad0_bit_t;
mcm 1:d4b35641a624 107
mcm 1:d4b35641a624 108
mcm 1:d4b35641a624 109
mcm 1:d4b35641a624 110 /**
mcm 1:d4b35641a624 111 * @brief EXTENDED STATUS REGISTER 2
mcm 1:d4b35641a624 112 *
mcm 1:d4b35641a624 113 * The device status register reports various conditions of the device data, clock and sniff
mcm 1:d4b35641a624 114 * circuitry.
mcm 1:d4b35641a624 115 */
mcm 1:d4b35641a624 116 /* Bit 0 : OVR_DATA. */
mcm 1:d4b35641a624 117 typedef enum {
mcm 1:d4b35641a624 118 EXT_STAT_2_OVR_DATA_MASK = ( 1 << 0 ), /*!< OVR_DATA Mask */
mcm 1:d4b35641a624 119 EXT_STAT_2_OVR_DATA_SAMPLE_OVERWRITTEN = ( 1 << 0 ), /*!< Previous acceleration sample was not read by host and has been overwritten */
mcm 1:d4b35641a624 120 EXT_STAT_2_OVR_DATA_SAMPLE_NOT_OVERWRITTEN = ( 0 << 0 ) /*!< Previous acceleration sample has not been overwritten before read by host */
mcm 1:d4b35641a624 121 } MC3635_ext_stat_2_ovr_data_t;
mcm 1:d4b35641a624 122
mcm 1:d4b35641a624 123
mcm 1:d4b35641a624 124 /* Bit 1 : PD_CLK_STAT. */
mcm 1:d4b35641a624 125 typedef enum {
mcm 1:d4b35641a624 126 EXT_STAT_2_PD_CLK_STAT_MASK = ( 1 << 1 ), /*!< PD_CLK_STAT Mask */
mcm 1:d4b35641a624 127 EXT_STAT_2_PD_CLK_STAT_CLOCKS_ENABLED = ( 0 << 1 ), /*!< Clocks are enabled */
mcm 1:d4b35641a624 128 EXT_STAT_2_PD_CLK_STAT_CLOCKS_DISABLED = ( 1 << 1 ) /*!< Clocks are disabled */
mcm 1:d4b35641a624 129 } MC3635_ext_stat_2_pd_clk_stat_t;
mcm 1:d4b35641a624 130
mcm 1:d4b35641a624 131
mcm 1:d4b35641a624 132 /* Bit 5 : OTP_BUSY. */
mcm 1:d4b35641a624 133 typedef enum {
mcm 1:d4b35641a624 134 EXT_STAT_2_OTP_BUSY_MASK = ( 1 << 5 ), /*!< OTP_BUSY Mask */
mcm 1:d4b35641a624 135 EXT_STAT_2_OTP_BUSY_OTP_POWER_DOWN = ( 0 << 5 ), /*!< OTP_VDD supply is not enabled, OTP is powered down */
mcm 1:d4b35641a624 136 EXT_STAT_2_OTP_BUSY_OTP_POWERED = ( 1 << 5 ) /*!< OTP_VDD supply is enabled, OTP is powered */
mcm 1:d4b35641a624 137 } MC3635_ext_stat_2_otp_busy_t;
mcm 1:d4b35641a624 138
mcm 1:d4b35641a624 139
mcm 1:d4b35641a624 140 /* Bit 6 : SNIFF_EN. */
mcm 1:d4b35641a624 141 typedef enum {
mcm 1:d4b35641a624 142 EXT_STAT_2_SNIFF_EN_MASK = ( 1 << 6 ), /*!< SNIFF_EN Mask */
mcm 1:d4b35641a624 143 EXT_STAT_2_SNIFF_EN_DISABLED = ( 0 << 6 ), /*!< SNIFF mode is not active */
mcm 1:d4b35641a624 144 EXT_STAT_2_SNIFF_EN_ENABLED = ( 1 << 6 ) /*!< SNIFF mode is active */
mcm 1:d4b35641a624 145 } MC3635_ext_stat_2_sniff_en_t;
mcm 1:d4b35641a624 146
mcm 1:d4b35641a624 147
mcm 1:d4b35641a624 148 /* Bit 7 : SNIFF_DETECT. */
mcm 1:d4b35641a624 149 typedef enum {
mcm 1:d4b35641a624 150 EXT_STAT_2_SNIFF_DETECT_MASK = ( 1 << 7 ), /*!< SNIFF_DETECT Mask */
mcm 1:d4b35641a624 151 EXT_STAT_2_SNIFF_DETECT_NOT_EVENT = ( 0 << 7 ), /*!< No sniff event detected */
mcm 1:d4b35641a624 152 EXT_STAT_2_SNIFF_DETECT_EVENT = ( 1 << 7 ) /*!< Sniff event detected, move to CWAKE mode */
mcm 1:d4b35641a624 153 } MC3635_ext_stat_2_sniff_detect_t;
mcm 1:d4b35641a624 154
mcm 1:d4b35641a624 155
mcm 1:d4b35641a624 156
mcm 1:d4b35641a624 157 /**
mcm 1:d4b35641a624 158 * @brief STATUS REGISTER 1
mcm 1:d4b35641a624 159 *
mcm 1:d4b35641a624 160 * This register reports the operational mode of the device. Note that the lower 3-bits, the
mcm 1:d4b35641a624 161 * MODE[2:0] field, do not immediately change once a command is written to the MODE register,
mcm 1:d4b35641a624 162 * but may take up to 3 transitions of the heartbeat clock.
mcm 1:d4b35641a624 163 */
mcm 1:d4b35641a624 164 /* Bits 2:0 : MODE. */
mcm 1:d4b35641a624 165 typedef enum {
mcm 1:d4b35641a624 166 STATUS_1_MODE_MASK = ( 0b111 << 0 ), /*!< MODE Mask */
mcm 1:d4b35641a624 167 STATUS_1_MODE_SLEEP = ( 0b000 << 0 ), /*!< Lowest power mode, regulators on, no clock activity, partial chip power-down */
mcm 1:d4b35641a624 168 STATUS_1_MODE_STANDBY = ( 0b001 << 0 ), /*!< Low power mode, no sampling, clocks active */
mcm 1:d4b35641a624 169 STATUS_1_MODE_SNIFF = ( 0b010 << 0 ), /*!< Sniff activity detection mode, sniff enabled, sniff sampling, no FIFO operations, automatically transition to CWAKE mode upon activity detection */
mcm 1:d4b35641a624 170 STATUS_1_MODE_CWAKE = ( 0b101 << 0 ), /*!< Continuous wake. Active XYZ sampling. Sniff circuitry not active */
mcm 1:d4b35641a624 171 STATUS_1_MODE_SWAKE = ( 0b110 << 0 ), /*!< Use Sniff logic, main XYZ pipeline and optional FIFO at the same time; highest power consumption */
mcm 1:d4b35641a624 172 STATUS_1_MODE_TRIG = ( 0b111 << 0 ) /*!< Trigger mode, 1 to 254 samples or continuous, return to sleep upon completion */
mcm 1:d4b35641a624 173 } MC3635_status_1_mode_t;
mcm 1:d4b35641a624 174
mcm 1:d4b35641a624 175
mcm 1:d4b35641a624 176 /* Bit 3 : NEW_DATA. */
mcm 1:d4b35641a624 177 typedef enum {
mcm 1:d4b35641a624 178 STATUS_1_NEW_DATA_MASK = ( 1 << 3 ), /*!< NEW_DATA Mask */
mcm 1:d4b35641a624 179 STATUS_1_NEW_DATA_FALSE = ( 0 << 3 ), /*!< No new sample data has arrived since last read */
mcm 1:d4b35641a624 180 STATUS_1_NEW_DATA_TRUE = ( 1 << 3 ) /*!< New sample data has arrived and has been written to FIFO/registers. This bit is always enabled and valid, regardless of the settings of any interrupt enable bits */
mcm 1:d4b35641a624 181 } MC3635_status_1_new_data_t;
mcm 1:d4b35641a624 182
mcm 1:d4b35641a624 183
mcm 1:d4b35641a624 184 /* Bit 4 : FIFO_EMPTY. */
mcm 1:d4b35641a624 185 typedef enum {
mcm 1:d4b35641a624 186 STATUS_1_FIFO_EMPTY_MASK = ( 1 << 4 ), /*!< FIFO_EMPTY Mask */
mcm 1:d4b35641a624 187 STATUS_1_FIFO_EMPTY_FALSE = ( 0 << 4 ), /*!< FIFO has one or more samples in storage (level) */
mcm 1:d4b35641a624 188 STATUS_1_FIFO_EMPTY_TRUE = ( 1 << 4 ) /*!< FIFO is empty (level) (default). This bit is set to 1 immediately after device power-up or device reset */
mcm 1:d4b35641a624 189 } MC3635_status_1_fifo_empty_t;
mcm 1:d4b35641a624 190
mcm 1:d4b35641a624 191
mcm 1:d4b35641a624 192 /* Bit 5 : FIFO_FULL. */
mcm 1:d4b35641a624 193 typedef enum {
mcm 1:d4b35641a624 194 STATUS_1_FIFO_FULL_MASK = ( 1 << 5 ), /*!< FIFO_FULL Mask */
mcm 1:d4b35641a624 195 STATUS_1_FIFO_FULL_FALSE = ( 0 << 5 ), /*!< FIFO has space or 1 or more samples (up to 32) (level) */
mcm 1:d4b35641a624 196 STATUS_1_FIFO_FULL_TRUE = ( 1 << 5 ) /*!< FIFO is full, all 32 samples are used (level) */
mcm 1:d4b35641a624 197 } MC3635_status_1_fifo_full_t;
mcm 1:d4b35641a624 198
mcm 1:d4b35641a624 199
mcm 1:d4b35641a624 200 /* Bit 6 : FIFO_THRESH. */
mcm 1:d4b35641a624 201 typedef enum {
mcm 1:d4b35641a624 202 STATUS_1_FIFO_THRESH_MASK = ( 1 << 6 ), /*!< FIFO_THRESH Mask */
mcm 1:d4b35641a624 203 STATUS_1_FIFO_THRESH_LESS = ( 0 << 6 ), /*!< Amount of data in FIFO is less than the threshold (level) */
mcm 1:d4b35641a624 204 STATUS_1_FIFO_THRESH_EQUAL_GREATER = ( 1 << 6 ) /*!< Amount of data in FIFO is equal to or greater than the threshold (level) */
mcm 1:d4b35641a624 205 } MC3635_status_1_fifo_thresh_t;
mcm 1:d4b35641a624 206
mcm 1:d4b35641a624 207
mcm 1:d4b35641a624 208 /* Bit 7 : INT_PEND. */
mcm 1:d4b35641a624 209 typedef enum {
mcm 1:d4b35641a624 210 STATUS_1_INT_PEND_MASK = ( 1 << 7 ), /*!< INT_PEND Mask */
mcm 1:d4b35641a624 211 STATUS_1_INT_PEND_FALSE = ( 0 << 7 ), /*!< No interrupt flags are pending in register 0x09 (level) */
mcm 1:d4b35641a624 212 STATUS_1_INT_PEND_TRUE = ( 1 << 7 ) /*!< One or more interrupt flags are pending in register 0x09 (logical OR) (level) */
mcm 1:d4b35641a624 213 } MC3635_status_1_int_pend_t;
mcm 1:d4b35641a624 214
mcm 1:d4b35641a624 215
mcm 1:d4b35641a624 216
mcm 1:d4b35641a624 217 /**
mcm 1:d4b35641a624 218 * @brief STATUS REGISTER 2
mcm 1:d4b35641a624 219 *
mcm 1:d4b35641a624 220 * This register reports the state of the interrupts ('0' means not pending; '1' means pending). A
mcm 1:d4b35641a624 221 * bit in this register will only be set if the corresponding interrupt enable is set to '1' in (0x17)
mcm 1:d4b35641a624 222 * Interrupt Control Register.
mcm 1:d4b35641a624 223 */
mcm 1:d4b35641a624 224 /* Bit 2 : INT_WAKE. */
mcm 1:d4b35641a624 225 typedef enum {
mcm 1:d4b35641a624 226 STATUS_2_INT_WAKE_MASK = ( 1 << 2 ), /*!< INT_WAKE Mask */
mcm 1:d4b35641a624 227 STATUS_2_INT_WAKE_FALSE = ( 0 << 2 ), /*!< INT_WAKE not triggered */
mcm 1:d4b35641a624 228 STATUS_2_INT_WAKE_TRUE = ( 1 << 2 ) /*!< INT_WAKE triggered */
mcm 1:d4b35641a624 229 } MC3635_status_2_int_wake_t;
mcm 1:d4b35641a624 230
mcm 1:d4b35641a624 231
mcm 1:d4b35641a624 232 /* Bit 3 : INT_ACQ. */
mcm 1:d4b35641a624 233 typedef enum {
mcm 1:d4b35641a624 234 STATUS_2_INT_ACQ_MASK = ( 1 << 3 ), /*!< INT_ACQ Mask */
mcm 1:d4b35641a624 235 STATUS_2_INT_ACQ_FALSE = ( 0 << 3 ), /*!< INT_ACQ not triggered */
mcm 1:d4b35641a624 236 STATUS_2_INT_ACQ_TRUE = ( 1 << 3 ) /*!< INT_ACQ triggered */
mcm 1:d4b35641a624 237 } MC3635_status_2_int_acq_t;
mcm 1:d4b35641a624 238
mcm 1:d4b35641a624 239
mcm 1:d4b35641a624 240 /* Bit 4 : INT_FIFO_EMPTY. */
mcm 1:d4b35641a624 241 typedef enum {
mcm 1:d4b35641a624 242 STATUS_2_INT_FIFO_EMPTY_MASK = ( 1 << 4 ), /*!< INT_FIFO_EMPTY Mask */
mcm 1:d4b35641a624 243 STATUS_2_INT_FIFO_EMPTY_FALSE = ( 0 << 4 ), /*!< INT_FIFO_EMPTY not triggered */
mcm 1:d4b35641a624 244 STATUS_2_INT_FIFO_EMPTY_TRUE = ( 1 << 4 ) /*!< INT_FIFO_EMPTY triggered */
mcm 1:d4b35641a624 245 } MC3635_status_2_int_fifo_empty_t;
mcm 1:d4b35641a624 246
mcm 1:d4b35641a624 247
mcm 1:d4b35641a624 248 /* Bit 5 : INT_FIFO_FULL. */
mcm 1:d4b35641a624 249 typedef enum {
mcm 1:d4b35641a624 250 STATUS_2_INT_FIFO_FULL_MASK = ( 1 << 5 ), /*!< INT_FIFO_FULL Mask */
mcm 1:d4b35641a624 251 STATUS_2_INT_FIFO_FULL_FALSE = ( 0 << 5 ), /*!< INT_FIFO_FULL not triggered */
mcm 1:d4b35641a624 252 STATUS_2_INT_FIFO_FULL_TRUE = ( 1 << 5 ) /*!< INT_FIFO_FULL triggered */
mcm 1:d4b35641a624 253 } MC3635_status_2_int_fifo_full_t;
mcm 1:d4b35641a624 254
mcm 1:d4b35641a624 255
mcm 1:d4b35641a624 256 /* Bit 6 : INT_FIFO_THRESH. */
mcm 1:d4b35641a624 257 typedef enum {
mcm 1:d4b35641a624 258 STATUS_2_INT_FIFO_THRESH_MASK = ( 1 << 6 ), /*!< INT_FIFO_THRESH Mask */
mcm 1:d4b35641a624 259 STATUS_2_INT_FIFO_THRESH_FALSE = ( 0 << 6 ), /*!< INT_FIFO_THRESH not triggered */
mcm 1:d4b35641a624 260 STATUS_2_INT_FIFO_THRESH_TRUE = ( 1 << 6 ) /*!< INT_FIFO_THRESH triggered */
mcm 1:d4b35641a624 261 } MC3635_status_2_int_fifo_thresh_t;
mcm 1:d4b35641a624 262
mcm 1:d4b35641a624 263
mcm 1:d4b35641a624 264 /* Bit 7 : INT_SWAKE. */
mcm 1:d4b35641a624 265 typedef enum {
mcm 1:d4b35641a624 266 STATUS_2_INT_SWAKE_MASK = ( 1 << 7 ), /*!< INT_SWAKE Mask */
mcm 1:d4b35641a624 267 STATUS_2_INT_SWAKE_FALSE = ( 0 << 7 ), /*!< INT_SWAKE not triggered */
mcm 1:d4b35641a624 268 STATUS_2_INT_SWAKE_TRUE = ( 1 << 7 ) /*!< INT_SWAKE triggered */
mcm 1:d4b35641a624 269 } MC3635_status_2_int_swake_t;
mcm 1:d4b35641a624 270
mcm 1:d4b35641a624 271
mcm 1:d4b35641a624 272
mcm 1:d4b35641a624 273 /**
mcm 1:d4b35641a624 274 * @brief FEATURE REGISTER 1
mcm 1:d4b35641a624 275 *
mcm 1:d4b35641a624 276 * This register is used to select the interface mode as well as the operation style of the FIFO and
mcm 1:d4b35641a624 277 * interrupt in SWAKE mode.
mcm 1:d4b35641a624 278 */
mcm 1:d4b35641a624 279 /* Bit 3 : FREEZE. */
mcm 1:d4b35641a624 280 typedef enum {
mcm 1:d4b35641a624 281 FREG_1_FREEZE_MASK = ( 1 << 3 ), /*!< FREEZE Mask */
mcm 1:d4b35641a624 282 FREG_1_FREEZE_FIFO_STANDARD_MODE = ( 0 << 3 ), /*!< FIFO operates in standard mode, does not stop capturing data in SWAKE interrupt (default) */
mcm 1:d4b35641a624 283 FREG_1_FREEZE_FIFO_STOP_SWAKE = ( 1 << 3 ) /*!< FIFO stops capturing on SWAKE interrupt, software can examine the conditions which generated the SWAKE event */
mcm 1:d4b35641a624 284 } MC3635_freg_1_freeze_t;
mcm 1:d4b35641a624 285
mcm 1:d4b35641a624 286
mcm 1:d4b35641a624 287 /* Bit 4 : INTSC_EN. */
mcm 1:d4b35641a624 288 typedef enum {
mcm 1:d4b35641a624 289 FREG_1_INTSC_EN_MASK = ( 1 << 4 ), /*!< INTSC_EN Mask */
mcm 1:d4b35641a624 290 FREG_1_INTSC_EN_DISABLED = ( 0 << 4 ), /*!< Do not re-arm SNIFF block following a SWAKE event (requires the SNIFF block to be reset by exiting SWAKE mode). (default) */
mcm 1:d4b35641a624 291 FREG_1_INTSC_EN_ENABLED = ( 1 << 4 ) /*!< Clearing the SWAKE interrupt clears and rearms the SNIFF block for subsequent detections (device may stay in SWAKE mode and continuing processing subsequent SWAKE events once interrupt is cleared) */
mcm 1:d4b35641a624 292 } MC3635_freg_1_intsc_en_t;
mcm 1:d4b35641a624 293
mcm 1:d4b35641a624 294
mcm 1:d4b35641a624 295 /* Bit 5 : SPI3_EN. */
mcm 1:d4b35641a624 296 typedef enum {
mcm 1:d4b35641a624 297 FREG_1_SPI3_EN_MASK = ( 1 << 5 ), /*!< SPI3_EN Mask */
mcm 1:d4b35641a624 298 FREG_1_SPI3_EN_DISABLED = ( 0 << 5 ), /*!< SPI interface is 4-wire */
mcm 1:d4b35641a624 299 FREG_1_SPI3_EN_ENABLED = ( 1 << 5 ) /*!< SPI interface is 3-wire (DOUT_A1 is the bidirectional pin) */
mcm 1:d4b35641a624 300 } MC3635_freg_1_spi3_en_t;
mcm 1:d4b35641a624 301
mcm 1:d4b35641a624 302
mcm 1:d4b35641a624 303 /* Bit 6 : I2C_EN. */
mcm 1:d4b35641a624 304 typedef enum {
mcm 1:d4b35641a624 305 FREG_1_I2C_EN_MASK = ( 1 << 6 ), /*!< I2C_EN Mask */
mcm 1:d4b35641a624 306 FREG_1_I2C_EN_DISABLED = ( 0 << 6 ), /*!< Device interface is still defined as it was at power-up but no data will appear in XOUT, YOUT and ZOUT registers if both this bit and SPI_EN are set to 0 (default). */
mcm 1:d4b35641a624 307 FREG_1_I2C_EN_ENABLED = ( 1 << 6 ) /*!< Disables any SPI communications */
mcm 1:d4b35641a624 308 } MC3635_freg_1_i2c_en_t;
mcm 1:d4b35641a624 309
mcm 1:d4b35641a624 310
mcm 1:d4b35641a624 311 /* Bit 7 : SPI_EN. */
mcm 1:d4b35641a624 312 typedef enum {
mcm 1:d4b35641a624 313 FREG_1_SPI_EN_MASK = ( 1 << 7 ), /*!< SPI_EN Mask */
mcm 1:d4b35641a624 314 FREG_1_SPI_EN_DISABLED = ( 0 << 7 ), /*!< Device interface is still defined as it was at power-up but no data will appear in XOUT, YOUT and ZOUT registers if both this bit and I2C_EN are set to 0 (default). */
mcm 1:d4b35641a624 315 FREG_1_SPI_EN_ENABLED = ( 1 << 7 ) /*!< Disables any I2C communications */
mcm 1:d4b35641a624 316 } MC3635_freg_1_spi_en_t;
mcm 1:d4b35641a624 317
mcm 1:d4b35641a624 318
mcm 1:d4b35641a624 319
mcm 1:d4b35641a624 320 /**
mcm 1:d4b35641a624 321 * @brief FEATURE REGISTER 2
mcm 1:d4b35641a624 322 *
mcm 1:d4b35641a624 323 * This register allows selection of various features for the FIFO, external trigger input, method of interrupt clearing and burst address wrapping.
mcm 1:d4b35641a624 324 */
mcm 1:d4b35641a624 325 /* Bit 0 : WRAPA. */
mcm 1:d4b35641a624 326 typedef enum {
mcm 1:d4b35641a624 327 FREG_2_WRAPA_MASK = ( 1 << 0 ), /*!< WRAPA Mask */
mcm 1:d4b35641a624 328 FREG_2_WRAPA_ADDRESS_0X07 = ( 0 << 0 ), /*!< Burst read cycle address wrap address is 0x07, counter automatically returns to 0x02. (default) */
mcm 1:d4b35641a624 329 FREG_2_WRAPA_ADDRESS_0X09 = ( 1 << 0 ) /*!< Burst read cycle address wrap address is 0x09, counter automatically returns to 0x02. This setting allows for status registers 0x08 and 0x09 to be included in the burst read */
mcm 1:d4b35641a624 330 } MC3635_freg_2_wrapa_t;
mcm 1:d4b35641a624 331
mcm 1:d4b35641a624 332
mcm 1:d4b35641a624 333 /* Bit 1 : FIFO_BURST. */
mcm 1:d4b35641a624 334 typedef enum {
mcm 1:d4b35641a624 335 FREG_2_FIFO_BURST_MASK = ( 1 << 1 ), /*!< FIFO_BURST Mask */
mcm 1:d4b35641a624 336 FREG_2_FIFO_BURST_DISABLED = ( 0 << 1 ), /*!< FIFO burst read cycles are 6-bytes in length, 0x02 to 0x07 per read cycle transaction (default) */
mcm 1:d4b35641a624 337 FREG_2_FIFO_BURST_ENABLED = ( 1 << 1 ) /*!< FIFO burst read cycle can be any number of 6-byte reads, up to 32 x 6 bytes (i.e. the entire FIFO contents can be read). */
mcm 1:d4b35641a624 338 } MC3635_freg_2_fifo_burst_t;
mcm 1:d4b35641a624 339
mcm 1:d4b35641a624 340
mcm 1:d4b35641a624 341 /* Bit 2 : SPI_STAT_EN. */
mcm 1:d4b35641a624 342 typedef enum {
mcm 1:d4b35641a624 343 FREG_2_SPI_STAT_EN_MASK = ( 1 << 2 ), /*!< SPI_STAT_EN Mask */
mcm 1:d4b35641a624 344 FREG_2_SPI_STAT_EN_SPI_FLAGS_DISABLED= ( 0 << 2 ), /*!< No SPI status flags are shifted out (default) */
mcm 1:d4b35641a624 345 FREG_2_SPI_STAT_EN_SPI_FLAGS_ENABLED = ( 1 << 2 ) /*!< SPI status flags are shifted out on the first byte of all 4-wire SPI transactions (SPI 3-wire and I2C modes are not supported, so no effect will be seen in those modes).*/
mcm 1:d4b35641a624 346 } MC3635_freg_2_spi_stat_en_t;
mcm 1:d4b35641a624 347
mcm 1:d4b35641a624 348
mcm 1:d4b35641a624 349 /* Bit 3 : FIFO_STAT_EN. */
mcm 1:d4b35641a624 350 typedef enum {
mcm 1:d4b35641a624 351 FREG_2_FIFO_STAT_EN_MASK = ( 1 << 3 ), /*!< FIFO_STAT_EN Mask */
mcm 1:d4b35641a624 352 FREG_2_FIFO_STAT_EN_DISABLED = ( 0 << 3 ), /*!< FIFO status feature is disabled, Z channel FIFO data is not overwritten with FIFO status information. (default) */
mcm 1:d4b35641a624 353 FREG_2_FIFO_STAT_EN_ENABLED = ( 1 << 3 ) /*!< FIFO status feature is enabled. When the resolution is less than 14-bits, the top 4-bits of 16-bit Z channel FIFO data are replaced with FIFO status information */
mcm 1:d4b35641a624 354 } MC3635_freg_2_fifo_stat_en_t;
mcm 1:d4b35641a624 355
mcm 1:d4b35641a624 356
mcm 1:d4b35641a624 357 /* Bit 4 : I2CINT_WRCLRE. */
mcm 1:d4b35641a624 358 typedef enum {
mcm 1:d4b35641a624 359 FREG_2_I2CINT_WRCLRE_MASK = ( 1 << 4 ), /*!< I2CINT_WRCLRE Mask */
mcm 1:d4b35641a624 360 FREG_2_I2CINT_WRCLRE_DISABLED = ( 0 << 4 ), /*!< In I2C mode, interrupts are cleared when reading register 0x09 (default) */
mcm 1:d4b35641a624 361 FREG_2_I2CINT_WRCLRE_ENABLED = ( 1 << 4 ) /*!< if I2C_EN is '1', then interrupts are cleared when writing to register 0x09. Otherwise I2C reads to register 0x09 will still clear pending interrupts */
mcm 1:d4b35641a624 362 } MC3635_freg_2_i2cint_wrclre_t;
mcm 1:d4b35641a624 363
mcm 1:d4b35641a624 364
mcm 1:d4b35641a624 365 /* Bit 5 : FIFO_STREAM. */
mcm 1:d4b35641a624 366 typedef enum {
mcm 1:d4b35641a624 367 FREG_2_FIFO_STREAM_MASK = ( 1 << 5 ), /*!< FIFO_STREAM Mask */
mcm 1:d4b35641a624 368 FREG_2_FIFO_STREAM_DISABLED = ( 0 << 5 ), /*!< FIFO steam mode is disabled, FIFO stops accepting new data when FULL (default) */
mcm 1:d4b35641a624 369 FREG_2_FIFO_STREAM_ENABLED = ( 1 << 5 ) /*!< FIFO stream mode is enabled, FIFO discards oldest samples once new data arrives */
mcm 1:d4b35641a624 370 } MC3635_freg_2_fifo_stream_t;
mcm 1:d4b35641a624 371
mcm 1:d4b35641a624 372
mcm 1:d4b35641a624 373 /* Bit 6 : EXT_TRIG_POL. */
mcm 1:d4b35641a624 374 typedef enum {
mcm 1:d4b35641a624 375 FREG_2_EXT_TRIG_POL_MASK = ( 1 << 6 ), /*!< EXT_TRIG_POL Mask */
mcm 1:d4b35641a624 376 FREG_2_EXT_TRIG_POL_NEGATIVE_EDGE = ( 0 << 6 ), /*!< Trigger polarity is negative edge triggered (default) */
mcm 1:d4b35641a624 377 FREG_2_EXT_TRIG_POL_POSITIVE_EDGE = ( 1 << 6 ) /*!< Trigger polarity is positive edge triggered */
mcm 1:d4b35641a624 378 } MC3635_freg_2_ext_trig_pol_t;
mcm 1:d4b35641a624 379
mcm 1:d4b35641a624 380
mcm 1:d4b35641a624 381 /* Bit 7 : EXT_TRIG_EN. */
mcm 1:d4b35641a624 382 typedef enum {
mcm 1:d4b35641a624 383 FREG_2_EXT_TRIG_EN_MASK = ( 1 << 7 ), /*!< EXT_TRIG_EN Mask */
mcm 1:d4b35641a624 384 FREG_2_EXT_TRIG_EN_DISABLED = ( 0 << 7 ), /*!< External trigger mode is not enabled (default) */
mcm 1:d4b35641a624 385 FREG_2_EXT_TRIG_EN_ENABLED = ( 1 << 7 ) /*!< External trigger mode is enabled, use INTN pin as the external trigger input. */
mcm 1:d4b35641a624 386 } MC3635_freg_2_ext_trig_en_t;
mcm 1:d4b35641a624 387
mcm 1:d4b35641a624 388
mcm 1:d4b35641a624 389
mcm 1:d4b35641a624 390 /**
mcm 1:d4b35641a624 391 * @brief INITIALIZATION REGISTER 1
mcm 1:d4b35641a624 392 *
mcm 1:d4b35641a624 393 * Software must write a fixed value to this register immediately after power-up or reset. This register will not typically read-back the value which was written.
mcm 1:d4b35641a624 394 */
mcm 1:d4b35641a624 395 /* Bits 7:0 : INIT_1. */
mcm 1:d4b35641a624 396 typedef enum {
mcm 1:d4b35641a624 397 INIT_1_INIT_1_FIXED_VALUE = 0x42 /*!< INIT_1 fix value */
mcm 1:d4b35641a624 398 } MC3635_init_1_init_1_t;
mcm 1:d4b35641a624 399
mcm 1:d4b35641a624 400
mcm 1:d4b35641a624 401
mcm 1:d4b35641a624 402 /**
mcm 1:d4b35641a624 403 * @brief MODE CONTROL REGISTER
mcm 1:d4b35641a624 404 *
mcm 1:d4b35641a624 405 * This register is the primary control register for the accelerometer. The operational mode of the device, X/Y/Z axis enables, and the TRIG one-shot
mcm 1:d4b35641a624 406 * mode can be written through this register. The mode transitions controlled by this register may take up to 3 transitions of the heartbeat clock.
mcm 1:d4b35641a624 407 * Depending on the operation, the lower 3-bits (MCTRL[2:0]) may be automatically set or cleared by hardware if auto-triggered events are executed.
mcm 1:d4b35641a624 408 * In general, when software sets an operational mode using the MCTRL [2:0] bits, there might be a delay time of 2 to 10 mSec before the operational mode
mcm 1:d4b35641a624 409 * is reflected by the MODE[2:0] bits in Status Register 1.
mcm 1:d4b35641a624 410 */
mcm 1:d4b35641a624 411 /* Bits 2:0 : MCTRL. */
mcm 1:d4b35641a624 412 typedef enum {
mcm 1:d4b35641a624 413 MODE_C_MCTRL_MASK = ( 0b111 << 0 ), /*!< MCTRL Mask */
mcm 1:d4b35641a624 414 MODE_C_MCTRL_SLEEP = ( 0b000 << 0 ), /*!< Lowest power mode, regulators on, no clock activity, partial chip power-down */
mcm 1:d4b35641a624 415 MODE_C_MCTRL_STANDBY = ( 0b001 << 0 ), /*!< Low power mode, no sampling, clocks active */
mcm 1:d4b35641a624 416 MODE_C_MCTRL_SNIFF = ( 0b010 << 0 ), /*!< Sniff activity detection mode, sniff enabled, no sampling, no FIFO operations, automatically transition to CWAKE mode upon activity detection */
mcm 1:d4b35641a624 417 MODE_C_MCTRL_CWAKE = ( 0b101 << 0 ), /*!< Continuous wake. Active XYZ sampling. Sniff circuitry not active */
mcm 1:d4b35641a624 418 MODE_C_MCTRL_SWAKE = ( 0b110 << 0 ), /*!< Use Sniff logic, main XYZ pipeline and optional FIFO at the same time; highest power consumption */
mcm 1:d4b35641a624 419 MODE_C_MCTRL_TRIG = ( 0b111 << 0 ) /*!< Trigger mode, 1 to 254 samples or continuous, return to sleep upon completion */
mcm 1:d4b35641a624 420 } MC3635_mode_c_mctrl_t;
mcm 1:d4b35641a624 421
mcm 1:d4b35641a624 422
mcm 1:d4b35641a624 423 /* Bit 4 : X_AXIS_PD. */
mcm 1:d4b35641a624 424 typedef enum {
mcm 1:d4b35641a624 425 MODE_C_X_AXIS_PD_MASK = ( 1 << 4 ), /*!< X_AXIS_PD Mask */
mcm 1:d4b35641a624 426 MODE_C_X_AXIS_PD_ENABLED = ( 0 << 4 ), /*!< X-axis is enabled */
mcm 1:d4b35641a624 427 MODE_C_X_AXIS_PD_DISABLED = ( 1 << 4 ) /*!< X-axis is disabled */
mcm 1:d4b35641a624 428 } MC3635_mode_c_x_axis_pd_t;
mcm 1:d4b35641a624 429
mcm 1:d4b35641a624 430
mcm 1:d4b35641a624 431 /* Bit 5 : Y_AXIS_PD. */
mcm 1:d4b35641a624 432 typedef enum {
mcm 1:d4b35641a624 433 MODE_C_Y_AXIS_PD_MASK = ( 1 << 5 ), /*!< Y_AXIS_PD Mask */
mcm 1:d4b35641a624 434 MODE_C_Y_AXIS_PD_ENABLED = ( 0 << 5 ), /*!< Y-axis is enabled */
mcm 1:d4b35641a624 435 MODE_C_Y_AXIS_PD_DISABLED = ( 1 << 5 ) /*!< Y-axis is disabled */
mcm 1:d4b35641a624 436 } MC3635_mode_c_y_axis_pd_t;
mcm 1:d4b35641a624 437
mcm 1:d4b35641a624 438
mcm 1:d4b35641a624 439 /* Bit 6 : Z_AXIS_PD. */
mcm 1:d4b35641a624 440 typedef enum {
mcm 1:d4b35641a624 441 MODE_C_Z_AXIS_PD_MASK = ( 1 << 6 ), /*!< Z_AXIS_PD Mask */
mcm 1:d4b35641a624 442 MODE_C_Z_AXIS_PD_ENABLED = ( 0 << 6 ), /*!< Z-axis is enabled */
mcm 1:d4b35641a624 443 MODE_C_Z_AXIS_PD_DISABLED = ( 1 << 6 ) /*!< Z-axis is disabled */
mcm 1:d4b35641a624 444 } MC3635_mode_c_z_axis_pd_t;
mcm 1:d4b35641a624 445
mcm 1:d4b35641a624 446
mcm 1:d4b35641a624 447 /* Bit 7 : TRIG_CMD. */
mcm 1:d4b35641a624 448 typedef enum {
mcm 1:d4b35641a624 449 MODE_C_TRIG_CMD_MASK = ( 1 << 7 ), /*!< TRIG_CMD Mask */
mcm 1:d4b35641a624 450 MODE_C_TRIG_CMD_DISABLED = ( 0 << 7 ),
mcm 1:d4b35641a624 451 MODE_C_TRIG_CMD_ENABLED = ( 1 << 7 )
mcm 1:d4b35641a624 452 } MC3635_mode_c_trig_cmd_t;
mcm 1:d4b35641a624 453
mcm 1:d4b35641a624 454
mcm 1:d4b35641a624 455 /**
mcm 1:d4b35641a624 456 * @brief RATE REGISTER 1
mcm 1:d4b35641a624 457 *
mcm 1:d4b35641a624 458 * This register configures the sample rates for wake modes. The rates also depend upon the value in register 0x1C.
mcm 1:d4b35641a624 459 * The device has several power modes which can be adjusted to achieve a desired power consumption at a certain ODR.
mcm 1:d4b35641a624 460 * The trade-off for lower power is either higher noise or lower ODR.
mcm 1:d4b35641a624 461 */
mcm 1:d4b35641a624 462 /* Bits 3:0 : RR. */
mcm 1:d4b35641a624 463 typedef enum {
mcm 1:d4b35641a624 464 RATE_1_RR_MASK = ( 0b1111 << 0 ), /*!< RR Mask */
mcm 1:d4b35641a624 465 RATE_1_RR_0X05 = ( 0x05 << 0 ), /*!< RR value: 0x05 */
mcm 1:d4b35641a624 466 RATE_1_RR_0X06 = ( 0x06 << 0 ), /*!< RR value: 0x06 */
mcm 1:d4b35641a624 467 RATE_1_RR_0X07 = ( 0x07 << 0 ), /*!< RR value: 0x07 */
mcm 1:d4b35641a624 468 RATE_1_RR_0X08 = ( 0x08 << 0 ), /*!< RR value: 0x08 */
mcm 1:d4b35641a624 469 RATE_1_RR_0X09 = ( 0x09 << 0 ), /*!< RR value: 0x09 */
mcm 1:d4b35641a624 470 RATE_1_RR_0X0A = ( 0x0A << 0 ), /*!< RR value: 0x0A */
mcm 1:d4b35641a624 471 RATE_1_RR_0X0B = ( 0x0B << 0 ), /*!< RR value: 0x0B */
mcm 1:d4b35641a624 472 RATE_1_RR_0X0C = ( 0x0C << 0 ), /*!< RR value: 0x0C */
mcm 1:d4b35641a624 473 RATE_1_RR_0X0F = ( 0x0F << 0 ) /*!< RR value: 0x0F */
mcm 1:d4b35641a624 474 } MC3635_rate_1_rr_t;
mcm 1:d4b35641a624 475
mcm 1:d4b35641a624 476
mcm 1:d4b35641a624 477 /**
mcm 1:d4b35641a624 478 * @brief SNIFF CONTROL REGISTER
mcm 1:d4b35641a624 479 *
mcm 1:d4b35641a624 480 * This register selects the sample rate for SNIFF mode and the clock rate for STANDBY mode.
mcm 1:d4b35641a624 481 */
mcm 1:d4b35641a624 482 /* Bits 3:0 : SNIFF_SR. */
mcm 1:d4b35641a624 483 typedef enum {
mcm 1:d4b35641a624 484 SNIFF_C_SNIFF_SR_MASK = ( 0b1111 << 0 ), /*!< SNIFF_SR Mask */
mcm 1:d4b35641a624 485 SNIFF_C_SNIFF_SR_0 = ( 0b0000 << 0 ),
mcm 1:d4b35641a624 486 SNIFF_C_SNIFF_SR_1 = ( 0b0001 << 0 ),
mcm 1:d4b35641a624 487 SNIFF_C_SNIFF_SR_2 = ( 0b0010 << 0 ),
mcm 1:d4b35641a624 488 SNIFF_C_SNIFF_SR_3 = ( 0b0011 << 0 ),
mcm 1:d4b35641a624 489 SNIFF_C_SNIFF_SR_4 = ( 0b0100 << 0 ),
mcm 1:d4b35641a624 490 SNIFF_C_SNIFF_SR_5 = ( 0b0101 << 0 ),
mcm 1:d4b35641a624 491 SNIFF_C_SNIFF_SR_6 = ( 0b0110 << 0 ),
mcm 1:d4b35641a624 492 SNIFF_C_SNIFF_SR_7 = ( 0b0111 << 0 ),
mcm 1:d4b35641a624 493 SNIFF_C_SNIFF_SR_8 = ( 0b1000 << 0 ),
mcm 1:d4b35641a624 494 SNIFF_C_SNIFF_SR_9 = ( 0b1001 << 0 ),
mcm 1:d4b35641a624 495 SNIFF_C_SNIFF_SR_10 = ( 0b1010 << 0 ),
mcm 1:d4b35641a624 496 SNIFF_C_SNIFF_SR_11 = ( 0b1011 << 0 ),
mcm 1:d4b35641a624 497 SNIFF_C_SNIFF_SR_12 = ( 0b1100 << 0 ),
mcm 1:d4b35641a624 498 SNIFF_C_SNIFF_SR_13 = ( 0b1101 << 0 ),
mcm 1:d4b35641a624 499 SNIFF_C_SNIFF_SR_14 = ( 0b1110 << 0 ),
mcm 1:d4b35641a624 500 SNIFF_C_SNIFF_SR_15 = ( 0b1111 << 0 )
mcm 1:d4b35641a624 501 } MC3635_sniff_c_sniff_sr_t;
mcm 1:d4b35641a624 502
mcm 1:d4b35641a624 503
mcm 1:d4b35641a624 504 /* Bits 7:5 : STB_RATE. */
mcm 1:d4b35641a624 505 typedef enum {
mcm 1:d4b35641a624 506 SNIFF_C_STB_RATE_MASK = ( 0b111 << 5 ), /*!< STB_RATE Mask */
mcm 1:d4b35641a624 507 SNIFF_C_STB_RATE_0 = ( 0b000 << 5 ),
mcm 1:d4b35641a624 508 SNIFF_C_STB_RATE_1 = ( 0b001 << 5 ),
mcm 1:d4b35641a624 509 SNIFF_C_STB_RATE_2 = ( 0b010 << 5 ),
mcm 1:d4b35641a624 510 SNIFF_C_STB_RATE_3 = ( 0b011 << 5 ),
mcm 1:d4b35641a624 511 SNIFF_C_STB_RATE_4 = ( 0b100 << 5 ),
mcm 1:d4b35641a624 512 SNIFF_C_STB_RATE_5 = ( 0b101 << 5 ),
mcm 1:d4b35641a624 513 SNIFF_C_STB_RATE_6 = ( 0b110 << 5 ),
mcm 1:d4b35641a624 514 SNIFF_C_STB_RATE_7 = ( 0b111 << 5 )
mcm 1:d4b35641a624 515 } MC3635_sniff_c_stb_rate_t;
mcm 1:d4b35641a624 516
mcm 1:d4b35641a624 517
mcm 1:d4b35641a624 518
mcm 1:d4b35641a624 519 /**
mcm 1:d4b35641a624 520 * @brief SNIFF THRESHOLD CONTROL REGISTER
mcm 1:d4b35641a624 521 *
mcm 1:d4b35641a624 522 * This register sets the threshold values used by the SNIFF logic for activity detection. For each axis,
mcm 1:d4b35641a624 523 * a delta count is generated and compared to the threshold. When the delta count is greater than the threshold,
mcm 1:d4b35641a624 524 * a SNIFF wakeup event occurs. There is a unique sniff threshold for each axis, and an optional 'false detection count'
mcm 1:d4b35641a624 525 * which requires multiple sniff detection events to occur before a wakeup condition is declared. These features are set by
mcm 1:d4b35641a624 526 * six shadow registers accessed by register 0x13[5:0] and register 0x14 bits [2:0].
mcm 1:d4b35641a624 527 */
mcm 1:d4b35641a624 528 /* Bits 5:0 : SNIFF_TH. */
mcm 1:d4b35641a624 529 typedef enum {
mcm 1:d4b35641a624 530 SNIFFTH_C_SNIFF_TH_MASK = ( 0b111111 << 0 ) /*!< SNIFF_TH Mask */
mcm 1:d4b35641a624 531 } MC3635_sniffth_c_sniff_th_t;
mcm 1:d4b35641a624 532
mcm 1:d4b35641a624 533
mcm 1:d4b35641a624 534 /* Bits 6 : SNIFF_AND_OR. */
mcm 1:d4b35641a624 535 typedef enum {
mcm 1:d4b35641a624 536 SNIFFTH_C_SNIFF_AND_OR_MASK = ( 1 << 6 ), /*!< SNIFF_AND_OR Mask */
mcm 1:d4b35641a624 537 SNIFFTH_C_SNIFF_AND_OR_OR_ENABLED = ( 0 << 6 ), /*!< OR - SNIFF wakeup/interrupt is triggered when any of the active channels have met detection threshold and count requirements (default) */
mcm 1:d4b35641a624 538 SNIFFTH_C_SNIFF_AND_OR_AND_ENABLED = ( 1 << 6 ) /*!< AND - SNIFF wakeup/interrupt is triggered when all active channels have met detection threshold and count requirements */
mcm 1:d4b35641a624 539 } MC3635_sniffth_c_sniff_and_or_t;
mcm 1:d4b35641a624 540
mcm 1:d4b35641a624 541
mcm 1:d4b35641a624 542 /* Bits 7 : SNIFF_MODE. */
mcm 1:d4b35641a624 543 typedef enum {
mcm 1:d4b35641a624 544 SNIFFTH_C_SNIFF_MODE_MASK = ( 1 << 7 ), /*!< SNIFF_MODE Mask */
mcm 1:d4b35641a624 545 SNIFFTH_C_SNIFF_MODE_C2P_ENABLED = ( 0 << 7 ), /*!< C2P Mode (Current to Previous): The delta count between current and previous samples is a moving window. The SNIFF logic uses the current sample and the immediate previous sample to compute a delta (default) */
mcm 1:d4b35641a624 546 SNIFFTH_C_SNIFF_MODE_C2B_ENABLED = ( 1 << 7 ) /*!< C2B Mode (Current to Baseline): The delta count is generated from subtracting the current sample from the first sample stored when entering SNIFF mode */
mcm 1:d4b35641a624 547 } MC3635_sniffth_c_sniff_mode_t;
mcm 1:d4b35641a624 548
mcm 1:d4b35641a624 549
mcm 1:d4b35641a624 550
mcm 1:d4b35641a624 551 /**
mcm 1:d4b35641a624 552 * @brief SNIFF CONFIGURATION REGISTER
mcm 1:d4b35641a624 553 *
mcm 1:d4b35641a624 554 * This register selects which of the six shadow registers is being accessed in register 0x13, and controls settings of the SNIFF hardware.
mcm 1:d4b35641a624 555 */
mcm 1:d4b35641a624 556 /* Bits 2:0 : SNIFF_THADR. */
mcm 1:d4b35641a624 557 typedef enum {
mcm 1:d4b35641a624 558 SNIFFCF_C_SNIFF_THADR_MASK = ( 0b111 << 0 ), /*!< SNIFF_THADR Mask */
mcm 1:d4b35641a624 559 SNIFFCF_C_SNIFF_THADR_NONE = ( 0b000 << 0 ), /*!< None */
mcm 1:d4b35641a624 560 SNIFFCF_C_SNIFF_THADR_SNIFF_THRESHOLD_X_AXIS = ( 0b001 << 0 ), /*!< SNIFF Threshold, X-axis */
mcm 1:d4b35641a624 561 SNIFFCF_C_SNIFF_THADR_SNIFF_THRESHOLD_Y_AXIS = ( 0b010 << 0 ), /*!< SNIFF Threshold, X-axis */
mcm 1:d4b35641a624 562 SNIFFCF_C_SNIFF_THADR_SNIFF_THRESHOLD_Z_AXIS = ( 0b011 << 0 ), /*!< SNIFF Threshold, X-axis */
mcm 1:d4b35641a624 563 //SNIFFCF_C_SNIFF_THADR_NONE = ( 0b100 << 0 ), /*!< None */
mcm 1:d4b35641a624 564 SNIFFCF_C_SNIFF_THADR_SNIFF_DETECTION_X_AXIS = ( 0b101 << 0 ), /*!< SNIFF Detection Count, X-axis */
mcm 1:d4b35641a624 565 SNIFFCF_C_SNIFF_THADR_SNIFF_DETECTION_Y_AXIS = ( 0b110 << 0 ), /*!< SNIFF Detection Count, X-axis */
mcm 1:d4b35641a624 566 SNIFFCF_C_SNIFF_THADR_SNIFF_DETECTION_Z_AXIS = ( 0b111 << 0 ) /*!< SNIFF Detection Count, X-axis */
mcm 1:d4b35641a624 567 } MC3635_sniffcf_c_sniff_thadr_t;
mcm 1:d4b35641a624 568
mcm 1:d4b35641a624 569
mcm 1:d4b35641a624 570 /* Bits 3 : SNIFF_CNTEN. */
mcm 1:d4b35641a624 571 typedef enum {
mcm 1:d4b35641a624 572 SNIFFCF_C_SNIFF_CNTEN_MASK = ( 1 << 3 ), /*!< SNIFF_CNTEN Mask */
mcm 1:d4b35641a624 573 SNIFFCF_C_SNIFF_CNTEN_DISABLED = ( 0 << 3 ), /*!< Do not use SNIFF detection counters. (default) */
mcm 1:d4b35641a624 574 SNIFFCF_C_SNIFF_CNTEN_ENABLED = ( 1 << 3 ) /*!< Enable SNIFF detection counts, required for valid SNIFF wakeup */
mcm 1:d4b35641a624 575 } MC3635_sniffcf_c_sniff_cnten_t;
mcm 1:d4b35641a624 576
mcm 1:d4b35641a624 577
mcm 1:d4b35641a624 578 /* Bits 6:4 : SNIFF_MUX. */
mcm 1:d4b35641a624 579 typedef enum {
mcm 1:d4b35641a624 580 SNIFFCF_C_SNIFF_MUX_MASK = ( 0b111 << 4 ), /*!< SNIFF_MUX Mask */
mcm 1:d4b35641a624 581 SNIFFCF_C_SNIFF_MUX_DELTA_5_0 = ( 0b000 << 4 ), /*!< DELTA[5:0] */
mcm 1:d4b35641a624 582 SNIFFCF_C_SNIFF_MUX_DELTA_6_1 = ( 0b001 << 4 ), /*!< DELTA[6:1] */
mcm 1:d4b35641a624 583 SNIFFCF_C_SNIFF_MUX_DELTA_7_2 = ( 0b010 << 4 ), /*!< DELTA[7:2] */
mcm 1:d4b35641a624 584 SNIFFCF_C_SNIFF_MUX_DELTA_8_3 = ( 0b011 << 4 ), /*!< DELTA[8:3] */
mcm 1:d4b35641a624 585 SNIFFCF_C_SNIFF_MUX_DELTA_9_4 = ( 0b100 << 4 ), /*!< DELTA[9:4] */
mcm 1:d4b35641a624 586 SNIFFCF_C_SNIFF_MUX_DELTA_10_5 = ( 0b101 << 4 ) /*!< DELTA[10:5] */
mcm 1:d4b35641a624 587 } MC3635_sniffcf_c_sniff_mux_t;
mcm 1:d4b35641a624 588
mcm 1:d4b35641a624 589
mcm 1:d4b35641a624 590 /* Bits 7 : SNIFF_RESET. */
mcm 1:d4b35641a624 591 typedef enum {
mcm 1:d4b35641a624 592 SNIFFCF_C_SNIFF_RESET_MASK = ( 1 << 7 ), /*!< SNIFF_RESET Mask */
mcm 1:d4b35641a624 593 SNIFFCF_C_SNIFF_RESET_NOT_APPLIED = ( 0 << 7 ), /*!< SNIFF block reset is not applied (default). */
mcm 1:d4b35641a624 594 SNIFFCF_C_SNIFF_RESET_APPLIED = ( 1 << 7 ) /*!< SNIFF block reset is applied */
mcm 1:d4b35641a624 595 } MC3635_sniffcf_c_sniff_reset_t;
mcm 1:d4b35641a624 596
mcm 1:d4b35641a624 597
mcm 1:d4b35641a624 598
mcm 1:d4b35641a624 599 /**
mcm 1:d4b35641a624 600 * @brief RANGE AND RESOLUTION CONTROL REGISTER
mcm 1:d4b35641a624 601 *
mcm 1:d4b35641a624 602 * The RANGE register sets the resolution and range options for the accelerometer. All numbers are sign-extended, 2's complement format.
mcm 1:d4b35641a624 603 * All results are reported in registers 0x02 to 0x07. When the FIFO is enabled, only 6 to 12-bit resolutions are supported due to the
mcm 1:d4b35641a624 604 * 12-bit width of the FIFO.
mcm 1:d4b35641a624 605 */
mcm 1:d4b35641a624 606 /* Bits 2:0 : RES. */
mcm 1:d4b35641a624 607 typedef enum {
mcm 1:d4b35641a624 608 RANGE_C_RES_MASK = ( 0b111 << 0 ), /*!< RES Mask */
mcm 1:d4b35641a624 609 RANGE_C_RES_6_BITS = ( 0b000 << 0 ), /*!< 6 bits */
mcm 1:d4b35641a624 610 RANGE_C_RES_7_BITS = ( 0b001 << 0 ), /*!< 7 bits */
mcm 1:d4b35641a624 611 RANGE_C_RES_8_BITS = ( 0b010 << 0 ), /*!< 8 bits */
mcm 1:d4b35641a624 612 RANGE_C_RES_10_BITS = ( 0b011 << 0 ), /*!< 10 bits */
mcm 1:d4b35641a624 613 RANGE_C_RES_12_BITS = ( 0b100 << 0 ), /*!< 12 bits */
mcm 1:d4b35641a624 614 RANGE_C_RES_14_BITS = ( 0b101 << 0 ) /*!< 14 bits (only 12-bits if FIFO enabled) */
mcm 1:d4b35641a624 615 } MC3635_range_c_res_t;
mcm 1:d4b35641a624 616
mcm 1:d4b35641a624 617
mcm 1:d4b35641a624 618 /* Bits 6:4 : RANGE. */
mcm 1:d4b35641a624 619 typedef enum {
mcm 1:d4b35641a624 620 RANGE_C_RANGE_MASK = ( 0b111 << 4 ), /*!< RANGE Mask */
mcm 1:d4b35641a624 621 RANGE_C_RANGE_2G = ( 0b000 << 4 ), /*!< ±2g */
mcm 1:d4b35641a624 622 RANGE_C_RANGE_4G = ( 0b001 << 4 ), /*!< ±4g */
mcm 1:d4b35641a624 623 RANGE_C_RANGE_8G = ( 0b010 << 4 ), /*!< ±8g */
mcm 1:d4b35641a624 624 RANGE_C_RANGE_16G = ( 0b011 << 4 ), /*!< ±16g */
mcm 1:d4b35641a624 625 RANGE_C_RANGE_12G = ( 0b100 << 4 ) /*!< ±12g */
mcm 1:d4b35641a624 626 } MC3635_range_c_range_t;
mcm 1:d4b35641a624 627
mcm 1:d4b35641a624 628
mcm 1:d4b35641a624 629
mcm 1:d4b35641a624 630 /**
mcm 1:d4b35641a624 631 * @brief FIFO CONTROL REGISTER
mcm 1:d4b35641a624 632 *
mcm 1:d4b35641a624 633 * This register selects the FIFO threshold level, operation mode, FIFO reset and enable. With the exception of FIFO_RESET,
mcm 1:d4b35641a624 634 * the FIFO_EN bit must be '1' for any FIFO interrupts, thresholds, or modes to be enabled. The FIFO flags in register 0x08 will
mcm 1:d4b35641a624 635 * continue to report FIFO defaults even if the FIFO_EN is '0'.
mcm 1:d4b35641a624 636 */
mcm 1:d4b35641a624 637 /* Bits 4:0 : FIFO_TH. */
mcm 1:d4b35641a624 638 typedef enum {
mcm 1:d4b35641a624 639 FIFO_C_FIFO_TH_MASK = ( 0b11111 << 0 ) /*!< The FIFO threshold level selects the number of samples in the FIFO for different FIFO events. The threshold value may be 1 to 31 (00001 to 11111) */
mcm 1:d4b35641a624 640 } MC3635_fifo_c_fifo_th_t;
mcm 1:d4b35641a624 641
mcm 1:d4b35641a624 642
mcm 1:d4b35641a624 643 /* Bit 5 : FIFO_MODE. */
mcm 1:d4b35641a624 644 typedef enum {
mcm 1:d4b35641a624 645 FIFO_C_FIFO_MODE_MASK = ( 1 << 5 ), /*!< FIFO_MODE Mask */
mcm 1:d4b35641a624 646 FIFO_C_FIFO_MODE_NORMAL = ( 0 << 5 ), /*!< Normal operation, the FIFO continues to accept new sample data as long as there is space remaining (default) */
mcm 1:d4b35641a624 647 FIFO_C_FIFO_MODE_WATERMARK = ( 1 << 5 ) /*!< Watermark, once the amount of samples in the FIFO reaches or exceeds the threshold level, the FIFO stops accepting new sample data. Any additional sample data is 'dropped' */
mcm 1:d4b35641a624 648 } MC3635_fifo_c_fifo_mode_t;
mcm 1:d4b35641a624 649
mcm 1:d4b35641a624 650
mcm 1:d4b35641a624 651 /* Bit 6 : FIFO_EN. */
mcm 1:d4b35641a624 652 typedef enum {
mcm 1:d4b35641a624 653 FIFO_C_FIFO_EN_MASK = ( 1 << 6 ), /*!< FIFO_EN Mask */
mcm 1:d4b35641a624 654 FIFO_C_FIFO_EN_DISABLED = ( 0 << 6 ), /*!< No FIFO operation, sample data written directly to output registers */
mcm 1:d4b35641a624 655 FIFO_C_FIFO_EN_ENABLED = ( 1 << 6 ) /*!< FIFO enabled, all sample data written to FIFO write port if there is room. The FIFO write clock is controlled by this enable, resulting in higher dynamic power */
mcm 1:d4b35641a624 656 } MC3635_fifo_c_fifo_en_t;
mcm 1:d4b35641a624 657
mcm 1:d4b35641a624 658
mcm 1:d4b35641a624 659 /* Bit 7 : FIFO_RESET. */
mcm 1:d4b35641a624 660 typedef enum {
mcm 1:d4b35641a624 661 FIFO_C_FIFO_RESET_MASK = ( 1 << 7 ), /*!< FIFO_RESET Mask */
mcm 1:d4b35641a624 662 FIFO_C_FIFO_RESET_DISABLED = ( 0 << 7 ), /*!< FIFO reset is disabled, normal operation (default) */
mcm 1:d4b35641a624 663 FIFO_C_FIFO_RESET_ENABLED = ( 1 << 7 ) /*!< FIFO read and write pointers are cleared, FIFO contents returned to 0 */
mcm 1:d4b35641a624 664 } MC3635_fifo_c_fifo_reset_t;
mcm 1:d4b35641a624 665
mcm 1:d4b35641a624 666
mcm 1:d4b35641a624 667
mcm 1:d4b35641a624 668 /**
mcm 1:d4b35641a624 669 * @brief INTERRUPT CONTROL REGISTER
mcm 1:d4b35641a624 670 *
mcm 1:d4b35641a624 671 */
mcm 1:d4b35641a624 672 /* Bit 0 : IPP. */
mcm 1:d4b35641a624 673 typedef enum {
mcm 1:d4b35641a624 674 INTR_C_IPP_MASK = ( 1 << 0 ), /*!< IPP Mask */
mcm 1:d4b35641a624 675 INTR_C_IPP_OPEN_DRAIN_MODE = ( 0 << 0 ), /*!< INTN pin is configured for open-drain mode (external pull-up to VDDIO required) (default) */
mcm 1:d4b35641a624 676 INTR_C_IPP_PUSH_PULL_MODE = ( 1 << 0 ) /*!< INTN pin is configured for active drive or 'push-pull' mode. Drive level is to VDDIO */
mcm 1:d4b35641a624 677 } MC3635_intr_c_ipp_t;
mcm 1:d4b35641a624 678
mcm 1:d4b35641a624 679
mcm 1:d4b35641a624 680 /* Bit 1 : IAH. */
mcm 1:d4b35641a624 681 typedef enum {
mcm 1:d4b35641a624 682 INTR_C_IAH_MASK = ( 1 << 1 ), /*!< IAH Mask */
mcm 1:d4b35641a624 683 INTR_C_IAH_ACTIVE_LOW = ( 0 << 1 ), /*!< Interrupt request is active low (default). */
mcm 1:d4b35641a624 684 INTR_C_IAH_ACTIVE_HIGH = ( 1 << 1 ) /*!< Interrupt request is active high */
mcm 1:d4b35641a624 685 } MC3635_intr_c_iah_t;
mcm 1:d4b35641a624 686
mcm 1:d4b35641a624 687
mcm 1:d4b35641a624 688 /* Bit 2 : INT_WAKE. */
mcm 1:d4b35641a624 689 typedef enum {
mcm 1:d4b35641a624 690 INTR_C_INT_WAKE_MASK = ( 1 << 2 ), /*!< INT_WAKE Mask */
mcm 1:d4b35641a624 691 INTR_C_INT_WAKE_DISABLED = ( 0 << 2 ), /*!< No interrupt is generated when SNIFF activity is detected and the device auto-transitions to CWAKE mode (default) */
mcm 1:d4b35641a624 692 INTR_C_INT_WAKE_ENABLED = ( 1 << 2 ) /*!< Generate an interrupt when activity is detected in SNIFF mode and the device auto-transitions to CWAKE mode. */
mcm 1:d4b35641a624 693 } MC3635_intr_c_int_wake_t;
mcm 1:d4b35641a624 694
mcm 1:d4b35641a624 695
mcm 1:d4b35641a624 696 /* Bit 3 : INT_ACQ. */
mcm 1:d4b35641a624 697 typedef enum {
mcm 1:d4b35641a624 698 INTR_C_INT_ACQ_MASK = ( 1 << 3 ), /*!< INT_ACQ Mask */
mcm 1:d4b35641a624 699 INTR_C_INT_ACQ_DISABLED = ( 0 << 3 ), /*!< No interrupt generated when new sample data is acquired (default) */
mcm 1:d4b35641a624 700 INTR_C_INT_ACQ_ENABLED = ( 1 << 3 ) /*!< Generate an interrupt when new sample data is acquired (applies to new data written to output registers or FIFO). This enable is paired with the NEW_DATA flag in register 0x08 */
mcm 1:d4b35641a624 701 } MC3635_intr_c_int_acq_t;
mcm 1:d4b35641a624 702
mcm 1:d4b35641a624 703
mcm 1:d4b35641a624 704 /* Bit 4 : INT_FIFO_EMPTY. */
mcm 1:d4b35641a624 705 typedef enum {
mcm 1:d4b35641a624 706 INTR_C_INT_FIFO_EMPTY_MASK = ( 1 << 4 ), /*!< INT_FIFO_EMPTY Mask */
mcm 1:d4b35641a624 707 INTR_C_INT_FIFO_EMPTY_DISABLED = ( 0 << 4 ), /*!< No interrupt is generated when the FIFO is empty or completely drained of sample data (default) */
mcm 1:d4b35641a624 708 INTR_C_INT_FIFO_EMPTY_ENABLED = ( 1 << 4 ) /*!< Generate an interrupt when the FIFO is empty. This interrupt is paired with the FIFO_EMPTY flag in register 0x08. Note that this interrupt is independent of the FIFO threshold level, and will only activate when the FIFO sample count has reached a value of 0 */
mcm 1:d4b35641a624 709 } MC3635_intr_c_int_fifo_empty_t;
mcm 1:d4b35641a624 710
mcm 1:d4b35641a624 711
mcm 1:d4b35641a624 712 /* Bit 5 : INT_FIFO_FULL. */
mcm 1:d4b35641a624 713 typedef enum {
mcm 1:d4b35641a624 714 INTR_C_INT_FIFO_FULL_MASK = ( 1 << 5 ), /*!< INT_FIFO_FULL Mask */
mcm 1:d4b35641a624 715 INTR_C_INT_FIFO_FULL_DISABLED = ( 0 << 5 ), /*!< No interrupt is generated when the FIFO is empty or completely filled of sample data (default) */
mcm 1:d4b35641a624 716 INTR_C_INT_FIFO_FULL_ENABLED = ( 1 << 5 ) /*!< Generate an interrupt when the FIFO is full. This interrupt is paired with the FIFO_FULL flag in register 0x08. Note that this interrupt is independent of the FIFO threshold level, and will only activate when the FIFO sample count has reached a value of 32 */
mcm 1:d4b35641a624 717 } MC3635_intr_c_int_fifo_full_t;
mcm 1:d4b35641a624 718
mcm 1:d4b35641a624 719
mcm 1:d4b35641a624 720 /* Bit 6 : INT_FIFO_THRESH. */
mcm 1:d4b35641a624 721 typedef enum {
mcm 1:d4b35641a624 722 INTR_C_INT_FIFO_THRESH_MASK = ( 1 << 6 ), /*!< INT_FIFO_THRESH Mask */
mcm 1:d4b35641a624 723 INTR_C_INT_FIFO_THRESH_DISABLED = ( 0 << 6 ), /*!< No interrupt is generated when the FIFO threshold level is reached (default) */
mcm 1:d4b35641a624 724 INTR_C_INT_FIFO_THRESH_ENABLED = ( 1 << 6 ) /*!< Generate an interrupt when the FIFO threshold level is reached */
mcm 1:d4b35641a624 725 } MC3635_intr_c_int_fifo_thresh_t;
mcm 1:d4b35641a624 726
mcm 1:d4b35641a624 727
mcm 1:d4b35641a624 728 /* Bit 7 : INT_SWAKE. */
mcm 1:d4b35641a624 729 typedef enum {
mcm 1:d4b35641a624 730 INTR_C_INT_SWAKE_MASK = ( 1 << 7 ), /*!< INT_SWAKE Mask */
mcm 1:d4b35641a624 731 INTR_C_INT_SWAKE_DISABLED = ( 0 << 7 ), /*!< No interrupt generated when SNIFF activity is detected (default) */
mcm 1:d4b35641a624 732 INTR_C_INT_SWAKE_ENABLED = ( 1 << 7 ) /*!< Generate an interrupt when SNIFF activity is detected */
mcm 1:d4b35641a624 733 } MC3635_intr_c_int_fifo_swake_t;
mcm 1:d4b35641a624 734
mcm 1:d4b35641a624 735
mcm 1:d4b35641a624 736
mcm 1:d4b35641a624 737 /**
mcm 1:d4b35641a624 738 * @brief INITIALIZATION REGISTER 3
mcm 1:d4b35641a624 739 *
mcm 1:d4b35641a624 740 * Software must write a fixed value to this register immediately after power-up or reset
mcm 1:d4b35641a624 741 */
mcm 1:d4b35641a624 742 /* Bits 7:0 : INIT_3. */
mcm 1:d4b35641a624 743 typedef enum {
mcm 1:d4b35641a624 744 INIT_3_INT_3_FIXED_VALUE = 0 /*!< INIT_3 fixed value */
mcm 1:d4b35641a624 745 } MC3635_init_3_int_3t;
mcm 1:d4b35641a624 746
mcm 1:d4b35641a624 747
mcm 1:d4b35641a624 748
mcm 1:d4b35641a624 749 /**
mcm 1:d4b35641a624 750 * @brief POWER MODE CONTROL REGISTER
mcm 1:d4b35641a624 751 *
mcm 1:d4b35641a624 752 * This register selects the power setting for CWAKE, SWAKE and SNIFF modes.
mcm 1:d4b35641a624 753 */
mcm 1:d4b35641a624 754 /* Bits 2:0 : CSPM. */
mcm 1:d4b35641a624 755 typedef enum {
mcm 1:d4b35641a624 756 PMCR_CSPM_MASK = ( 0b111 << 0 ), /*!< CSPM Mask */
mcm 1:d4b35641a624 757 PMCR_CSPM_LOW_POWER_MODE = ( 0b000 << 0 ), /*!< Low Power Mode (nominal noise levels) (default) */
mcm 1:d4b35641a624 758 PMCR_CSPM_ULTRA_LOW_POWER_MODE = ( 0b011 << 0 ), /*!< Ultra-Low Power Mode (highest noise levels) */
mcm 1:d4b35641a624 759 PMCR_CSPM_PRECISION_MODE = ( 0b100 << 0 ) /*!< Precision Mode (lowest noise levels) */
mcm 1:d4b35641a624 760 } MC3635_pmcr_cspm_t;
mcm 1:d4b35641a624 761
mcm 1:d4b35641a624 762
mcm 1:d4b35641a624 763 /* Bits 6:4 : SPM. */
mcm 1:d4b35641a624 764 typedef enum {
mcm 1:d4b35641a624 765 PMCR_SPM_MASK = ( 0b111 << 4 ), /*!< SPM Mask */
mcm 1:d4b35641a624 766 PMCR_SPM_LOW_POWER_MODE = ( 0b000 << 4 ), /*!< Low Power Mode (nominal noise levels) (default) */
mcm 1:d4b35641a624 767 PMCR_SPM_ULTRA_LOW_POWER_MODE = ( 0b011 << 4 ), /*!< Ultra-Low Power Mode (highest noise levels) */
mcm 1:d4b35641a624 768 PMCR_SPM_PRECISION_MODE = ( 0b100 << 4 ) /*!< Precision Mode (lowest noise levels) */
mcm 1:d4b35641a624 769 } MC3635_pmcr_spm_t;
mcm 1:d4b35641a624 770
mcm 1:d4b35641a624 771
mcm 1:d4b35641a624 772 /* Bit 7 : SPI_HS_EN. */
mcm 1:d4b35641a624 773 typedef enum {
mcm 1:d4b35641a624 774 PMCR_SPI_HS_EN_MASK = ( 1 << 7 ), /*!< SPI_HS_EN Mask */
mcm 1:d4b35641a624 775 PMCR_SPI_HS_EN_DISABLED = ( 0 << 7 ), /*!< This bit will always return a '0' when read. Software must keep track of the state of this bit */
mcm 1:d4b35641a624 776 PMCR_SPI_HS_EN_ENABLED = ( 1 << 7 ) /*!< SPI High-Speed Enable */
mcm 1:d4b35641a624 777 } MC3635_pmcr_spi_hs_en_t;
mcm 1:d4b35641a624 778
mcm 1:d4b35641a624 779
mcm 1:d4b35641a624 780
mcm 1:d4b35641a624 781 /**
mcm 1:d4b35641a624 782 * @brief DRIVE MOTION X REGISTER
mcm 1:d4b35641a624 783 *
mcm 1:d4b35641a624 784 * This register controls the test mode which moves the sensor in the X axis direction and initializes specific hardware bits.
mcm 1:d4b35641a624 785 */
mcm 1:d4b35641a624 786 /* Bit 2 : DPX. */
mcm 1:d4b35641a624 787 typedef enum {
mcm 1:d4b35641a624 788 DMX_DPX_MASK = ( 1 << 2 ), /*!< DPX Mask */
mcm 1:d4b35641a624 789 DMX_DPX_DISABLED = ( 0 << 2 ), /*!< Disabled (default) */
mcm 1:d4b35641a624 790 DMX_DPX_ENABLED = ( 1 << 2 ) /*!< Move the sensor in X Positive direction */
mcm 1:d4b35641a624 791 } MC3635_dmx_dpx_t;
mcm 1:d4b35641a624 792
mcm 1:d4b35641a624 793
mcm 1:d4b35641a624 794 /* Bit 3 : DNX. */
mcm 1:d4b35641a624 795 typedef enum {
mcm 1:d4b35641a624 796 DMX_DNX_MASK = ( 1 << 3 ), /*!< DNX Mask */
mcm 1:d4b35641a624 797 DMX_DNX_DISABLED = ( 0 << 3 ), /*!< Disabled (default) */
mcm 1:d4b35641a624 798 DMX_DNX_ENABLED = ( 1 << 3 ) /*!< Move the sensor in X Negative direction */
mcm 1:d4b35641a624 799 } MC3635_dmx_dpnx_t;
mcm 1:d4b35641a624 800
mcm 1:d4b35641a624 801
mcm 1:d4b35641a624 802
mcm 1:d4b35641a624 803 /**
mcm 1:d4b35641a624 804 * @brief DRIVE MOTION Y REGISTER
mcm 1:d4b35641a624 805 *
mcm 1:d4b35641a624 806 * This register controls the test mode which moves the sensor in the Y axis direction and initializes specific hardware bits.
mcm 1:d4b35641a624 807 */
mcm 1:d4b35641a624 808 /* Bit 2 : DPY. */
mcm 1:d4b35641a624 809 typedef enum {
mcm 1:d4b35641a624 810 DMY_DPX_MASK = ( 1 << 2 ), /*!< DPY Mask */
mcm 1:d4b35641a624 811 DMY_DPX_DISABLED = ( 0 << 2 ), /*!< Disabled (default) */
mcm 1:d4b35641a624 812 DMY_DPX_ENABLED = ( 1 << 2 ) /*!< Move the sensor in Y Positive direction */
mcm 1:d4b35641a624 813 } MC3635_dmy_dpy_t;
mcm 1:d4b35641a624 814
mcm 1:d4b35641a624 815
mcm 1:d4b35641a624 816 /* Bit 3 : DNY. */
mcm 1:d4b35641a624 817 typedef enum {
mcm 1:d4b35641a624 818 DMY_DNY_MASK = ( 1 << 3 ), /*!< DNY Mask */
mcm 1:d4b35641a624 819 DMY_DNY_DISABLED = ( 0 << 3 ), /*!< Disabled (default) */
mcm 1:d4b35641a624 820 DMY_DNY_ENABLED = ( 1 << 3 ) /*!< Move the sensor in Y Negative direction */
mcm 1:d4b35641a624 821 } MC3635_dmy_dpny_t;
mcm 1:d4b35641a624 822
mcm 1:d4b35641a624 823
mcm 1:d4b35641a624 824
mcm 1:d4b35641a624 825 /**
mcm 1:d4b35641a624 826 * @brief DRIVE MOTION Z REGISTER
mcm 1:d4b35641a624 827 *
mcm 1:d4b35641a624 828 * This register controls the test mode which moves the sensor in the Z axis direction.
mcm 1:d4b35641a624 829 */
mcm 1:d4b35641a624 830 /* Bit 2 : DPZ. */
mcm 1:d4b35641a624 831 typedef enum {
mcm 1:d4b35641a624 832 DMZ_DPZ_MASK = ( 1 << 2 ), /*!< DPZ Mask */
mcm 1:d4b35641a624 833 DMZ_DPZ_DISABLED = ( 0 << 2 ), /*!< Disabled (default) */
mcm 1:d4b35641a624 834 DMZ_DPZ_ENABLED = ( 1 << 2 ) /*!< Move the sensor in Z Positive direction */
mcm 1:d4b35641a624 835 } MC3635_dmz_dpz_t;
mcm 1:d4b35641a624 836
mcm 1:d4b35641a624 837
mcm 1:d4b35641a624 838 /* Bit 3 : DNZ. */
mcm 1:d4b35641a624 839 typedef enum {
mcm 1:d4b35641a624 840 DMZ_DNZ_MASK = ( 1 << 3 ), /*!< DNZ Mask */
mcm 1:d4b35641a624 841 DMZ_DNZ_DISABLED = ( 0 << 3 ), /*!< Disabled (default) */
mcm 1:d4b35641a624 842 DMZ_DNZ_ENABLED = ( 1 << 3 ) /*!< Move the sensor in Z Negative direction */
mcm 1:d4b35641a624 843 } MC3635_dmz_dpnz_t;
mcm 1:d4b35641a624 844
mcm 1:d4b35641a624 845
mcm 1:d4b35641a624 846
mcm 1:d4b35641a624 847 /**
mcm 1:d4b35641a624 848 * @brief RESET REGISTER
mcm 1:d4b35641a624 849 *
mcm 1:d4b35641a624 850 * This register can be used to reset the device. Anytime there is a reset to the device, a POR event, or a
mcm 1:d4b35641a624 851 * power cycle the SPI 3-wire configuration will reset to 4-wire mode.
mcm 1:d4b35641a624 852 */
mcm 1:d4b35641a624 853 /* Bit 6 : RESET. */
mcm 1:d4b35641a624 854 typedef enum {
mcm 1:d4b35641a624 855 RESET_RESET_MASK = ( 1 << 6 ), /*!< RESET Mask */
mcm 1:d4b35641a624 856 RESET_RESET_NORMAL_OPERATION = ( 0 << 6 ), /*!< Normal operation (default) */
mcm 1:d4b35641a624 857 RESET_RESET_FORCE_POWER_ON_RESET = ( 1 << 6 ) /*!< Force a power-on-reset (POR) sequence */
mcm 1:d4b35641a624 858 } MC3635_reset_reset_t;
mcm 1:d4b35641a624 859
mcm 1:d4b35641a624 860
mcm 1:d4b35641a624 861 /* Bit 7 : RELOAD. */
mcm 1:d4b35641a624 862 typedef enum {
mcm 1:d4b35641a624 863 RESET_RELOAD_MASK = ( 1 << 7 ), /*!< RELOAD Mask */
mcm 1:d4b35641a624 864 RESET_RELOAD_NORMAL_OPERATION = ( 0 << 7 ), /*!< Normal operation (default) */
mcm 1:d4b35641a624 865 RESET_RELOAD_RELOAD_REGISTER_FROM_OTP = ( 1 << 7 ) /*!< Reloads the registers from OTP */
mcm 1:d4b35641a624 866 } MC3635_reset_reload_t;
mcm 1:d4b35641a624 867
mcm 1:d4b35641a624 868
mcm 1:d4b35641a624 869
mcm 1:d4b35641a624 870 /**
mcm 1:d4b35641a624 871 * @brief INITIALIZATION REGISTER 2
mcm 1:d4b35641a624 872 *
mcm 1:d4b35641a624 873 * Software must write a fixed value to this register immediately after power-up or reset
mcm 1:d4b35641a624 874 */
mcm 1:d4b35641a624 875 /* Bits 7:0 : INIT_2. */
mcm 1:d4b35641a624 876 typedef enum {
mcm 1:d4b35641a624 877 INIT_2_INT_2_FIXED_VALUE = 0 /*!< INIT_2 fixed value */
mcm 1:d4b35641a624 878 } MC3635_init_2_int_2_t;
mcm 1:d4b35641a624 879
mcm 1:d4b35641a624 880
mcm 1:d4b35641a624 881
mcm 1:d4b35641a624 882 /**
mcm 1:d4b35641a624 883 * @brief TRIGGER COUNT REGISTER
mcm 1:d4b35641a624 884 *
mcm 1:d4b35641a624 885 * This register selects the number of samples to be taken after the one-shot trigger is started
mcm 1:d4b35641a624 886 */
mcm 1:d4b35641a624 887 /* Bits 7:0 : TRIGC. */
mcm 1:d4b35641a624 888 typedef enum {
mcm 1:d4b35641a624 889 TRIGC_MASK = 0xFF /*!< TRIGC Mask */
mcm 1:d4b35641a624 890 } MC3635_trigc_t;
mcm 1:d4b35641a624 891
mcm 1:d4b35641a624 892
mcm 1:d4b35641a624 893
mcm 1:d4b35641a624 894
mcm 1:d4b35641a624 895 /**
mcm 1:d4b35641a624 896 * @brief X-AXIS OFFSET REGISTERS
mcm 1:d4b35641a624 897 *
mcm 1:d4b35641a624 898 * This register contains a signed 2's complement 15-bit value applied as an offset adjustment to the output
mcm 1:d4b35641a624 899 * of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each
mcm 1:d4b35641a624 900 * chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software.
mcm 1:d4b35641a624 901 */
mcm 1:d4b35641a624 902 /* Bits 7:0 : XOFFL. */
mcm 1:d4b35641a624 903 typedef enum {
mcm 1:d4b35641a624 904 XOFFL_MASK = 0xFF /*!< XOFFL Mask */
mcm 1:d4b35641a624 905 } MC3635_x_axis_offset_xoffl_t;
mcm 1:d4b35641a624 906
mcm 1:d4b35641a624 907
mcm 1:d4b35641a624 908 /* Bits 7:0 : XOFFH. */
mcm 1:d4b35641a624 909 typedef enum {
mcm 1:d4b35641a624 910 XOFFH_MASK = ( 0b01111111 << 0 ) /*!< XOFFH Mask */
mcm 1:d4b35641a624 911 } MC3635_x_axis_offset_xoffh_t;
mcm 1:d4b35641a624 912
mcm 1:d4b35641a624 913
mcm 1:d4b35641a624 914
mcm 1:d4b35641a624 915 /**
mcm 1:d4b35641a624 916 * @brief Y-AXIS OFFSET REGISTERS
mcm 1:d4b35641a624 917 *
mcm 1:d4b35641a624 918 * This register contains a signed 2's complement 15-bit value applied as an offset adjustment to the output
mcm 1:d4b35641a624 919 * of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each
mcm 1:d4b35641a624 920 * chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software.
mcm 1:d4b35641a624 921 */
mcm 1:d4b35641a624 922 /* Bits 7:0 : YOFFL. */
mcm 1:d4b35641a624 923 typedef enum {
mcm 1:d4b35641a624 924 YOFFL_MASK = 0xFF /*!< YOFFL Mask */
mcm 1:d4b35641a624 925 } MC3635_y_axis_offset_yoffl_t;
mcm 1:d4b35641a624 926
mcm 1:d4b35641a624 927
mcm 1:d4b35641a624 928 /* Bits 7:0 : YOFFH. */
mcm 1:d4b35641a624 929 typedef enum {
mcm 1:d4b35641a624 930 YOFFH_MASK = ( 0b01111111 << 0 ) /*!< YOFFH Mask */
mcm 1:d4b35641a624 931 } MC3635_y_axis_offset_yoffh_t;
mcm 1:d4b35641a624 932
mcm 1:d4b35641a624 933
mcm 1:d4b35641a624 934
mcm 1:d4b35641a624 935 /**
mcm 1:d4b35641a624 936 * @brief Z-AXIS OFFSET REGISTERS
mcm 1:d4b35641a624 937 *
mcm 1:d4b35641a624 938 * This register contains a signed 2's complement 15-bit value applied as an offset adjustment to the output
mcm 1:d4b35641a624 939 * of the acceleration values, prior to being sent to the OUT_EX registers. The Power-On-Reset value for each
mcm 1:d4b35641a624 940 * chip is unique and is set as part of factory calibration. If necessary, this value can be overwritten by software.
mcm 1:d4b35641a624 941 */
mcm 1:d4b35641a624 942 /* Bits 7:0 : ZOFFL. */
mcm 1:d4b35641a624 943 typedef enum {
mcm 1:d4b35641a624 944 ZOFFL_MASL = 0xFF /*!< ZOFFL Mask */
mcm 1:d4b35641a624 945 } MC3635_z_axis_offset_zoffl_t;
mcm 1:d4b35641a624 946
mcm 1:d4b35641a624 947
mcm 1:d4b35641a624 948 /* Bits 7:0 : ZOFFH. */
mcm 1:d4b35641a624 949 typedef enum {
mcm 1:d4b35641a624 950 ZOFFH_MASK = ( 0b01111111 << 0 ) /*!< ZOFFH Mask */
mcm 1:d4b35641a624 951 } MC3635_z_axis_offset_zoffh_t;
mcm 1:d4b35641a624 952
mcm 1:d4b35641a624 953
mcm 1:d4b35641a624 954
mcm 1:d4b35641a624 955 /**
mcm 1:d4b35641a624 956 * @brief X-AXIS GAIN REGISTERS
mcm 1:d4b35641a624 957 *
mcm 1:d4b35641a624 958 * The gain value is an unsigned 9-bit number.
mcm 1:d4b35641a624 959 */
mcm 1:d4b35641a624 960 /* Bits 7:0 : GAIN LSB. */
mcm 1:d4b35641a624 961 typedef enum {
mcm 1:d4b35641a624 962 XGAINL_GAIN_MASK = 0xFF /*!< XGAINL GAIN Mask */
mcm 1:d4b35641a624 963 } MC3635_x_axis_xgainl_t;
mcm 1:d4b35641a624 964
mcm 1:d4b35641a624 965
mcm 1:d4b35641a624 966 /* Bits 7:0 : GAIN HSB. */
mcm 1:d4b35641a624 967 typedef enum {
mcm 1:d4b35641a624 968 XGAINH_GAIN_MASK = ( 1 << 7 ) /*!< XGAINH GAIN Mask */
mcm 1:d4b35641a624 969 } MC3635_x_axis_xgainh_t;
mcm 1:d4b35641a624 970
mcm 1:d4b35641a624 971
mcm 1:d4b35641a624 972
mcm 1:d4b35641a624 973 /**
mcm 1:d4b35641a624 974 * @brief Y-AXIS GAIN REGISTERS
mcm 1:d4b35641a624 975 *
mcm 1:d4b35641a624 976 * The gain value is an unsigned 9-bit number.
mcm 1:d4b35641a624 977 */
mcm 1:d4b35641a624 978 /* Bits 7:0 : GAIN LSB. */
mcm 1:d4b35641a624 979 typedef enum {
mcm 1:d4b35641a624 980 YGAINL_GAIN_MASK = 0xFF /*!< YGAINL GAIN Mask */
mcm 1:d4b35641a624 981 } MC3635_y_axis_ygainl_t;
mcm 1:d4b35641a624 982
mcm 1:d4b35641a624 983
mcm 1:d4b35641a624 984 /* Bits 7:0 : GAIN HSB. */
mcm 1:d4b35641a624 985 typedef enum {
mcm 1:d4b35641a624 986 YGAINH_GAIN_MASK = ( 1 << 7 ) /*!< YGAINH GAIN Mask */
mcm 1:d4b35641a624 987 } MC3635_y_axis_ygainh_t;
mcm 1:d4b35641a624 988
mcm 1:d4b35641a624 989
mcm 1:d4b35641a624 990
mcm 1:d4b35641a624 991 /**
mcm 1:d4b35641a624 992 * @brief Z-AXIS GAIN REGISTERS
mcm 1:d4b35641a624 993 *
mcm 1:d4b35641a624 994 * The gain value is an unsigned 9-bit number.
mcm 1:d4b35641a624 995 */
mcm 1:d4b35641a624 996 /* Bits 7:0 : GAIN LSB. */
mcm 1:d4b35641a624 997 typedef enum {
mcm 1:d4b35641a624 998 ZGAINL_GAIN_MASK = 0xFF /*!< ZGAINL GAIN Mask */
mcm 1:d4b35641a624 999 } MC3635_z_axis_zgainl_t;
mcm 1:d4b35641a624 1000
mcm 1:d4b35641a624 1001
mcm 1:d4b35641a624 1002 /* Bits 7:0 : GAIN HSB. */
mcm 1:d4b35641a624 1003 typedef enum {
mcm 1:d4b35641a624 1004 ZGAINH_GAIN_MASK = ( 1 << 7 ) /*!< ZGAINH GAIN Mask */
mcm 1:d4b35641a624 1005 } MC3635_z_axis_zgainh_t;
mcm 1:d4b35641a624 1006
mcm 1:d4b35641a624 1007
mcm 1:d4b35641a624 1008
mcm 1:d4b35641a624 1009
mcm 1:d4b35641a624 1010
mcm 1:d4b35641a624 1011 /**
mcm 1:d4b35641a624 1012 * @brief POWER MODE FOR SNIFF, CWAKE and SWAKE
mcm 1:d4b35641a624 1013 *
mcm 1:d4b35641a624 1014 */
mcm 1:d4b35641a624 1015 typedef enum {
mcm 1:d4b35641a624 1016 ULTRA_LOW_POWER_MODE = 0b011, /*!< MODE: ULTRA-LOW POWER MODE */
mcm 1:d4b35641a624 1017 LOW_POWER_MODE = 0b000, /*!< MODE: LOW POWER MODE */
mcm 1:d4b35641a624 1018 PRECISION = 0b100 /*!< MODE: PRECISION */
mcm 1:d4b35641a624 1019 } MC3635_power_mode_t;
mcm 1:d4b35641a624 1020
mcm 1:d4b35641a624 1021
mcm 1:d4b35641a624 1022 /**
mcm 1:d4b35641a624 1023 * @brief SAMPLE RATE FOR SNIFF, CWAKE and SWAKE
mcm 1:d4b35641a624 1024 *
mcm 1:d4b35641a624 1025 */
mcm 1:d4b35641a624 1026 typedef enum {
mcm 1:d4b35641a624 1027 ODR_0 = 0b0000, /*!< ODR: 0b0000 */
mcm 1:d4b35641a624 1028 ODR_1 = 0b0001, /*!< ODR: 0b0001 */
mcm 1:d4b35641a624 1029 ODR_2 = 0b0010, /*!< ODR: 0b0010 */
mcm 1:d4b35641a624 1030 ODR_3 = 0b0011, /*!< ODR: 0b0011 */
mcm 1:d4b35641a624 1031 ODR_4 = 0b0100, /*!< ODR: 0b0100 */
mcm 1:d4b35641a624 1032 ODR_5 = 0b0101, /*!< ODR: 0b0101 */
mcm 1:d4b35641a624 1033 ODR_6 = 0b0110, /*!< ODR: 0b0110 */
mcm 1:d4b35641a624 1034 ODR_7 = 0b0111, /*!< ODR: 0b0111 */
mcm 1:d4b35641a624 1035 ODR_8 = 0b1000, /*!< ODR: 0b1000 */
mcm 1:d4b35641a624 1036 ODR_9 = 0b1001, /*!< ODR: 0b1001 */
mcm 1:d4b35641a624 1037 ODR_10 = 0b1010, /*!< ODR: 0b1010 */
mcm 1:d4b35641a624 1038 ODR_11 = 0b1011, /*!< ODR: 0b1011 */
mcm 1:d4b35641a624 1039 ODR_12 = 0b1100, /*!< ODR: 0b1100 */
mcm 1:d4b35641a624 1040 ODR_13 = 0b1101, /*!< ODR: 0b1101 */
mcm 1:d4b35641a624 1041 ODR_14 = 0b1110, /*!< ODR: 0b1110 */
mcm 1:d4b35641a624 1042 ODR_15 = 0b1111 /*!< ODR: 0b1111 */
mcm 1:d4b35641a624 1043 } MC3635_sample_rate_t;
mcm 1:d4b35641a624 1044
mcm 1:d4b35641a624 1045
mcm 1:d4b35641a624 1046
mcm 1:d4b35641a624 1047 /**
mcm 1:d4b35641a624 1048 * @brief AXIS
mcm 1:d4b35641a624 1049 *
mcm 1:d4b35641a624 1050 */
mcm 1:d4b35641a624 1051 typedef enum {
mcm 1:d4b35641a624 1052 X_AXIS = 0, /*!< X-Axis chosen */
mcm 1:d4b35641a624 1053 Y_AXIS = 1, /*!< Y-Axis chosen */
mcm 1:d4b35641a624 1054 Z_AXIS = 2 /*!< Z-Axis chosen */
mcm 1:d4b35641a624 1055 } MC3635_axis_t;
mcm 1:d4b35641a624 1056
mcm 1:d4b35641a624 1057
mcm 1:d4b35641a624 1058
mcm 1:d4b35641a624 1059
mcm 1:d4b35641a624 1060 #ifndef MC3635_VECTOR_STRUCT_H
mcm 1:d4b35641a624 1061 #define MC3635_VECTOR_STRUCT_H
mcm 1:d4b35641a624 1062 typedef struct {
mcm 1:d4b35641a624 1063 int16_t XAxis_mg; /*!< X Axis raw data in mg */
mcm 1:d4b35641a624 1064 int16_t YAxis_mg; /*!< Y Axis raw data in mg */
mcm 1:d4b35641a624 1065 int16_t ZAxis_mg; /*!< Z Axis raw data in mg */
mcm 1:d4b35641a624 1066
mcm 1:d4b35641a624 1067 uint8_t scratch; /*!< Any value can be written and read-back */
mcm 1:d4b35641a624 1068 uint8_t ext_stat_2; /*!< It contains the value for the Extended Status Register 2 */
mcm 1:d4b35641a624 1069 uint8_t status_1; /*!< It contains the value for the Status Register 1 */
mcm 1:d4b35641a624 1070 uint8_t status_2; /*!< It contains the value for the Status Register 2 */
mcm 1:d4b35641a624 1071 uint8_t FeatureRegister1; /*!< It contains the value for the Feature Register 1 */
mcm 1:d4b35641a624 1072 uint8_t FeatureRegister2; /*!< It contains the value for the Feature Register 2 */
mcm 1:d4b35641a624 1073
mcm 1:d4b35641a624 1074 MC3635_range_c_res_t resolution; /*!< It contains the accelerometer resolution */
mcm 1:d4b35641a624 1075 MC3635_range_c_range_t range; /*!< It contains the accelerometer range */
mcm 1:d4b35641a624 1076
mcm 1:d4b35641a624 1077 uint16_t XGAIN; /*!< It contains the value for X-Axis gain */
mcm 1:d4b35641a624 1078 uint16_t YGAIN; /*!< It contains the value for Y-Axis gain */
mcm 1:d4b35641a624 1079 uint16_t ZGAIN; /*!< It contains the value for Z-Axis gain */
mcm 1:d4b35641a624 1080
mcm 1:d4b35641a624 1081 int16_t XOffset; /*!< It contains the value for X-Axis offset */
mcm 1:d4b35641a624 1082 int16_t YOffset; /*!< It contains the value for Y-Axis offset */
mcm 1:d4b35641a624 1083 int16_t ZOffset; /*!< It contains the value for Z-Axis offset */
mcm 1:d4b35641a624 1084 } MC3635_data_t;
mcm 1:d4b35641a624 1085 #endif
mcm 1:d4b35641a624 1086
mcm 1:d4b35641a624 1087
mcm 1:d4b35641a624 1088
mcm 1:d4b35641a624 1089 /**
mcm 1:d4b35641a624 1090 * @brief INTERNAL CONSTANTS
mcm 1:d4b35641a624 1091 */
mcm 1:d4b35641a624 1092 typedef enum {
mcm 1:d4b35641a624 1093 MC3635_SUCCESS = 0,
mcm 1:d4b35641a624 1094 MC3635_FAILURE = 1,
mcm 1:d4b35641a624 1095 I2C_SUCCESS = 1
mcm 1:d4b35641a624 1096 } MC3635_status_t;
mcm 1:d4b35641a624 1097
mcm 1:d4b35641a624 1098
mcm 1:d4b35641a624 1099
mcm 1:d4b35641a624 1100
mcm 1:d4b35641a624 1101 /** Create an MC3635 object connected to the specified SPI pins.
mcm 1:d4b35641a624 1102 *
mcm 1:d4b35641a624 1103 * @param sda I2C data pin
mcm 1:d4b35641a624 1104 * @param scl I2C clock pin
mcm 1:d4b35641a624 1105 * @param addr I2C slave address
mcm 1:d4b35641a624 1106 * @param freq I2C frequency in Hz.
mcm 1:d4b35641a624 1107 */
mcm 1:d4b35641a624 1108 MC3635 ( PinName sda, PinName scl, uint32_t addr, uint32_t freq );
mcm 1:d4b35641a624 1109
mcm 1:d4b35641a624 1110 /** Delete MC3635 object.
mcm 1:d4b35641a624 1111 */
mcm 1:d4b35641a624 1112 ~MC3635();
mcm 1:d4b35641a624 1113
mcm 1:d4b35641a624 1114 /** It starts an initialization sequence.
mcm 1:d4b35641a624 1115 */
mcm 1:d4b35641a624 1116 MC3635_status_t MC3635_InitializationSequence ( void );
mcm 1:d4b35641a624 1117
mcm 1:d4b35641a624 1118 /** It writes into the scratch pad register.
mcm 1:d4b35641a624 1119 */
mcm 1:d4b35641a624 1120 MC3635_status_t MC3635_WriteScratchpadRegister ( MC3635_data_t myScratchpadRegister );
mcm 1:d4b35641a624 1121
mcm 1:d4b35641a624 1122 /** It reads the scratch pad register.
mcm 1:d4b35641a624 1123 */
mcm 1:d4b35641a624 1124 MC3635_status_t MC3635_ReadScratchpadRegister ( MC3635_data_t* myScratchpadRegister );
mcm 1:d4b35641a624 1125
mcm 1:d4b35641a624 1126 /** It performs a software reset.
mcm 1:d4b35641a624 1127 */
mcm 1:d4b35641a624 1128 MC3635_status_t MC3635_SetSoftwareReset ( void );
mcm 1:d4b35641a624 1129
mcm 1:d4b35641a624 1130 /** It performs a reload.
mcm 1:d4b35641a624 1131 */
mcm 1:d4b35641a624 1132 MC3635_status_t MC3635_SetReload ( void );
mcm 1:d4b35641a624 1133
mcm 1:d4b35641a624 1134 /** It reads the Extended Status Register 2.
mcm 1:d4b35641a624 1135 */
mcm 1:d4b35641a624 1136 MC3635_status_t MC3635_ReadExtendedStatusRegister2 ( MC3635_data_t* myExt_stat_2 );
mcm 1:d4b35641a624 1137
mcm 1:d4b35641a624 1138 /** It reads X, Y and Z raw data output.
mcm 1:d4b35641a624 1139 */
mcm 1:d4b35641a624 1140 MC3635_status_t MC3635_ReadRawData ( MC3635_data_t* myRawData );
mcm 1:d4b35641a624 1141
mcm 1:d4b35641a624 1142 /** It reads the Status Register 1.
mcm 1:d4b35641a624 1143 */
mcm 1:d4b35641a624 1144 MC3635_status_t MC3635_ReadStatusRegister1 ( MC3635_data_t* myStatus_1 );
mcm 1:d4b35641a624 1145
mcm 1:d4b35641a624 1146 /** It reads the Status Register 2.
mcm 1:d4b35641a624 1147 */
mcm 1:d4b35641a624 1148 MC3635_status_t MC3635_ReadStatusRegister2 ( MC3635_data_t* myStatus_2 );
mcm 1:d4b35641a624 1149
mcm 1:d4b35641a624 1150 /** It reads the Feature Register 1.
mcm 1:d4b35641a624 1151 */
mcm 1:d4b35641a624 1152 MC3635_status_t MC3635_ReadFeatureRegister1 ( MC3635_data_t* myFeatureRegister1 );
mcm 1:d4b35641a624 1153
mcm 1:d4b35641a624 1154 /** It reads the Feature Register 2.
mcm 1:d4b35641a624 1155 */
mcm 1:d4b35641a624 1156 MC3635_status_t MC3635_ReadFeatureRegister2 ( MC3635_data_t* myFeatureRegister2 );
mcm 1:d4b35641a624 1157
mcm 1:d4b35641a624 1158 /** It enables/disables X/Y/Z Axis.
mcm 1:d4b35641a624 1159 */
mcm 1:d4b35641a624 1160 MC3635_status_t MC3635_EnableAxis ( MC3635_mode_c_x_axis_pd_t myXAxis, MC3635_mode_c_y_axis_pd_t myYAxis, MC3635_mode_c_z_axis_pd_t myZAxis );
mcm 1:d4b35641a624 1161
mcm 1:d4b35641a624 1162 /** It sets the clock rate for STANDBY mode.
mcm 1:d4b35641a624 1163 */
mcm 1:d4b35641a624 1164 MC3635_status_t MC3635_SetStandbyClockRate ( MC3635_sniff_c_stb_rate_t myStandbyCloclRate );
mcm 1:d4b35641a624 1165
mcm 1:d4b35641a624 1166 /** It sets the accelerometer resolution.
mcm 1:d4b35641a624 1167 */
mcm 1:d4b35641a624 1168 MC3635_status_t MC3635_SetResolution ( MC3635_range_c_res_t myResolution );
mcm 1:d4b35641a624 1169
mcm 1:d4b35641a624 1170 /** It reads the accelerometer resolution.
mcm 1:d4b35641a624 1171 */
mcm 1:d4b35641a624 1172 MC3635_status_t MC3635_GetResolution ( MC3635_data_t* myResolution );
mcm 1:d4b35641a624 1173
mcm 1:d4b35641a624 1174 /** It sets the accelerometer range.
mcm 1:d4b35641a624 1175 */
mcm 1:d4b35641a624 1176 MC3635_status_t MC3635_SetRange ( MC3635_range_c_range_t myRange );
mcm 1:d4b35641a624 1177
mcm 1:d4b35641a624 1178 /** It reads the accelerometer range.
mcm 1:d4b35641a624 1179 */
mcm 1:d4b35641a624 1180 MC3635_status_t MC3635_GetRange ( MC3635_data_t* myRange );
mcm 1:d4b35641a624 1181
mcm 1:d4b35641a624 1182 /** It sets the FIFO behavior.
mcm 1:d4b35641a624 1183 */
mcm 1:d4b35641a624 1184 MC3635_status_t MC3635_SetFIFO ( uint8_t myNumberOfSamples, MC3635_fifo_c_fifo_mode_t myFIFO_Mode );
mcm 1:d4b35641a624 1185
mcm 1:d4b35641a624 1186 /** It enables/disables the FIFO.
mcm 1:d4b35641a624 1187 */
mcm 1:d4b35641a624 1188 MC3635_status_t MC3635_EnableFIFO ( MC3635_fifo_c_fifo_en_t myFIFO_Enable );
mcm 1:d4b35641a624 1189
mcm 1:d4b35641a624 1190 /** It resets the FIFO pointers.
mcm 1:d4b35641a624 1191 */
mcm 1:d4b35641a624 1192 MC3635_status_t MC3635_ResetFIFO ( void );
mcm 1:d4b35641a624 1193
mcm 1:d4b35641a624 1194 /** It configures the interrupt pin mode and level control.
mcm 1:d4b35641a624 1195 */
mcm 1:d4b35641a624 1196 MC3635_status_t MC3635_Conf_INTN ( MC3635_intr_c_ipp_t myINTN_ModeControl, MC3635_intr_c_iah_t myINTN_LevelControl );
mcm 1:d4b35641a624 1197
mcm 1:d4b35641a624 1198 /** It activates the interrupts on INTN pin.
mcm 1:d4b35641a624 1199 */
mcm 1:d4b35641a624 1200 MC3635_status_t MC3635_Set_INTN ( MC3635_intr_c_int_wake_t myINT_WakeMode, MC3635_intr_c_int_acq_t myINT_ACQMode,
mcm 1:d4b35641a624 1201 MC3635_intr_c_int_fifo_empty_t myINT_FIFO_EmptyMode, MC3635_intr_c_int_fifo_full_t myINT_FIFO_FullMode,
mcm 1:d4b35641a624 1202 MC3635_intr_c_int_fifo_thresh_t myINT_FIFO_ThreshMode, MC3635_intr_c_int_fifo_swake_t myINT_SwakeMode );
mcm 1:d4b35641a624 1203 /** It sets the device mode, power mode and the ODR.
mcm 1:d4b35641a624 1204 */
mcm 1:d4b35641a624 1205 MC3635_status_t MC3635_SetMode ( MC3635_mode_c_mctrl_t myMode, MC3635_power_mode_t myPowerMode, MC3635_sample_rate_t myODR );
mcm 1:d4b35641a624 1206
mcm 1:d4b35641a624 1207 /** It configures the parameters for the SNIFF mode.
mcm 1:d4b35641a624 1208 */
mcm 1:d4b35641a624 1209 MC3635_status_t MC3635_ConfSniffMode ( MC3635_sniffcf_c_sniff_thadr_t mySniffADR, uint8_t mySniffThreshold,
mcm 1:d4b35641a624 1210 MC3635_sniffth_c_sniff_and_or_t mySniffLogicalMode, MC3635_sniffth_c_sniff_mode_t mySniffDeltaCount,
mcm 1:d4b35641a624 1211 MC3635_sniffcf_c_sniff_cnten_t mySniffEnableDetectionCount, MC3635_sniffcf_c_sniff_mux_t mySniffMux );
mcm 1:d4b35641a624 1212 /** It is a manual reset for the Sniff block.
mcm 1:d4b35641a624 1213 */
mcm 1:d4b35641a624 1214 MC3635_status_t MC3635_ManualSniffReset ( MC3635_sniffcf_c_sniff_reset_t mySniffResetBit );
mcm 1:d4b35641a624 1215
mcm 1:d4b35641a624 1216 /** It sets the TRIGGER mode.
mcm 1:d4b35641a624 1217 */
mcm 1:d4b35641a624 1218 MC3635_status_t MC3635_SetTriggerMode ( MC3635_mode_c_trig_cmd_t myTriggerEnable, uint8_t myTriggerSamples, MC3635_sniff_c_stb_rate_t mySTANDBY_ClockRate );
mcm 1:d4b35641a624 1219
mcm 1:d4b35641a624 1220 /** It sets the clock rate for STANDBY mode.
mcm 1:d4b35641a624 1221 */
mcm 1:d4b35641a624 1222 MC3635_status_t MC3635_SetStandbyClockRate ( MC3635_sniff_c_stb_rate_t mySTANDBY_ClockRate );
mcm 1:d4b35641a624 1223
mcm 1:d4b35641a624 1224 /** It sets the device into the STANDBY mode.
mcm 1:d4b35641a624 1225 */
mcm 1:d4b35641a624 1226 MC3635_status_t MC3635_SetStandbyMode ( void );
mcm 1:d4b35641a624 1227
mcm 1:d4b35641a624 1228 /** It sets the device into the SLEEP mode.
mcm 1:d4b35641a624 1229 */
mcm 1:d4b35641a624 1230 MC3635_status_t MC3635_SetSleepMode ( void );
mcm 1:d4b35641a624 1231
mcm 1:d4b35641a624 1232 /** It gets the gain for a certain axis.
mcm 1:d4b35641a624 1233 */
mcm 1:d4b35641a624 1234 MC3635_status_t MC3635_GetGain ( MC3635_axis_t myChosenAxis, MC3635_data_t* myGain );
mcm 1:d4b35641a624 1235
mcm 1:d4b35641a624 1236 /** It gets the offset for a certain axis.
mcm 1:d4b35641a624 1237 */
mcm 1:d4b35641a624 1238 MC3635_status_t MC3635_GetOffset ( MC3635_axis_t myChosenAxis, MC3635_data_t* myOffset );
mcm 1:d4b35641a624 1239
mcm 1:d4b35641a624 1240
mcm 1:d4b35641a624 1241 private:
mcm 1:d4b35641a624 1242 I2C _i2c;
mcm 1:d4b35641a624 1243 uint32_t _MC3635_Addr;
mcm 1:d4b35641a624 1244 };
mcm 1:d4b35641a624 1245
mcm 1:d4b35641a624 1246 #endif