Manuel Caballero / AS3933

3D Low Frequency Wakeup Receiver

AS3933.cpp@3:2de552c4ffbc, 2018-03-07 (annotated)

Committer:
mcm
Date:
Wed Mar 07 16:43:51 2018 +0000
Revision:
3:2de552c4ffbc
Parent:
2:c3435a136e50
Child:
4:10d482ca4eb1
Little example was added into the header file to write and read the wakeup pattern. It seems to work fine but it needs a in-depth review.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mcm 2:c3435a136e50 1 /**
mcm 2:c3435a136e50 2 * @brief AS3933.cpp
mcm 2:c3435a136e50 3 * @details 3D Low Frequency Wakeup Receiver.
mcm 2:c3435a136e50 4 * Function file.
mcm 2:c3435a136e50 5 *
mcm 2:c3435a136e50 6 *
mcm 2:c3435a136e50 7 * @return N/A
mcm 2:c3435a136e50 8 *
mcm 2:c3435a136e50 9 * @author Manuel Caballero
mcm 2:c3435a136e50 10 * @date 7/March/2018
mcm 2:c3435a136e50 11 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 12 * @pre N/A.
mcm 2:c3435a136e50 13 * @warning N/A
mcm 2:c3435a136e50 14 * @pre This code belongs to Nimbus Centre ( http://unbarquero.blogspot.com ).
mcm 2:c3435a136e50 15 */
mcm 2:c3435a136e50 16
mcm 2:c3435a136e50 17 #include "AS3933.h"
mcm 2:c3435a136e50 18
mcm 2:c3435a136e50 19
mcm 2:c3435a136e50 20 AS3933::AS3933 ( PinName mosi, PinName miso, PinName sclk, PinName cs, uint32_t freq )
mcm 2:c3435a136e50 21 : _spi ( mosi, miso, sclk )
mcm 2:c3435a136e50 22 , _cs ( cs )
mcm 2:c3435a136e50 23 {
mcm 2:c3435a136e50 24 _spi.frequency( freq );
mcm 2:c3435a136e50 25 _spi.format ( 8, 1 ); // 8-bits, mode1: CPOL = 0 | CPHA = 1
mcm 2:c3435a136e50 26 }
mcm 2:c3435a136e50 27
mcm 2:c3435a136e50 28
mcm 2:c3435a136e50 29 AS3933::~AS3933()
mcm 2:c3435a136e50 30 {
mcm 2:c3435a136e50 31 }
mcm 2:c3435a136e50 32
mcm 2:c3435a136e50 33
mcm 2:c3435a136e50 34
mcm 2:c3435a136e50 35 /**
mcm 2:c3435a136e50 36 * @brief AS3933_SetLowPowerMode ( AS3933_channels_enable_t , AS3933_scanning_mode_t , AS3933_r4_t_off_value_t )
mcm 2:c3435a136e50 37 *
mcm 2:c3435a136e50 38 * @details It configures the low power mode.
mcm 2:c3435a136e50 39 *
mcm 2:c3435a136e50 40 * @param[in] myEnabledChannels: Number of channels enabled.
mcm 2:c3435a136e50 41 * @param[in] myLowPowerMode: Low power mode.
mcm 2:c3435a136e50 42 * @param[in] myT_Off: Period only if ON/OFF mode is selected ( in myLowPowerMode ), it is ignored otherwise.
mcm 2:c3435a136e50 43 *
mcm 2:c3435a136e50 44 * @param[out] N/A.
mcm 2:c3435a136e50 45 *
mcm 2:c3435a136e50 46 *
mcm 2:c3435a136e50 47 * @return Status of AS3933_SetLowPowerMode.
mcm 2:c3435a136e50 48 *
mcm 2:c3435a136e50 49 *
mcm 2:c3435a136e50 50 * @author Manuel Caballero
mcm 2:c3435a136e50 51 * @date 7/March/2018
mcm 2:c3435a136e50 52 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 53 * @pre N/A
mcm 2:c3435a136e50 54 * @warning Data-sheet p.14 8.1.1 Listening Mode. It is NOT clear which channels have to be enabled according to the
mcm 2:c3435a136e50 55 * low power mode: '...If the three dimensional detection is not required, then it is possible to deactivate one
mcm 2:c3435a136e50 56 * or more channels. In case only two channels are required, then the deactivated channel must be the number
mcm 2:c3435a136e50 57 * three; while in case only one channel is needed, then the active channel must be the number one'.
mcm 2:c3435a136e50 58 *
mcm 2:c3435a136e50 59 * Data-sheet p.37 8.10 Channel Selection in Scanning Mode and ON/OFF Mode: 'In case only 2 channels are active and
mcm 2:c3435a136e50 60 * one of the Low Power modes is enabled, then the channels 1 and 3 have to be active. If the chip works in On-Off
mcm 2:c3435a136e50 61 * mode and only one channel is active then the active channel has to be the channel 1.'.
mcm 2:c3435a136e50 62 *
mcm 2:c3435a136e50 63 * This function follows the methodology in: Low Power Modes/Channels enabled: Data-sheet p.37 8.10 Channel
mcm 2:c3435a136e50 64 * Selection in Scanning Mode and ON/OFF Mode.
mcm 2:c3435a136e50 65 */
mcm 2:c3435a136e50 66 AS3933::AS3933_status_t AS3933::AS3933_SetLowPowerMode ( AS3933_channels_enable_t myEnabledChannels, AS3933_scanning_mode_t myLowPowerMode, AS3933_r4_t_off_value_t myT_Off )
mcm 2:c3435a136e50 67 {
mcm 2:c3435a136e50 68 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 69 int mySPI_status;
mcm 2:c3435a136e50 70
mcm 2:c3435a136e50 71
mcm 2:c3435a136e50 72 // Read R0 register
mcm 2:c3435a136e50 73 cmd[0] = ( AS3933_READ | AS3933_R0 );
mcm 3:2de552c4ffbc 74 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 75
mcm 2:c3435a136e50 76 // Mask Channels 1:3
mcm 2:c3435a136e50 77 cmd[1] &= ~( EN_A1_MASK | EN_A2_MASK | EN_A3_MASK );
mcm 2:c3435a136e50 78
mcm 2:c3435a136e50 79 // Mask Scanning Mode
mcm 2:c3435a136e50 80 cmd[1] &= ~( MUX_123_MASK | ON_OFF_MASK );
mcm 2:c3435a136e50 81
mcm 2:c3435a136e50 82
mcm 2:c3435a136e50 83
mcm 2:c3435a136e50 84 // Set the channels enabled
mcm 2:c3435a136e50 85 switch ( myEnabledChannels )
mcm 2:c3435a136e50 86 {
mcm 2:c3435a136e50 87 case AS3933_CH1_OFF_CH2_OFF_CH3_OFF:
mcm 2:c3435a136e50 88 cmd[1] &= ( EN_A1_DISABLED | EN_A2_DISABLED | EN_A3_DISABLED );
mcm 2:c3435a136e50 89 break;
mcm 2:c3435a136e50 90
mcm 2:c3435a136e50 91 case AS3933_CH1_ON_CH2_OFF_CH3_OFF:
mcm 2:c3435a136e50 92 cmd[1] |= ( EN_A1_ENABLED );
mcm 2:c3435a136e50 93 break;
mcm 2:c3435a136e50 94
mcm 2:c3435a136e50 95 case AS3933_CH1_OFF_CH2_ON_CH3_OFF:
mcm 2:c3435a136e50 96 cmd[1] |= ( EN_A2_ENABLED );
mcm 2:c3435a136e50 97 break;
mcm 2:c3435a136e50 98
mcm 2:c3435a136e50 99 case AS3933_CH1_ON_CH2_ON_CH3_OFF:
mcm 2:c3435a136e50 100 cmd[1] |= ( EN_A1_ENABLED | EN_A2_ENABLED );
mcm 2:c3435a136e50 101 break;
mcm 2:c3435a136e50 102
mcm 2:c3435a136e50 103 case AS3933_CH1_OFF_CH2_OFF_CH3_ON:
mcm 2:c3435a136e50 104 cmd[1] |= ( EN_A3_ENABLED );
mcm 2:c3435a136e50 105 break;
mcm 2:c3435a136e50 106
mcm 2:c3435a136e50 107 case AS3933_CH1_ON_CH2_OFF_CH3_ON:
mcm 2:c3435a136e50 108 cmd[1] |= ( EN_A1_ENABLED | EN_A3_ENABLED );
mcm 2:c3435a136e50 109 break;
mcm 2:c3435a136e50 110
mcm 2:c3435a136e50 111 case AS3933_CH1_OFF_CH2_ON_CH3_ON:
mcm 2:c3435a136e50 112 cmd[1] |= ( EN_A2_ENABLED | EN_A3_ENABLED );
mcm 2:c3435a136e50 113 break;
mcm 2:c3435a136e50 114
mcm 2:c3435a136e50 115 default:
mcm 2:c3435a136e50 116 case AS3933_CH1_ON_CH2_ON_CH3_ON:
mcm 2:c3435a136e50 117 cmd[1] |= ( EN_A1_ENABLED | EN_A2_ENABLED | EN_A3_ENABLED );
mcm 2:c3435a136e50 118 break;
mcm 2:c3435a136e50 119 }
mcm 2:c3435a136e50 120
mcm 2:c3435a136e50 121
mcm 2:c3435a136e50 122 // Set Scanning mode
mcm 2:c3435a136e50 123 switch ( myLowPowerMode )
mcm 2:c3435a136e50 124 {
mcm 2:c3435a136e50 125 default:
mcm 2:c3435a136e50 126 case AS3933_STANDARD_LISTENING_MODE:
mcm 2:c3435a136e50 127 break;
mcm 2:c3435a136e50 128
mcm 2:c3435a136e50 129 case AS3933_SCANNING_MODE:
mcm 2:c3435a136e50 130 if ( ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_ON_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_OFF ) ||
mcm 2:c3435a136e50 131 ( myEnabledChannels == AS3933_CH1_OFF_CH2_ON_CH3_OFF ) || ( myEnabledChannels == AS3933_CH1_OFF_CH2_OFF_CH3_ON ) )
mcm 2:c3435a136e50 132 cmd[1] |= ( MUX_123_ENABLED );
mcm 2:c3435a136e50 133 else
mcm 2:c3435a136e50 134 return AS3933_FAILURE;
mcm 2:c3435a136e50 135
mcm 2:c3435a136e50 136 break;
mcm 2:c3435a136e50 137
mcm 2:c3435a136e50 138 case AS3933_ON_OFF_MODE:
mcm 2:c3435a136e50 139 if ( ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_ON_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_OFF ) )
mcm 2:c3435a136e50 140 cmd[1] |= ( ON_OFF_ENABLED );
mcm 2:c3435a136e50 141 else
mcm 2:c3435a136e50 142 return AS3933_FAILURE;
mcm 2:c3435a136e50 143 break;
mcm 2:c3435a136e50 144 }
mcm 2:c3435a136e50 145
mcm 2:c3435a136e50 146 // Update power mode and active channels
mcm 2:c3435a136e50 147 cmd[0] = ( AS3933_WRITE | AS3933_R0 );
mcm 2:c3435a136e50 148 _cs = 1;
mcm 2:c3435a136e50 149 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 150 _cs = 0;
mcm 2:c3435a136e50 151
mcm 2:c3435a136e50 152
mcm 2:c3435a136e50 153 if ( myLowPowerMode == AS3933_ON_OFF_MODE )
mcm 2:c3435a136e50 154 {
mcm 2:c3435a136e50 155 // Read R4 register
mcm 2:c3435a136e50 156 cmd[0] = ( AS3933_READ | AS3933_R4 );
mcm 2:c3435a136e50 157 _cs = 1;
mcm 3:2de552c4ffbc 158 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 159 _cs = 0;
mcm 2:c3435a136e50 160
mcm 2:c3435a136e50 161 // Mask T_OFF
mcm 2:c3435a136e50 162 cmd[1] &= ~( T_OFF_MASK );
mcm 2:c3435a136e50 163
mcm 2:c3435a136e50 164 // Update Off time in ON/OFF operation mode
mcm 2:c3435a136e50 165 cmd[1] |= ( myT_Off );
mcm 2:c3435a136e50 166
mcm 2:c3435a136e50 167 cmd[0] = ( AS3933_WRITE | AS3933_R4 );
mcm 2:c3435a136e50 168 _cs = 1;
mcm 2:c3435a136e50 169 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 170 _cs = 0;
mcm 2:c3435a136e50 171 }
mcm 2:c3435a136e50 172
mcm 2:c3435a136e50 173
mcm 2:c3435a136e50 174
mcm 2:c3435a136e50 175 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 176 return AS3933_SUCCESS;
mcm 2:c3435a136e50 177 else
mcm 2:c3435a136e50 178 return AS3933_FAILURE;
mcm 2:c3435a136e50 179 }
mcm 2:c3435a136e50 180
mcm 2:c3435a136e50 181
mcm 2:c3435a136e50 182 /**
mcm 2:c3435a136e50 183 * @brief AS3933_SetArtificialWakeUp ( AS3933_r8_t_auto_value_t )
mcm 2:c3435a136e50 184 *
mcm 2:c3435a136e50 185 * @details It configures the artificial wakeup.
mcm 2:c3435a136e50 186 *
mcm 2:c3435a136e50 187 * @param[in] myArtificialWakeUp: Period only if ON/OFF mode is selected ( in myLowPowerMode ), it is ignored otherwise.
mcm 2:c3435a136e50 188 *
mcm 2:c3435a136e50 189 * @param[out] N/A.
mcm 2:c3435a136e50 190 *
mcm 2:c3435a136e50 191 *
mcm 2:c3435a136e50 192 * @return Status of AS3933_SetArtificialWakeUp.
mcm 2:c3435a136e50 193 *
mcm 2:c3435a136e50 194 *
mcm 2:c3435a136e50 195 * @author Manuel Caballero
mcm 2:c3435a136e50 196 * @date 7/March/2018
mcm 2:c3435a136e50 197 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 198 * @pre N/A
mcm 2:c3435a136e50 199 * @warning N/A.
mcm 2:c3435a136e50 200 */
mcm 2:c3435a136e50 201 AS3933::AS3933_status_t AS3933::AS3933_SetArtificialWakeUp ( AS3933_r8_t_auto_value_t myArtificialWakeUp )
mcm 2:c3435a136e50 202 {
mcm 2:c3435a136e50 203 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 204 int mySPI_status;
mcm 2:c3435a136e50 205
mcm 2:c3435a136e50 206
mcm 2:c3435a136e50 207 // Read R8 register
mcm 2:c3435a136e50 208 cmd[0] = ( AS3933_READ | AS3933_R8 );
mcm 2:c3435a136e50 209 _cs = 1;
mcm 3:2de552c4ffbc 210 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 211 _cs = 0;
mcm 2:c3435a136e50 212
mcm 2:c3435a136e50 213 // Mask Artificial wakeup
mcm 2:c3435a136e50 214 cmd[1] &= ~( T_AUTO_MASK );
mcm 2:c3435a136e50 215
mcm 2:c3435a136e50 216 // Update the value
mcm 2:c3435a136e50 217 cmd[1] |= myArtificialWakeUp;
mcm 2:c3435a136e50 218
mcm 2:c3435a136e50 219
mcm 2:c3435a136e50 220 // Update artificial wakeup
mcm 2:c3435a136e50 221 cmd[0] = ( AS3933_WRITE | AS3933_R8 );
mcm 2:c3435a136e50 222 _cs = 1;
mcm 2:c3435a136e50 223 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 224 _cs = 0;
mcm 2:c3435a136e50 225
mcm 2:c3435a136e50 226
mcm 2:c3435a136e50 227
mcm 2:c3435a136e50 228
mcm 2:c3435a136e50 229 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 230 return AS3933_SUCCESS;
mcm 2:c3435a136e50 231 else
mcm 2:c3435a136e50 232 return AS3933_FAILURE;
mcm 2:c3435a136e50 233 }
mcm 2:c3435a136e50 234
mcm 2:c3435a136e50 235
mcm 2:c3435a136e50 236 /**
mcm 2:c3435a136e50 237 * @brief AS3933_ReadFalseWakeUpRegister ( AS3933_data_t* )
mcm 2:c3435a136e50 238 *
mcm 2:c3435a136e50 239 * @details It gets feedback on the surrounding environment reading the false wakeup register.
mcm 2:c3435a136e50 240 *
mcm 2:c3435a136e50 241 * @param[in] N/A
mcm 2:c3435a136e50 242 *
mcm 2:c3435a136e50 243 * @param[out] myF_WAKE: F_WAKE register.
mcm 2:c3435a136e50 244 *
mcm 2:c3435a136e50 245 *
mcm 2:c3435a136e50 246 * @return Status of AS3933_ReadFalseWakeUpRegister.
mcm 2:c3435a136e50 247 *
mcm 2:c3435a136e50 248 *
mcm 2:c3435a136e50 249 * @author Manuel Caballero
mcm 2:c3435a136e50 250 * @date 7/March/2018
mcm 2:c3435a136e50 251 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 252 * @pre N/A
mcm 2:c3435a136e50 253 * @warning N/A.
mcm 2:c3435a136e50 254 */
mcm 2:c3435a136e50 255 AS3933::AS3933_status_t AS3933::AS3933_ReadFalseWakeUpRegister ( AS3933_data_t* myF_WAKE )
mcm 2:c3435a136e50 256 {
mcm 3:2de552c4ffbc 257 char cmd[] = { ( AS3933_READ | AS3933_R13 ), 0 };
mcm 2:c3435a136e50 258 int mySPI_status;
mcm 2:c3435a136e50 259
mcm 2:c3435a136e50 260
mcm 2:c3435a136e50 261 // Read R13 register
mcm 2:c3435a136e50 262 _cs = 1;
mcm 3:2de552c4ffbc 263 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 264 _cs = 0;
mcm 3:2de552c4ffbc 265
mcm 3:2de552c4ffbc 266
mcm 3:2de552c4ffbc 267 myF_WAKE->f_wake = cmd[1];
mcm 2:c3435a136e50 268
mcm 2:c3435a136e50 269
mcm 2:c3435a136e50 270
mcm 2:c3435a136e50 271 if ( mySPI_status == SPI_SUCCESS )
mcm 2:c3435a136e50 272 return AS3933_SUCCESS;
mcm 2:c3435a136e50 273 else
mcm 2:c3435a136e50 274 return AS3933_FAILURE;
mcm 2:c3435a136e50 275 }
mcm 2:c3435a136e50 276
mcm 2:c3435a136e50 277
mcm 2:c3435a136e50 278 /**
mcm 2:c3435a136e50 279 * @brief AS3933_SetClockGenerator ( AS3933_r1_en_xtal_value_t, AS3933_r16_clock_gen_dis_value_t )
mcm 2:c3435a136e50 280 *
mcm 2:c3435a136e50 281 * @details It configures the clock generator.
mcm 2:c3435a136e50 282 *
mcm 2:c3435a136e50 283 * @param[in] myClockGenerator: Enable/Disable external crystal oscillator.
mcm 2:c3435a136e50 284 * @param[in] myClockGeneratorOutputMode: Enable/Disable the clock generator output signal displayed on CL_DAT pin.
mcm 2:c3435a136e50 285 *
mcm 2:c3435a136e50 286 * @param[out] N/A.
mcm 2:c3435a136e50 287 *
mcm 2:c3435a136e50 288 *
mcm 2:c3435a136e50 289 * @return Status of AS3933_SetClockGenerator.
mcm 2:c3435a136e50 290 *
mcm 2:c3435a136e50 291 *
mcm 2:c3435a136e50 292 * @author Manuel Caballero
mcm 2:c3435a136e50 293 * @date 7/March/2018
mcm 2:c3435a136e50 294 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 295 * @pre N/A
mcm 2:c3435a136e50 296 * @warning N/A.
mcm 2:c3435a136e50 297 */
mcm 2:c3435a136e50 298 AS3933::AS3933_status_t AS3933::AS3933_SetClockGenerator ( AS3933_r1_en_xtal_value_t myClockGenerator, AS3933_r16_clock_gen_dis_value_t myClockGeneratorOutputMode )
mcm 2:c3435a136e50 299 {
mcm 2:c3435a136e50 300 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 301 int mySPI_status;
mcm 2:c3435a136e50 302
mcm 2:c3435a136e50 303
mcm 2:c3435a136e50 304 // Configure the Crystal oscillator
mcm 2:c3435a136e50 305 // Read R1 register
mcm 2:c3435a136e50 306 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 307 _cs = 1;
mcm 3:2de552c4ffbc 308 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 309 _cs = 0;
mcm 2:c3435a136e50 310
mcm 2:c3435a136e50 311 // Mask Crystal oscillator
mcm 2:c3435a136e50 312 cmd[1] &= ~( EN_XTAL_MASK );
mcm 2:c3435a136e50 313
mcm 2:c3435a136e50 314 // Update the value
mcm 2:c3435a136e50 315 cmd[1] |= myClockGenerator;
mcm 2:c3435a136e50 316
mcm 2:c3435a136e50 317
mcm 2:c3435a136e50 318 // Update Crystal oscillator
mcm 2:c3435a136e50 319 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 320 _cs = 1;
mcm 2:c3435a136e50 321 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 322 _cs = 0;
mcm 2:c3435a136e50 323
mcm 2:c3435a136e50 324
mcm 2:c3435a136e50 325 // Configure the Clock Generator Output
mcm 2:c3435a136e50 326 // Read R16 register
mcm 2:c3435a136e50 327 cmd[0] = ( AS3933_READ | AS3933_R16 );
mcm 2:c3435a136e50 328 _cs = 1;
mcm 3:2de552c4ffbc 329 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 330 _cs = 0;
mcm 2:c3435a136e50 331
mcm 2:c3435a136e50 332 // Mask Clock Generator output signal
mcm 2:c3435a136e50 333 cmd[1] &= ~( CLOCK_GEN_DIS_MASK );
mcm 2:c3435a136e50 334
mcm 2:c3435a136e50 335 // Update the value
mcm 2:c3435a136e50 336 cmd[1] |= myClockGeneratorOutputMode;
mcm 2:c3435a136e50 337
mcm 2:c3435a136e50 338
mcm 2:c3435a136e50 339 // Update Clock Generator output signal
mcm 2:c3435a136e50 340 cmd[0] = ( AS3933_WRITE | AS3933_R16 );
mcm 2:c3435a136e50 341 _cs = 1;
mcm 2:c3435a136e50 342 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 343 _cs = 0;
mcm 2:c3435a136e50 344
mcm 2:c3435a136e50 345
mcm 2:c3435a136e50 346
mcm 2:c3435a136e50 347
mcm 2:c3435a136e50 348 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 349 return AS3933_SUCCESS;
mcm 2:c3435a136e50 350 else
mcm 2:c3435a136e50 351 return AS3933_FAILURE;
mcm 2:c3435a136e50 352 }
mcm 2:c3435a136e50 353
mcm 2:c3435a136e50 354
mcm 2:c3435a136e50 355 /**
mcm 2:c3435a136e50 356 * @brief AS3933_CalibrateRC_Oscillator ( AS3933_r1_en_xtal_value_t, AS3933_r16_clock_gen_dis_value_t )
mcm 2:c3435a136e50 357 *
mcm 2:c3435a136e50 358 * @details It calibrates RC oscillator.
mcm 2:c3435a136e50 359 *
mcm 2:c3435a136e50 360 * @param[in] N/A
mcm 2:c3435a136e50 361 *
mcm 2:c3435a136e50 362 * @param[out] N/A.
mcm 2:c3435a136e50 363 *
mcm 2:c3435a136e50 364 *
mcm 2:c3435a136e50 365 * @return Status of AS3933_CalibrateRC_Oscillator.
mcm 2:c3435a136e50 366 *
mcm 2:c3435a136e50 367 *
mcm 2:c3435a136e50 368 * @author Manuel Caballero
mcm 2:c3435a136e50 369 * @date 7/March/2018
mcm 2:c3435a136e50 370 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 371 * @pre RC-Oscillator: Self Calibration is ONLY available.
mcm 2:c3435a136e50 372 * @warning In case the pattern detection and the Manchester decoder are not enabled ( R1<1>=0 and R1<3>=1 ) the calibration on the RC-oscillator
mcm 2:c3435a136e50 373 * is not needed. Should this not be the case, the RC-oscillator has to be calibrated.
mcm 2:c3435a136e50 374 */
mcm 2:c3435a136e50 375 AS3933::AS3933_status_t AS3933::AS3933_CalibrateRC_Oscillator ( void )
mcm 2:c3435a136e50 376 {
mcm 3:2de552c4ffbc 377 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 378 uint32_t myTimeout = 0;
mcm 2:c3435a136e50 379 int mySPI_status;
mcm 2:c3435a136e50 380
mcm 2:c3435a136e50 381
mcm 2:c3435a136e50 382 // Start the calibration
mcm 3:2de552c4ffbc 383 cmd[0] = ( AS3933_DIRECT_COMMAND | CALIB_RCO_LC );
mcm 2:c3435a136e50 384 _cs = 1;
mcm 3:2de552c4ffbc 385 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 0 );
mcm 2:c3435a136e50 386 _cs = 0;
mcm 2:c3435a136e50 387
mcm 2:c3435a136e50 388
mcm 2:c3435a136e50 389 // RC oscillator will be calibrated when RC_CAL_OK = '1' ( R14<6> )
mcm 2:c3435a136e50 390 myTimeout = 23232323;
mcm 2:c3435a136e50 391 do{
mcm 3:2de552c4ffbc 392 cmd[0] = ( AS3933_READ | AS3933_R14 );
mcm 2:c3435a136e50 393 _cs = 1;
mcm 3:2de552c4ffbc 394 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 395 _cs = 0;
mcm 2:c3435a136e50 396 myTimeout--;
mcm 3:2de552c4ffbc 397 } while ( ( ( cmd[1] & RC_CAL_OK_MASK ) != RC_CAL_OK_HIGH ) && ( myTimeout > 0 ) );
mcm 2:c3435a136e50 398
mcm 2:c3435a136e50 399
mcm 2:c3435a136e50 400
mcm 2:c3435a136e50 401 if ( ( mySPI_status == SPI_SUCCESS ) && ( myTimeout > 0 ) )
mcm 2:c3435a136e50 402 return AS3933_SUCCESS;
mcm 2:c3435a136e50 403 else
mcm 2:c3435a136e50 404 return AS3933_FAILURE;
mcm 2:c3435a136e50 405 }
mcm 2:c3435a136e50 406
mcm 2:c3435a136e50 407
mcm 2:c3435a136e50 408 /**
mcm 2:c3435a136e50 409 * @brief AS3933_SetAntennaDamper ( AS3933_r1_att_on_value_t, AS3933_r4_d_res_value_t )
mcm 2:c3435a136e50 410 *
mcm 2:c3435a136e50 411 * @details It configures the antenna damper and its shunt resistor.
mcm 2:c3435a136e50 412 *
mcm 2:c3435a136e50 413 * @param[in] myAntennaDamperMode: Enable/Disable antenna dumper.
mcm 2:c3435a136e50 414 * @param[in] myShuntResistor: Configure antenna dumping resistor.
mcm 2:c3435a136e50 415 *
mcm 2:c3435a136e50 416 * @param[out] N/A.
mcm 2:c3435a136e50 417 *
mcm 2:c3435a136e50 418 *
mcm 2:c3435a136e50 419 * @return Status of AS3933_SetAntennaDamper.
mcm 2:c3435a136e50 420 *
mcm 2:c3435a136e50 421 *
mcm 2:c3435a136e50 422 * @author Manuel Caballero
mcm 2:c3435a136e50 423 * @date 7/March/2018
mcm 2:c3435a136e50 424 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 425 * @pre N/A.
mcm 2:c3435a136e50 426 * @warning N/A.
mcm 2:c3435a136e50 427 */
mcm 2:c3435a136e50 428 AS3933::AS3933_status_t AS3933::AS3933_SetAntennaDamper ( AS3933_r1_att_on_value_t myAntennaDamperMode, AS3933_r4_d_res_value_t myShuntResistor )
mcm 2:c3435a136e50 429 {
mcm 2:c3435a136e50 430 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 431 int mySPI_status;
mcm 2:c3435a136e50 432
mcm 2:c3435a136e50 433
mcm 2:c3435a136e50 434 // Configure Antenna dumper
mcm 2:c3435a136e50 435 // Read R1 register
mcm 2:c3435a136e50 436 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 437 _cs = 1;
mcm 3:2de552c4ffbc 438 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 439 _cs = 0;
mcm 2:c3435a136e50 440
mcm 2:c3435a136e50 441 // Mask Antenna dumper
mcm 2:c3435a136e50 442 cmd[1] &= ~( ATT_ON_MASK );
mcm 2:c3435a136e50 443
mcm 2:c3435a136e50 444 // Update Antenna dumper
mcm 2:c3435a136e50 445 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 446 cmd[1] |= ( myAntennaDamperMode );
mcm 2:c3435a136e50 447 _cs = 1;
mcm 2:c3435a136e50 448 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 449 _cs = 0;
mcm 2:c3435a136e50 450
mcm 2:c3435a136e50 451
mcm 2:c3435a136e50 452 // Configure Antenna dumper resistor
mcm 2:c3435a136e50 453 // Read R4 register
mcm 2:c3435a136e50 454 cmd[0] = ( AS3933_READ | AS3933_R4 );
mcm 2:c3435a136e50 455 _cs = 1;
mcm 3:2de552c4ffbc 456 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 457 _cs = 0;
mcm 2:c3435a136e50 458
mcm 2:c3435a136e50 459 // Mask Antenna dumper resistor
mcm 2:c3435a136e50 460 cmd[1] &= ~( D_RES_MASK );
mcm 2:c3435a136e50 461
mcm 2:c3435a136e50 462 // Update Antenna dumper resistor
mcm 2:c3435a136e50 463 cmd[0] = ( AS3933_WRITE | AS3933_R4 );
mcm 2:c3435a136e50 464 cmd[1] |= ( myShuntResistor );
mcm 2:c3435a136e50 465 _cs = 1;
mcm 2:c3435a136e50 466 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 467 _cs = 0;
mcm 2:c3435a136e50 468
mcm 2:c3435a136e50 469
mcm 2:c3435a136e50 470
mcm 2:c3435a136e50 471
mcm 2:c3435a136e50 472 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 473 return AS3933_SUCCESS;
mcm 2:c3435a136e50 474 else
mcm 2:c3435a136e50 475 return AS3933_FAILURE;
mcm 2:c3435a136e50 476 }
mcm 2:c3435a136e50 477
mcm 2:c3435a136e50 478
mcm 2:c3435a136e50 479 /**
mcm 2:c3435a136e50 480 * @brief AS3933_SetEnvelopDetector ( AS3933_r3_fs_env_value_t )
mcm 2:c3435a136e50 481 *
mcm 2:c3435a136e50 482 * @details It configures the envelop detector for different symbol rates.
mcm 2:c3435a136e50 483 *
mcm 2:c3435a136e50 484 * @param[in] mySymbolRates: Envelop detector time constant.
mcm 2:c3435a136e50 485 *
mcm 2:c3435a136e50 486 * @param[out] N/A.
mcm 2:c3435a136e50 487 *
mcm 2:c3435a136e50 488 *
mcm 2:c3435a136e50 489 * @return Status of AS3933_SetEnvelopDetector.
mcm 2:c3435a136e50 490 *
mcm 2:c3435a136e50 491 *
mcm 2:c3435a136e50 492 * @author Manuel Caballero
mcm 2:c3435a136e50 493 * @date 7/March/2018
mcm 2:c3435a136e50 494 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 495 * @pre N/A.
mcm 2:c3435a136e50 496 * @warning N/A.
mcm 2:c3435a136e50 497 */
mcm 2:c3435a136e50 498 AS3933::AS3933_status_t AS3933::AS3933_SetEnvelopDetector ( AS3933_r3_fs_env_value_t mySymbolRates )
mcm 2:c3435a136e50 499 {
mcm 2:c3435a136e50 500 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 501 int mySPI_status;
mcm 2:c3435a136e50 502
mcm 2:c3435a136e50 503
mcm 2:c3435a136e50 504 // Read R3 register
mcm 2:c3435a136e50 505 cmd[0] = ( AS3933_READ | AS3933_R3 );
mcm 2:c3435a136e50 506 _cs = 1;
mcm 3:2de552c4ffbc 507 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 508 _cs = 0;
mcm 2:c3435a136e50 509
mcm 2:c3435a136e50 510 // Mask Symbol rate
mcm 2:c3435a136e50 511 cmd[1] &= ~( FS_ENV_MASK );
mcm 2:c3435a136e50 512
mcm 2:c3435a136e50 513 // Update symbol rate
mcm 2:c3435a136e50 514 cmd[0] = ( AS3933_WRITE | AS3933_R3 );
mcm 2:c3435a136e50 515 cmd[1] |= ( mySymbolRates );
mcm 2:c3435a136e50 516 _cs = 1;
mcm 2:c3435a136e50 517 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 518 _cs = 0;
mcm 2:c3435a136e50 519
mcm 2:c3435a136e50 520
mcm 2:c3435a136e50 521
mcm 2:c3435a136e50 522
mcm 2:c3435a136e50 523
mcm 2:c3435a136e50 524 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 525 return AS3933_SUCCESS;
mcm 2:c3435a136e50 526 else
mcm 2:c3435a136e50 527 return AS3933_FAILURE;
mcm 2:c3435a136e50 528 }
mcm 2:c3435a136e50 529
mcm 2:c3435a136e50 530
mcm 2:c3435a136e50 531 /**
mcm 2:c3435a136e50 532 * @brief AS3933_SetDataSlicer ( AS3933_r1_abs_hy_value_t , AS3933_r3_fs_scl_value_t )
mcm 2:c3435a136e50 533 *
mcm 2:c3435a136e50 534 * @details It configures the data slicer for different preamble length.
mcm 2:c3435a136e50 535 *
mcm 2:c3435a136e50 536 * @param[in] myAbsoluteThresholdMode: Enable Data slicer absolute reference.
mcm 2:c3435a136e50 537 * @param[in] myMinimumPreambleLength: Data slices time constant.
mcm 2:c3435a136e50 538 *
mcm 2:c3435a136e50 539 * @param[out] N/A.
mcm 2:c3435a136e50 540 *
mcm 2:c3435a136e50 541 *
mcm 2:c3435a136e50 542 * @return Status of AS3933_SetDataSlicer.
mcm 2:c3435a136e50 543 *
mcm 2:c3435a136e50 544 *
mcm 2:c3435a136e50 545 * @author Manuel Caballero
mcm 2:c3435a136e50 546 * @date 7/March/2018
mcm 2:c3435a136e50 547 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 548 * @pre N/A.
mcm 2:c3435a136e50 549 * @warning N/A.
mcm 2:c3435a136e50 550 */
mcm 2:c3435a136e50 551 AS3933::AS3933_status_t AS3933::AS3933_SetDataSlicer ( AS3933_r1_abs_hy_value_t myAbsoluteThresholdMode, AS3933_r3_fs_scl_value_t myMinimumPreambleLength )
mcm 2:c3435a136e50 552 {
mcm 2:c3435a136e50 553 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 554 int mySPI_status;
mcm 2:c3435a136e50 555
mcm 2:c3435a136e50 556
mcm 2:c3435a136e50 557 // Configure Data slicer absolute reference
mcm 2:c3435a136e50 558 // Read R1 register
mcm 2:c3435a136e50 559 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 560 _cs = 1;
mcm 3:2de552c4ffbc 561 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 562 _cs = 0;
mcm 2:c3435a136e50 563
mcm 2:c3435a136e50 564 // Mask Data slicer absolute reference
mcm 2:c3435a136e50 565 cmd[1] &= ~( ABS_HY_MASK );
mcm 2:c3435a136e50 566
mcm 2:c3435a136e50 567 // Update symbol rate
mcm 2:c3435a136e50 568 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 569 cmd[1] |= ( myAbsoluteThresholdMode );
mcm 2:c3435a136e50 570 _cs = 1;
mcm 2:c3435a136e50 571 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 572 _cs = 0;
mcm 2:c3435a136e50 573
mcm 2:c3435a136e50 574
mcm 2:c3435a136e50 575 // Configure Data slices time constant
mcm 2:c3435a136e50 576 // Read R3 register
mcm 2:c3435a136e50 577 cmd[0] = ( AS3933_READ | AS3933_R3 );
mcm 2:c3435a136e50 578 _cs = 1;
mcm 3:2de552c4ffbc 579 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 580 _cs = 0;
mcm 2:c3435a136e50 581
mcm 2:c3435a136e50 582 // Mask Data slices time constant
mcm 2:c3435a136e50 583 cmd[1] &= ~( FS_SCL_MASK );
mcm 2:c3435a136e50 584
mcm 2:c3435a136e50 585 // Update Data slices time constant
mcm 2:c3435a136e50 586 cmd[0] = ( AS3933_WRITE | AS3933_R3 );
mcm 2:c3435a136e50 587 cmd[1] |= ( myMinimumPreambleLength );
mcm 2:c3435a136e50 588 _cs = 1;
mcm 2:c3435a136e50 589 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 590 _cs = 0;
mcm 2:c3435a136e50 591
mcm 2:c3435a136e50 592
mcm 2:c3435a136e50 593
mcm 2:c3435a136e50 594
mcm 2:c3435a136e50 595 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 596 return AS3933_SUCCESS;
mcm 2:c3435a136e50 597 else
mcm 2:c3435a136e50 598 return AS3933_FAILURE;
mcm 2:c3435a136e50 599 }
mcm 2:c3435a136e50 600
mcm 2:c3435a136e50 601
mcm 2:c3435a136e50 602 /**
mcm 2:c3435a136e50 603 * @brief AS3933_SetComparatorHysteresis ( AS3933_r3_hy_pos_value_t , AS3933_r3_hy_20m_value_t )
mcm 2:c3435a136e50 604 *
mcm 2:c3435a136e50 605 * @details It configures the hysteresis on the data slicer comparator.
mcm 2:c3435a136e50 606 *
mcm 2:c3435a136e50 607 * @param[in] myHysteresisMode: Data slicer hysteresis, edge.
mcm 2:c3435a136e50 608 * @param[in] myHysteresisRange: Data slicer hysteresis, comparator.
mcm 2:c3435a136e50 609 *
mcm 2:c3435a136e50 610 * @param[out] N/A.
mcm 2:c3435a136e50 611 *
mcm 2:c3435a136e50 612 *
mcm 2:c3435a136e50 613 * @return Status of AS3933_SetComparatorHysteresis.
mcm 2:c3435a136e50 614 *
mcm 2:c3435a136e50 615 *
mcm 2:c3435a136e50 616 * @author Manuel Caballero
mcm 2:c3435a136e50 617 * @date 7/March/2018
mcm 2:c3435a136e50 618 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 619 * @pre N/A.
mcm 2:c3435a136e50 620 * @warning N/A.
mcm 2:c3435a136e50 621 */
mcm 2:c3435a136e50 622 AS3933::AS3933_status_t AS3933::AS3933_SetComparatorHysteresis ( AS3933_r3_hy_pos_value_t myHysteresisMode, AS3933_r3_hy_20m_value_t myHysteresisRange )
mcm 2:c3435a136e50 623 {
mcm 2:c3435a136e50 624 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 625 int mySPI_status;
mcm 2:c3435a136e50 626
mcm 2:c3435a136e50 627
mcm 2:c3435a136e50 628 // Read R3 register
mcm 2:c3435a136e50 629 cmd[0] = ( AS3933_READ | AS3933_R3 );
mcm 2:c3435a136e50 630 _cs = 1;
mcm 3:2de552c4ffbc 631 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 632 _cs = 0;
mcm 2:c3435a136e50 633
mcm 2:c3435a136e50 634 // Mask both hysteresis edge and comparator
mcm 2:c3435a136e50 635 cmd[1] &= ~( HY_POS_MASK | HY_20M_MASK );
mcm 2:c3435a136e50 636
mcm 2:c3435a136e50 637 // Update hysteresis on the data slicer comparator
mcm 2:c3435a136e50 638 cmd[0] = ( AS3933_WRITE | AS3933_R3 );
mcm 2:c3435a136e50 639 cmd[1] |= ( myHysteresisMode | myHysteresisRange );
mcm 2:c3435a136e50 640 _cs = 1;
mcm 2:c3435a136e50 641 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 642 _cs = 0;
mcm 2:c3435a136e50 643
mcm 2:c3435a136e50 644
mcm 2:c3435a136e50 645
mcm 2:c3435a136e50 646
mcm 2:c3435a136e50 647 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 648 return AS3933_SUCCESS;
mcm 2:c3435a136e50 649 else
mcm 2:c3435a136e50 650 return AS3933_FAILURE;
mcm 2:c3435a136e50 651 }
mcm 2:c3435a136e50 652
mcm 2:c3435a136e50 653
mcm 2:c3435a136e50 654 /**
mcm 2:c3435a136e50 655 * @brief AS3933_SetGainReduction ( AS3933_r4_gr_value_t )
mcm 2:c3435a136e50 656 *
mcm 2:c3435a136e50 657 * @details It configures the gain reduction.
mcm 2:c3435a136e50 658 *
mcm 2:c3435a136e50 659 * @param[in] myGainReductionValue: Gain reduction.
mcm 2:c3435a136e50 660 *
mcm 2:c3435a136e50 661 * @param[out] N/A.
mcm 2:c3435a136e50 662 *
mcm 2:c3435a136e50 663 *
mcm 2:c3435a136e50 664 * @return Status of AS3933_SetGainReduction.
mcm 2:c3435a136e50 665 *
mcm 2:c3435a136e50 666 *
mcm 2:c3435a136e50 667 * @author Manuel Caballero
mcm 2:c3435a136e50 668 * @date 7/March/2018
mcm 2:c3435a136e50 669 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 670 * @pre N/A.
mcm 2:c3435a136e50 671 * @warning N/A.
mcm 2:c3435a136e50 672 */
mcm 2:c3435a136e50 673 AS3933::AS3933_status_t AS3933::AS3933_SetGainReduction ( AS3933_r4_gr_value_t myGainReductionValue )
mcm 2:c3435a136e50 674 {
mcm 2:c3435a136e50 675 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 676 int mySPI_status;
mcm 2:c3435a136e50 677
mcm 2:c3435a136e50 678
mcm 2:c3435a136e50 679 // Read R4 register
mcm 2:c3435a136e50 680 cmd[0] = ( AS3933_READ | AS3933_R4 );
mcm 2:c3435a136e50 681 _cs = 1;
mcm 3:2de552c4ffbc 682 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 683 _cs = 0;
mcm 2:c3435a136e50 684
mcm 2:c3435a136e50 685 // Mask Gain reduction
mcm 2:c3435a136e50 686 cmd[1] &= ~( GR_MASK );
mcm 2:c3435a136e50 687
mcm 2:c3435a136e50 688 // Update Gain reduction
mcm 2:c3435a136e50 689 cmd[0] = ( AS3933_WRITE | AS3933_R4 );
mcm 2:c3435a136e50 690 cmd[1] |= ( myGainReductionValue );
mcm 2:c3435a136e50 691 _cs = 1;
mcm 2:c3435a136e50 692 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 693 _cs = 0;
mcm 2:c3435a136e50 694
mcm 2:c3435a136e50 695
mcm 2:c3435a136e50 696
mcm 2:c3435a136e50 697
mcm 2:c3435a136e50 698 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 699 return AS3933_SUCCESS;
mcm 2:c3435a136e50 700 else
mcm 2:c3435a136e50 701 return AS3933_FAILURE;
mcm 2:c3435a136e50 702 }
mcm 2:c3435a136e50 703
mcm 2:c3435a136e50 704
mcm 2:c3435a136e50 705 /**
mcm 2:c3435a136e50 706 * @brief AS3933_SetOperatingFrequencyRange ( AS3933_r8_band_sel_value_t )
mcm 2:c3435a136e50 707 *
mcm 2:c3435a136e50 708 * @details It configures the operating frequency range.
mcm 2:c3435a136e50 709 *
mcm 2:c3435a136e50 710 * @param[in] myOperatingFrequencyRange: Band selection.
mcm 2:c3435a136e50 711 *
mcm 2:c3435a136e50 712 * @param[out] N/A.
mcm 2:c3435a136e50 713 *
mcm 2:c3435a136e50 714 *
mcm 2:c3435a136e50 715 * @return Status of AS3933_SetOperatingFrequencyRange.
mcm 2:c3435a136e50 716 *
mcm 2:c3435a136e50 717 *
mcm 2:c3435a136e50 718 * @author Manuel Caballero
mcm 2:c3435a136e50 719 * @date 7/March/2018
mcm 2:c3435a136e50 720 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 721 * @pre N/A.
mcm 2:c3435a136e50 722 * @warning N/A.
mcm 2:c3435a136e50 723 */
mcm 2:c3435a136e50 724 AS3933::AS3933_status_t AS3933::AS3933_SetOperatingFrequencyRange ( AS3933_r8_band_sel_value_t myOperatingFrequencyRange )
mcm 2:c3435a136e50 725 {
mcm 2:c3435a136e50 726 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 727 int mySPI_status;
mcm 2:c3435a136e50 728
mcm 2:c3435a136e50 729
mcm 2:c3435a136e50 730 // Read R8 register
mcm 2:c3435a136e50 731 cmd[0] = ( AS3933_READ | AS3933_R8 );
mcm 2:c3435a136e50 732 _cs = 1;
mcm 3:2de552c4ffbc 733 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 734 _cs = 0;
mcm 2:c3435a136e50 735
mcm 2:c3435a136e50 736 // Mask Band selection
mcm 2:c3435a136e50 737 cmd[1] &= ~( BAND_SEL_MASK );
mcm 2:c3435a136e50 738
mcm 2:c3435a136e50 739 // Update Band selection
mcm 2:c3435a136e50 740 cmd[0] = ( AS3933_WRITE | AS3933_R8 );
mcm 2:c3435a136e50 741 cmd[1] |= ( myOperatingFrequencyRange );
mcm 2:c3435a136e50 742 _cs = 1;
mcm 2:c3435a136e50 743 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 744 _cs = 0;
mcm 2:c3435a136e50 745
mcm 2:c3435a136e50 746
mcm 2:c3435a136e50 747
mcm 2:c3435a136e50 748
mcm 2:c3435a136e50 749 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 750 return AS3933_SUCCESS;
mcm 2:c3435a136e50 751 else
mcm 2:c3435a136e50 752 return AS3933_FAILURE;
mcm 2:c3435a136e50 753 }
mcm 2:c3435a136e50 754
mcm 2:c3435a136e50 755
mcm 2:c3435a136e50 756 /**
mcm 2:c3435a136e50 757 * @brief AS3933_SetFrequencyDetectionTolerance ( AS3933_tolerance_settings_t )
mcm 2:c3435a136e50 758 *
mcm 2:c3435a136e50 759 * @details It configures the frequency detection tolerance.
mcm 2:c3435a136e50 760 *
mcm 2:c3435a136e50 761 * @param[in] myTolerance: Tolerance band.
mcm 2:c3435a136e50 762 *
mcm 2:c3435a136e50 763 * @param[out] N/A.
mcm 2:c3435a136e50 764 *
mcm 2:c3435a136e50 765 *
mcm 2:c3435a136e50 766 * @return Status of AS3933_SetFrequencyDetectionTolerance.
mcm 2:c3435a136e50 767 *
mcm 2:c3435a136e50 768 *
mcm 2:c3435a136e50 769 * @author Manuel Caballero
mcm 2:c3435a136e50 770 * @date 7/March/2018
mcm 2:c3435a136e50 771 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 772 * @pre N/A.
mcm 2:c3435a136e50 773 * @warning N/A.
mcm 2:c3435a136e50 774 */
mcm 2:c3435a136e50 775 AS3933::AS3933_status_t AS3933::AS3933_SetFrequencyDetectionTolerance ( AS3933_tolerance_settings_t myTolerance )
mcm 2:c3435a136e50 776 {
mcm 2:c3435a136e50 777 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 778 int mySPI_status;
mcm 2:c3435a136e50 779
mcm 2:c3435a136e50 780
mcm 2:c3435a136e50 781 // Read R2 register
mcm 2:c3435a136e50 782 cmd[0] = ( AS3933_READ | AS3933_R2 );
mcm 2:c3435a136e50 783 _cs = 1;
mcm 3:2de552c4ffbc 784 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 785 _cs = 0;
mcm 2:c3435a136e50 786
mcm 2:c3435a136e50 787 // Mask Tolerance band
mcm 2:c3435a136e50 788 cmd[1] &= ~( AS3933_TOLERANCE_MASK );
mcm 2:c3435a136e50 789
mcm 2:c3435a136e50 790 // Update Tolerance band
mcm 2:c3435a136e50 791 cmd[0] = ( AS3933_WRITE | AS3933_R2 );
mcm 2:c3435a136e50 792 cmd[1] |= ( myTolerance );
mcm 2:c3435a136e50 793 _cs = 1;
mcm 2:c3435a136e50 794 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 795 _cs = 0;
mcm 2:c3435a136e50 796
mcm 2:c3435a136e50 797
mcm 2:c3435a136e50 798
mcm 2:c3435a136e50 799
mcm 2:c3435a136e50 800 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 801 return AS3933_SUCCESS;
mcm 2:c3435a136e50 802 else
mcm 2:c3435a136e50 803 return AS3933_FAILURE;
mcm 2:c3435a136e50 804 }
mcm 2:c3435a136e50 805
mcm 2:c3435a136e50 806
mcm 2:c3435a136e50 807 /**
mcm 2:c3435a136e50 808 * @brief AS3933_SetGainBoost ( AS3933_r2_g_boost_value_t )
mcm 2:c3435a136e50 809 *
mcm 2:c3435a136e50 810 * @details It configures the +3dB gain boost.
mcm 2:c3435a136e50 811 *
mcm 2:c3435a136e50 812 * @param[in] myGainBoostMode: Enable/Disable +3dB Amplifier Gain Boost.
mcm 2:c3435a136e50 813 *
mcm 2:c3435a136e50 814 * @param[out] N/A.
mcm 2:c3435a136e50 815 *
mcm 2:c3435a136e50 816 *
mcm 2:c3435a136e50 817 * @return Status of AS3933_SetGainBoost.
mcm 2:c3435a136e50 818 *
mcm 2:c3435a136e50 819 *
mcm 2:c3435a136e50 820 * @author Manuel Caballero
mcm 2:c3435a136e50 821 * @date 7/March/2018
mcm 2:c3435a136e50 822 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 823 * @pre N/A.
mcm 2:c3435a136e50 824 * @warning N/A.
mcm 2:c3435a136e50 825 */
mcm 2:c3435a136e50 826 AS3933::AS3933_status_t AS3933::AS3933_SetGainBoost ( AS3933_r2_g_boost_value_t myGainBoostMode )
mcm 2:c3435a136e50 827 {
mcm 2:c3435a136e50 828 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 829 int mySPI_status;
mcm 2:c3435a136e50 830
mcm 2:c3435a136e50 831
mcm 2:c3435a136e50 832 // Read R2 register
mcm 2:c3435a136e50 833 cmd[0] = ( AS3933_READ | AS3933_R2 );
mcm 2:c3435a136e50 834 _cs = 1;
mcm 3:2de552c4ffbc 835 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 836 _cs = 0;
mcm 2:c3435a136e50 837
mcm 2:c3435a136e50 838 // Mask Gain boost
mcm 2:c3435a136e50 839 cmd[1] &= ~( G_BOOST_MASK );
mcm 2:c3435a136e50 840
mcm 2:c3435a136e50 841 // Update Gain boost
mcm 2:c3435a136e50 842 cmd[0] = ( AS3933_WRITE | AS3933_R2 );
mcm 2:c3435a136e50 843 cmd[1] |= ( myGainBoostMode );
mcm 2:c3435a136e50 844 _cs = 1;
mcm 2:c3435a136e50 845 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 846 _cs = 0;
mcm 2:c3435a136e50 847
mcm 2:c3435a136e50 848
mcm 2:c3435a136e50 849
mcm 2:c3435a136e50 850
mcm 2:c3435a136e50 851 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 852 return AS3933_SUCCESS;
mcm 2:c3435a136e50 853 else
mcm 2:c3435a136e50 854 return AS3933_FAILURE;
mcm 2:c3435a136e50 855 }
mcm 2:c3435a136e50 856
mcm 2:c3435a136e50 857
mcm 2:c3435a136e50 858 /**
mcm 2:c3435a136e50 859 * @brief AS3933_SetAGC ( AS3933_r1_agc_tlim_value_t , AS3933_r1_agc_ud_value_t )
mcm 2:c3435a136e50 860 *
mcm 2:c3435a136e50 861 * @details It configures the Automatic Gain Control ( AGC ).
mcm 2:c3435a136e50 862 *
mcm 2:c3435a136e50 863 * @param[in] myAGC_CarrierBurstMode: Enable/Disable AGC acting only on the first carrier burst.
mcm 2:c3435a136e50 864 * @param[in] myAGC_OperatingDirection: Configure AGC direction operating.
mcm 2:c3435a136e50 865 *
mcm 2:c3435a136e50 866 * @param[out] N/A.
mcm 2:c3435a136e50 867 *
mcm 2:c3435a136e50 868 *
mcm 2:c3435a136e50 869 * @return Status of AS3933_SetAGC.
mcm 2:c3435a136e50 870 *
mcm 2:c3435a136e50 871 *
mcm 2:c3435a136e50 872 * @author Manuel Caballero
mcm 2:c3435a136e50 873 * @date 7/March/2018
mcm 2:c3435a136e50 874 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 875 * @pre N/A.
mcm 2:c3435a136e50 876 * @warning N/A.
mcm 2:c3435a136e50 877 */
mcm 2:c3435a136e50 878 AS3933::AS3933_status_t AS3933::AS3933_SetAGC ( AS3933_r1_agc_tlim_value_t myAGC_CarrierBurstMode, AS3933_r1_agc_ud_value_t myAGC_OperatingDirection )
mcm 2:c3435a136e50 879 {
mcm 2:c3435a136e50 880 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 881 int mySPI_status;
mcm 2:c3435a136e50 882
mcm 2:c3435a136e50 883
mcm 2:c3435a136e50 884 // Read R1 register
mcm 2:c3435a136e50 885 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 886 _cs = 1;
mcm 3:2de552c4ffbc 887 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 888 _cs = 0;
mcm 2:c3435a136e50 889
mcm 2:c3435a136e50 890 // Mask both AGC acting only on the first carrier burst and AGC direction operating
mcm 2:c3435a136e50 891 cmd[1] &= ~( AGC_TLIM_MASK | AGC_UD_MASK );
mcm 2:c3435a136e50 892
mcm 2:c3435a136e50 893 // Update both AGC acting only on the first carrier burst and AGC direction operating
mcm 2:c3435a136e50 894 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 895 cmd[1] |= ( myAGC_CarrierBurstMode | myAGC_OperatingDirection );
mcm 2:c3435a136e50 896 _cs = 1;
mcm 2:c3435a136e50 897 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 898 _cs = 0;
mcm 2:c3435a136e50 899
mcm 2:c3435a136e50 900
mcm 2:c3435a136e50 901
mcm 2:c3435a136e50 902
mcm 2:c3435a136e50 903 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 904 return AS3933_SUCCESS;
mcm 2:c3435a136e50 905 else
mcm 2:c3435a136e50 906 return AS3933_FAILURE;
mcm 2:c3435a136e50 907 }
mcm 2:c3435a136e50 908
mcm 2:c3435a136e50 909
mcm 2:c3435a136e50 910 /**
mcm 2:c3435a136e50 911 * @brief AS3933_SetDataMask ( AS3933_r0_dat_mask_value_t )
mcm 2:c3435a136e50 912 *
mcm 2:c3435a136e50 913 * @details It configures the mask data before wakeup.
mcm 2:c3435a136e50 914 *
mcm 2:c3435a136e50 915 * @param[in] myDataMaskMode: Mask data on DAT pin before wakeup happens.
mcm 2:c3435a136e50 916 *
mcm 2:c3435a136e50 917 * @param[out] N/A.
mcm 2:c3435a136e50 918 *
mcm 2:c3435a136e50 919 *
mcm 2:c3435a136e50 920 * @return Status of AS3933_SetDataMask.
mcm 2:c3435a136e50 921 *
mcm 2:c3435a136e50 922 *
mcm 2:c3435a136e50 923 * @author Manuel Caballero
mcm 2:c3435a136e50 924 * @date 7/March/2018
mcm 2:c3435a136e50 925 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 926 * @pre N/A.
mcm 2:c3435a136e50 927 * @warning N/A.
mcm 2:c3435a136e50 928 */
mcm 2:c3435a136e50 929 AS3933::AS3933_status_t AS3933::AS3933_SetDataMask ( AS3933_r0_dat_mask_value_t myDataMaskMode )
mcm 2:c3435a136e50 930 {
mcm 2:c3435a136e50 931 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 932 int mySPI_status;
mcm 2:c3435a136e50 933
mcm 2:c3435a136e50 934
mcm 2:c3435a136e50 935 // Read R0 register
mcm 2:c3435a136e50 936 cmd[0] = ( AS3933_READ | AS3933_R0 );
mcm 2:c3435a136e50 937 _cs = 1;
mcm 3:2de552c4ffbc 938 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 939 _cs = 0;
mcm 2:c3435a136e50 940
mcm 2:c3435a136e50 941 // Mask Mask data on DAT pin before wakeup happens
mcm 2:c3435a136e50 942 cmd[1] &= ~( DAT_MASK_MASK );
mcm 2:c3435a136e50 943
mcm 2:c3435a136e50 944 // Update Mask data on DAT pin before wakeup happens
mcm 2:c3435a136e50 945 cmd[0] = ( AS3933_WRITE | AS3933_R0 );
mcm 2:c3435a136e50 946 cmd[1] |= ( myDataMaskMode );
mcm 2:c3435a136e50 947 _cs = 1;
mcm 2:c3435a136e50 948 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 949 _cs = 0;
mcm 2:c3435a136e50 950
mcm 2:c3435a136e50 951
mcm 2:c3435a136e50 952
mcm 2:c3435a136e50 953
mcm 2:c3435a136e50 954 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 955 return AS3933_SUCCESS;
mcm 2:c3435a136e50 956 else
mcm 2:c3435a136e50 957 return AS3933_FAILURE;
mcm 2:c3435a136e50 958 }
mcm 2:c3435a136e50 959
mcm 2:c3435a136e50 960
mcm 2:c3435a136e50 961 /**
mcm 2:c3435a136e50 962 * @brief AS3933_SetCorrelator ( AS3933_r1_en_wpat_value_t , AS3933_r0_patt32_value_t , AS3933_r7_t_hbit_value_t , AS3933_r1_en_manch_value_t )
mcm 2:c3435a136e50 963 *
mcm 2:c3435a136e50 964 * @details It configures the correlator and the Manchester Decoder.
mcm 2:c3435a136e50 965 *
mcm 2:c3435a136e50 966 * @param[in] myCorrelatorMode: Enable/Disable Correlator.
mcm 2:c3435a136e50 967 * @param[in] mySymbolPattern: Pattern extended.
mcm 2:c3435a136e50 968 * @param[in] myRate: Bit rate definition.
mcm 2:c3435a136e50 969 * @param[in] myManchesterDecoderMode: Enable/Disable Manchester decoder.
mcm 2:c3435a136e50 970 *
mcm 2:c3435a136e50 971 * @param[out] N/A.
mcm 2:c3435a136e50 972 *
mcm 2:c3435a136e50 973 *
mcm 2:c3435a136e50 974 * @return Status of AS3933_SetCorrelator.
mcm 2:c3435a136e50 975 *
mcm 2:c3435a136e50 976 *
mcm 2:c3435a136e50 977 * @author Manuel Caballero
mcm 2:c3435a136e50 978 * @date 7/March/2018
mcm 2:c3435a136e50 979 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 980 * @pre N/A.
mcm 2:c3435a136e50 981 * @warning N/A.
mcm 2:c3435a136e50 982 */
mcm 2:c3435a136e50 983 AS3933::AS3933_status_t AS3933::AS3933_SetCorrelator ( AS3933_r1_en_wpat_value_t myCorrelatorMode, AS3933_r0_patt32_value_t mySymbolPattern, AS3933_r7_t_hbit_value_t myRate,
mcm 2:c3435a136e50 984 AS3933_r1_en_manch_value_t myManchesterDecoderMode )
mcm 2:c3435a136e50 985 {
mcm 2:c3435a136e50 986 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 987 int mySPI_status;
mcm 2:c3435a136e50 988
mcm 2:c3435a136e50 989
mcm 2:c3435a136e50 990 // Configure Correlator mode and Manchester decoder mode
mcm 2:c3435a136e50 991 // Read R1 register
mcm 2:c3435a136e50 992 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 993 _cs = 1;
mcm 3:2de552c4ffbc 994 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 995 _cs = 0;
mcm 2:c3435a136e50 996
mcm 2:c3435a136e50 997 // Mask both Correlator mode and Manchester decoder mode
mcm 2:c3435a136e50 998 cmd[1] &= ~( EN_WPAT_MASK | EN_MANCH_MASK );
mcm 2:c3435a136e50 999
mcm 2:c3435a136e50 1000 // Update both Correlator mode and Manchester decoder mode
mcm 2:c3435a136e50 1001 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 1002 cmd[1] |= ( myCorrelatorMode | myManchesterDecoderMode );
mcm 2:c3435a136e50 1003 _cs = 1;
mcm 2:c3435a136e50 1004 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 1005 _cs = 0;
mcm 2:c3435a136e50 1006
mcm 2:c3435a136e50 1007
mcm 2:c3435a136e50 1008 // Configure Pattern extended
mcm 2:c3435a136e50 1009 // Read R0 register
mcm 2:c3435a136e50 1010 cmd[0] = ( AS3933_READ | AS3933_R0 );
mcm 2:c3435a136e50 1011 _cs = 1;
mcm 2:c3435a136e50 1012 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[1], 1 );
mcm 2:c3435a136e50 1013 _cs = 0;
mcm 2:c3435a136e50 1014
mcm 2:c3435a136e50 1015 // Mask Pattern extended
mcm 2:c3435a136e50 1016 cmd[1] &= ~( PATT32_MASK );
mcm 2:c3435a136e50 1017
mcm 2:c3435a136e50 1018 // Update Pattern extended
mcm 2:c3435a136e50 1019 cmd[0] = ( AS3933_WRITE | AS3933_R0 );
mcm 2:c3435a136e50 1020 cmd[1] |= ( mySymbolPattern );
mcm 2:c3435a136e50 1021 _cs = 1;
mcm 2:c3435a136e50 1022 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 1023 _cs = 0;
mcm 2:c3435a136e50 1024
mcm 2:c3435a136e50 1025
mcm 2:c3435a136e50 1026 // Configure Bit rate definition
mcm 2:c3435a136e50 1027 // Read R7 register
mcm 2:c3435a136e50 1028 cmd[0] = ( AS3933_READ | AS3933_R7 );
mcm 2:c3435a136e50 1029 _cs = 1;
mcm 3:2de552c4ffbc 1030 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1031 _cs = 0;
mcm 2:c3435a136e50 1032
mcm 2:c3435a136e50 1033 // Mask Bit rate definition
mcm 2:c3435a136e50 1034 cmd[1] &= ~( T_HBIT_MASK );
mcm 2:c3435a136e50 1035
mcm 2:c3435a136e50 1036 // Update Bit rate definition
mcm 2:c3435a136e50 1037 cmd[0] = ( AS3933_WRITE | AS3933_R7 );
mcm 2:c3435a136e50 1038 cmd[1] |= ( myRate );
mcm 2:c3435a136e50 1039 _cs = 1;
mcm 2:c3435a136e50 1040 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 1041 _cs = 0;
mcm 2:c3435a136e50 1042
mcm 2:c3435a136e50 1043
mcm 2:c3435a136e50 1044
mcm 2:c3435a136e50 1045
mcm 2:c3435a136e50 1046
mcm 2:c3435a136e50 1047 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1048 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1049 else
mcm 2:c3435a136e50 1050 return AS3933_FAILURE;
mcm 2:c3435a136e50 1051 }
mcm 2:c3435a136e50 1052
mcm 2:c3435a136e50 1053
mcm 2:c3435a136e50 1054 /**
mcm 2:c3435a136e50 1055 * @brief AS3933_SetWakeUpPattern ( AS3933_data_t )
mcm 2:c3435a136e50 1056 *
mcm 2:c3435a136e50 1057 * @details It sets the wakeup pattern ( Manchester ).
mcm 2:c3435a136e50 1058 *
mcm 2:c3435a136e50 1059 * @param[in] myWakeUpPattern: PATT1B and PATT2B ( Manchester ).
mcm 2:c3435a136e50 1060 *
mcm 2:c3435a136e50 1061 * @param[out] N/A.
mcm 2:c3435a136e50 1062 *
mcm 2:c3435a136e50 1063 *
mcm 2:c3435a136e50 1064 * @return Status of AS3933_SetWakeUpPattern.
mcm 2:c3435a136e50 1065 *
mcm 2:c3435a136e50 1066 *
mcm 2:c3435a136e50 1067 * @author Manuel Caballero
mcm 2:c3435a136e50 1068 * @date 7/March/2018
mcm 2:c3435a136e50 1069 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1070 * @pre N/A.
mcm 2:c3435a136e50 1071 * @warning N/A.
mcm 2:c3435a136e50 1072 */
mcm 2:c3435a136e50 1073 AS3933::AS3933_status_t AS3933::AS3933_SetWakeUpPattern ( AS3933_data_t myWakeUpPattern )
mcm 2:c3435a136e50 1074 {
mcm 2:c3435a136e50 1075 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1076 int mySPI_status;
mcm 2:c3435a136e50 1077
mcm 2:c3435a136e50 1078
mcm 2:c3435a136e50 1079 // Update PATT2B
mcm 2:c3435a136e50 1080 cmd[0] = ( AS3933_WRITE | AS3933_R5 );
mcm 2:c3435a136e50 1081 cmd[1] = ( myWakeUpPattern.patt2b );
mcm 2:c3435a136e50 1082 _cs = 1;
mcm 3:2de552c4ffbc 1083 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 1 );
mcm 2:c3435a136e50 1084 _cs = 0;
mcm 2:c3435a136e50 1085
mcm 2:c3435a136e50 1086 // Update PATT1B
mcm 2:c3435a136e50 1087 cmd[0] = ( AS3933_WRITE | AS3933_R6 );
mcm 2:c3435a136e50 1088 cmd[1] = ( myWakeUpPattern.patt1b );
mcm 2:c3435a136e50 1089 _cs = 1;
mcm 3:2de552c4ffbc 1090 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 1 );
mcm 2:c3435a136e50 1091 _cs = 0;
mcm 2:c3435a136e50 1092
mcm 2:c3435a136e50 1093
mcm 2:c3435a136e50 1094
mcm 2:c3435a136e50 1095
mcm 2:c3435a136e50 1096 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1097 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1098 else
mcm 2:c3435a136e50 1099 return AS3933_FAILURE;
mcm 2:c3435a136e50 1100 }
mcm 2:c3435a136e50 1101
mcm 2:c3435a136e50 1102
mcm 2:c3435a136e50 1103 /**
mcm 2:c3435a136e50 1104 * @brief AS3933_GetWakeUpPattern ( AS3933_data_t* )
mcm 2:c3435a136e50 1105 *
mcm 2:c3435a136e50 1106 * @details It gets the wakeup pattern ( Manchester ).
mcm 2:c3435a136e50 1107 *
mcm 2:c3435a136e50 1108 * @param[in] N/A
mcm 2:c3435a136e50 1109 *
mcm 2:c3435a136e50 1110 * @param[out] myWakeUpPattern: PATT1B and PATT2B ( Manchester ).
mcm 2:c3435a136e50 1111 *
mcm 2:c3435a136e50 1112 *
mcm 2:c3435a136e50 1113 * @return Status of AS3933_GetWakeUpPattern.
mcm 2:c3435a136e50 1114 *
mcm 2:c3435a136e50 1115 *
mcm 2:c3435a136e50 1116 * @author Manuel Caballero
mcm 2:c3435a136e50 1117 * @date 7/March/2018
mcm 2:c3435a136e50 1118 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1119 * @pre N/A.
mcm 2:c3435a136e50 1120 * @warning N/A.
mcm 2:c3435a136e50 1121 */
mcm 2:c3435a136e50 1122 AS3933::AS3933_status_t AS3933::AS3933_GetWakeUpPattern ( AS3933_data_t* myWakeUpPattern )
mcm 2:c3435a136e50 1123 {
mcm 3:2de552c4ffbc 1124 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1125 int mySPI_status;
mcm 2:c3435a136e50 1126
mcm 2:c3435a136e50 1127
mcm 2:c3435a136e50 1128 // Read R5 register
mcm 3:2de552c4ffbc 1129 cmd[0] = ( AS3933_READ | AS3933_R5 );
mcm 2:c3435a136e50 1130 _cs = 1;
mcm 3:2de552c4ffbc 1131 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 3:2de552c4ffbc 1132 _cs = 0;
mcm 3:2de552c4ffbc 1133
mcm 3:2de552c4ffbc 1134 myWakeUpPattern->patt2b = cmd[1];
mcm 3:2de552c4ffbc 1135
mcm 3:2de552c4ffbc 1136 // Read R6 register
mcm 3:2de552c4ffbc 1137 cmd[0] = ( AS3933_READ | AS3933_R6 );
mcm 3:2de552c4ffbc 1138 _cs = 1;
mcm 3:2de552c4ffbc 1139 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1140 _cs = 0;
mcm 2:c3435a136e50 1141
mcm 3:2de552c4ffbc 1142 myWakeUpPattern->patt1b = cmd[1];
mcm 2:c3435a136e50 1143
mcm 2:c3435a136e50 1144
mcm 2:c3435a136e50 1145 if ( mySPI_status == SPI_SUCCESS )
mcm 2:c3435a136e50 1146 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1147 else
mcm 2:c3435a136e50 1148 return AS3933_FAILURE;
mcm 2:c3435a136e50 1149 }
mcm 2:c3435a136e50 1150
mcm 2:c3435a136e50 1151
mcm 2:c3435a136e50 1152 /**
mcm 2:c3435a136e50 1153 * @brief AS3933_SetAutomaticTimeOut ( AS3933_r7_t_out_value_t )
mcm 2:c3435a136e50 1154 *
mcm 2:c3435a136e50 1155 * @details It sets the automatic time-out setup.
mcm 2:c3435a136e50 1156 *
mcm 2:c3435a136e50 1157 * @param[in] myAutomaticTimeOut: Automatic time-out.
mcm 2:c3435a136e50 1158 *
mcm 2:c3435a136e50 1159 * @param[out] N/A.
mcm 2:c3435a136e50 1160 *
mcm 2:c3435a136e50 1161 *
mcm 2:c3435a136e50 1162 * @return Status of AS3933_SetAutomaticTimeOut.
mcm 2:c3435a136e50 1163 *
mcm 2:c3435a136e50 1164 *
mcm 2:c3435a136e50 1165 * @author Manuel Caballero
mcm 2:c3435a136e50 1166 * @date 7/March/2018
mcm 2:c3435a136e50 1167 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1168 * @pre N/A.
mcm 2:c3435a136e50 1169 * @warning N/A.
mcm 2:c3435a136e50 1170 */
mcm 2:c3435a136e50 1171 AS3933::AS3933_status_t AS3933::AS3933_SetAutomaticTimeOut ( AS3933_r7_t_out_value_t myAutomaticTimeOut )
mcm 2:c3435a136e50 1172 {
mcm 2:c3435a136e50 1173 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1174 int mySPI_status;
mcm 2:c3435a136e50 1175
mcm 2:c3435a136e50 1176
mcm 2:c3435a136e50 1177 // Read R7 register
mcm 2:c3435a136e50 1178 cmd[0] = ( AS3933_READ | AS3933_R7 );
mcm 2:c3435a136e50 1179 _cs = 1;
mcm 3:2de552c4ffbc 1180 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1181 _cs = 0;
mcm 2:c3435a136e50 1182
mcm 2:c3435a136e50 1183 // Mask Automatic time-out
mcm 2:c3435a136e50 1184 cmd[1] &= ~( T_OUT_MASK );
mcm 2:c3435a136e50 1185
mcm 2:c3435a136e50 1186 // Update Automatic time-out
mcm 2:c3435a136e50 1187 cmd[0] = ( AS3933_WRITE | AS3933_R7 );
mcm 2:c3435a136e50 1188 cmd[1] |= ( myAutomaticTimeOut );
mcm 2:c3435a136e50 1189 _cs = 1;
mcm 2:c3435a136e50 1190 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 1191 _cs = 0;
mcm 2:c3435a136e50 1192
mcm 2:c3435a136e50 1193
mcm 2:c3435a136e50 1194
mcm 2:c3435a136e50 1195
mcm 2:c3435a136e50 1196 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1197 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1198 else
mcm 2:c3435a136e50 1199 return AS3933_FAILURE;
mcm 2:c3435a136e50 1200 }
mcm 2:c3435a136e50 1201
mcm 2:c3435a136e50 1202
mcm 2:c3435a136e50 1203 /**
mcm 2:c3435a136e50 1204 * @brief AS3933_SetParallelTuningCapacitance ( AS3933_parallel_tuning_channels_t , AS3933_parallel_tuning_capacitance_t )
mcm 2:c3435a136e50 1205 *
mcm 2:c3435a136e50 1206 * @details It sets the parallel tuning capacitance on the chosen channel.
mcm 2:c3435a136e50 1207 *
mcm 2:c3435a136e50 1208 * @param[in] myChannel: Channel for Parallel Tuning Capacitance.
mcm 2:c3435a136e50 1209 * @param[in] myAddedCapacitance: Parallel Tuning Capacitance.
mcm 2:c3435a136e50 1210 *
mcm 2:c3435a136e50 1211 * @param[out] N/A.
mcm 2:c3435a136e50 1212 *
mcm 2:c3435a136e50 1213 *
mcm 2:c3435a136e50 1214 * @return Status of AS3933_SetParallelTuningCapacitance.
mcm 2:c3435a136e50 1215 *
mcm 2:c3435a136e50 1216 *
mcm 2:c3435a136e50 1217 * @author Manuel Caballero
mcm 2:c3435a136e50 1218 * @date 7/March/2018
mcm 2:c3435a136e50 1219 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1220 * @pre N/A.
mcm 2:c3435a136e50 1221 * @warning N/A.
mcm 2:c3435a136e50 1222 */
mcm 2:c3435a136e50 1223 AS3933::AS3933_status_t AS3933::AS3933_SetParallelTuningCapacitance ( AS3933_parallel_tuning_channels_t myChannel, AS3933_parallel_tuning_capacitance_t myAddedCapacitance )
mcm 2:c3435a136e50 1224 {
mcm 2:c3435a136e50 1225 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1226 int mySPI_status;
mcm 2:c3435a136e50 1227
mcm 2:c3435a136e50 1228 AS3933_spi_command_structure_registers_t myAuxRegister;
mcm 2:c3435a136e50 1229
mcm 2:c3435a136e50 1230
mcm 2:c3435a136e50 1231 // Select the channel
mcm 2:c3435a136e50 1232 switch ( myChannel ){
mcm 2:c3435a136e50 1233 default:
mcm 2:c3435a136e50 1234 case AS3933_CHANNEL_LF1P:
mcm 2:c3435a136e50 1235 myAuxRegister = AS3933_R17;
mcm 2:c3435a136e50 1236 break;
mcm 2:c3435a136e50 1237
mcm 2:c3435a136e50 1238 case AS3933_CHANNEL_LF2P:
mcm 2:c3435a136e50 1239 myAuxRegister = AS3933_R18;
mcm 2:c3435a136e50 1240 break;
mcm 2:c3435a136e50 1241
mcm 2:c3435a136e50 1242 case AS3933_CHANNEL_LF3P:
mcm 2:c3435a136e50 1243 myAuxRegister = AS3933_R19;
mcm 2:c3435a136e50 1244 break;
mcm 2:c3435a136e50 1245 }
mcm 2:c3435a136e50 1246
mcm 2:c3435a136e50 1247
mcm 2:c3435a136e50 1248 // Read register
mcm 2:c3435a136e50 1249 cmd[0] = ( AS3933_READ | myAuxRegister );
mcm 2:c3435a136e50 1250 _cs = 1;
mcm 3:2de552c4ffbc 1251 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1252 _cs = 0;
mcm 2:c3435a136e50 1253
mcm 2:c3435a136e50 1254 // Mask Parallel Tuning Capacitance
mcm 2:c3435a136e50 1255 cmd[1] &= ~( AS3933_CAPACITANCE_MASK );
mcm 2:c3435a136e50 1256
mcm 2:c3435a136e50 1257 // Update Parallel Tuning Capacitance
mcm 2:c3435a136e50 1258 cmd[0] = ( AS3933_WRITE | myAuxRegister );
mcm 2:c3435a136e50 1259 cmd[1] |= ( myAddedCapacitance );
mcm 2:c3435a136e50 1260 _cs = 1;
mcm 2:c3435a136e50 1261 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 0 );
mcm 2:c3435a136e50 1262 _cs = 0;
mcm 2:c3435a136e50 1263
mcm 2:c3435a136e50 1264
mcm 2:c3435a136e50 1265
mcm 2:c3435a136e50 1266
mcm 2:c3435a136e50 1267
mcm 2:c3435a136e50 1268 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1269 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1270 else
mcm 2:c3435a136e50 1271 return AS3933_FAILURE;
mcm 2:c3435a136e50 1272 }
mcm 2:c3435a136e50 1273
mcm 2:c3435a136e50 1274
mcm 2:c3435a136e50 1275 /**
mcm 2:c3435a136e50 1276 * @brief AS3933_GetRSSI ( AS3933_data_t* )
mcm 2:c3435a136e50 1277 *
mcm 2:c3435a136e50 1278 * @details It gets the RSSI for all channels.
mcm 2:c3435a136e50 1279 *
mcm 2:c3435a136e50 1280 * @param[in] mySPI_parameters: N/A
mcm 2:c3435a136e50 1281 *
mcm 2:c3435a136e50 1282 * @param[out] myChannelRSSI: RSSI.
mcm 2:c3435a136e50 1283 *
mcm 2:c3435a136e50 1284 *
mcm 2:c3435a136e50 1285 * @return Status of AS3933_GetRSSI.
mcm 2:c3435a136e50 1286 *
mcm 2:c3435a136e50 1287 *
mcm 2:c3435a136e50 1288 * @author Manuel Caballero
mcm 2:c3435a136e50 1289 * @date 7/March/2018
mcm 2:c3435a136e50 1290 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1291 * @pre N/A.
mcm 2:c3435a136e50 1292 * @warning N/A.
mcm 2:c3435a136e50 1293 */
mcm 2:c3435a136e50 1294 AS3933::AS3933_status_t AS3933::AS3933_GetRSSI ( AS3933_data_t* myChannelRSSI )
mcm 2:c3435a136e50 1295 {
mcm 2:c3435a136e50 1296 char cmd[] = { 0, 0, 0 };
mcm 2:c3435a136e50 1297 int mySPI_status;
mcm 2:c3435a136e50 1298
mcm 2:c3435a136e50 1299
mcm 2:c3435a136e50 1300 // Get All RSSIs
mcm 2:c3435a136e50 1301 // Read R10 register ( auto-increment )
mcm 2:c3435a136e50 1302 cmd[0] = ( AS3933_READ | AS3933_R10 );
mcm 2:c3435a136e50 1303 _cs = 1;
mcm 2:c3435a136e50 1304 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], sizeof( cmd )/sizeof( cmd[0] ) );
mcm 2:c3435a136e50 1305 _cs = 0;
mcm 2:c3435a136e50 1306
mcm 2:c3435a136e50 1307 // Parse the data
mcm 2:c3435a136e50 1308 myChannelRSSI->rssi1 = ( cmd[0] & RSSI1_MASK ); // Channel1: RSSI1
mcm 2:c3435a136e50 1309 myChannelRSSI->rssi3 = ( cmd[1] & RSSI3_MASK ); // Channel3: RSSI3
mcm 2:c3435a136e50 1310 myChannelRSSI->rssi2 = ( cmd[2] & RSSI2_MASK ); // Channel2: RSSI2
mcm 2:c3435a136e50 1311
mcm 2:c3435a136e50 1312
mcm 2:c3435a136e50 1313
mcm 2:c3435a136e50 1314
mcm 2:c3435a136e50 1315
mcm 2:c3435a136e50 1316 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1317 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1318 else
mcm 2:c3435a136e50 1319 return AS3933_FAILURE;
mcm 2:c3435a136e50 1320 }
mcm 2:c3435a136e50 1321
mcm 2:c3435a136e50 1322
mcm 2:c3435a136e50 1323
mcm 2:c3435a136e50 1324 /**
mcm 2:c3435a136e50 1325 * @brief AS3933_Send_DirectCommand ( AS3933_spi_direct_commands_t )
mcm 2:c3435a136e50 1326 *
mcm 2:c3435a136e50 1327 * @details It sends a direct command.
mcm 2:c3435a136e50 1328 *
mcm 2:c3435a136e50 1329 * @param[in] myDirectCommand: Direct command to be sent.
mcm 2:c3435a136e50 1330 *
mcm 2:c3435a136e50 1331 * @param[out] N/A.
mcm 2:c3435a136e50 1332 *
mcm 2:c3435a136e50 1333 *
mcm 2:c3435a136e50 1334 * @return Status of AS3933_Send_DirectCommand.
mcm 2:c3435a136e50 1335 *
mcm 2:c3435a136e50 1336 *
mcm 2:c3435a136e50 1337 * @author Manuel Caballero
mcm 2:c3435a136e50 1338 * @date 7/March/2018
mcm 2:c3435a136e50 1339 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1340 * @pre N/A.
mcm 2:c3435a136e50 1341 * @warning N/A.
mcm 2:c3435a136e50 1342 */
mcm 2:c3435a136e50 1343 AS3933::AS3933_status_t AS3933::AS3933_Send_DirectCommand ( AS3933_spi_direct_commands_t myDirectCommand )
mcm 2:c3435a136e50 1344 {
mcm 3:2de552c4ffbc 1345 char cmd = 0;
mcm 2:c3435a136e50 1346 int mySPI_status;
mcm 2:c3435a136e50 1347
mcm 2:c3435a136e50 1348
mcm 2:c3435a136e50 1349 // Send a direct command
mcm 2:c3435a136e50 1350 cmd = ( AS3933_DIRECT_COMMAND | myDirectCommand );
mcm 2:c3435a136e50 1351 _cs = 1;
mcm 2:c3435a136e50 1352 mySPI_status = _spi.write ( &cmd, 1, &cmd, 0 );
mcm 2:c3435a136e50 1353 _cs = 0;
mcm 2:c3435a136e50 1354
mcm 2:c3435a136e50 1355
mcm 2:c3435a136e50 1356
mcm 2:c3435a136e50 1357
mcm 2:c3435a136e50 1358 if ( mySPI_status == SPI_SUCCESS )
mcm 2:c3435a136e50 1359 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1360 else
mcm 2:c3435a136e50 1361 return AS3933_FAILURE;
mcm 2:c3435a136e50 1362 }