Manuel Caballero / AS3933

3D Low Frequency Wakeup Receiver

AS3933.cpp@4:10d482ca4eb1, 2018-03-13 (annotated)

Committer:
mcm
Date:
Tue Mar 13 15:08:21 2018 +0000
Revision:
4:10d482ca4eb1
Parent:
3:2de552c4ffbc 
The driver was completed and tested ( NUCLEO-L152RE ), it works as expected.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mcm 2:c3435a136e50 1 /**
mcm 2:c3435a136e50 2 * @brief AS3933.cpp
mcm 2:c3435a136e50 3 * @details 3D Low Frequency Wakeup Receiver.
mcm 2:c3435a136e50 4 * Function file.
mcm 2:c3435a136e50 5 *
mcm 2:c3435a136e50 6 *
mcm 2:c3435a136e50 7 * @return N/A
mcm 2:c3435a136e50 8 *
mcm 2:c3435a136e50 9 * @author Manuel Caballero
mcm 2:c3435a136e50 10 * @date 7/March/2018
mcm 2:c3435a136e50 11 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 12 * @pre N/A.
mcm 2:c3435a136e50 13 * @warning N/A
mcm 4:10d482ca4eb1 14 * @pre This code belongs to Nimbus Centre ( http://www.nimbus.cit.ie ).
mcm 2:c3435a136e50 15 */
mcm 2:c3435a136e50 16
mcm 2:c3435a136e50 17 #include "AS3933.h"
mcm 2:c3435a136e50 18
mcm 2:c3435a136e50 19
mcm 2:c3435a136e50 20 AS3933::AS3933 ( PinName mosi, PinName miso, PinName sclk, PinName cs, uint32_t freq )
mcm 2:c3435a136e50 21 : _spi ( mosi, miso, sclk )
mcm 2:c3435a136e50 22 , _cs ( cs )
mcm 2:c3435a136e50 23 {
mcm 2:c3435a136e50 24 _spi.frequency( freq );
mcm 2:c3435a136e50 25 _spi.format ( 8, 1 ); // 8-bits, mode1: CPOL = 0 | CPHA = 1
mcm 2:c3435a136e50 26 }
mcm 2:c3435a136e50 27
mcm 2:c3435a136e50 28
mcm 2:c3435a136e50 29 AS3933::~AS3933()
mcm 2:c3435a136e50 30 {
mcm 2:c3435a136e50 31 }
mcm 2:c3435a136e50 32
mcm 2:c3435a136e50 33
mcm 2:c3435a136e50 34
mcm 2:c3435a136e50 35 /**
mcm 2:c3435a136e50 36 * @brief AS3933_SetLowPowerMode ( AS3933_channels_enable_t , AS3933_scanning_mode_t , AS3933_r4_t_off_value_t )
mcm 2:c3435a136e50 37 *
mcm 2:c3435a136e50 38 * @details It configures the low power mode.
mcm 2:c3435a136e50 39 *
mcm 2:c3435a136e50 40 * @param[in] myEnabledChannels: Number of channels enabled.
mcm 2:c3435a136e50 41 * @param[in] myLowPowerMode: Low power mode.
mcm 2:c3435a136e50 42 * @param[in] myT_Off: Period only if ON/OFF mode is selected ( in myLowPowerMode ), it is ignored otherwise.
mcm 2:c3435a136e50 43 *
mcm 2:c3435a136e50 44 * @param[out] N/A.
mcm 2:c3435a136e50 45 *
mcm 2:c3435a136e50 46 *
mcm 2:c3435a136e50 47 * @return Status of AS3933_SetLowPowerMode.
mcm 2:c3435a136e50 48 *
mcm 2:c3435a136e50 49 *
mcm 2:c3435a136e50 50 * @author Manuel Caballero
mcm 2:c3435a136e50 51 * @date 7/March/2018
mcm 2:c3435a136e50 52 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 53 * @pre N/A
mcm 2:c3435a136e50 54 * @warning Data-sheet p.14 8.1.1 Listening Mode. It is NOT clear which channels have to be enabled according to the
mcm 2:c3435a136e50 55 * low power mode: '...If the three dimensional detection is not required, then it is possible to deactivate one
mcm 2:c3435a136e50 56 * or more channels. In case only two channels are required, then the deactivated channel must be the number
mcm 2:c3435a136e50 57 * three; while in case only one channel is needed, then the active channel must be the number one'.
mcm 2:c3435a136e50 58 *
mcm 2:c3435a136e50 59 * Data-sheet p.37 8.10 Channel Selection in Scanning Mode and ON/OFF Mode: 'In case only 2 channels are active and
mcm 2:c3435a136e50 60 * one of the Low Power modes is enabled, then the channels 1 and 3 have to be active. If the chip works in On-Off
mcm 2:c3435a136e50 61 * mode and only one channel is active then the active channel has to be the channel 1.'.
mcm 2:c3435a136e50 62 *
mcm 2:c3435a136e50 63 * This function follows the methodology in: Low Power Modes/Channels enabled: Data-sheet p.37 8.10 Channel
mcm 2:c3435a136e50 64 * Selection in Scanning Mode and ON/OFF Mode.
mcm 2:c3435a136e50 65 */
mcm 2:c3435a136e50 66 AS3933::AS3933_status_t AS3933::AS3933_SetLowPowerMode ( AS3933_channels_enable_t myEnabledChannels, AS3933_scanning_mode_t myLowPowerMode, AS3933_r4_t_off_value_t myT_Off )
mcm 2:c3435a136e50 67 {
mcm 2:c3435a136e50 68 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 69 int mySPI_status;
mcm 2:c3435a136e50 70
mcm 2:c3435a136e50 71
mcm 2:c3435a136e50 72 // Read R0 register
mcm 2:c3435a136e50 73 cmd[0] = ( AS3933_READ | AS3933_R0 );
mcm 4:10d482ca4eb1 74 _cs = 1;
mcm 3:2de552c4ffbc 75 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 4:10d482ca4eb1 76 _cs = 0;
mcm 2:c3435a136e50 77
mcm 2:c3435a136e50 78 // Mask Channels 1:3
mcm 2:c3435a136e50 79 cmd[1] &= ~( EN_A1_MASK | EN_A2_MASK | EN_A3_MASK );
mcm 2:c3435a136e50 80
mcm 2:c3435a136e50 81 // Mask Scanning Mode
mcm 2:c3435a136e50 82 cmd[1] &= ~( MUX_123_MASK | ON_OFF_MASK );
mcm 2:c3435a136e50 83
mcm 2:c3435a136e50 84
mcm 2:c3435a136e50 85
mcm 2:c3435a136e50 86 // Set the channels enabled
mcm 4:10d482ca4eb1 87 switch ( myEnabledChannels ) {
mcm 4:10d482ca4eb1 88 case AS3933_CH1_OFF_CH2_OFF_CH3_OFF:
mcm 4:10d482ca4eb1 89 cmd[1] &= ( EN_A1_DISABLED | EN_A2_DISABLED | EN_A3_DISABLED );
mcm 4:10d482ca4eb1 90 break;
mcm 2:c3435a136e50 91
mcm 4:10d482ca4eb1 92 case AS3933_CH1_ON_CH2_OFF_CH3_OFF:
mcm 4:10d482ca4eb1 93 cmd[1] |= ( EN_A1_ENABLED );
mcm 4:10d482ca4eb1 94 break;
mcm 2:c3435a136e50 95
mcm 4:10d482ca4eb1 96 case AS3933_CH1_OFF_CH2_ON_CH3_OFF:
mcm 4:10d482ca4eb1 97 cmd[1] |= ( EN_A2_ENABLED );
mcm 4:10d482ca4eb1 98 break;
mcm 4:10d482ca4eb1 99
mcm 4:10d482ca4eb1 100 case AS3933_CH1_ON_CH2_ON_CH3_OFF:
mcm 4:10d482ca4eb1 101 cmd[1] |= ( EN_A1_ENABLED | EN_A2_ENABLED );
mcm 4:10d482ca4eb1 102 break;
mcm 2:c3435a136e50 103
mcm 4:10d482ca4eb1 104 case AS3933_CH1_OFF_CH2_OFF_CH3_ON:
mcm 4:10d482ca4eb1 105 cmd[1] |= ( EN_A3_ENABLED );
mcm 4:10d482ca4eb1 106 break;
mcm 2:c3435a136e50 107
mcm 4:10d482ca4eb1 108 case AS3933_CH1_ON_CH2_OFF_CH3_ON:
mcm 4:10d482ca4eb1 109 cmd[1] |= ( EN_A1_ENABLED | EN_A3_ENABLED );
mcm 4:10d482ca4eb1 110 break;
mcm 2:c3435a136e50 111
mcm 4:10d482ca4eb1 112 case AS3933_CH1_OFF_CH2_ON_CH3_ON:
mcm 4:10d482ca4eb1 113 cmd[1] |= ( EN_A2_ENABLED | EN_A3_ENABLED );
mcm 4:10d482ca4eb1 114 break;
mcm 2:c3435a136e50 115
mcm 4:10d482ca4eb1 116 default:
mcm 4:10d482ca4eb1 117 case AS3933_CH1_ON_CH2_ON_CH3_ON:
mcm 4:10d482ca4eb1 118 cmd[1] |= ( EN_A1_ENABLED | EN_A2_ENABLED | EN_A3_ENABLED );
mcm 4:10d482ca4eb1 119 break;
mcm 2:c3435a136e50 120 }
mcm 2:c3435a136e50 121
mcm 2:c3435a136e50 122
mcm 2:c3435a136e50 123 // Set Scanning mode
mcm 4:10d482ca4eb1 124 switch ( myLowPowerMode ) {
mcm 4:10d482ca4eb1 125 default:
mcm 4:10d482ca4eb1 126 case AS3933_STANDARD_LISTENING_MODE:
mcm 4:10d482ca4eb1 127 break;
mcm 2:c3435a136e50 128
mcm 4:10d482ca4eb1 129 case AS3933_SCANNING_MODE:
mcm 4:10d482ca4eb1 130 if ( ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_ON_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_OFF ) ||
mcm 4:10d482ca4eb1 131 ( myEnabledChannels == AS3933_CH1_OFF_CH2_ON_CH3_OFF ) || ( myEnabledChannels == AS3933_CH1_OFF_CH2_OFF_CH3_ON ) )
mcm 4:10d482ca4eb1 132 cmd[1] |= ( MUX_123_ENABLED );
mcm 4:10d482ca4eb1 133 else
mcm 4:10d482ca4eb1 134 return AS3933_FAILURE;
mcm 2:c3435a136e50 135
mcm 4:10d482ca4eb1 136 break;
mcm 2:c3435a136e50 137
mcm 4:10d482ca4eb1 138 case AS3933_ON_OFF_MODE:
mcm 4:10d482ca4eb1 139 if ( ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_ON_CH3_ON ) || ( myEnabledChannels == AS3933_CH1_ON_CH2_OFF_CH3_OFF ) )
mcm 4:10d482ca4eb1 140 cmd[1] |= ( ON_OFF_ENABLED );
mcm 4:10d482ca4eb1 141 else
mcm 4:10d482ca4eb1 142 return AS3933_FAILURE;
mcm 4:10d482ca4eb1 143 break;
mcm 2:c3435a136e50 144 }
mcm 2:c3435a136e50 145
mcm 2:c3435a136e50 146 // Update power mode and active channels
mcm 2:c3435a136e50 147 cmd[0] = ( AS3933_WRITE | AS3933_R0 );
mcm 2:c3435a136e50 148 _cs = 1;
mcm 4:10d482ca4eb1 149 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 150 _cs = 0;
mcm 2:c3435a136e50 151
mcm 2:c3435a136e50 152
mcm 4:10d482ca4eb1 153 if ( myLowPowerMode == AS3933_ON_OFF_MODE ) {
mcm 2:c3435a136e50 154 // Read R4 register
mcm 2:c3435a136e50 155 cmd[0] = ( AS3933_READ | AS3933_R4 );
mcm 2:c3435a136e50 156 _cs = 1;
mcm 3:2de552c4ffbc 157 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 158 _cs = 0;
mcm 2:c3435a136e50 159
mcm 2:c3435a136e50 160 // Mask T_OFF
mcm 2:c3435a136e50 161 cmd[1] &= ~( T_OFF_MASK );
mcm 2:c3435a136e50 162
mcm 2:c3435a136e50 163 // Update Off time in ON/OFF operation mode
mcm 2:c3435a136e50 164 cmd[1] |= ( myT_Off );
mcm 2:c3435a136e50 165
mcm 2:c3435a136e50 166 cmd[0] = ( AS3933_WRITE | AS3933_R4 );
mcm 2:c3435a136e50 167 _cs = 1;
mcm 4:10d482ca4eb1 168 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 169 _cs = 0;
mcm 2:c3435a136e50 170 }
mcm 2:c3435a136e50 171
mcm 2:c3435a136e50 172
mcm 2:c3435a136e50 173
mcm 2:c3435a136e50 174 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 175 return AS3933_SUCCESS;
mcm 2:c3435a136e50 176 else
mcm 2:c3435a136e50 177 return AS3933_FAILURE;
mcm 2:c3435a136e50 178 }
mcm 2:c3435a136e50 179
mcm 2:c3435a136e50 180
mcm 2:c3435a136e50 181 /**
mcm 2:c3435a136e50 182 * @brief AS3933_SetArtificialWakeUp ( AS3933_r8_t_auto_value_t )
mcm 2:c3435a136e50 183 *
mcm 2:c3435a136e50 184 * @details It configures the artificial wakeup.
mcm 2:c3435a136e50 185 *
mcm 2:c3435a136e50 186 * @param[in] myArtificialWakeUp: Period only if ON/OFF mode is selected ( in myLowPowerMode ), it is ignored otherwise.
mcm 2:c3435a136e50 187 *
mcm 2:c3435a136e50 188 * @param[out] N/A.
mcm 2:c3435a136e50 189 *
mcm 2:c3435a136e50 190 *
mcm 2:c3435a136e50 191 * @return Status of AS3933_SetArtificialWakeUp.
mcm 2:c3435a136e50 192 *
mcm 2:c3435a136e50 193 *
mcm 2:c3435a136e50 194 * @author Manuel Caballero
mcm 2:c3435a136e50 195 * @date 7/March/2018
mcm 2:c3435a136e50 196 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 197 * @pre N/A
mcm 2:c3435a136e50 198 * @warning N/A.
mcm 2:c3435a136e50 199 */
mcm 2:c3435a136e50 200 AS3933::AS3933_status_t AS3933::AS3933_SetArtificialWakeUp ( AS3933_r8_t_auto_value_t myArtificialWakeUp )
mcm 2:c3435a136e50 201 {
mcm 2:c3435a136e50 202 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 203 int mySPI_status;
mcm 2:c3435a136e50 204
mcm 2:c3435a136e50 205
mcm 2:c3435a136e50 206 // Read R8 register
mcm 2:c3435a136e50 207 cmd[0] = ( AS3933_READ | AS3933_R8 );
mcm 2:c3435a136e50 208 _cs = 1;
mcm 3:2de552c4ffbc 209 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 210 _cs = 0;
mcm 2:c3435a136e50 211
mcm 2:c3435a136e50 212 // Mask Artificial wakeup
mcm 2:c3435a136e50 213 cmd[1] &= ~( T_AUTO_MASK );
mcm 2:c3435a136e50 214
mcm 2:c3435a136e50 215 // Update the value
mcm 2:c3435a136e50 216 cmd[1] |= myArtificialWakeUp;
mcm 2:c3435a136e50 217
mcm 2:c3435a136e50 218
mcm 2:c3435a136e50 219 // Update artificial wakeup
mcm 2:c3435a136e50 220 cmd[0] = ( AS3933_WRITE | AS3933_R8 );
mcm 2:c3435a136e50 221 _cs = 1;
mcm 4:10d482ca4eb1 222 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 223 _cs = 0;
mcm 2:c3435a136e50 224
mcm 2:c3435a136e50 225
mcm 2:c3435a136e50 226
mcm 2:c3435a136e50 227
mcm 2:c3435a136e50 228 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 229 return AS3933_SUCCESS;
mcm 2:c3435a136e50 230 else
mcm 2:c3435a136e50 231 return AS3933_FAILURE;
mcm 2:c3435a136e50 232 }
mcm 2:c3435a136e50 233
mcm 2:c3435a136e50 234
mcm 2:c3435a136e50 235 /**
mcm 2:c3435a136e50 236 * @brief AS3933_ReadFalseWakeUpRegister ( AS3933_data_t* )
mcm 2:c3435a136e50 237 *
mcm 2:c3435a136e50 238 * @details It gets feedback on the surrounding environment reading the false wakeup register.
mcm 2:c3435a136e50 239 *
mcm 2:c3435a136e50 240 * @param[in] N/A
mcm 2:c3435a136e50 241 *
mcm 2:c3435a136e50 242 * @param[out] myF_WAKE: F_WAKE register.
mcm 2:c3435a136e50 243 *
mcm 2:c3435a136e50 244 *
mcm 2:c3435a136e50 245 * @return Status of AS3933_ReadFalseWakeUpRegister.
mcm 2:c3435a136e50 246 *
mcm 2:c3435a136e50 247 *
mcm 2:c3435a136e50 248 * @author Manuel Caballero
mcm 2:c3435a136e50 249 * @date 7/March/2018
mcm 2:c3435a136e50 250 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 251 * @pre N/A
mcm 2:c3435a136e50 252 * @warning N/A.
mcm 2:c3435a136e50 253 */
mcm 2:c3435a136e50 254 AS3933::AS3933_status_t AS3933::AS3933_ReadFalseWakeUpRegister ( AS3933_data_t* myF_WAKE )
mcm 2:c3435a136e50 255 {
mcm 3:2de552c4ffbc 256 char cmd[] = { ( AS3933_READ | AS3933_R13 ), 0 };
mcm 2:c3435a136e50 257 int mySPI_status;
mcm 2:c3435a136e50 258
mcm 2:c3435a136e50 259
mcm 2:c3435a136e50 260 // Read R13 register
mcm 2:c3435a136e50 261 _cs = 1;
mcm 3:2de552c4ffbc 262 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 263 _cs = 0;
mcm 4:10d482ca4eb1 264
mcm 4:10d482ca4eb1 265
mcm 3:2de552c4ffbc 266 myF_WAKE->f_wake = cmd[1];
mcm 2:c3435a136e50 267
mcm 2:c3435a136e50 268
mcm 2:c3435a136e50 269
mcm 2:c3435a136e50 270 if ( mySPI_status == SPI_SUCCESS )
mcm 2:c3435a136e50 271 return AS3933_SUCCESS;
mcm 2:c3435a136e50 272 else
mcm 2:c3435a136e50 273 return AS3933_FAILURE;
mcm 2:c3435a136e50 274 }
mcm 2:c3435a136e50 275
mcm 2:c3435a136e50 276
mcm 2:c3435a136e50 277 /**
mcm 2:c3435a136e50 278 * @brief AS3933_SetClockGenerator ( AS3933_r1_en_xtal_value_t, AS3933_r16_clock_gen_dis_value_t )
mcm 2:c3435a136e50 279 *
mcm 2:c3435a136e50 280 * @details It configures the clock generator.
mcm 2:c3435a136e50 281 *
mcm 2:c3435a136e50 282 * @param[in] myClockGenerator: Enable/Disable external crystal oscillator.
mcm 2:c3435a136e50 283 * @param[in] myClockGeneratorOutputMode: Enable/Disable the clock generator output signal displayed on CL_DAT pin.
mcm 2:c3435a136e50 284 *
mcm 2:c3435a136e50 285 * @param[out] N/A.
mcm 2:c3435a136e50 286 *
mcm 2:c3435a136e50 287 *
mcm 2:c3435a136e50 288 * @return Status of AS3933_SetClockGenerator.
mcm 2:c3435a136e50 289 *
mcm 2:c3435a136e50 290 *
mcm 2:c3435a136e50 291 * @author Manuel Caballero
mcm 2:c3435a136e50 292 * @date 7/March/2018
mcm 2:c3435a136e50 293 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 294 * @pre N/A
mcm 2:c3435a136e50 295 * @warning N/A.
mcm 2:c3435a136e50 296 */
mcm 2:c3435a136e50 297 AS3933::AS3933_status_t AS3933::AS3933_SetClockGenerator ( AS3933_r1_en_xtal_value_t myClockGenerator, AS3933_r16_clock_gen_dis_value_t myClockGeneratorOutputMode )
mcm 2:c3435a136e50 298 {
mcm 2:c3435a136e50 299 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 300 int mySPI_status;
mcm 2:c3435a136e50 301
mcm 2:c3435a136e50 302
mcm 2:c3435a136e50 303 // Configure the Crystal oscillator
mcm 2:c3435a136e50 304 // Read R1 register
mcm 2:c3435a136e50 305 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 306 _cs = 1;
mcm 3:2de552c4ffbc 307 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 308 _cs = 0;
mcm 2:c3435a136e50 309
mcm 2:c3435a136e50 310 // Mask Crystal oscillator
mcm 2:c3435a136e50 311 cmd[1] &= ~( EN_XTAL_MASK );
mcm 2:c3435a136e50 312
mcm 2:c3435a136e50 313 // Update the value
mcm 2:c3435a136e50 314 cmd[1] |= myClockGenerator;
mcm 2:c3435a136e50 315
mcm 2:c3435a136e50 316
mcm 2:c3435a136e50 317 // Update Crystal oscillator
mcm 2:c3435a136e50 318 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 319 _cs = 1;
mcm 4:10d482ca4eb1 320 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 321 _cs = 0;
mcm 2:c3435a136e50 322
mcm 2:c3435a136e50 323
mcm 2:c3435a136e50 324 // Configure the Clock Generator Output
mcm 2:c3435a136e50 325 // Read R16 register
mcm 2:c3435a136e50 326 cmd[0] = ( AS3933_READ | AS3933_R16 );
mcm 2:c3435a136e50 327 _cs = 1;
mcm 3:2de552c4ffbc 328 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 329 _cs = 0;
mcm 2:c3435a136e50 330
mcm 2:c3435a136e50 331 // Mask Clock Generator output signal
mcm 2:c3435a136e50 332 cmd[1] &= ~( CLOCK_GEN_DIS_MASK );
mcm 2:c3435a136e50 333
mcm 2:c3435a136e50 334 // Update the value
mcm 2:c3435a136e50 335 cmd[1] |= myClockGeneratorOutputMode;
mcm 2:c3435a136e50 336
mcm 2:c3435a136e50 337
mcm 2:c3435a136e50 338 // Update Clock Generator output signal
mcm 2:c3435a136e50 339 cmd[0] = ( AS3933_WRITE | AS3933_R16 );
mcm 2:c3435a136e50 340 _cs = 1;
mcm 4:10d482ca4eb1 341 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 342 _cs = 0;
mcm 2:c3435a136e50 343
mcm 2:c3435a136e50 344
mcm 2:c3435a136e50 345
mcm 2:c3435a136e50 346
mcm 2:c3435a136e50 347 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 348 return AS3933_SUCCESS;
mcm 2:c3435a136e50 349 else
mcm 2:c3435a136e50 350 return AS3933_FAILURE;
mcm 2:c3435a136e50 351 }
mcm 2:c3435a136e50 352
mcm 2:c3435a136e50 353
mcm 2:c3435a136e50 354 /**
mcm 2:c3435a136e50 355 * @brief AS3933_CalibrateRC_Oscillator ( AS3933_r1_en_xtal_value_t, AS3933_r16_clock_gen_dis_value_t )
mcm 2:c3435a136e50 356 *
mcm 2:c3435a136e50 357 * @details It calibrates RC oscillator.
mcm 2:c3435a136e50 358 *
mcm 2:c3435a136e50 359 * @param[in] N/A
mcm 2:c3435a136e50 360 *
mcm 2:c3435a136e50 361 * @param[out] N/A.
mcm 2:c3435a136e50 362 *
mcm 2:c3435a136e50 363 *
mcm 2:c3435a136e50 364 * @return Status of AS3933_CalibrateRC_Oscillator.
mcm 2:c3435a136e50 365 *
mcm 2:c3435a136e50 366 *
mcm 2:c3435a136e50 367 * @author Manuel Caballero
mcm 2:c3435a136e50 368 * @date 7/March/2018
mcm 4:10d482ca4eb1 369 * @version 12/March/2018 The timeout was removed, the bits for calibration are checked instead.
mcm 4:10d482ca4eb1 370 * 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 371 * @pre RC-Oscillator: Self Calibration is ONLY available.
mcm 4:10d482ca4eb1 372 * @pre There is NO need to calibrate the RC oscillator if the crystal oscillator is enabled.
mcm 2:c3435a136e50 373 * @warning In case the pattern detection and the Manchester decoder are not enabled ( R1<1>=0 and R1<3>=1 ) the calibration on the RC-oscillator
mcm 2:c3435a136e50 374 * is not needed. Should this not be the case, the RC-oscillator has to be calibrated.
mcm 2:c3435a136e50 375 */
mcm 2:c3435a136e50 376 AS3933::AS3933_status_t AS3933::AS3933_CalibrateRC_Oscillator ( void )
mcm 2:c3435a136e50 377 {
mcm 3:2de552c4ffbc 378 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 379 int mySPI_status;
mcm 2:c3435a136e50 380
mcm 2:c3435a136e50 381
mcm 2:c3435a136e50 382 // Start the calibration
mcm 3:2de552c4ffbc 383 cmd[0] = ( AS3933_DIRECT_COMMAND | CALIB_RCO_LC );
mcm 2:c3435a136e50 384 _cs = 1;
mcm 4:10d482ca4eb1 385 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 386 _cs = 0;
mcm 2:c3435a136e50 387
mcm 2:c3435a136e50 388
mcm 2:c3435a136e50 389 // RC oscillator will be calibrated when RC_CAL_OK = '1' ( R14<6> )
mcm 4:10d482ca4eb1 390 do {
mcm 3:2de552c4ffbc 391 cmd[0] = ( AS3933_READ | AS3933_R14 );
mcm 2:c3435a136e50 392 _cs = 1;
mcm 3:2de552c4ffbc 393 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 394 _cs = 0;
mcm 4:10d482ca4eb1 395 } while ( ( ( cmd[1] & RC_CAL_OK_MASK ) != RC_CAL_OK_HIGH ) && ( ( cmd[1] & RC_CAL_KO_MASK ) != RC_CAL_KO_HIGH ) );
mcm 2:c3435a136e50 396
mcm 2:c3435a136e50 397
mcm 2:c3435a136e50 398
mcm 4:10d482ca4eb1 399 if ( ( mySPI_status == SPI_SUCCESS ) && ( ( cmd[1] & RC_CAL_KO_MASK ) != RC_CAL_KO_HIGH ) )
mcm 2:c3435a136e50 400 return AS3933_SUCCESS;
mcm 2:c3435a136e50 401 else
mcm 2:c3435a136e50 402 return AS3933_FAILURE;
mcm 2:c3435a136e50 403 }
mcm 2:c3435a136e50 404
mcm 2:c3435a136e50 405
mcm 2:c3435a136e50 406 /**
mcm 2:c3435a136e50 407 * @brief AS3933_SetAntennaDamper ( AS3933_r1_att_on_value_t, AS3933_r4_d_res_value_t )
mcm 2:c3435a136e50 408 *
mcm 2:c3435a136e50 409 * @details It configures the antenna damper and its shunt resistor.
mcm 2:c3435a136e50 410 *
mcm 2:c3435a136e50 411 * @param[in] myAntennaDamperMode: Enable/Disable antenna dumper.
mcm 2:c3435a136e50 412 * @param[in] myShuntResistor: Configure antenna dumping resistor.
mcm 2:c3435a136e50 413 *
mcm 2:c3435a136e50 414 * @param[out] N/A.
mcm 2:c3435a136e50 415 *
mcm 2:c3435a136e50 416 *
mcm 2:c3435a136e50 417 * @return Status of AS3933_SetAntennaDamper.
mcm 2:c3435a136e50 418 *
mcm 2:c3435a136e50 419 *
mcm 2:c3435a136e50 420 * @author Manuel Caballero
mcm 2:c3435a136e50 421 * @date 7/March/2018
mcm 2:c3435a136e50 422 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 423 * @pre N/A.
mcm 2:c3435a136e50 424 * @warning N/A.
mcm 2:c3435a136e50 425 */
mcm 2:c3435a136e50 426 AS3933::AS3933_status_t AS3933::AS3933_SetAntennaDamper ( AS3933_r1_att_on_value_t myAntennaDamperMode, AS3933_r4_d_res_value_t myShuntResistor )
mcm 2:c3435a136e50 427 {
mcm 2:c3435a136e50 428 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 429 int mySPI_status;
mcm 2:c3435a136e50 430
mcm 2:c3435a136e50 431
mcm 2:c3435a136e50 432 // Configure Antenna dumper
mcm 2:c3435a136e50 433 // Read R1 register
mcm 2:c3435a136e50 434 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 435 _cs = 1;
mcm 3:2de552c4ffbc 436 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 437 _cs = 0;
mcm 2:c3435a136e50 438
mcm 2:c3435a136e50 439 // Mask Antenna dumper
mcm 2:c3435a136e50 440 cmd[1] &= ~( ATT_ON_MASK );
mcm 2:c3435a136e50 441
mcm 2:c3435a136e50 442 // Update Antenna dumper
mcm 2:c3435a136e50 443 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 444 cmd[1] |= ( myAntennaDamperMode );
mcm 2:c3435a136e50 445 _cs = 1;
mcm 4:10d482ca4eb1 446 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 447 _cs = 0;
mcm 2:c3435a136e50 448
mcm 2:c3435a136e50 449
mcm 2:c3435a136e50 450 // Configure Antenna dumper resistor
mcm 2:c3435a136e50 451 // Read R4 register
mcm 2:c3435a136e50 452 cmd[0] = ( AS3933_READ | AS3933_R4 );
mcm 2:c3435a136e50 453 _cs = 1;
mcm 3:2de552c4ffbc 454 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 455 _cs = 0;
mcm 2:c3435a136e50 456
mcm 2:c3435a136e50 457 // Mask Antenna dumper resistor
mcm 2:c3435a136e50 458 cmd[1] &= ~( D_RES_MASK );
mcm 2:c3435a136e50 459
mcm 2:c3435a136e50 460 // Update Antenna dumper resistor
mcm 2:c3435a136e50 461 cmd[0] = ( AS3933_WRITE | AS3933_R4 );
mcm 2:c3435a136e50 462 cmd[1] |= ( myShuntResistor );
mcm 2:c3435a136e50 463 _cs = 1;
mcm 4:10d482ca4eb1 464 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 465 _cs = 0;
mcm 2:c3435a136e50 466
mcm 2:c3435a136e50 467
mcm 2:c3435a136e50 468
mcm 2:c3435a136e50 469
mcm 2:c3435a136e50 470 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 471 return AS3933_SUCCESS;
mcm 2:c3435a136e50 472 else
mcm 2:c3435a136e50 473 return AS3933_FAILURE;
mcm 2:c3435a136e50 474 }
mcm 2:c3435a136e50 475
mcm 2:c3435a136e50 476
mcm 2:c3435a136e50 477 /**
mcm 2:c3435a136e50 478 * @brief AS3933_SetEnvelopDetector ( AS3933_r3_fs_env_value_t )
mcm 2:c3435a136e50 479 *
mcm 2:c3435a136e50 480 * @details It configures the envelop detector for different symbol rates.
mcm 2:c3435a136e50 481 *
mcm 2:c3435a136e50 482 * @param[in] mySymbolRates: Envelop detector time constant.
mcm 2:c3435a136e50 483 *
mcm 2:c3435a136e50 484 * @param[out] N/A.
mcm 2:c3435a136e50 485 *
mcm 2:c3435a136e50 486 *
mcm 2:c3435a136e50 487 * @return Status of AS3933_SetEnvelopDetector.
mcm 2:c3435a136e50 488 *
mcm 2:c3435a136e50 489 *
mcm 2:c3435a136e50 490 * @author Manuel Caballero
mcm 2:c3435a136e50 491 * @date 7/March/2018
mcm 2:c3435a136e50 492 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 493 * @pre N/A.
mcm 2:c3435a136e50 494 * @warning N/A.
mcm 2:c3435a136e50 495 */
mcm 2:c3435a136e50 496 AS3933::AS3933_status_t AS3933::AS3933_SetEnvelopDetector ( AS3933_r3_fs_env_value_t mySymbolRates )
mcm 2:c3435a136e50 497 {
mcm 2:c3435a136e50 498 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 499 int mySPI_status;
mcm 2:c3435a136e50 500
mcm 2:c3435a136e50 501
mcm 2:c3435a136e50 502 // Read R3 register
mcm 2:c3435a136e50 503 cmd[0] = ( AS3933_READ | AS3933_R3 );
mcm 2:c3435a136e50 504 _cs = 1;
mcm 3:2de552c4ffbc 505 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 506 _cs = 0;
mcm 2:c3435a136e50 507
mcm 2:c3435a136e50 508 // Mask Symbol rate
mcm 2:c3435a136e50 509 cmd[1] &= ~( FS_ENV_MASK );
mcm 2:c3435a136e50 510
mcm 2:c3435a136e50 511 // Update symbol rate
mcm 2:c3435a136e50 512 cmd[0] = ( AS3933_WRITE | AS3933_R3 );
mcm 2:c3435a136e50 513 cmd[1] |= ( mySymbolRates );
mcm 2:c3435a136e50 514 _cs = 1;
mcm 4:10d482ca4eb1 515 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 516 _cs = 0;
mcm 2:c3435a136e50 517
mcm 2:c3435a136e50 518
mcm 2:c3435a136e50 519
mcm 2:c3435a136e50 520
mcm 2:c3435a136e50 521
mcm 2:c3435a136e50 522 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 523 return AS3933_SUCCESS;
mcm 2:c3435a136e50 524 else
mcm 2:c3435a136e50 525 return AS3933_FAILURE;
mcm 2:c3435a136e50 526 }
mcm 2:c3435a136e50 527
mcm 2:c3435a136e50 528
mcm 2:c3435a136e50 529 /**
mcm 2:c3435a136e50 530 * @brief AS3933_SetDataSlicer ( AS3933_r1_abs_hy_value_t , AS3933_r3_fs_scl_value_t )
mcm 2:c3435a136e50 531 *
mcm 2:c3435a136e50 532 * @details It configures the data slicer for different preamble length.
mcm 2:c3435a136e50 533 *
mcm 2:c3435a136e50 534 * @param[in] myAbsoluteThresholdMode: Enable Data slicer absolute reference.
mcm 2:c3435a136e50 535 * @param[in] myMinimumPreambleLength: Data slices time constant.
mcm 2:c3435a136e50 536 *
mcm 2:c3435a136e50 537 * @param[out] N/A.
mcm 2:c3435a136e50 538 *
mcm 2:c3435a136e50 539 *
mcm 2:c3435a136e50 540 * @return Status of AS3933_SetDataSlicer.
mcm 2:c3435a136e50 541 *
mcm 2:c3435a136e50 542 *
mcm 2:c3435a136e50 543 * @author Manuel Caballero
mcm 2:c3435a136e50 544 * @date 7/March/2018
mcm 2:c3435a136e50 545 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 546 * @pre N/A.
mcm 2:c3435a136e50 547 * @warning N/A.
mcm 2:c3435a136e50 548 */
mcm 2:c3435a136e50 549 AS3933::AS3933_status_t AS3933::AS3933_SetDataSlicer ( AS3933_r1_abs_hy_value_t myAbsoluteThresholdMode, AS3933_r3_fs_scl_value_t myMinimumPreambleLength )
mcm 2:c3435a136e50 550 {
mcm 2:c3435a136e50 551 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 552 int mySPI_status;
mcm 2:c3435a136e50 553
mcm 2:c3435a136e50 554
mcm 2:c3435a136e50 555 // Configure Data slicer absolute reference
mcm 2:c3435a136e50 556 // Read R1 register
mcm 2:c3435a136e50 557 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 558 _cs = 1;
mcm 3:2de552c4ffbc 559 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 560 _cs = 0;
mcm 2:c3435a136e50 561
mcm 2:c3435a136e50 562 // Mask Data slicer absolute reference
mcm 2:c3435a136e50 563 cmd[1] &= ~( ABS_HY_MASK );
mcm 2:c3435a136e50 564
mcm 2:c3435a136e50 565 // Update symbol rate
mcm 2:c3435a136e50 566 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 567 cmd[1] |= ( myAbsoluteThresholdMode );
mcm 2:c3435a136e50 568 _cs = 1;
mcm 4:10d482ca4eb1 569 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 570 _cs = 0;
mcm 2:c3435a136e50 571
mcm 2:c3435a136e50 572
mcm 2:c3435a136e50 573 // Configure Data slices time constant
mcm 2:c3435a136e50 574 // Read R3 register
mcm 2:c3435a136e50 575 cmd[0] = ( AS3933_READ | AS3933_R3 );
mcm 2:c3435a136e50 576 _cs = 1;
mcm 3:2de552c4ffbc 577 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 578 _cs = 0;
mcm 2:c3435a136e50 579
mcm 2:c3435a136e50 580 // Mask Data slices time constant
mcm 2:c3435a136e50 581 cmd[1] &= ~( FS_SCL_MASK );
mcm 2:c3435a136e50 582
mcm 2:c3435a136e50 583 // Update Data slices time constant
mcm 2:c3435a136e50 584 cmd[0] = ( AS3933_WRITE | AS3933_R3 );
mcm 2:c3435a136e50 585 cmd[1] |= ( myMinimumPreambleLength );
mcm 2:c3435a136e50 586 _cs = 1;
mcm 4:10d482ca4eb1 587 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 588 _cs = 0;
mcm 2:c3435a136e50 589
mcm 2:c3435a136e50 590
mcm 2:c3435a136e50 591
mcm 2:c3435a136e50 592
mcm 2:c3435a136e50 593 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 594 return AS3933_SUCCESS;
mcm 2:c3435a136e50 595 else
mcm 2:c3435a136e50 596 return AS3933_FAILURE;
mcm 2:c3435a136e50 597 }
mcm 2:c3435a136e50 598
mcm 2:c3435a136e50 599
mcm 2:c3435a136e50 600 /**
mcm 2:c3435a136e50 601 * @brief AS3933_SetComparatorHysteresis ( AS3933_r3_hy_pos_value_t , AS3933_r3_hy_20m_value_t )
mcm 2:c3435a136e50 602 *
mcm 2:c3435a136e50 603 * @details It configures the hysteresis on the data slicer comparator.
mcm 2:c3435a136e50 604 *
mcm 2:c3435a136e50 605 * @param[in] myHysteresisMode: Data slicer hysteresis, edge.
mcm 2:c3435a136e50 606 * @param[in] myHysteresisRange: Data slicer hysteresis, comparator.
mcm 2:c3435a136e50 607 *
mcm 2:c3435a136e50 608 * @param[out] N/A.
mcm 2:c3435a136e50 609 *
mcm 2:c3435a136e50 610 *
mcm 2:c3435a136e50 611 * @return Status of AS3933_SetComparatorHysteresis.
mcm 2:c3435a136e50 612 *
mcm 2:c3435a136e50 613 *
mcm 2:c3435a136e50 614 * @author Manuel Caballero
mcm 2:c3435a136e50 615 * @date 7/March/2018
mcm 2:c3435a136e50 616 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 617 * @pre N/A.
mcm 2:c3435a136e50 618 * @warning N/A.
mcm 2:c3435a136e50 619 */
mcm 2:c3435a136e50 620 AS3933::AS3933_status_t AS3933::AS3933_SetComparatorHysteresis ( AS3933_r3_hy_pos_value_t myHysteresisMode, AS3933_r3_hy_20m_value_t myHysteresisRange )
mcm 2:c3435a136e50 621 {
mcm 2:c3435a136e50 622 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 623 int mySPI_status;
mcm 2:c3435a136e50 624
mcm 2:c3435a136e50 625
mcm 2:c3435a136e50 626 // Read R3 register
mcm 2:c3435a136e50 627 cmd[0] = ( AS3933_READ | AS3933_R3 );
mcm 2:c3435a136e50 628 _cs = 1;
mcm 3:2de552c4ffbc 629 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 630 _cs = 0;
mcm 2:c3435a136e50 631
mcm 2:c3435a136e50 632 // Mask both hysteresis edge and comparator
mcm 2:c3435a136e50 633 cmd[1] &= ~( HY_POS_MASK | HY_20M_MASK );
mcm 2:c3435a136e50 634
mcm 2:c3435a136e50 635 // Update hysteresis on the data slicer comparator
mcm 2:c3435a136e50 636 cmd[0] = ( AS3933_WRITE | AS3933_R3 );
mcm 2:c3435a136e50 637 cmd[1] |= ( myHysteresisMode | myHysteresisRange );
mcm 2:c3435a136e50 638 _cs = 1;
mcm 4:10d482ca4eb1 639 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 640 _cs = 0;
mcm 2:c3435a136e50 641
mcm 2:c3435a136e50 642
mcm 2:c3435a136e50 643
mcm 2:c3435a136e50 644
mcm 2:c3435a136e50 645 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 646 return AS3933_SUCCESS;
mcm 2:c3435a136e50 647 else
mcm 2:c3435a136e50 648 return AS3933_FAILURE;
mcm 2:c3435a136e50 649 }
mcm 2:c3435a136e50 650
mcm 2:c3435a136e50 651
mcm 2:c3435a136e50 652 /**
mcm 2:c3435a136e50 653 * @brief AS3933_SetGainReduction ( AS3933_r4_gr_value_t )
mcm 2:c3435a136e50 654 *
mcm 2:c3435a136e50 655 * @details It configures the gain reduction.
mcm 2:c3435a136e50 656 *
mcm 2:c3435a136e50 657 * @param[in] myGainReductionValue: Gain reduction.
mcm 2:c3435a136e50 658 *
mcm 2:c3435a136e50 659 * @param[out] N/A.
mcm 2:c3435a136e50 660 *
mcm 2:c3435a136e50 661 *
mcm 2:c3435a136e50 662 * @return Status of AS3933_SetGainReduction.
mcm 2:c3435a136e50 663 *
mcm 2:c3435a136e50 664 *
mcm 2:c3435a136e50 665 * @author Manuel Caballero
mcm 2:c3435a136e50 666 * @date 7/March/2018
mcm 2:c3435a136e50 667 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 668 * @pre N/A.
mcm 2:c3435a136e50 669 * @warning N/A.
mcm 2:c3435a136e50 670 */
mcm 2:c3435a136e50 671 AS3933::AS3933_status_t AS3933::AS3933_SetGainReduction ( AS3933_r4_gr_value_t myGainReductionValue )
mcm 2:c3435a136e50 672 {
mcm 2:c3435a136e50 673 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 674 int mySPI_status;
mcm 2:c3435a136e50 675
mcm 2:c3435a136e50 676
mcm 2:c3435a136e50 677 // Read R4 register
mcm 2:c3435a136e50 678 cmd[0] = ( AS3933_READ | AS3933_R4 );
mcm 2:c3435a136e50 679 _cs = 1;
mcm 3:2de552c4ffbc 680 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 681 _cs = 0;
mcm 2:c3435a136e50 682
mcm 2:c3435a136e50 683 // Mask Gain reduction
mcm 2:c3435a136e50 684 cmd[1] &= ~( GR_MASK );
mcm 2:c3435a136e50 685
mcm 2:c3435a136e50 686 // Update Gain reduction
mcm 2:c3435a136e50 687 cmd[0] = ( AS3933_WRITE | AS3933_R4 );
mcm 2:c3435a136e50 688 cmd[1] |= ( myGainReductionValue );
mcm 2:c3435a136e50 689 _cs = 1;
mcm 4:10d482ca4eb1 690 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 691 _cs = 0;
mcm 2:c3435a136e50 692
mcm 2:c3435a136e50 693
mcm 2:c3435a136e50 694
mcm 2:c3435a136e50 695
mcm 2:c3435a136e50 696 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 697 return AS3933_SUCCESS;
mcm 2:c3435a136e50 698 else
mcm 2:c3435a136e50 699 return AS3933_FAILURE;
mcm 2:c3435a136e50 700 }
mcm 2:c3435a136e50 701
mcm 2:c3435a136e50 702
mcm 2:c3435a136e50 703 /**
mcm 2:c3435a136e50 704 * @brief AS3933_SetOperatingFrequencyRange ( AS3933_r8_band_sel_value_t )
mcm 2:c3435a136e50 705 *
mcm 2:c3435a136e50 706 * @details It configures the operating frequency range.
mcm 2:c3435a136e50 707 *
mcm 2:c3435a136e50 708 * @param[in] myOperatingFrequencyRange: Band selection.
mcm 2:c3435a136e50 709 *
mcm 2:c3435a136e50 710 * @param[out] N/A.
mcm 2:c3435a136e50 711 *
mcm 2:c3435a136e50 712 *
mcm 2:c3435a136e50 713 * @return Status of AS3933_SetOperatingFrequencyRange.
mcm 2:c3435a136e50 714 *
mcm 2:c3435a136e50 715 *
mcm 2:c3435a136e50 716 * @author Manuel Caballero
mcm 2:c3435a136e50 717 * @date 7/March/2018
mcm 2:c3435a136e50 718 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 719 * @pre N/A.
mcm 2:c3435a136e50 720 * @warning N/A.
mcm 2:c3435a136e50 721 */
mcm 2:c3435a136e50 722 AS3933::AS3933_status_t AS3933::AS3933_SetOperatingFrequencyRange ( AS3933_r8_band_sel_value_t myOperatingFrequencyRange )
mcm 2:c3435a136e50 723 {
mcm 2:c3435a136e50 724 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 725 int mySPI_status;
mcm 2:c3435a136e50 726
mcm 2:c3435a136e50 727
mcm 2:c3435a136e50 728 // Read R8 register
mcm 2:c3435a136e50 729 cmd[0] = ( AS3933_READ | AS3933_R8 );
mcm 2:c3435a136e50 730 _cs = 1;
mcm 3:2de552c4ffbc 731 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 732 _cs = 0;
mcm 2:c3435a136e50 733
mcm 2:c3435a136e50 734 // Mask Band selection
mcm 2:c3435a136e50 735 cmd[1] &= ~( BAND_SEL_MASK );
mcm 2:c3435a136e50 736
mcm 2:c3435a136e50 737 // Update Band selection
mcm 2:c3435a136e50 738 cmd[0] = ( AS3933_WRITE | AS3933_R8 );
mcm 2:c3435a136e50 739 cmd[1] |= ( myOperatingFrequencyRange );
mcm 2:c3435a136e50 740 _cs = 1;
mcm 4:10d482ca4eb1 741 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 742 _cs = 0;
mcm 2:c3435a136e50 743
mcm 2:c3435a136e50 744
mcm 2:c3435a136e50 745
mcm 2:c3435a136e50 746
mcm 2:c3435a136e50 747 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 748 return AS3933_SUCCESS;
mcm 2:c3435a136e50 749 else
mcm 2:c3435a136e50 750 return AS3933_FAILURE;
mcm 2:c3435a136e50 751 }
mcm 2:c3435a136e50 752
mcm 2:c3435a136e50 753
mcm 2:c3435a136e50 754 /**
mcm 2:c3435a136e50 755 * @brief AS3933_SetFrequencyDetectionTolerance ( AS3933_tolerance_settings_t )
mcm 2:c3435a136e50 756 *
mcm 2:c3435a136e50 757 * @details It configures the frequency detection tolerance.
mcm 2:c3435a136e50 758 *
mcm 2:c3435a136e50 759 * @param[in] myTolerance: Tolerance band.
mcm 2:c3435a136e50 760 *
mcm 2:c3435a136e50 761 * @param[out] N/A.
mcm 2:c3435a136e50 762 *
mcm 2:c3435a136e50 763 *
mcm 2:c3435a136e50 764 * @return Status of AS3933_SetFrequencyDetectionTolerance.
mcm 2:c3435a136e50 765 *
mcm 2:c3435a136e50 766 *
mcm 2:c3435a136e50 767 * @author Manuel Caballero
mcm 2:c3435a136e50 768 * @date 7/March/2018
mcm 2:c3435a136e50 769 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 770 * @pre N/A.
mcm 2:c3435a136e50 771 * @warning N/A.
mcm 2:c3435a136e50 772 */
mcm 2:c3435a136e50 773 AS3933::AS3933_status_t AS3933::AS3933_SetFrequencyDetectionTolerance ( AS3933_tolerance_settings_t myTolerance )
mcm 2:c3435a136e50 774 {
mcm 2:c3435a136e50 775 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 776 int mySPI_status;
mcm 2:c3435a136e50 777
mcm 2:c3435a136e50 778
mcm 2:c3435a136e50 779 // Read R2 register
mcm 2:c3435a136e50 780 cmd[0] = ( AS3933_READ | AS3933_R2 );
mcm 2:c3435a136e50 781 _cs = 1;
mcm 3:2de552c4ffbc 782 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 783 _cs = 0;
mcm 2:c3435a136e50 784
mcm 2:c3435a136e50 785 // Mask Tolerance band
mcm 2:c3435a136e50 786 cmd[1] &= ~( AS3933_TOLERANCE_MASK );
mcm 2:c3435a136e50 787
mcm 2:c3435a136e50 788 // Update Tolerance band
mcm 2:c3435a136e50 789 cmd[0] = ( AS3933_WRITE | AS3933_R2 );
mcm 2:c3435a136e50 790 cmd[1] |= ( myTolerance );
mcm 2:c3435a136e50 791 _cs = 1;
mcm 4:10d482ca4eb1 792 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 793 _cs = 0;
mcm 2:c3435a136e50 794
mcm 2:c3435a136e50 795
mcm 2:c3435a136e50 796
mcm 2:c3435a136e50 797
mcm 2:c3435a136e50 798 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 799 return AS3933_SUCCESS;
mcm 2:c3435a136e50 800 else
mcm 2:c3435a136e50 801 return AS3933_FAILURE;
mcm 2:c3435a136e50 802 }
mcm 2:c3435a136e50 803
mcm 2:c3435a136e50 804
mcm 2:c3435a136e50 805 /**
mcm 2:c3435a136e50 806 * @brief AS3933_SetGainBoost ( AS3933_r2_g_boost_value_t )
mcm 2:c3435a136e50 807 *
mcm 2:c3435a136e50 808 * @details It configures the +3dB gain boost.
mcm 2:c3435a136e50 809 *
mcm 2:c3435a136e50 810 * @param[in] myGainBoostMode: Enable/Disable +3dB Amplifier Gain Boost.
mcm 2:c3435a136e50 811 *
mcm 2:c3435a136e50 812 * @param[out] N/A.
mcm 2:c3435a136e50 813 *
mcm 2:c3435a136e50 814 *
mcm 2:c3435a136e50 815 * @return Status of AS3933_SetGainBoost.
mcm 2:c3435a136e50 816 *
mcm 2:c3435a136e50 817 *
mcm 2:c3435a136e50 818 * @author Manuel Caballero
mcm 2:c3435a136e50 819 * @date 7/March/2018
mcm 2:c3435a136e50 820 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 821 * @pre N/A.
mcm 2:c3435a136e50 822 * @warning N/A.
mcm 2:c3435a136e50 823 */
mcm 2:c3435a136e50 824 AS3933::AS3933_status_t AS3933::AS3933_SetGainBoost ( AS3933_r2_g_boost_value_t myGainBoostMode )
mcm 2:c3435a136e50 825 {
mcm 2:c3435a136e50 826 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 827 int mySPI_status;
mcm 2:c3435a136e50 828
mcm 2:c3435a136e50 829
mcm 2:c3435a136e50 830 // Read R2 register
mcm 2:c3435a136e50 831 cmd[0] = ( AS3933_READ | AS3933_R2 );
mcm 2:c3435a136e50 832 _cs = 1;
mcm 3:2de552c4ffbc 833 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 834 _cs = 0;
mcm 2:c3435a136e50 835
mcm 2:c3435a136e50 836 // Mask Gain boost
mcm 2:c3435a136e50 837 cmd[1] &= ~( G_BOOST_MASK );
mcm 2:c3435a136e50 838
mcm 2:c3435a136e50 839 // Update Gain boost
mcm 2:c3435a136e50 840 cmd[0] = ( AS3933_WRITE | AS3933_R2 );
mcm 2:c3435a136e50 841 cmd[1] |= ( myGainBoostMode );
mcm 2:c3435a136e50 842 _cs = 1;
mcm 4:10d482ca4eb1 843 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 844 _cs = 0;
mcm 2:c3435a136e50 845
mcm 2:c3435a136e50 846
mcm 2:c3435a136e50 847
mcm 2:c3435a136e50 848
mcm 2:c3435a136e50 849 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 850 return AS3933_SUCCESS;
mcm 2:c3435a136e50 851 else
mcm 2:c3435a136e50 852 return AS3933_FAILURE;
mcm 2:c3435a136e50 853 }
mcm 2:c3435a136e50 854
mcm 2:c3435a136e50 855
mcm 2:c3435a136e50 856 /**
mcm 2:c3435a136e50 857 * @brief AS3933_SetAGC ( AS3933_r1_agc_tlim_value_t , AS3933_r1_agc_ud_value_t )
mcm 2:c3435a136e50 858 *
mcm 2:c3435a136e50 859 * @details It configures the Automatic Gain Control ( AGC ).
mcm 2:c3435a136e50 860 *
mcm 2:c3435a136e50 861 * @param[in] myAGC_CarrierBurstMode: Enable/Disable AGC acting only on the first carrier burst.
mcm 2:c3435a136e50 862 * @param[in] myAGC_OperatingDirection: Configure AGC direction operating.
mcm 2:c3435a136e50 863 *
mcm 2:c3435a136e50 864 * @param[out] N/A.
mcm 2:c3435a136e50 865 *
mcm 2:c3435a136e50 866 *
mcm 2:c3435a136e50 867 * @return Status of AS3933_SetAGC.
mcm 2:c3435a136e50 868 *
mcm 2:c3435a136e50 869 *
mcm 2:c3435a136e50 870 * @author Manuel Caballero
mcm 2:c3435a136e50 871 * @date 7/March/2018
mcm 2:c3435a136e50 872 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 873 * @pre N/A.
mcm 2:c3435a136e50 874 * @warning N/A.
mcm 2:c3435a136e50 875 */
mcm 2:c3435a136e50 876 AS3933::AS3933_status_t AS3933::AS3933_SetAGC ( AS3933_r1_agc_tlim_value_t myAGC_CarrierBurstMode, AS3933_r1_agc_ud_value_t myAGC_OperatingDirection )
mcm 2:c3435a136e50 877 {
mcm 2:c3435a136e50 878 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 879 int mySPI_status;
mcm 2:c3435a136e50 880
mcm 2:c3435a136e50 881
mcm 2:c3435a136e50 882 // Read R1 register
mcm 2:c3435a136e50 883 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 884 _cs = 1;
mcm 3:2de552c4ffbc 885 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 886 _cs = 0;
mcm 2:c3435a136e50 887
mcm 2:c3435a136e50 888 // Mask both AGC acting only on the first carrier burst and AGC direction operating
mcm 2:c3435a136e50 889 cmd[1] &= ~( AGC_TLIM_MASK | AGC_UD_MASK );
mcm 2:c3435a136e50 890
mcm 2:c3435a136e50 891 // Update both AGC acting only on the first carrier burst and AGC direction operating
mcm 2:c3435a136e50 892 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 893 cmd[1] |= ( myAGC_CarrierBurstMode | myAGC_OperatingDirection );
mcm 2:c3435a136e50 894 _cs = 1;
mcm 4:10d482ca4eb1 895 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 896 _cs = 0;
mcm 2:c3435a136e50 897
mcm 2:c3435a136e50 898
mcm 2:c3435a136e50 899
mcm 2:c3435a136e50 900
mcm 2:c3435a136e50 901 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 902 return AS3933_SUCCESS;
mcm 2:c3435a136e50 903 else
mcm 2:c3435a136e50 904 return AS3933_FAILURE;
mcm 2:c3435a136e50 905 }
mcm 2:c3435a136e50 906
mcm 2:c3435a136e50 907
mcm 2:c3435a136e50 908 /**
mcm 2:c3435a136e50 909 * @brief AS3933_SetDataMask ( AS3933_r0_dat_mask_value_t )
mcm 2:c3435a136e50 910 *
mcm 2:c3435a136e50 911 * @details It configures the mask data before wakeup.
mcm 2:c3435a136e50 912 *
mcm 2:c3435a136e50 913 * @param[in] myDataMaskMode: Mask data on DAT pin before wakeup happens.
mcm 2:c3435a136e50 914 *
mcm 2:c3435a136e50 915 * @param[out] N/A.
mcm 2:c3435a136e50 916 *
mcm 2:c3435a136e50 917 *
mcm 2:c3435a136e50 918 * @return Status of AS3933_SetDataMask.
mcm 2:c3435a136e50 919 *
mcm 2:c3435a136e50 920 *
mcm 2:c3435a136e50 921 * @author Manuel Caballero
mcm 2:c3435a136e50 922 * @date 7/March/2018
mcm 2:c3435a136e50 923 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 924 * @pre N/A.
mcm 2:c3435a136e50 925 * @warning N/A.
mcm 2:c3435a136e50 926 */
mcm 2:c3435a136e50 927 AS3933::AS3933_status_t AS3933::AS3933_SetDataMask ( AS3933_r0_dat_mask_value_t myDataMaskMode )
mcm 2:c3435a136e50 928 {
mcm 2:c3435a136e50 929 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 930 int mySPI_status;
mcm 2:c3435a136e50 931
mcm 2:c3435a136e50 932
mcm 2:c3435a136e50 933 // Read R0 register
mcm 2:c3435a136e50 934 cmd[0] = ( AS3933_READ | AS3933_R0 );
mcm 2:c3435a136e50 935 _cs = 1;
mcm 3:2de552c4ffbc 936 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 937 _cs = 0;
mcm 2:c3435a136e50 938
mcm 2:c3435a136e50 939 // Mask Mask data on DAT pin before wakeup happens
mcm 2:c3435a136e50 940 cmd[1] &= ~( DAT_MASK_MASK );
mcm 2:c3435a136e50 941
mcm 2:c3435a136e50 942 // Update Mask data on DAT pin before wakeup happens
mcm 2:c3435a136e50 943 cmd[0] = ( AS3933_WRITE | AS3933_R0 );
mcm 2:c3435a136e50 944 cmd[1] |= ( myDataMaskMode );
mcm 2:c3435a136e50 945 _cs = 1;
mcm 4:10d482ca4eb1 946 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 947 _cs = 0;
mcm 2:c3435a136e50 948
mcm 2:c3435a136e50 949
mcm 2:c3435a136e50 950
mcm 2:c3435a136e50 951
mcm 2:c3435a136e50 952 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 953 return AS3933_SUCCESS;
mcm 2:c3435a136e50 954 else
mcm 2:c3435a136e50 955 return AS3933_FAILURE;
mcm 2:c3435a136e50 956 }
mcm 2:c3435a136e50 957
mcm 2:c3435a136e50 958
mcm 2:c3435a136e50 959 /**
mcm 2:c3435a136e50 960 * @brief AS3933_SetCorrelator ( AS3933_r1_en_wpat_value_t , AS3933_r0_patt32_value_t , AS3933_r7_t_hbit_value_t , AS3933_r1_en_manch_value_t )
mcm 2:c3435a136e50 961 *
mcm 2:c3435a136e50 962 * @details It configures the correlator and the Manchester Decoder.
mcm 2:c3435a136e50 963 *
mcm 2:c3435a136e50 964 * @param[in] myCorrelatorMode: Enable/Disable Correlator.
mcm 2:c3435a136e50 965 * @param[in] mySymbolPattern: Pattern extended.
mcm 2:c3435a136e50 966 * @param[in] myRate: Bit rate definition.
mcm 2:c3435a136e50 967 * @param[in] myManchesterDecoderMode: Enable/Disable Manchester decoder.
mcm 2:c3435a136e50 968 *
mcm 2:c3435a136e50 969 * @param[out] N/A.
mcm 2:c3435a136e50 970 *
mcm 2:c3435a136e50 971 *
mcm 2:c3435a136e50 972 * @return Status of AS3933_SetCorrelator.
mcm 2:c3435a136e50 973 *
mcm 2:c3435a136e50 974 *
mcm 2:c3435a136e50 975 * @author Manuel Caballero
mcm 2:c3435a136e50 976 * @date 7/March/2018
mcm 2:c3435a136e50 977 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 978 * @pre N/A.
mcm 2:c3435a136e50 979 * @warning N/A.
mcm 2:c3435a136e50 980 */
mcm 2:c3435a136e50 981 AS3933::AS3933_status_t AS3933::AS3933_SetCorrelator ( AS3933_r1_en_wpat_value_t myCorrelatorMode, AS3933_r0_patt32_value_t mySymbolPattern, AS3933_r7_t_hbit_value_t myRate,
mcm 4:10d482ca4eb1 982 AS3933_r1_en_manch_value_t myManchesterDecoderMode )
mcm 2:c3435a136e50 983 {
mcm 2:c3435a136e50 984 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 985 int mySPI_status;
mcm 2:c3435a136e50 986
mcm 2:c3435a136e50 987
mcm 2:c3435a136e50 988 // Configure Correlator mode and Manchester decoder mode
mcm 2:c3435a136e50 989 // Read R1 register
mcm 2:c3435a136e50 990 cmd[0] = ( AS3933_READ | AS3933_R1 );
mcm 2:c3435a136e50 991 _cs = 1;
mcm 3:2de552c4ffbc 992 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 993 _cs = 0;
mcm 2:c3435a136e50 994
mcm 2:c3435a136e50 995 // Mask both Correlator mode and Manchester decoder mode
mcm 2:c3435a136e50 996 cmd[1] &= ~( EN_WPAT_MASK | EN_MANCH_MASK );
mcm 2:c3435a136e50 997
mcm 2:c3435a136e50 998 // Update both Correlator mode and Manchester decoder mode
mcm 2:c3435a136e50 999 cmd[0] = ( AS3933_WRITE | AS3933_R1 );
mcm 2:c3435a136e50 1000 cmd[1] |= ( myCorrelatorMode | myManchesterDecoderMode );
mcm 2:c3435a136e50 1001 _cs = 1;
mcm 4:10d482ca4eb1 1002 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1003 _cs = 0;
mcm 2:c3435a136e50 1004
mcm 2:c3435a136e50 1005
mcm 2:c3435a136e50 1006 // Configure Pattern extended
mcm 2:c3435a136e50 1007 // Read R0 register
mcm 2:c3435a136e50 1008 cmd[0] = ( AS3933_READ | AS3933_R0 );
mcm 2:c3435a136e50 1009 _cs = 1;
mcm 4:10d482ca4eb1 1010 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1011 _cs = 0;
mcm 2:c3435a136e50 1012
mcm 2:c3435a136e50 1013 // Mask Pattern extended
mcm 2:c3435a136e50 1014 cmd[1] &= ~( PATT32_MASK );
mcm 2:c3435a136e50 1015
mcm 2:c3435a136e50 1016 // Update Pattern extended
mcm 2:c3435a136e50 1017 cmd[0] = ( AS3933_WRITE | AS3933_R0 );
mcm 2:c3435a136e50 1018 cmd[1] |= ( mySymbolPattern );
mcm 2:c3435a136e50 1019 _cs = 1;
mcm 4:10d482ca4eb1 1020 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1021 _cs = 0;
mcm 2:c3435a136e50 1022
mcm 2:c3435a136e50 1023
mcm 2:c3435a136e50 1024 // Configure Bit rate definition
mcm 2:c3435a136e50 1025 // Read R7 register
mcm 2:c3435a136e50 1026 cmd[0] = ( AS3933_READ | AS3933_R7 );
mcm 2:c3435a136e50 1027 _cs = 1;
mcm 3:2de552c4ffbc 1028 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1029 _cs = 0;
mcm 2:c3435a136e50 1030
mcm 2:c3435a136e50 1031 // Mask Bit rate definition
mcm 2:c3435a136e50 1032 cmd[1] &= ~( T_HBIT_MASK );
mcm 2:c3435a136e50 1033
mcm 2:c3435a136e50 1034 // Update Bit rate definition
mcm 2:c3435a136e50 1035 cmd[0] = ( AS3933_WRITE | AS3933_R7 );
mcm 2:c3435a136e50 1036 cmd[1] |= ( myRate );
mcm 2:c3435a136e50 1037 _cs = 1;
mcm 4:10d482ca4eb1 1038 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1039 _cs = 0;
mcm 2:c3435a136e50 1040
mcm 2:c3435a136e50 1041
mcm 2:c3435a136e50 1042
mcm 2:c3435a136e50 1043
mcm 2:c3435a136e50 1044
mcm 2:c3435a136e50 1045 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1046 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1047 else
mcm 2:c3435a136e50 1048 return AS3933_FAILURE;
mcm 2:c3435a136e50 1049 }
mcm 2:c3435a136e50 1050
mcm 2:c3435a136e50 1051
mcm 2:c3435a136e50 1052 /**
mcm 2:c3435a136e50 1053 * @brief AS3933_SetWakeUpPattern ( AS3933_data_t )
mcm 2:c3435a136e50 1054 *
mcm 2:c3435a136e50 1055 * @details It sets the wakeup pattern ( Manchester ).
mcm 2:c3435a136e50 1056 *
mcm 2:c3435a136e50 1057 * @param[in] myWakeUpPattern: PATT1B and PATT2B ( Manchester ).
mcm 2:c3435a136e50 1058 *
mcm 2:c3435a136e50 1059 * @param[out] N/A.
mcm 2:c3435a136e50 1060 *
mcm 2:c3435a136e50 1061 *
mcm 2:c3435a136e50 1062 * @return Status of AS3933_SetWakeUpPattern.
mcm 2:c3435a136e50 1063 *
mcm 2:c3435a136e50 1064 *
mcm 2:c3435a136e50 1065 * @author Manuel Caballero
mcm 2:c3435a136e50 1066 * @date 7/March/2018
mcm 2:c3435a136e50 1067 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1068 * @pre N/A.
mcm 2:c3435a136e50 1069 * @warning N/A.
mcm 2:c3435a136e50 1070 */
mcm 2:c3435a136e50 1071 AS3933::AS3933_status_t AS3933::AS3933_SetWakeUpPattern ( AS3933_data_t myWakeUpPattern )
mcm 2:c3435a136e50 1072 {
mcm 2:c3435a136e50 1073 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1074 int mySPI_status;
mcm 2:c3435a136e50 1075
mcm 2:c3435a136e50 1076
mcm 2:c3435a136e50 1077 // Update PATT2B
mcm 2:c3435a136e50 1078 cmd[0] = ( AS3933_WRITE | AS3933_R5 );
mcm 2:c3435a136e50 1079 cmd[1] = ( myWakeUpPattern.patt2b );
mcm 2:c3435a136e50 1080 _cs = 1;
mcm 4:10d482ca4eb1 1081 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1082 _cs = 0;
mcm 2:c3435a136e50 1083
mcm 2:c3435a136e50 1084 // Update PATT1B
mcm 2:c3435a136e50 1085 cmd[0] = ( AS3933_WRITE | AS3933_R6 );
mcm 2:c3435a136e50 1086 cmd[1] = ( myWakeUpPattern.patt1b );
mcm 2:c3435a136e50 1087 _cs = 1;
mcm 4:10d482ca4eb1 1088 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1089 _cs = 0;
mcm 2:c3435a136e50 1090
mcm 2:c3435a136e50 1091
mcm 2:c3435a136e50 1092
mcm 2:c3435a136e50 1093
mcm 2:c3435a136e50 1094 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1095 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1096 else
mcm 2:c3435a136e50 1097 return AS3933_FAILURE;
mcm 2:c3435a136e50 1098 }
mcm 2:c3435a136e50 1099
mcm 2:c3435a136e50 1100
mcm 2:c3435a136e50 1101 /**
mcm 2:c3435a136e50 1102 * @brief AS3933_GetWakeUpPattern ( AS3933_data_t* )
mcm 2:c3435a136e50 1103 *
mcm 2:c3435a136e50 1104 * @details It gets the wakeup pattern ( Manchester ).
mcm 2:c3435a136e50 1105 *
mcm 2:c3435a136e50 1106 * @param[in] N/A
mcm 2:c3435a136e50 1107 *
mcm 2:c3435a136e50 1108 * @param[out] myWakeUpPattern: PATT1B and PATT2B ( Manchester ).
mcm 2:c3435a136e50 1109 *
mcm 2:c3435a136e50 1110 *
mcm 2:c3435a136e50 1111 * @return Status of AS3933_GetWakeUpPattern.
mcm 2:c3435a136e50 1112 *
mcm 2:c3435a136e50 1113 *
mcm 2:c3435a136e50 1114 * @author Manuel Caballero
mcm 2:c3435a136e50 1115 * @date 7/March/2018
mcm 2:c3435a136e50 1116 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1117 * @pre N/A.
mcm 2:c3435a136e50 1118 * @warning N/A.
mcm 2:c3435a136e50 1119 */
mcm 2:c3435a136e50 1120 AS3933::AS3933_status_t AS3933::AS3933_GetWakeUpPattern ( AS3933_data_t* myWakeUpPattern )
mcm 2:c3435a136e50 1121 {
mcm 3:2de552c4ffbc 1122 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1123 int mySPI_status;
mcm 2:c3435a136e50 1124
mcm 2:c3435a136e50 1125
mcm 2:c3435a136e50 1126 // Read R5 register
mcm 3:2de552c4ffbc 1127 cmd[0] = ( AS3933_READ | AS3933_R5 );
mcm 2:c3435a136e50 1128 _cs = 1;
mcm 3:2de552c4ffbc 1129 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 3:2de552c4ffbc 1130 _cs = 0;
mcm 4:10d482ca4eb1 1131
mcm 3:2de552c4ffbc 1132 myWakeUpPattern->patt2b = cmd[1];
mcm 4:10d482ca4eb1 1133
mcm 3:2de552c4ffbc 1134 // Read R6 register
mcm 3:2de552c4ffbc 1135 cmd[0] = ( AS3933_READ | AS3933_R6 );
mcm 3:2de552c4ffbc 1136 _cs = 1;
mcm 3:2de552c4ffbc 1137 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1138 _cs = 0;
mcm 2:c3435a136e50 1139
mcm 3:2de552c4ffbc 1140 myWakeUpPattern->patt1b = cmd[1];
mcm 2:c3435a136e50 1141
mcm 2:c3435a136e50 1142
mcm 2:c3435a136e50 1143 if ( mySPI_status == SPI_SUCCESS )
mcm 2:c3435a136e50 1144 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1145 else
mcm 2:c3435a136e50 1146 return AS3933_FAILURE;
mcm 2:c3435a136e50 1147 }
mcm 2:c3435a136e50 1148
mcm 2:c3435a136e50 1149
mcm 2:c3435a136e50 1150 /**
mcm 2:c3435a136e50 1151 * @brief AS3933_SetAutomaticTimeOut ( AS3933_r7_t_out_value_t )
mcm 2:c3435a136e50 1152 *
mcm 2:c3435a136e50 1153 * @details It sets the automatic time-out setup.
mcm 2:c3435a136e50 1154 *
mcm 2:c3435a136e50 1155 * @param[in] myAutomaticTimeOut: Automatic time-out.
mcm 2:c3435a136e50 1156 *
mcm 2:c3435a136e50 1157 * @param[out] N/A.
mcm 2:c3435a136e50 1158 *
mcm 2:c3435a136e50 1159 *
mcm 2:c3435a136e50 1160 * @return Status of AS3933_SetAutomaticTimeOut.
mcm 2:c3435a136e50 1161 *
mcm 2:c3435a136e50 1162 *
mcm 2:c3435a136e50 1163 * @author Manuel Caballero
mcm 2:c3435a136e50 1164 * @date 7/March/2018
mcm 2:c3435a136e50 1165 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1166 * @pre N/A.
mcm 2:c3435a136e50 1167 * @warning N/A.
mcm 2:c3435a136e50 1168 */
mcm 2:c3435a136e50 1169 AS3933::AS3933_status_t AS3933::AS3933_SetAutomaticTimeOut ( AS3933_r7_t_out_value_t myAutomaticTimeOut )
mcm 2:c3435a136e50 1170 {
mcm 2:c3435a136e50 1171 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1172 int mySPI_status;
mcm 2:c3435a136e50 1173
mcm 2:c3435a136e50 1174
mcm 2:c3435a136e50 1175 // Read R7 register
mcm 2:c3435a136e50 1176 cmd[0] = ( AS3933_READ | AS3933_R7 );
mcm 2:c3435a136e50 1177 _cs = 1;
mcm 3:2de552c4ffbc 1178 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1179 _cs = 0;
mcm 2:c3435a136e50 1180
mcm 2:c3435a136e50 1181 // Mask Automatic time-out
mcm 2:c3435a136e50 1182 cmd[1] &= ~( T_OUT_MASK );
mcm 2:c3435a136e50 1183
mcm 2:c3435a136e50 1184 // Update Automatic time-out
mcm 2:c3435a136e50 1185 cmd[0] = ( AS3933_WRITE | AS3933_R7 );
mcm 2:c3435a136e50 1186 cmd[1] |= ( myAutomaticTimeOut );
mcm 2:c3435a136e50 1187 _cs = 1;
mcm 4:10d482ca4eb1 1188 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1189 _cs = 0;
mcm 2:c3435a136e50 1190
mcm 2:c3435a136e50 1191
mcm 2:c3435a136e50 1192
mcm 2:c3435a136e50 1193
mcm 2:c3435a136e50 1194 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1195 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1196 else
mcm 2:c3435a136e50 1197 return AS3933_FAILURE;
mcm 2:c3435a136e50 1198 }
mcm 2:c3435a136e50 1199
mcm 2:c3435a136e50 1200
mcm 2:c3435a136e50 1201 /**
mcm 2:c3435a136e50 1202 * @brief AS3933_SetParallelTuningCapacitance ( AS3933_parallel_tuning_channels_t , AS3933_parallel_tuning_capacitance_t )
mcm 2:c3435a136e50 1203 *
mcm 2:c3435a136e50 1204 * @details It sets the parallel tuning capacitance on the chosen channel.
mcm 2:c3435a136e50 1205 *
mcm 2:c3435a136e50 1206 * @param[in] myChannel: Channel for Parallel Tuning Capacitance.
mcm 2:c3435a136e50 1207 * @param[in] myAddedCapacitance: Parallel Tuning Capacitance.
mcm 2:c3435a136e50 1208 *
mcm 2:c3435a136e50 1209 * @param[out] N/A.
mcm 2:c3435a136e50 1210 *
mcm 2:c3435a136e50 1211 *
mcm 2:c3435a136e50 1212 * @return Status of AS3933_SetParallelTuningCapacitance.
mcm 2:c3435a136e50 1213 *
mcm 2:c3435a136e50 1214 *
mcm 2:c3435a136e50 1215 * @author Manuel Caballero
mcm 2:c3435a136e50 1216 * @date 7/March/2018
mcm 2:c3435a136e50 1217 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1218 * @pre N/A.
mcm 2:c3435a136e50 1219 * @warning N/A.
mcm 2:c3435a136e50 1220 */
mcm 2:c3435a136e50 1221 AS3933::AS3933_status_t AS3933::AS3933_SetParallelTuningCapacitance ( AS3933_parallel_tuning_channels_t myChannel, AS3933_parallel_tuning_capacitance_t myAddedCapacitance )
mcm 2:c3435a136e50 1222 {
mcm 2:c3435a136e50 1223 char cmd[] = { 0, 0 };
mcm 2:c3435a136e50 1224 int mySPI_status;
mcm 2:c3435a136e50 1225
mcm 2:c3435a136e50 1226 AS3933_spi_command_structure_registers_t myAuxRegister;
mcm 2:c3435a136e50 1227
mcm 2:c3435a136e50 1228
mcm 2:c3435a136e50 1229 // Select the channel
mcm 4:10d482ca4eb1 1230 switch ( myChannel ) {
mcm 2:c3435a136e50 1231 default:
mcm 2:c3435a136e50 1232 case AS3933_CHANNEL_LF1P:
mcm 2:c3435a136e50 1233 myAuxRegister = AS3933_R17;
mcm 2:c3435a136e50 1234 break;
mcm 2:c3435a136e50 1235
mcm 4:10d482ca4eb1 1236 case AS3933_CHANNEL_LF2P:
mcm 4:10d482ca4eb1 1237 myAuxRegister = AS3933_R18;
mcm 2:c3435a136e50 1238 break;
mcm 2:c3435a136e50 1239
mcm 4:10d482ca4eb1 1240 case AS3933_CHANNEL_LF3P:
mcm 4:10d482ca4eb1 1241 myAuxRegister = AS3933_R19;
mcm 2:c3435a136e50 1242 break;
mcm 2:c3435a136e50 1243 }
mcm 2:c3435a136e50 1244
mcm 2:c3435a136e50 1245
mcm 2:c3435a136e50 1246 // Read register
mcm 2:c3435a136e50 1247 cmd[0] = ( AS3933_READ | myAuxRegister );
mcm 2:c3435a136e50 1248 _cs = 1;
mcm 3:2de552c4ffbc 1249 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1250 _cs = 0;
mcm 2:c3435a136e50 1251
mcm 2:c3435a136e50 1252 // Mask Parallel Tuning Capacitance
mcm 2:c3435a136e50 1253 cmd[1] &= ~( AS3933_CAPACITANCE_MASK );
mcm 2:c3435a136e50 1254
mcm 2:c3435a136e50 1255 // Update Parallel Tuning Capacitance
mcm 2:c3435a136e50 1256 cmd[0] = ( AS3933_WRITE | myAuxRegister );
mcm 2:c3435a136e50 1257 cmd[1] |= ( myAddedCapacitance );
mcm 2:c3435a136e50 1258 _cs = 1;
mcm 4:10d482ca4eb1 1259 mySPI_status = _spi.write ( &cmd[0], sizeof( cmd )/sizeof( cmd[0] ), &cmd[0], 2 );
mcm 2:c3435a136e50 1260 _cs = 0;
mcm 2:c3435a136e50 1261
mcm 2:c3435a136e50 1262
mcm 2:c3435a136e50 1263
mcm 2:c3435a136e50 1264
mcm 2:c3435a136e50 1265
mcm 2:c3435a136e50 1266 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1267 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1268 else
mcm 2:c3435a136e50 1269 return AS3933_FAILURE;
mcm 2:c3435a136e50 1270 }
mcm 2:c3435a136e50 1271
mcm 2:c3435a136e50 1272
mcm 2:c3435a136e50 1273 /**
mcm 2:c3435a136e50 1274 * @brief AS3933_GetRSSI ( AS3933_data_t* )
mcm 2:c3435a136e50 1275 *
mcm 2:c3435a136e50 1276 * @details It gets the RSSI for all channels.
mcm 2:c3435a136e50 1277 *
mcm 2:c3435a136e50 1278 * @param[in] mySPI_parameters: N/A
mcm 2:c3435a136e50 1279 *
mcm 2:c3435a136e50 1280 * @param[out] myChannelRSSI: RSSI.
mcm 2:c3435a136e50 1281 *
mcm 2:c3435a136e50 1282 *
mcm 2:c3435a136e50 1283 * @return Status of AS3933_GetRSSI.
mcm 2:c3435a136e50 1284 *
mcm 2:c3435a136e50 1285 *
mcm 2:c3435a136e50 1286 * @author Manuel Caballero
mcm 2:c3435a136e50 1287 * @date 7/March/2018
mcm 4:10d482ca4eb1 1288 * @version 12/March/2018 Auto-increment does NOT work when the registers are read
mcm 4:10d482ca4eb1 1289 * 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1290 * @pre N/A.
mcm 2:c3435a136e50 1291 * @warning N/A.
mcm 2:c3435a136e50 1292 */
mcm 2:c3435a136e50 1293 AS3933::AS3933_status_t AS3933::AS3933_GetRSSI ( AS3933_data_t* myChannelRSSI )
mcm 2:c3435a136e50 1294 {
mcm 2:c3435a136e50 1295 char cmd[] = { 0, 0, 0 };
mcm 2:c3435a136e50 1296 int mySPI_status;
mcm 2:c3435a136e50 1297
mcm 2:c3435a136e50 1298
mcm 4:10d482ca4eb1 1299 // Get RSSI1
mcm 4:10d482ca4eb1 1300 // Read R10 register
mcm 2:c3435a136e50 1301 cmd[0] = ( AS3933_READ | AS3933_R10 );
mcm 2:c3435a136e50 1302 _cs = 1;
mcm 4:10d482ca4eb1 1303 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 2:c3435a136e50 1304 _cs = 0;
mcm 2:c3435a136e50 1305
mcm 2:c3435a136e50 1306 // Parse the data
mcm 4:10d482ca4eb1 1307 myChannelRSSI->rssi1 = ( cmd[1] & RSSI1_MASK ); // Channel1: RSSI1
mcm 4:10d482ca4eb1 1308
mcm 4:10d482ca4eb1 1309
mcm 4:10d482ca4eb1 1310 // Get RSSI3
mcm 4:10d482ca4eb1 1311 // Read R11 register
mcm 4:10d482ca4eb1 1312 cmd[0] = ( AS3933_READ | AS3933_R11 );
mcm 4:10d482ca4eb1 1313 _cs = 1;
mcm 4:10d482ca4eb1 1314 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 4:10d482ca4eb1 1315 _cs = 0;
mcm 2:c3435a136e50 1316
mcm 4:10d482ca4eb1 1317 // Parse the data
mcm 4:10d482ca4eb1 1318 myChannelRSSI->rssi3 = ( cmd[1] & RSSI3_MASK ); // Channel1: RSSI1
mcm 4:10d482ca4eb1 1319
mcm 4:10d482ca4eb1 1320
mcm 4:10d482ca4eb1 1321 // Get RSSI2
mcm 4:10d482ca4eb1 1322 // Read R12 register
mcm 4:10d482ca4eb1 1323 cmd[0] = ( AS3933_READ | AS3933_R12 );
mcm 4:10d482ca4eb1 1324 _cs = 1;
mcm 4:10d482ca4eb1 1325 mySPI_status = _spi.write ( &cmd[0], 1, &cmd[0], 2 );
mcm 4:10d482ca4eb1 1326 _cs = 0;
mcm 4:10d482ca4eb1 1327
mcm 4:10d482ca4eb1 1328 // Parse the data
mcm 4:10d482ca4eb1 1329 myChannelRSSI->rssi2 = ( cmd[1] & RSSI2_MASK ); // Channel1: RSSI1
mcm 2:c3435a136e50 1330
mcm 2:c3435a136e50 1331
mcm 2:c3435a136e50 1332
mcm 2:c3435a136e50 1333
mcm 2:c3435a136e50 1334 if ( ( mySPI_status / ( sizeof( cmd )/sizeof( cmd[0] ) ) ) == SPI_SUCCESS )
mcm 2:c3435a136e50 1335 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1336 else
mcm 2:c3435a136e50 1337 return AS3933_FAILURE;
mcm 2:c3435a136e50 1338 }
mcm 2:c3435a136e50 1339
mcm 2:c3435a136e50 1340
mcm 2:c3435a136e50 1341
mcm 2:c3435a136e50 1342 /**
mcm 2:c3435a136e50 1343 * @brief AS3933_Send_DirectCommand ( AS3933_spi_direct_commands_t )
mcm 2:c3435a136e50 1344 *
mcm 2:c3435a136e50 1345 * @details It sends a direct command.
mcm 2:c3435a136e50 1346 *
mcm 2:c3435a136e50 1347 * @param[in] myDirectCommand: Direct command to be sent.
mcm 2:c3435a136e50 1348 *
mcm 2:c3435a136e50 1349 * @param[out] N/A.
mcm 2:c3435a136e50 1350 *
mcm 2:c3435a136e50 1351 *
mcm 2:c3435a136e50 1352 * @return Status of AS3933_Send_DirectCommand.
mcm 2:c3435a136e50 1353 *
mcm 2:c3435a136e50 1354 *
mcm 2:c3435a136e50 1355 * @author Manuel Caballero
mcm 2:c3435a136e50 1356 * @date 7/March/2018
mcm 2:c3435a136e50 1357 * @version 7/March/2018 The ORIGIN
mcm 2:c3435a136e50 1358 * @pre N/A.
mcm 2:c3435a136e50 1359 * @warning N/A.
mcm 2:c3435a136e50 1360 */
mcm 2:c3435a136e50 1361 AS3933::AS3933_status_t AS3933::AS3933_Send_DirectCommand ( AS3933_spi_direct_commands_t myDirectCommand )
mcm 2:c3435a136e50 1362 {
mcm 3:2de552c4ffbc 1363 char cmd = 0;
mcm 2:c3435a136e50 1364 int mySPI_status;
mcm 2:c3435a136e50 1365
mcm 2:c3435a136e50 1366
mcm 2:c3435a136e50 1367 // Send a direct command
mcm 2:c3435a136e50 1368 cmd = ( AS3933_DIRECT_COMMAND | myDirectCommand );
mcm 2:c3435a136e50 1369 _cs = 1;
mcm 4:10d482ca4eb1 1370 mySPI_status = _spi.write ( &cmd, 1, &cmd, 1 );
mcm 2:c3435a136e50 1371 _cs = 0;
mcm 2:c3435a136e50 1372
mcm 2:c3435a136e50 1373
mcm 2:c3435a136e50 1374
mcm 2:c3435a136e50 1375
mcm 2:c3435a136e50 1376 if ( mySPI_status == SPI_SUCCESS )
mcm 2:c3435a136e50 1377 return AS3933_SUCCESS;
mcm 2:c3435a136e50 1378 else
mcm 2:c3435a136e50 1379 return AS3933_FAILURE;
mcm 2:c3435a136e50 1380 }