Manuel Caballero / ADS111X

Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator

ADS111X.h@1:8593e6fcf0c3, 2020-06-18 (annotated)

Committer:
mcm
Date:
Thu Jun 18 15:39:34 2020 +0000
Revision:
1:8593e6fcf0c3
Parent:
0:9dd3592a3761
Child:
3:4a9619b441f0
The header file is ready for review.

Who changed what in which revision?

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mcm 1:8593e6fcf0c3 1 /**
mcm 1:8593e6fcf0c3 2 * @brief ADS111X.h
mcm 1:8593e6fcf0c3 3 * @details Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator.
mcm 1:8593e6fcf0c3 4 * Header file.
mcm 1:8593e6fcf0c3 5 *
mcm 1:8593e6fcf0c3 6 *
mcm 1:8593e6fcf0c3 7 * @return N/A
mcm 1:8593e6fcf0c3 8 *
mcm 1:8593e6fcf0c3 9 * @author Manuel Caballero
mcm 1:8593e6fcf0c3 10 * @date 18/June/2020
mcm 1:8593e6fcf0c3 11 * @version 18/June/2020 The ORIGIN
mcm 1:8593e6fcf0c3 12 * @pre N/A.
mcm 1:8593e6fcf0c3 13 * @warning N/A
mcm 1:8593e6fcf0c3 14 * @pre This code belongs to AqueronteBlog ( http://unbarquero.blogspot.com ).
mcm 1:8593e6fcf0c3 15 */
mcm 1:8593e6fcf0c3 16 #ifndef ADS111X_H
mcm 1:8593e6fcf0c3 17 #define ADS111X_H
mcm 1:8593e6fcf0c3 18
mcm 1:8593e6fcf0c3 19 #include "mbed.h"
mcm 1:8593e6fcf0c3 20
mcm 1:8593e6fcf0c3 21
mcm 1:8593e6fcf0c3 22 /**
mcm 1:8593e6fcf0c3 23 Example:
mcm 1:8593e6fcf0c3 24 @code
mcm 1:8593e6fcf0c3 25
mcm 1:8593e6fcf0c3 26 @endcode
mcm 1:8593e6fcf0c3 27 */
mcm 1:8593e6fcf0c3 28
mcm 1:8593e6fcf0c3 29
mcm 1:8593e6fcf0c3 30 /*!
mcm 1:8593e6fcf0c3 31 Library for the ADS111X Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator.
mcm 1:8593e6fcf0c3 32 */
mcm 1:8593e6fcf0c3 33 class ADS111X
mcm 1:8593e6fcf0c3 34 {
mcm 1:8593e6fcf0c3 35 public:
mcm 1:8593e6fcf0c3 36 /**
mcm 1:8593e6fcf0c3 37 * @brief DEFAULT ADDRESSES
mcm 1:8593e6fcf0c3 38 */
mcm 1:8593e6fcf0c3 39 typedef enum {
mcm 1:8593e6fcf0c3 40 ADS111X_ADDRESS_GND = 0b1001000, /*!< I2C slave address byte, ADDR = GND */
mcm 1:8593e6fcf0c3 41 ADS111X_ADDRESS_VDD = 0b1001001, /*!< I2C slave address byte, ADDR = VDD */
mcm 1:8593e6fcf0c3 42 ADS111X_ADDRESS_SDA = 0b1001010, /*!< I2C slave address byte, ADDR = SDA */
mcm 1:8593e6fcf0c3 43 ADS111X_ADDRESS_SCL = 0b1001011 /*!< I2C slave address byte, ADDR = SCL */
mcm 1:8593e6fcf0c3 44 } ADS111X_addresses_t;
mcm 1:8593e6fcf0c3 45
mcm 1:8593e6fcf0c3 46
mcm 1:8593e6fcf0c3 47
mcm 1:8593e6fcf0c3 48 /**
mcm 1:8593e6fcf0c3 49 * @brief REGISTER MAP
mcm 1:8593e6fcf0c3 50 */
mcm 1:8593e6fcf0c3 51 typedef enum {
mcm 1:8593e6fcf0c3 52 ADS111X_CONVERSION = 0x00, /*!< Conversion register */
mcm 1:8593e6fcf0c3 53 ADS111X_CONFIG = 0x01, /*!< Config register */
mcm 1:8593e6fcf0c3 54 ADS111X_LO_THRESH = 0x02, /*!< Lo threshold register */
mcm 1:8593e6fcf0c3 55 ADS111X_HI_THRESH = 0x03, /*!< Hi threshold register */
mcm 1:8593e6fcf0c3 56 ADS111X_RESET_COMMAND = 0x06 /*!< Reset command ( with a general call ) */
mcm 1:8593e6fcf0c3 57 } ADS111X_register_map_t;
mcm 1:8593e6fcf0c3 58
mcm 1:8593e6fcf0c3 59
mcm 1:8593e6fcf0c3 60
mcm 1:8593e6fcf0c3 61 /**
mcm 1:8593e6fcf0c3 62 * @brief DEVICE.
mcm 1:8593e6fcf0c3 63 * NOTE: The user MUST define which device to use: ADS1013, ADS1014 or ADS1015.
mcm 1:8593e6fcf0c3 64 */
mcm 1:8593e6fcf0c3 65 typedef enum {
mcm 1:8593e6fcf0c3 66 DEVICE_ADS1113 = 0x00, /*!< Device: ADS1113 */
mcm 1:8593e6fcf0c3 67 DEVICE_ADS1114 = 0x01, /*!< Device: ADS1114 */
mcm 1:8593e6fcf0c3 68 DEVICE_ADS1115 = 0x02 /*!< Device: ADS1115 */
mcm 1:8593e6fcf0c3 69 } ADS111X_device_t;
mcm 1:8593e6fcf0c3 70
mcm 1:8593e6fcf0c3 71
mcm 1:8593e6fcf0c3 72
mcm 1:8593e6fcf0c3 73 /**
mcm 1:8593e6fcf0c3 74 * @brief CONFIG REGISTER. ( Default: 0x8583 )
mcm 1:8593e6fcf0c3 75 * NOTE: The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and
mcm 1:8593e6fcf0c3 76 * comparator modes.
mcm 1:8593e6fcf0c3 77 */
mcm 1:8593e6fcf0c3 78 /* OS <15>
mcm 1:8593e6fcf0c3 79 * NOTE: Operational status or single-shot conversion start.
mcm 1:8593e6fcf0c3 80 */
mcm 1:8593e6fcf0c3 81 typedef enum {
mcm 1:8593e6fcf0c3 82 CONFIG_OS_MASK = ( 1U << 15U ), /*!< OS mask */
mcm 1:8593e6fcf0c3 83 CONFIG_OS_BUSY = ( 1U << 15U ), /*!< Device is not currently performing a conversion/Start a single conversion (when in power-down state) [Default] */
mcm 1:8593e6fcf0c3 84 CONFIG_OS_NOT_BUSY = ( 0U << 15U ) /*!< Device is currently performing a conversion */
mcm 1:8593e6fcf0c3 85 } ADS111X_config_os_t;
mcm 1:8593e6fcf0c3 86
mcm 1:8593e6fcf0c3 87
mcm 1:8593e6fcf0c3 88 /* MUX <14:12>
mcm 1:8593e6fcf0c3 89 * NOTE: Input multiplexer configuration ( ADS1115 only ).
mcm 1:8593e6fcf0c3 90 */
mcm 1:8593e6fcf0c3 91 typedef enum {
mcm 1:8593e6fcf0c3 92 CONFIG_MUX_MASK = ( 0b111 << 12U ), /*!< MUX mask */
mcm 1:8593e6fcf0c3 93 CONFIG_MUX_AINP_AIN0_AND_AINN_AIN1 = ( 0b000 << 12U ), /*!< AINP = AIN0 and AINN = AIN1 [ Default ] */
mcm 1:8593e6fcf0c3 94 CONFIG_MUX_AINP_AIN0_AND_AINN_AIN3 = ( 0b001 << 12U ), /*!< AINP = AIN0 and AINN = AIN3 */
mcm 1:8593e6fcf0c3 95 CONFIG_MUX_AINP_AIN1_AND_AINN_AIN3 = ( 0b010 << 12U ), /*!< AINP = AIN1 and AINN = AIN3 */
mcm 1:8593e6fcf0c3 96 CONFIG_MUX_AINP_AIN2_AND_AINN_AIN3 = ( 0b011 << 12U ), /*!< AINP = AIN2 and AINN = AIN3 */
mcm 1:8593e6fcf0c3 97 CONFIG_MUX_AINP_AIN0_AND_AINN_GND = ( 0b100 << 12U ), /*!< AINP = AIN0 and AINN = GND */
mcm 1:8593e6fcf0c3 98 CONFIG_MUX_AINP_AIN1_AND_AINN_GND = ( 0b101 << 12U ), /*!< AINP = AIN1 and AINN = GND */
mcm 1:8593e6fcf0c3 99 CONFIG_MUX_AINP_AIN2_AND_AINN_GND = ( 0b110 << 12U ), /*!< AINP = AIN2 and AINN = GND */
mcm 1:8593e6fcf0c3 100 CONFIG_MUX_AINP_AIN3_AND_AINN_GND = ( 0b111 << 12U ) /*!< AINP = AIN3 and AINN = GND */
mcm 1:8593e6fcf0c3 101 } ADS111X_config_mux_t;
mcm 1:8593e6fcf0c3 102
mcm 1:8593e6fcf0c3 103
mcm 1:8593e6fcf0c3 104 /* PGA <11:9>
mcm 1:8593e6fcf0c3 105 * NOTE: Programmable gain amplifier configuration ( These bits serve NO function on the ADS1113 ).
mcm 1:8593e6fcf0c3 106 */
mcm 1:8593e6fcf0c3 107 typedef enum {
mcm 1:8593e6fcf0c3 108 CONFIG_PGA_MASK = ( 0b111 << 9U ), /*!< PGA mask */
mcm 1:8593e6fcf0c3 109 CONFIG_PGA_FSR_6_144_V = ( 0b000 << 9U ), /*!< FSR = �6.144 V */
mcm 1:8593e6fcf0c3 110 CONFIG_PGA_FSR_4_096_V = ( 0b001 << 9U ), /*!< FSR = �4.096 V */
mcm 1:8593e6fcf0c3 111 CONFIG_PGA_FSR_2_048_V = ( 0b010 << 9U ), /*!< FSR = �2.048 V [ Default ] */
mcm 1:8593e6fcf0c3 112 CONFIG_PGA_FSR_1_024_V = ( 0b011 << 9U ), /*!< FSR = �1.024 V */
mcm 1:8593e6fcf0c3 113 CONFIG_PGA_FSR_0_512_V = ( 0b100 << 9U ), /*!< FSR = �0.512 V */
mcm 1:8593e6fcf0c3 114 CONFIG_PGA_FSR_0_256_V = ( 0b101 << 9U ) /*!< FSR = �0.256 V */
mcm 1:8593e6fcf0c3 115 } ADS111X_config_pga_t;
mcm 1:8593e6fcf0c3 116
mcm 1:8593e6fcf0c3 117
mcm 1:8593e6fcf0c3 118 /* MODE <8>
mcm 1:8593e6fcf0c3 119 * NOTE: Device operating mode.
mcm 1:8593e6fcf0c3 120 */
mcm 1:8593e6fcf0c3 121 typedef enum {
mcm 1:8593e6fcf0c3 122 CONFIG_MODE_MASK = ( 1U << 8U ), /*!< MODE mask */
mcm 1:8593e6fcf0c3 123 CONFIG_MODE_CONTINUOUS_CONVERSION = ( 0U << 8U ), /*!< Continuous-conversion mode */
mcm 1:8593e6fcf0c3 124 CONFIG_MODE_SINGLE_SHOT = ( 1U << 8U ) /*!< Single-shot mode or power-down state [ Default ] */
mcm 1:8593e6fcf0c3 125 } ADS111X_config_mode_t;
mcm 1:8593e6fcf0c3 126
mcm 1:8593e6fcf0c3 127
mcm 1:8593e6fcf0c3 128 /* DR <7:5>
mcm 1:8593e6fcf0c3 129 * NOTE: Data rate.
mcm 1:8593e6fcf0c3 130 */
mcm 1:8593e6fcf0c3 131 typedef enum {
mcm 1:8593e6fcf0c3 132 CONFIG_DR_MASK = ( 0b111 << 5U ), /*!< DR mask */
mcm 1:8593e6fcf0c3 133 CONFIG_DR_8_SPS = ( 0b000 << 5U ), /*!< 8 SPS */
mcm 1:8593e6fcf0c3 134 CONFIG_DR_16_SPS = ( 0b001 << 5U ), /*!< 16 SPS */
mcm 1:8593e6fcf0c3 135 CONFIG_DR_32_SPS = ( 0b010 << 5U ), /*!< 32 SPS */
mcm 1:8593e6fcf0c3 136 CONFIG_DR_64_SPS = ( 0b011 << 5U ), /*!< 64 SPS */
mcm 1:8593e6fcf0c3 137 CONFIG_DR_128_SPS = ( 0b100 << 5U ), /*!< 128 SPS [ Default ] */
mcm 1:8593e6fcf0c3 138 CONFIG_DR_250_SPS = ( 0b101 << 5U ), /*!< 250 SPS */
mcm 1:8593e6fcf0c3 139 CONFIG_DR_475_SPS = ( 0b110 << 5U ), /*!< 475 SPS */
mcm 1:8593e6fcf0c3 140 CONFIG_DR_860_SPS = ( 0b111 << 5U ) /*!< 860 SPS */
mcm 1:8593e6fcf0c3 141 } ADS111X_config_dr_t;
mcm 1:8593e6fcf0c3 142
mcm 1:8593e6fcf0c3 143
mcm 1:8593e6fcf0c3 144 /* COMP_MODE <4>
mcm 1:8593e6fcf0c3 145 * NOTE: Comparator mode ( ADS1114 and ADS1115 only )
mcm 1:8593e6fcf0c3 146 */
mcm 1:8593e6fcf0c3 147 typedef enum {
mcm 1:8593e6fcf0c3 148 CONFIG_COMP_MODE_MASK = ( 1U << 4U ), /*!< COMP_MODE mask */
mcm 1:8593e6fcf0c3 149 CONFIG_COMP_MODE_TRADITIONAL_COMPARATOR = ( 0U << 4U ), /*!< Traditional comparator [ Default ] */
mcm 1:8593e6fcf0c3 150 CONFIG_COMP_MODE_WINDOW_COMPARATOR = ( 1U << 4U ) /*!< Window comparator */
mcm 1:8593e6fcf0c3 151 } ADS111X_config_comp_mode_t;
mcm 1:8593e6fcf0c3 152
mcm 1:8593e6fcf0c3 153
mcm 1:8593e6fcf0c3 154 /* COMP_POL <3>
mcm 1:8593e6fcf0c3 155 * NOTE: Comparator polarity ( ADS1114 and ADS1115 only )
mcm 1:8593e6fcf0c3 156 */
mcm 1:8593e6fcf0c3 157 typedef enum {
mcm 1:8593e6fcf0c3 158 CONFIG_COMP_POL_MASK = ( 1U << 3U ), /*!< COMP_POL mask */
mcm 1:8593e6fcf0c3 159 CONFIG_COMP_POL_ACTIVE_LOW = ( 0U << 3U ), /*!< Active low [ Default ] */
mcm 1:8593e6fcf0c3 160 CONFIG_COMP_POL_ACTIVE_HIGH = ( 1U << 3U ) /*!< Active high */
mcm 1:8593e6fcf0c3 161 } ADS111X_config_comp_pol_t;
mcm 1:8593e6fcf0c3 162
mcm 1:8593e6fcf0c3 163
mcm 1:8593e6fcf0c3 164 /* COMP_LAT <2>
mcm 1:8593e6fcf0c3 165 * NOTE: Latching comparator ( ADS1114 and ADS1115 only )
mcm 1:8593e6fcf0c3 166 */
mcm 1:8593e6fcf0c3 167 typedef enum {
mcm 1:8593e6fcf0c3 168 CONFIG_COMP_LAT_MASK = ( 1U << 2U ), /*!< COMP_LAT mask */
mcm 1:8593e6fcf0c3 169 CONFIG_COMP_LAT_NONLATCHING_COMPARATOR = ( 0U << 2U ), /*!< Nonlatching comparator [ Default ] */
mcm 1:8593e6fcf0c3 170 CONFIG_COMP_LAT_LATCHING_COMPARATOR = ( 1U << 2U ) /*!< Latching comparator */
mcm 1:8593e6fcf0c3 171 } ADS111X_config_comp_lat_t;
mcm 1:8593e6fcf0c3 172
mcm 1:8593e6fcf0c3 173
mcm 1:8593e6fcf0c3 174 /* COMP_QUE <1:0>
mcm 1:8593e6fcf0c3 175 * NOTE: Comparator queue and disable ( ADS1114 and ADS1115 only )
mcm 1:8593e6fcf0c3 176 */
mcm 1:8593e6fcf0c3 177 typedef enum {
mcm 1:8593e6fcf0c3 178 CONFIG_COMP_QUE_MASK = ( 0b11 << 0U ), /*!< COMP_QUE mask */
mcm 1:8593e6fcf0c3 179 CONFIG_COMP_QUE_ASSERT_AFTER_ONE_CONVERSION = ( 0b00 << 0U ), /*!< Assert after one conversion */
mcm 1:8593e6fcf0c3 180 CONFIG_COMP_QUE_ASSERT_AFTER_TWO_CONVERSION = ( 0b01 << 0U ), /*!< Assert after two conversions */
mcm 1:8593e6fcf0c3 181 CONFIG_COMP_QUE_ASSERT_AFTER_FOUR_CONVERSION = ( 0b10 << 0U ), /*!< Assert after four conversions */
mcm 1:8593e6fcf0c3 182 CONFIG_COMP_QUE_DISABLED = ( 0b11 << 0U ) /*!< Disable comparator and set ALERT/RDY pin to high-impedance [ Default ] */
mcm 1:8593e6fcf0c3 183 } ADS111X_config_comp_que_t;
mcm 1:8593e6fcf0c3 184
mcm 1:8593e6fcf0c3 185
mcm 1:8593e6fcf0c3 186
mcm 1:8593e6fcf0c3 187 /**
mcm 1:8593e6fcf0c3 188 * @brief LO_THRESH REGISTER. ( Default: 0x8000 )
mcm 1:8593e6fcf0c3 189 */
mcm 1:8593e6fcf0c3 190 /* LO_THRESH <15:0>
mcm 1:8593e6fcf0c3 191 * NOTE: N/A.
mcm 1:8593e6fcf0c3 192 */
mcm 1:8593e6fcf0c3 193 typedef enum {
mcm 1:8593e6fcf0c3 194 LO_THRESH_MASK = 0xFFFF /*!< LO_THRESH mask */
mcm 1:8593e6fcf0c3 195 } ADS111X_lo_thresh_t;
mcm 1:8593e6fcf0c3 196
mcm 1:8593e6fcf0c3 197
mcm 1:8593e6fcf0c3 198
mcm 1:8593e6fcf0c3 199 /**
mcm 1:8593e6fcf0c3 200 * @brief HI_THRESH REGISTER. ( Default: 0x7FFF )
mcm 1:8593e6fcf0c3 201 */
mcm 1:8593e6fcf0c3 202 /* HI_THRESH <15:0>
mcm 1:8593e6fcf0c3 203 * NOTE: N/A.
mcm 1:8593e6fcf0c3 204 */
mcm 1:8593e6fcf0c3 205 typedef enum {
mcm 1:8593e6fcf0c3 206 HI_THRESH_MASK = 0xFFFF /*!< HI_THRESH mask */
mcm 1:8593e6fcf0c3 207 } ADS111X_hi_thresh_t;
mcm 1:8593e6fcf0c3 208
mcm 1:8593e6fcf0c3 209
mcm 1:8593e6fcf0c3 210
mcm 1:8593e6fcf0c3 211
mcm 1:8593e6fcf0c3 212
mcm 1:8593e6fcf0c3 213 #ifndef ADS111X_VECTOR_STRUCT_H
mcm 1:8593e6fcf0c3 214 #define ADS111X_VECTOR_STRUCT_H
mcm 1:8593e6fcf0c3 215 /* Configuration parameters */
mcm 1:8593e6fcf0c3 216 typedef struct {
mcm 1:8593e6fcf0c3 217 ADS111X_config_os_t os; /*!< Operational status */
mcm 1:8593e6fcf0c3 218 ADS111X_config_mux_t mux; /*!< Input multiplexer configuration (ADS1015 only) */
mcm 1:8593e6fcf0c3 219 ADS111X_config_pga_t pga; /*!< Programmable gain amplifier configuration (not ADS1013) */
mcm 1:8593e6fcf0c3 220 ADS111X_config_mode_t mode; /*!< Device operating mode */
mcm 1:8593e6fcf0c3 221 ADS111X_config_dr_t dr; /*!< Data rate */
mcm 1:8593e6fcf0c3 222 ADS111X_config_comp_mode_t comp_mode; /*!< Comparator mode (ADS1014 and ADS1015 only) */
mcm 1:8593e6fcf0c3 223 ADS111X_config_comp_pol_t comp_pol; /*!< Comparator polarity (ADS1014 and ADS1015 only) */
mcm 1:8593e6fcf0c3 224 ADS111X_config_comp_lat_t comp_lat; /*!< Latching comparator (ADS1014 and ADS1015 only) */
mcm 1:8593e6fcf0c3 225 ADS111X_config_comp_que_t comp_que; /*!< Comparator queue and disable (ADS1014 and ADS1015 only) */
mcm 1:8593e6fcf0c3 226 } ADS111X_config_t;
mcm 1:8593e6fcf0c3 227
mcm 1:8593e6fcf0c3 228
mcm 1:8593e6fcf0c3 229 /* Thresholds: High and low thresholds */
mcm 1:8593e6fcf0c3 230 typedef struct {
mcm 1:8593e6fcf0c3 231 int16_t lo_thresh; /*!< Low threshold value */
mcm 1:8593e6fcf0c3 232 int16_t hi_thresh; /*!< High threshold value */
mcm 1:8593e6fcf0c3 233 } ADS111X_thresh_t;
mcm 1:8593e6fcf0c3 234
mcm 1:8593e6fcf0c3 235
mcm 1:8593e6fcf0c3 236 /* Result Conversion: Raw value and conversion value */
mcm 1:8593e6fcf0c3 237 typedef struct {
mcm 1:8593e6fcf0c3 238 float conversion; /*!< Conversion value */
mcm 1:8593e6fcf0c3 239 int16_t raw_conversion; /*!< Raw conversion value */
mcm 1:8593e6fcf0c3 240 } ADS111X_conversion_t;
mcm 1:8593e6fcf0c3 241
mcm 1:8593e6fcf0c3 242
mcm 1:8593e6fcf0c3 243
mcm 1:8593e6fcf0c3 244 /* USER: User's global variables */
mcm 1:8593e6fcf0c3 245 typedef struct {
mcm 1:8593e6fcf0c3 246 /* Output */
mcm 1:8593e6fcf0c3 247 ADS111X_conversion_t conversion; /*!< Conversion values */
mcm 1:8593e6fcf0c3 248
mcm 1:8593e6fcf0c3 249 /* Configuration */
mcm 1:8593e6fcf0c3 250 ADS111X_config_t config; /*!< Configuration register */
mcm 1:8593e6fcf0c3 251
mcm 1:8593e6fcf0c3 252 /* Thresholds */
mcm 1:8593e6fcf0c3 253 ADS111X_thresh_t thresh; /*!< High/Low threshold values */
mcm 1:8593e6fcf0c3 254
mcm 1:8593e6fcf0c3 255 /* Device identification */
mcm 1:8593e6fcf0c3 256 ADS111X_device_t device; /*!< Device. The user MUST identify the device */
mcm 1:8593e6fcf0c3 257 } ADS111X_data_t;
mcm 1:8593e6fcf0c3 258 #endif
mcm 1:8593e6fcf0c3 259
mcm 1:8593e6fcf0c3 260
mcm 1:8593e6fcf0c3 261 /**
mcm 1:8593e6fcf0c3 262 * @brief INTERNAL CONSTANTS
mcm 1:8593e6fcf0c3 263 */
mcm 1:8593e6fcf0c3 264 typedef enum {
mcm 1:8593e6fcf0c3 265 ADS111X_SUCCESS = 0U, /*!< I2C communication success */
mcm 1:8593e6fcf0c3 266 ADS111X_FAILURE = 1U, /*!< I2C communication failure */
mcm 1:8593e6fcf0c3 267 ADS111X_DEVICE_NOT_SUPPORTED = 2U, /*!< Device not supported */
mcm 1:8593e6fcf0c3 268 ADS111X_VALUE_OUT_OF_RANGE = 3U, /*!< Value aout of range */
mcm 1:8593e6fcf0c3 269 ADS111X_DATA_CORRUPTED = 4U, /*!< D and lo/hi threshold data */
mcm 1:8593e6fcf0c3 270 I2C_SUCCESS = 0U /*!< I2C communication was fine */
mcm 1:8593e6fcf0c3 271 } ADS111X_status_t;
mcm 1:8593e6fcf0c3 272
mcm 1:8593e6fcf0c3 273
mcm 1:8593e6fcf0c3 274
mcm 1:8593e6fcf0c3 275
mcm 1:8593e6fcf0c3 276 /** Create an ADS111X object connected to the specified I2C pins.
mcm 1:8593e6fcf0c3 277 *
mcm 1:8593e6fcf0c3 278 * @param sda I2C data pin
mcm 1:8593e6fcf0c3 279 * @param scl I2C clock pin
mcm 1:8593e6fcf0c3 280 * @param addr I2C slave address
mcm 1:8593e6fcf0c3 281 * @param freq I2C frequency
mcm 1:8593e6fcf0c3 282 * @param device Device to use: ADS1113, ADS1114 or ADS1115
mcm 1:8593e6fcf0c3 283 */
mcm 1:8593e6fcf0c3 284 ADS111X ( PinName sda, PinName scl, uint32_t addr, uint32_t freq, ADS111X_device_t device );
mcm 1:8593e6fcf0c3 285
mcm 1:8593e6fcf0c3 286 /** Delete ADS111X object.
mcm 1:8593e6fcf0c3 287 */
mcm 1:8593e6fcf0c3 288 ~ADS111X();
mcm 1:8593e6fcf0c3 289
mcm 1:8593e6fcf0c3 290 /** It triggers a softreset.
mcm 1:8593e6fcf0c3 291 */
mcm 1:8593e6fcf0c3 292 ADS111X_status_t ADS111X_SoftReset ( void );
mcm 1:8593e6fcf0c3 293
mcm 1:8593e6fcf0c3 294 /** It gets the raw conversion value.
mcm 1:8593e6fcf0c3 295 */
mcm 1:8593e6fcf0c3 296 ADS111X_status_t ADS111X_GetRawConversion ( ADS111X_conversion_t* myRawD );
mcm 1:8593e6fcf0c3 297
mcm 1:8593e6fcf0c3 298 /** It gets the conversion value.
mcm 1:8593e6fcf0c3 299 */
mcm 1:8593e6fcf0c3 300 ADS111X_status_t ADS111X_GetConversion ( ADS111X_data_t* myD );
mcm 1:8593e6fcf0c3 301
mcm 1:8593e6fcf0c3 302 /** It starts a new single conversion.
mcm 1:8593e6fcf0c3 303 */
mcm 1:8593e6fcf0c3 304 ADS111X_status_t ADS111X_StartSingleConversion ( void );
mcm 1:8593e6fcf0c3 305
mcm 1:8593e6fcf0c3 306 /** It checks if the device is not currently performing a conversion.
mcm 1:8593e6fcf0c3 307 */
mcm 1:8593e6fcf0c3 308 ADS111X_status_t ADS111X_GetOS ( ADS111X_config_t* myADS111X );
mcm 1:8593e6fcf0c3 309
mcm 1:8593e6fcf0c3 310 /** It sets input multiplexer configuration ( ADS1015 only ).
mcm 1:8593e6fcf0c3 311 */
mcm 1:8593e6fcf0c3 312 ADS111X_status_t ADS111X_SetMux ( ADS111X_data_t myADS111X );
mcm 1:8593e6fcf0c3 313
mcm 1:8593e6fcf0c3 314 /** It gets input multiplexer configuration ( ADS1015 only ).
mcm 1:8593e6fcf0c3 315 */
mcm 1:8593e6fcf0c3 316 ADS111X_status_t ADS111X_GetMux ( ADS111X_data_t* myADS111X );
mcm 1:8593e6fcf0c3 317
mcm 1:8593e6fcf0c3 318 /** It sets programmable gain amplifier ( not ADS1013 ).
mcm 1:8593e6fcf0c3 319 */
mcm 1:8593e6fcf0c3 320 ADS111X_status_t ADS111X_SetGain ( ADS111X_data_t myPGA );
mcm 1:8593e6fcf0c3 321
mcm 1:8593e6fcf0c3 322 /** It gets programmable gain amplifier ( not ADS1013 ).
mcm 1:8593e6fcf0c3 323 */
mcm 1:8593e6fcf0c3 324 ADS111X_status_t ADS111X_GetGain ( ADS111X_data_t* myPGA );
mcm 1:8593e6fcf0c3 325
mcm 1:8593e6fcf0c3 326 /** It sets the device operating mode.
mcm 1:8593e6fcf0c3 327 */
mcm 1:8593e6fcf0c3 328 ADS111X_status_t ADS111X_SetMode ( ADS111X_config_t myMode );
mcm 1:8593e6fcf0c3 329
mcm 1:8593e6fcf0c3 330 /** It gets the device operating mode.
mcm 1:8593e6fcf0c3 331 */
mcm 1:8593e6fcf0c3 332 ADS111X_status_t ADS111X_GetMode ( ADS111X_config_t* myMode );
mcm 1:8593e6fcf0c3 333
mcm 1:8593e6fcf0c3 334 /** It sets the data rate.
mcm 1:8593e6fcf0c3 335 */
mcm 1:8593e6fcf0c3 336 ADS111X_status_t ADS111X_SetDataRate ( ADS111X_config_t myDR );
mcm 1:8593e6fcf0c3 337
mcm 1:8593e6fcf0c3 338 /** It gets the data rate.
mcm 1:8593e6fcf0c3 339 */
mcm 1:8593e6fcf0c3 340 ADS111X_status_t ADS111X_GetDataRate ( ADS111X_config_t* myDR );
mcm 1:8593e6fcf0c3 341
mcm 1:8593e6fcf0c3 342 /** It sets the comparator configuration.
mcm 1:8593e6fcf0c3 343 */
mcm 1:8593e6fcf0c3 344 ADS111X_status_t ADS111X_SetComparator ( ADS111X_data_t myCOMP );
mcm 1:8593e6fcf0c3 345
mcm 1:8593e6fcf0c3 346 /** It gets the comparator configuration.
mcm 1:8593e6fcf0c3 347 */
mcm 1:8593e6fcf0c3 348 ADS111X_status_t ADS111X_GetComparator ( ADS111X_data_t* myCOMP );
mcm 1:8593e6fcf0c3 349
mcm 1:8593e6fcf0c3 350 /** It sets the low threshold value.
mcm 1:8593e6fcf0c3 351 */
mcm 1:8593e6fcf0c3 352 ADS111X_status_t ADS111X_SetLowThresholdValue ( ADS111X_thresh_t myLoThres );
mcm 1:8593e6fcf0c3 353
mcm 1:8593e6fcf0c3 354 /** It gets the low threshold value.
mcm 1:8593e6fcf0c3 355 */
mcm 1:8593e6fcf0c3 356 ADS111X_status_t ADS111X_GetLowThresholdValue ( ADS111X_thresh_t* myLoThres );
mcm 1:8593e6fcf0c3 357
mcm 1:8593e6fcf0c3 358 /** It sets the high threshold value.
mcm 1:8593e6fcf0c3 359 */
mcm 1:8593e6fcf0c3 360 ADS111X_status_t ADS111X_SetHighThresholdValue ( ADS111X_thresh_t myHiThres );
mcm 1:8593e6fcf0c3 361
mcm 1:8593e6fcf0c3 362 /** It gets the high threshold value.
mcm 1:8593e6fcf0c3 363 */
mcm 1:8593e6fcf0c3 364 ADS111X_status_t ADS111X_GetHighThresholdValue ( ADS111X_thresh_t* myHiThres );
mcm 1:8593e6fcf0c3 365
mcm 1:8593e6fcf0c3 366
mcm 1:8593e6fcf0c3 367
mcm 1:8593e6fcf0c3 368 private:
mcm 1:8593e6fcf0c3 369 I2C _i2c;
mcm 1:8593e6fcf0c3 370 uint32_t _ADS111X_Addr;
mcm 1:8593e6fcf0c3 371 ADS111X_device_t _device;
mcm 1:8593e6fcf0c3 372 };
mcm 1:8593e6fcf0c3 373
mcm 1:8593e6fcf0c3 374 #endif