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TARGET_EFM32ZG_STK3200/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h@139:856d2700e60b, 2017-03-30 (annotated)

Committer:: <>
Date:: Thu Mar 30 13:26:47 2017 +0100
Revision:: 139:856d2700e60b
Parent:: 128:9bcdf88f62b0

Release 139 of the mbed library

Ports for Upcoming Targets

3934: [Silicon Labs] Update to HAL and devices https://github.com/ARMmbed/mbed-os/pull/3934

Known Issues

There is an issue with LPC1768 failing the 'Semihost file system' test with this release.

Fixes and Changes

3691: [TLS / hw acceleration] AES ECB for NUCLEO_F439ZI https://github.com/ARMmbed/mbed-os/pull/3691

3869: NCS36510: Default range changed from 0 to 950mV - ADC https://github.com/ARMmbed/mbed-os/pull/3869

3893: [STM32F7] Update STM32 Cube version v1.6.0 https://github.com/ARMmbed/mbed-os/pull/3893

3917: Fix mistake register setting in serial_format() https://github.com/ARMmbed/mbed-os/pull/3917

3927: [DELTA_DFBM_NQ620] Add RC calibration setting and revise mbed_overrides.c https://github.com/ARMmbed/mbed-os/pull/3927

3918: [NUC472/M453] Support unique locally administered MAC address and other driver updates https://github.com/ARMmbed/mbed-os/pull/3918

3920: Heap size adjusted to work for both tls-client and mbed-client https://github.com/ARMmbed/mbed-os/pull/3920

3969: NUCLEO_F302R8: Add missing PB_8/PB_9 CAN pins https://github.com/ARMmbed/mbed-os/pull/3969

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	98:8ab26030e058	1	/*************************************************************************//
Kojto	98:8ab26030e058	2	* @file em_cmu.h
Kojto	98:8ab26030e058	3	* @brief Clock management unit (CMU) API
<>	139:856d2700e60b	4	* @version 5.1.2
Kojto	98:8ab26030e058	5	*******************************************************************************
Kojto	98:8ab26030e058	6	* @section License
<>	128:9bcdf88f62b0	7	* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
Kojto	98:8ab26030e058	8	*******************************************************************************
Kojto	98:8ab26030e058	9	*
Kojto	98:8ab26030e058	10	* Permission is granted to anyone to use this software for any purpose,
Kojto	98:8ab26030e058	11	* including commercial applications, and to alter it and redistribute it
Kojto	98:8ab26030e058	12	* freely, subject to the following restrictions:
Kojto	98:8ab26030e058	13	*
Kojto	98:8ab26030e058	14	* 1. The origin of this software must not be misrepresented; you must not
Kojto	98:8ab26030e058	15	* claim that you wrote the original software.
Kojto	98:8ab26030e058	16	* 2. Altered source versions must be plainly marked as such, and must not be
Kojto	98:8ab26030e058	17	* misrepresented as being the original software.
Kojto	98:8ab26030e058	18	* 3. This notice may not be removed or altered from any source distribution.
Kojto	98:8ab26030e058	19	*
Kojto	98:8ab26030e058	20	* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
Kojto	98:8ab26030e058	21	* obligation to support this Software. Silicon Labs is providing the
Kojto	98:8ab26030e058	22	* Software "AS IS", with no express or implied warranties of any kind,
Kojto	98:8ab26030e058	23	* including, but not limited to, any implied warranties of merchantability
Kojto	98:8ab26030e058	24	* or fitness for any particular purpose or warranties against infringement
Kojto	98:8ab26030e058	25	* of any proprietary rights of a third party.
Kojto	98:8ab26030e058	26	*
Kojto	98:8ab26030e058	27	* Silicon Labs will not be liable for any consequential, incidental, or
Kojto	98:8ab26030e058	28	* special damages, or any other relief, or for any claim by any third party,
Kojto	98:8ab26030e058	29	* arising from your use of this Software.
Kojto	98:8ab26030e058	30	*
Kojto	98:8ab26030e058	31	******************************************************************************/
<>	128:9bcdf88f62b0	32	#ifndef EM_CMU_H
<>	128:9bcdf88f62b0	33	#define EM_CMU_H
Kojto	98:8ab26030e058	34
Kojto	98:8ab26030e058	35	#include "em_device.h"
Kojto	98:8ab26030e058	36	#if defined( CMU_PRESENT )
Kojto	98:8ab26030e058	37
Kojto	98:8ab26030e058	38	#include <stdbool.h>
Kojto	113:f141b2784e32	39	#include "em_assert.h"
Kojto	113:f141b2784e32	40	#include "em_bus.h"
Kojto	98:8ab26030e058	41
Kojto	98:8ab26030e058	42	#ifdef __cplusplus
Kojto	98:8ab26030e058	43	extern "C" {
Kojto	98:8ab26030e058	44	#endif
Kojto	98:8ab26030e058	45
Kojto	98:8ab26030e058	46	/*************************************************************************//
<>	128:9bcdf88f62b0	47	* @addtogroup emlib
Kojto	98:8ab26030e058	48	* @{
Kojto	98:8ab26030e058	49	******************************************************************************/
Kojto	98:8ab26030e058	50
Kojto	98:8ab26030e058	51	/*************************************************************************//
Kojto	98:8ab26030e058	52	* @addtogroup CMU
Kojto	98:8ab26030e058	53	* @{
Kojto	98:8ab26030e058	54	******************************************************************************/
Kojto	98:8ab26030e058	55
Kojto	98:8ab26030e058	56	/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
Kojto	98:8ab26030e058	57
Kojto	113:f141b2784e32	58	/* Select register id's, for internal use. */
Kojto	98:8ab26030e058	59	#define CMU_NOSEL_REG 0
Kojto	98:8ab26030e058	60	#define CMU_HFCLKSEL_REG 1
Kojto	98:8ab26030e058	61	#define CMU_LFACLKSEL_REG 2
Kojto	98:8ab26030e058	62	#define CMU_LFBCLKSEL_REG 3
Kojto	113:f141b2784e32	63	#define CMU_LFCCLKSEL_REG 4
Kojto	113:f141b2784e32	64	#define CMU_LFECLKSEL_REG 5
Kojto	113:f141b2784e32	65	#define CMU_DBGCLKSEL_REG 6
Kojto	113:f141b2784e32	66	#define CMU_USBCCLKSEL_REG 7
Kojto	98:8ab26030e058	67
Kojto	98:8ab26030e058	68	#define CMU_SEL_REG_POS 0
Kojto	98:8ab26030e058	69	#define CMU_SEL_REG_MASK 0xf
Kojto	98:8ab26030e058	70
Kojto	113:f141b2784e32	71	/* Divisor/prescaler register id's, for internal use. */
Kojto	98:8ab26030e058	72	#define CMU_NODIV_REG 0
Kojto	113:f141b2784e32	73	#define CMU_NOPRESC_REG 0
Kojto	113:f141b2784e32	74	#define CMU_HFPRESC_REG 1
Kojto	113:f141b2784e32	75	#define CMU_HFCLKDIV_REG 1
Kojto	113:f141b2784e32	76	#define CMU_HFEXPPRESC_REG 2
Kojto	113:f141b2784e32	77	#define CMU_HFCLKLEPRESC_REG 3
Kojto	113:f141b2784e32	78	#define CMU_HFPERPRESC_REG 4
Kojto	113:f141b2784e32	79	#define CMU_HFPERCLKDIV_REG 4
Kojto	113:f141b2784e32	80	#define CMU_HFCOREPRESC_REG 5
Kojto	113:f141b2784e32	81	#define CMU_HFCORECLKDIV_REG 5
<>	128:9bcdf88f62b0	82	#define CMU_LFAPRESC0_REG 6
<>	128:9bcdf88f62b0	83	#define CMU_LFBPRESC0_REG 7
<>	128:9bcdf88f62b0	84	#define CMU_LFEPRESC0_REG 8
Kojto	98:8ab26030e058	85
Kojto	113:f141b2784e32	86	#define CMU_PRESC_REG_POS 4
Kojto	113:f141b2784e32	87	#define CMU_DIV_REG_POS CMU_PRESC_REG_POS
Kojto	113:f141b2784e32	88	#define CMU_PRESC_REG_MASK 0xf
Kojto	113:f141b2784e32	89	#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
Kojto	113:f141b2784e32	90
Kojto	113:f141b2784e32	91	/* Enable register id's, for internal use. */
Kojto	98:8ab26030e058	92	#define CMU_NO_EN_REG 0
Kojto	113:f141b2784e32	93	#define CMU_CTRL_EN_REG 1
Kojto	98:8ab26030e058	94	#define CMU_HFPERCLKDIV_EN_REG 1
Kojto	98:8ab26030e058	95	#define CMU_HFPERCLKEN0_EN_REG 2
Kojto	98:8ab26030e058	96	#define CMU_HFCORECLKEN0_EN_REG 3
Kojto	113:f141b2784e32	97	#define CMU_HFBUSCLKEN0_EN_REG 5
Kojto	113:f141b2784e32	98	#define CMU_LFACLKEN0_EN_REG 6
Kojto	113:f141b2784e32	99	#define CMU_LFBCLKEN0_EN_REG 7
Kojto	113:f141b2784e32	100	#define CMU_LFCCLKEN0_EN_REG 8
Kojto	113:f141b2784e32	101	#define CMU_LFECLKEN0_EN_REG 9
Kojto	113:f141b2784e32	102	#define CMU_PCNT_EN_REG 10
Kojto	98:8ab26030e058	103
Kojto	98:8ab26030e058	104	#define CMU_EN_REG_POS 8
Kojto	98:8ab26030e058	105	#define CMU_EN_REG_MASK 0xf
Kojto	98:8ab26030e058	106
Kojto	113:f141b2784e32	107	/* Enable register bit positions, for internal use. */
Kojto	98:8ab26030e058	108	#define CMU_EN_BIT_POS 12
Kojto	98:8ab26030e058	109	#define CMU_EN_BIT_MASK 0x1f
Kojto	98:8ab26030e058	110
Kojto	113:f141b2784e32	111	/* Clock branch bitfield positions, for internal use. */
Kojto	98:8ab26030e058	112	#define CMU_HF_CLK_BRANCH 0
Kojto	113:f141b2784e32	113	#define CMU_HFCORE_CLK_BRANCH 1
Kojto	113:f141b2784e32	114	#define CMU_HFPER_CLK_BRANCH 2
Kojto	113:f141b2784e32	115	#define CMU_HFBUS_CLK_BRANCH 4
Kojto	113:f141b2784e32	116	#define CMU_HFEXP_CLK_BRANCH 5
Kojto	113:f141b2784e32	117	#define CMU_DBG_CLK_BRANCH 6
Kojto	113:f141b2784e32	118	#define CMU_AUX_CLK_BRANCH 7
Kojto	113:f141b2784e32	119	#define CMU_RTC_CLK_BRANCH 8
<>	128:9bcdf88f62b0	120	#define CMU_RTCC_CLK_BRANCH 9
<>	128:9bcdf88f62b0	121	#define CMU_LETIMER0_CLK_BRANCH 10
<>	128:9bcdf88f62b0	122	#define CMU_LEUART0_CLK_BRANCH 11
<>	128:9bcdf88f62b0	123	#define CMU_LEUART1_CLK_BRANCH 12
<>	128:9bcdf88f62b0	124	#define CMU_LFA_CLK_BRANCH 13
<>	128:9bcdf88f62b0	125	#define CMU_LFB_CLK_BRANCH 14
<>	128:9bcdf88f62b0	126	#define CMU_LFC_CLK_BRANCH 15
<>	128:9bcdf88f62b0	127	#define CMU_LFE_CLK_BRANCH 16
<>	128:9bcdf88f62b0	128	#define CMU_USBC_CLK_BRANCH 17
<>	128:9bcdf88f62b0	129	#define CMU_USBLE_CLK_BRANCH 18
<>	128:9bcdf88f62b0	130	#define CMU_LCDPRE_CLK_BRANCH 19
<>	128:9bcdf88f62b0	131	#define CMU_LCD_CLK_BRANCH 20
<>	128:9bcdf88f62b0	132	#define CMU_LESENSE_CLK_BRANCH 21
<>	139:856d2700e60b	133	#define CMU_CSEN_LF_CLK_BRANCH 22
Kojto	98:8ab26030e058	134
Kojto	98:8ab26030e058	135	#define CMU_CLK_BRANCH_POS 17
Kojto	98:8ab26030e058	136	#define CMU_CLK_BRANCH_MASK 0x1f
Kojto	98:8ab26030e058	137
<>	139:856d2700e60b	138	#if defined( _EMU_CMD_EM01VSCALE0_MASK )
<>	139:856d2700e60b	139	/* Max clock frequency for VSCALE voltages */
<>	139:856d2700e60b	140	#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
<>	139:856d2700e60b	141	#endif
Kojto	98:8ab26030e058	142	/** @endcond */
Kojto	98:8ab26030e058	143
Kojto	98:8ab26030e058	144	/*******************************************************************************
Kojto	98:8ab26030e058	145	****************************** ENUMS **********************************
Kojto	98:8ab26030e058	146	******************************************************************************/
Kojto	98:8ab26030e058	147
Kojto	98:8ab26030e058	148	/** Clock divisors. These values are valid for prescalers. */
Kojto	98:8ab26030e058	149	#define cmuClkDiv_1 1 /*< Divide clock by 1. /
Kojto	98:8ab26030e058	150	#define cmuClkDiv_2 2 /*< Divide clock by 2. /
Kojto	98:8ab26030e058	151	#define cmuClkDiv_4 4 /*< Divide clock by 4. /
Kojto	98:8ab26030e058	152	#define cmuClkDiv_8 8 /*< Divide clock by 8. /
Kojto	98:8ab26030e058	153	#define cmuClkDiv_16 16 /*< Divide clock by 16. /
Kojto	98:8ab26030e058	154	#define cmuClkDiv_32 32 /*< Divide clock by 32. /
Kojto	98:8ab26030e058	155	#define cmuClkDiv_64 64 /*< Divide clock by 64. /
Kojto	98:8ab26030e058	156	#define cmuClkDiv_128 128 /*< Divide clock by 128. /
Kojto	98:8ab26030e058	157	#define cmuClkDiv_256 256 /*< Divide clock by 256. /
Kojto	98:8ab26030e058	158	#define cmuClkDiv_512 512 /*< Divide clock by 512. /
Kojto	98:8ab26030e058	159	#define cmuClkDiv_1024 1024 /*< Divide clock by 1024. /
Kojto	98:8ab26030e058	160	#define cmuClkDiv_2048 2048 /*< Divide clock by 2048. /
Kojto	98:8ab26030e058	161	#define cmuClkDiv_4096 4096 /*< Divide clock by 4096. /
Kojto	98:8ab26030e058	162	#define cmuClkDiv_8192 8192 /*< Divide clock by 8192. /
Kojto	98:8ab26030e058	163	#define cmuClkDiv_16384 16384 /*< Divide clock by 16384. /
Kojto	98:8ab26030e058	164	#define cmuClkDiv_32768 32768 /*< Divide clock by 32768. /
Kojto	98:8ab26030e058	165
Kojto	98:8ab26030e058	166	/** Clock divider configuration */
Kojto	98:8ab26030e058	167	typedef uint32_t CMU_ClkDiv_TypeDef;
Kojto	98:8ab26030e058	168
<>	139:856d2700e60b	169	#if defined( _SILICON_LABS_32B_SERIES_1 )
Kojto	113:f141b2784e32	170	/** Clockprescaler configuration */
Kojto	113:f141b2784e32	171	typedef uint32_t CMU_ClkPresc_TypeDef;
Kojto	113:f141b2784e32	172	#endif
Kojto	113:f141b2784e32	173
Kojto	113:f141b2784e32	174	#if defined( _CMU_HFRCOCTRL_BAND_MASK )
Kojto	113:f141b2784e32	175	/** High frequency system RCO bands */
Kojto	98:8ab26030e058	176	typedef enum
Kojto	98:8ab26030e058	177	{
Kojto	113:f141b2784e32	178	cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /*< 1MHz HFRCO band /
Kojto	113:f141b2784e32	179	cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /*< 7MHz HFRCO band /
Kojto	113:f141b2784e32	180	cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /*< 11MHz HFRCO band /
Kojto	113:f141b2784e32	181	cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /*< 14MHz HFRCO band /
Kojto	113:f141b2784e32	182	cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /*< 21MHz HFRCO band /
Kojto	113:f141b2784e32	183	#if defined( CMU_HFRCOCTRL_BAND_28MHZ )
Kojto	113:f141b2784e32	184	cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /*< 28MHz HFRCO band /
Kojto	98:8ab26030e058	185	#endif
Kojto	98:8ab26030e058	186	} CMU_HFRCOBand_TypeDef;
Kojto	113:f141b2784e32	187	#endif /* _CMU_HFRCOCTRL_BAND_MASK */
Kojto	98:8ab26030e058	188
Kojto	98:8ab26030e058	189	#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
Kojto	113:f141b2784e32	190	/** AUX High frequency RCO bands */
Kojto	98:8ab26030e058	191	typedef enum
Kojto	98:8ab26030e058	192	{
Kojto	113:f141b2784e32	193	cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /*< 1MHz RC band /
Kojto	113:f141b2784e32	194	cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /*< 7MHz RC band /
Kojto	113:f141b2784e32	195	cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /*< 11MHz RC band /
Kojto	113:f141b2784e32	196	cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /*< 14MHz RC band /
Kojto	113:f141b2784e32	197	cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /*< 21MHz RC band /
Kojto	113:f141b2784e32	198	#if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
Kojto	113:f141b2784e32	199	cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /*< 28MHz RC band /
Kojto	98:8ab26030e058	200	#endif
Kojto	98:8ab26030e058	201	} CMU_AUXHFRCOBand_TypeDef;
Kojto	98:8ab26030e058	202	#endif
Kojto	98:8ab26030e058	203
Kojto	98:8ab26030e058	204	#if defined( _CMU_USHFRCOCONF_BAND_MASK )
Kojto	98:8ab26030e058	205	/** USB High frequency RC bands. */
Kojto	98:8ab26030e058	206	typedef enum
Kojto	98:8ab26030e058	207	{
Kojto	98:8ab26030e058	208	/** 24MHz RC band. */
Kojto	98:8ab26030e058	209	cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
Kojto	98:8ab26030e058	210	/** 48MHz RC band. */
Kojto	98:8ab26030e058	211	cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
Kojto	98:8ab26030e058	212	} CMU_USHFRCOBand_TypeDef;
Kojto	98:8ab26030e058	213	#endif
Kojto	98:8ab26030e058	214
Kojto	113:f141b2784e32	215	#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
Kojto	113:f141b2784e32	216	/** High frequency system RCO bands */
Kojto	113:f141b2784e32	217	typedef enum
Kojto	113:f141b2784e32	218	{
Kojto	113:f141b2784e32	219	cmuHFRCOFreq_1M0Hz = 1000000U, /*< 1MHz RC band /
Kojto	113:f141b2784e32	220	cmuHFRCOFreq_2M0Hz = 2000000U, /*< 2MHz RC band /
Kojto	113:f141b2784e32	221	cmuHFRCOFreq_4M0Hz = 4000000U, /*< 4MHz RC band /
Kojto	113:f141b2784e32	222	cmuHFRCOFreq_7M0Hz = 7000000U, /*< 7MHz RC band /
Kojto	113:f141b2784e32	223	cmuHFRCOFreq_13M0Hz = 13000000U, /*< 13MHz RC band /
Kojto	113:f141b2784e32	224	cmuHFRCOFreq_16M0Hz = 16000000U, /*< 16MHz RC band /
Kojto	113:f141b2784e32	225	cmuHFRCOFreq_19M0Hz = 19000000U, /*< 19MHz RC band /
Kojto	113:f141b2784e32	226	cmuHFRCOFreq_26M0Hz = 26000000U, /*< 26MHz RC band /
Kojto	113:f141b2784e32	227	cmuHFRCOFreq_32M0Hz = 32000000U, /*< 32MHz RC band /
Kojto	113:f141b2784e32	228	cmuHFRCOFreq_38M0Hz = 38000000U, /*< 38MHz RC band /
Kojto	113:f141b2784e32	229	cmuHFRCOFreq_UserDefined = 0,
Kojto	113:f141b2784e32	230	} CMU_HFRCOFreq_TypeDef;
Kojto	113:f141b2784e32	231	#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
Kojto	113:f141b2784e32	232	#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
Kojto	113:f141b2784e32	233	#endif
Kojto	113:f141b2784e32	234
Kojto	113:f141b2784e32	235	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
Kojto	113:f141b2784e32	236	/** AUX High frequency RCO bands */
Kojto	113:f141b2784e32	237	typedef enum
Kojto	113:f141b2784e32	238	{
Kojto	113:f141b2784e32	239	cmuAUXHFRCOFreq_1M0Hz = 1000000U, /*< 1MHz RC band /
Kojto	113:f141b2784e32	240	cmuAUXHFRCOFreq_2M0Hz = 2000000U, /*< 2MHz RC band /
Kojto	113:f141b2784e32	241	cmuAUXHFRCOFreq_4M0Hz = 4000000U, /*< 4MHz RC band /
Kojto	113:f141b2784e32	242	cmuAUXHFRCOFreq_7M0Hz = 7000000U, /*< 7MHz RC band /
Kojto	113:f141b2784e32	243	cmuAUXHFRCOFreq_13M0Hz = 13000000U, /*< 13MHz RC band /
Kojto	113:f141b2784e32	244	cmuAUXHFRCOFreq_16M0Hz = 16000000U, /*< 16MHz RC band /
Kojto	113:f141b2784e32	245	cmuAUXHFRCOFreq_19M0Hz = 19000000U, /*< 19MHz RC band /
Kojto	113:f141b2784e32	246	cmuAUXHFRCOFreq_26M0Hz = 26000000U, /*< 26MHz RC band /
Kojto	113:f141b2784e32	247	cmuAUXHFRCOFreq_32M0Hz = 32000000U, /*< 32MHz RC band /
Kojto	113:f141b2784e32	248	cmuAUXHFRCOFreq_38M0Hz = 38000000U, /*< 38MHz RC band /
Kojto	113:f141b2784e32	249	cmuAUXHFRCOFreq_UserDefined = 0,
Kojto	113:f141b2784e32	250	} CMU_AUXHFRCOFreq_TypeDef;
Kojto	113:f141b2784e32	251	#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
Kojto	113:f141b2784e32	252	#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
Kojto	113:f141b2784e32	253	#endif
Kojto	113:f141b2784e32	254
Kojto	98:8ab26030e058	255
Kojto	98:8ab26030e058	256	/** Clock points in CMU. Please refer to CMU overview in reference manual. */
Kojto	98:8ab26030e058	257	typedef enum
Kojto	98:8ab26030e058	258	{
Kojto	98:8ab26030e058	259	/*******************/
Kojto	98:8ab26030e058	260	/* HF clock branch */
Kojto	98:8ab26030e058	261	/*******************/
Kojto	98:8ab26030e058	262
Kojto	98:8ab26030e058	263	/** High frequency clock */
Kojto	113:f141b2784e32	264	#if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
Kojto	113:f141b2784e32	265	\|\| defined( _CMU_HFPRESC_MASK )
Kojto	113:f141b2784e32	266	cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	267	\| (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	268	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	269	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	270	\| (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	271	#else
Kojto	113:f141b2784e32	272	cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	273	\| (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	274	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	275	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	276	\| (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	277	#endif
Kojto	98:8ab26030e058	278
Kojto	98:8ab26030e058	279	/** Debug clock */
Kojto	113:f141b2784e32	280	cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	281	\| (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	282	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	283	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	284	\| (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	285
Kojto	98:8ab26030e058	286	/** AUX clock */
Kojto	113:f141b2784e32	287	cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	288	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	289	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	290	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	291	\| (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	292
Kojto	113:f141b2784e32	293	#if defined( _CMU_HFEXPPRESC_MASK )
Kojto	113:f141b2784e32	294	/**********************/
Kojto	113:f141b2784e32	295	/* HF export sub-branch */
Kojto	113:f141b2784e32	296	/**********************/
Kojto	113:f141b2784e32	297
Kojto	113:f141b2784e32	298	/** Export clock */
Kojto	113:f141b2784e32	299	cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	300	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	301	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	302	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	303	\| (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	304	#endif
Kojto	113:f141b2784e32	305
Kojto	113:f141b2784e32	306	#if defined( _CMU_HFBUSCLKEN0_MASK )
Kojto	113:f141b2784e32	307	/**********************************/
Kojto	113:f141b2784e32	308	/* HF bus clock sub-branch */
Kojto	113:f141b2784e32	309	/**********************************/
Kojto	113:f141b2784e32	310
Kojto	113:f141b2784e32	311	/** High frequency bus clock. */
Kojto	113:f141b2784e32	312	cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	313	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	314	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	315	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	316	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	317
Kojto	113:f141b2784e32	318	#if defined( CMU_HFBUSCLKEN0_CRYPTO )
Kojto	113:f141b2784e32	319	/** Cryptography accelerator clock. */
Kojto	113:f141b2784e32	320	cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	321	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	322	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	323	\| (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	324	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	325	#endif
Kojto	113:f141b2784e32	326
<>	128:9bcdf88f62b0	327	#if defined( CMU_HFBUSCLKEN0_CRYPTO0 )
<>	128:9bcdf88f62b0	328	/** Cryptography accelerator 0 clock. */
<>	128:9bcdf88f62b0	329	cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
<>	128:9bcdf88f62b0	330	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	331	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	332	\| (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	333	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	334	#endif
<>	128:9bcdf88f62b0	335
<>	128:9bcdf88f62b0	336	#if defined( CMU_HFBUSCLKEN0_CRYPTO1 )
<>	128:9bcdf88f62b0	337	/** Cryptography accelerator 1 clock. */
<>	128:9bcdf88f62b0	338	cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
<>	128:9bcdf88f62b0	339	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	340	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	341	\| (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	342	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	343	#endif
<>	128:9bcdf88f62b0	344
Kojto	113:f141b2784e32	345	#if defined( CMU_HFBUSCLKEN0_LDMA )
Kojto	113:f141b2784e32	346	/** Direct memory access controller clock. */
Kojto	113:f141b2784e32	347	cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	348	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	349	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	350	\| (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	351	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	352	#endif
Kojto	113:f141b2784e32	353
Kojto	113:f141b2784e32	354	#if defined( CMU_HFBUSCLKEN0_GPCRC )
Kojto	113:f141b2784e32	355	/** General purpose cyclic redundancy checksum clock. */
Kojto	113:f141b2784e32	356	cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	357	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	358	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	359	\| (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	360	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	361	#endif
Kojto	113:f141b2784e32	362
Kojto	113:f141b2784e32	363	#if defined( CMU_HFBUSCLKEN0_GPIO )
Kojto	113:f141b2784e32	364	/** General purpose input/output clock. */
Kojto	113:f141b2784e32	365	cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	366	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	367	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	368	\| (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	369	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	370	#endif
Kojto	113:f141b2784e32	371
<>	128:9bcdf88f62b0	372	/** Low energy clock divided down from HFBUSCLK. */
<>	128:9bcdf88f62b0	373	cmuClock_HFLE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
<>	128:9bcdf88f62b0	374	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	375	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	376	\| (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	377	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	378
Kojto	113:f141b2784e32	379	#if defined( CMU_HFBUSCLKEN0_PRS )
Kojto	113:f141b2784e32	380	/** Peripheral reflex system clock. */
Kojto	113:f141b2784e32	381	cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	382	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	383	\| (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	384	\| (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	385	\| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	386	#endif
Kojto	113:f141b2784e32	387	#endif
Kojto	98:8ab26030e058	388
Kojto	98:8ab26030e058	389	/**********************************/
Kojto	98:8ab26030e058	390	/* HF peripheral clock sub-branch */
Kojto	98:8ab26030e058	391	/**********************************/
Kojto	98:8ab26030e058	392
Kojto	98:8ab26030e058	393	/** High frequency peripheral clock */
Kojto	113:f141b2784e32	394	#if defined( _CMU_HFPRESC_MASK )
Kojto	113:f141b2784e32	395	cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	396	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	397	\| (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	398	\| (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	399	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	400	#else
Kojto	113:f141b2784e32	401	cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	402	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	403	\| (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	404	\| (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	405	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	406	#endif
Kojto	98:8ab26030e058	407
Kojto	113:f141b2784e32	408	#if defined( CMU_HFPERCLKEN0_USART0 )
Kojto	98:8ab26030e058	409	/** Universal sync/async receiver/transmitter 0 clock. */
Kojto	113:f141b2784e32	410	cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	411	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	412	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	413	\| (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	414	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	415	#endif
Kojto	98:8ab26030e058	416
Kojto	113:f141b2784e32	417	#if defined( CMU_HFPERCLKEN0_USARTRF0 )
Kojto	98:8ab26030e058	418	/** Universal sync/async receiver/transmitter 0 clock. */
Kojto	113:f141b2784e32	419	cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	420	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	421	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	422	\| (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	423	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	424	#endif
Kojto	98:8ab26030e058	425
Kojto	113:f141b2784e32	426	#if defined( CMU_HFPERCLKEN0_USARTRF1 )
Kojto	113:f141b2784e32	427	/** Universal sync/async receiver/transmitter 0 clock. */
Kojto	113:f141b2784e32	428	cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	429	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	430	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	431	\| (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	432	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	433	#endif
Kojto	98:8ab26030e058	434
Kojto	113:f141b2784e32	435	#if defined( CMU_HFPERCLKEN0_USART1 )
Kojto	113:f141b2784e32	436	/** Universal sync/async receiver/transmitter 1 clock. */
Kojto	113:f141b2784e32	437	cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	438	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	439	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	440	\| (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	441	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	442	#endif
Kojto	113:f141b2784e32	443
Kojto	113:f141b2784e32	444	#if defined( CMU_HFPERCLKEN0_USART2 )
Kojto	98:8ab26030e058	445	/** Universal sync/async receiver/transmitter 2 clock. */
Kojto	113:f141b2784e32	446	cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	447	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	448	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	449	\| (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	450	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	451	#endif
Kojto	98:8ab26030e058	452
Kojto	113:f141b2784e32	453	#if defined( CMU_HFPERCLKEN0_USART3 )
Kojto	113:f141b2784e32	454	/** Universal sync/async receiver/transmitter 3 clock. */
Kojto	113:f141b2784e32	455	cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	456	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	457	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	458	\| (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	459	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	460	#endif
Kojto	98:8ab26030e058	461
Kojto	113:f141b2784e32	462	#if defined( CMU_HFPERCLKEN0_USART4 )
Kojto	113:f141b2784e32	463	/** Universal sync/async receiver/transmitter 4 clock. */
Kojto	113:f141b2784e32	464	cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	465	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	466	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	467	\| (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	468	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	469	#endif
Kojto	113:f141b2784e32	470
Kojto	113:f141b2784e32	471	#if defined( CMU_HFPERCLKEN0_USART5 )
Kojto	113:f141b2784e32	472	/** Universal sync/async receiver/transmitter 5 clock. */
Kojto	113:f141b2784e32	473	cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	474	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	475	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	476	\| (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	477	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	478	#endif
Kojto	98:8ab26030e058	479
Kojto	113:f141b2784e32	480
Kojto	113:f141b2784e32	481	#if defined( CMU_HFPERCLKEN0_UART0 )
Kojto	113:f141b2784e32	482	/** Universal async receiver/transmitter 0 clock. */
Kojto	113:f141b2784e32	483	cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	484	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	485	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	486	\| (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	487	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	488	#endif
Kojto	98:8ab26030e058	489
Kojto	113:f141b2784e32	490	#if defined( CMU_HFPERCLKEN0_UART1 )
Kojto	113:f141b2784e32	491	/** Universal async receiver/transmitter 1 clock. */
Kojto	113:f141b2784e32	492	cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	493	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	494	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	495	\| (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	496	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	497	#endif
Kojto	98:8ab26030e058	498
Kojto	113:f141b2784e32	499	#if defined( CMU_HFPERCLKEN0_TIMER0 )
Kojto	113:f141b2784e32	500	/** Timer 0 clock. */
Kojto	113:f141b2784e32	501	cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	502	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	503	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	504	\| (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	505	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	506	#endif
Kojto	113:f141b2784e32	507
Kojto	113:f141b2784e32	508	#if defined( CMU_HFPERCLKEN0_TIMER1 )
Kojto	113:f141b2784e32	509	/** Timer 1 clock. */
Kojto	113:f141b2784e32	510	cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	511	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	512	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	513	\| (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	514	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	515	#endif
Kojto	98:8ab26030e058	516
Kojto	113:f141b2784e32	517	#if defined( CMU_HFPERCLKEN0_TIMER2 )
Kojto	113:f141b2784e32	518	/** Timer 2 clock. */
Kojto	113:f141b2784e32	519	cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	520	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	521	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	522	\| (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	523	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	524	#endif
Kojto	98:8ab26030e058	525
Kojto	113:f141b2784e32	526	#if defined( CMU_HFPERCLKEN0_TIMER3 )
Kojto	113:f141b2784e32	527	/** Timer 3 clock. */
Kojto	113:f141b2784e32	528	cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	529	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	530	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	531	\| (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	532	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	533	#endif
Kojto	98:8ab26030e058	534
<>	128:9bcdf88f62b0	535	#if defined( CMU_HFPERCLKEN0_WTIMER0 )
<>	128:9bcdf88f62b0	536	/** Wide Timer 0 clock. */
<>	128:9bcdf88f62b0	537	cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	538	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	539	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	540	\| (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	541	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	542	#endif
<>	128:9bcdf88f62b0	543
<>	128:9bcdf88f62b0	544	#if defined( CMU_HFPERCLKEN0_WTIMER1 )
<>	128:9bcdf88f62b0	545	/** Wide Timer 1 clock. */
<>	128:9bcdf88f62b0	546	cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	547	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	548	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	549	\| (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	550	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	551	#endif
<>	128:9bcdf88f62b0	552
Kojto	113:f141b2784e32	553	#if defined( CMU_HFPERCLKEN0_CRYOTIMER )
Kojto	113:f141b2784e32	554	/** CRYOtimer clock. */
Kojto	113:f141b2784e32	555	cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	556	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	557	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	558	\| (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	559	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	560	#endif
Kojto	98:8ab26030e058	561
Kojto	113:f141b2784e32	562	#if defined( CMU_HFPERCLKEN0_ACMP0 )
Kojto	113:f141b2784e32	563	/** Analog comparator 0 clock. */
Kojto	113:f141b2784e32	564	cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	565	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	566	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	567	\| (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	568	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	569	#endif
Kojto	98:8ab26030e058	570
Kojto	113:f141b2784e32	571	#if defined( CMU_HFPERCLKEN0_ACMP1 )
Kojto	113:f141b2784e32	572	/** Analog comparator 1 clock. */
Kojto	113:f141b2784e32	573	cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	574	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	575	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	576	\| (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	577	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	578	#endif
Kojto	113:f141b2784e32	579
Kojto	113:f141b2784e32	580	#if defined( CMU_HFPERCLKEN0_PRS )
Kojto	113:f141b2784e32	581	/** Peripheral reflex system clock. */
Kojto	113:f141b2784e32	582	cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	583	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	584	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	585	\| (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	586	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	587	#endif
Kojto	98:8ab26030e058	588
Kojto	113:f141b2784e32	589	#if defined( CMU_HFPERCLKEN0_DAC0 )
Kojto	98:8ab26030e058	590	/** Digital to analog converter 0 clock. */
Kojto	113:f141b2784e32	591	cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	592	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	593	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	594	\| (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	595	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	596	#endif
Kojto	98:8ab26030e058	597
<>	128:9bcdf88f62b0	598	#if defined( CMU_HFPERCLKEN0_VDAC0 )
<>	128:9bcdf88f62b0	599	/** Voltage digital to analog converter 0 clock. */
<>	128:9bcdf88f62b0	600	cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	601	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	602	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	603	\| (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	604	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	605	#endif
<>	128:9bcdf88f62b0	606
Kojto	113:f141b2784e32	607	#if defined( CMU_HFPERCLKEN0_IDAC0 )
<>	128:9bcdf88f62b0	608	/** Current digital to analog converter 0 clock. */
Kojto	113:f141b2784e32	609	cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	610	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	611	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	612	\| (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	613	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	614	#endif
Kojto	113:f141b2784e32	615
Kojto	113:f141b2784e32	616	#if defined( CMU_HFPERCLKEN0_GPIO )
Kojto	98:8ab26030e058	617	/** General purpose input/output clock. */
Kojto	113:f141b2784e32	618	cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	619	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	620	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	621	\| (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	622	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	623	#endif
Kojto	98:8ab26030e058	624
Kojto	113:f141b2784e32	625	#if defined( CMU_HFPERCLKEN0_VCMP )
Kojto	98:8ab26030e058	626	/** Voltage comparator clock. */
Kojto	113:f141b2784e32	627	cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	628	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	629	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	630	\| (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	631	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	632	#endif
Kojto	113:f141b2784e32	633
Kojto	113:f141b2784e32	634	#if defined( CMU_HFPERCLKEN0_ADC0 )
Kojto	113:f141b2784e32	635	/** Analog to digital converter 0 clock. */
Kojto	113:f141b2784e32	636	cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	637	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	638	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	639	\| (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	640	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	641	#endif
Kojto	98:8ab26030e058	642
Kojto	113:f141b2784e32	643	#if defined( CMU_HFPERCLKEN0_I2C0 )
Kojto	113:f141b2784e32	644	/** I2C 0 clock. */
Kojto	113:f141b2784e32	645	cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	646	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	647	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	648	\| (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	649	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	650	#endif
Kojto	98:8ab26030e058	651
Kojto	113:f141b2784e32	652	#if defined( CMU_HFPERCLKEN0_I2C1 )
Kojto	113:f141b2784e32	653	/** I2C 1 clock. */
Kojto	113:f141b2784e32	654	cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	655	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	656	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	657	\| (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	658	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	659	#endif
Kojto	98:8ab26030e058	660
Kojto	113:f141b2784e32	661	#if defined( CMU_HFPERCLKEN0_I2C2 )
Kojto	113:f141b2784e32	662	/** I2C 2 clock. */
Kojto	113:f141b2784e32	663	cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	664	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	665	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	666	\| (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	667	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	668	#endif
Kojto	98:8ab26030e058	669
<>	128:9bcdf88f62b0	670	#if defined( CMU_HFPERCLKEN0_CSEN )
<>	128:9bcdf88f62b0	671	/** Capacitive Sense HF clock */
<>	128:9bcdf88f62b0	672	cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	673	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	674	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	675	\| (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	676	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	677	#endif
<>	128:9bcdf88f62b0	678
<>	128:9bcdf88f62b0	679	#if defined( CMU_HFPERCLKEN0_TRNG0 )
<>	128:9bcdf88f62b0	680	/** True random number generator clock */
<>	128:9bcdf88f62b0	681	cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	682	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	683	\| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	684	\| (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	685	\| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	686	#endif
<>	128:9bcdf88f62b0	687
Kojto	98:8ab26030e058	688	/**********************/
Kojto	98:8ab26030e058	689	/* HF core sub-branch */
Kojto	98:8ab26030e058	690	/**********************/
Kojto	98:8ab26030e058	691
Kojto	98:8ab26030e058	692	/** Core clock */
Kojto	113:f141b2784e32	693	cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	694	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	695	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	696	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	697	\| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	698
Kojto	113:f141b2784e32	699	#if defined( CMU_HFCORECLKEN0_AES )
Kojto	98:8ab26030e058	700	/** Advanced encryption standard accelerator clock. */
Kojto	113:f141b2784e32	701	cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	702	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	703	\| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	704	\| (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	705	\| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	706	#endif
Kojto	113:f141b2784e32	707
Kojto	113:f141b2784e32	708	#if defined( CMU_HFCORECLKEN0_DMA )
Kojto	113:f141b2784e32	709	/** Direct memory access controller clock. */
Kojto	113:f141b2784e32	710	cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	711	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	712	\| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	713	\| (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	714	\| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	715	#endif
Kojto	98:8ab26030e058	716
Kojto	113:f141b2784e32	717	#if defined( CMU_HFCORECLKEN0_LE )
<>	128:9bcdf88f62b0	718	/** Low energy clock divided down from HFCORECLK. */
<>	128:9bcdf88f62b0	719	cmuClock_HFLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	720	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	721	\| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	722	\| (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	723	\| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	724	#endif
Kojto	98:8ab26030e058	725
Kojto	113:f141b2784e32	726	#if defined( CMU_HFCORECLKEN0_EBI )
Kojto	113:f141b2784e32	727	/** External bus interface clock. */
Kojto	113:f141b2784e32	728	cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	729	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	730	\| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	731	\| (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	732	\| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	733	#endif
Kojto	113:f141b2784e32	734
Kojto	113:f141b2784e32	735	#if defined( CMU_HFCORECLKEN0_USBC )
Kojto	98:8ab26030e058	736	/** USB Core clock. */
Kojto	113:f141b2784e32	737	cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	738	\| (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	739	\| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	740	\| (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	741	\| (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	742
Kojto	98:8ab26030e058	743	#endif
Kojto	98:8ab26030e058	744
Kojto	113:f141b2784e32	745	#if defined( CMU_HFCORECLKEN0_USB )
Kojto	98:8ab26030e058	746	/** USB clock. */
Kojto	113:f141b2784e32	747	cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	748	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	749	\| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	750	\| (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	751	\| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	752	#endif
Kojto	113:f141b2784e32	753
Kojto	98:8ab26030e058	754	/***************/
Kojto	98:8ab26030e058	755	/* LF A branch */
Kojto	98:8ab26030e058	756	/***************/
Kojto	98:8ab26030e058	757
Kojto	98:8ab26030e058	758	/** Low frequency A clock */
Kojto	113:f141b2784e32	759	cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	760	\| (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	761	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	762	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	763	\| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	764
Kojto	113:f141b2784e32	765	#if defined( CMU_LFACLKEN0_RTC )
Kojto	98:8ab26030e058	766	/** Real time counter clock. */
Kojto	113:f141b2784e32	767	cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	768	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	769	\| (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	770	\| (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	771	\| (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	772	#endif
Kojto	98:8ab26030e058	773
Kojto	113:f141b2784e32	774	#if defined( CMU_LFACLKEN0_LETIMER0 )
Kojto	98:8ab26030e058	775	/** Low energy timer 0 clock. */
Kojto	113:f141b2784e32	776	cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	777	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	778	\| (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	779	\| (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	780	\| (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	781	#endif
Kojto	98:8ab26030e058	782
Kojto	113:f141b2784e32	783	#if defined( CMU_LFACLKEN0_LCD )
Kojto	98:8ab26030e058	784	/** Liquid crystal display, pre FDIV clock. */
Kojto	113:f141b2784e32	785	cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	786	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	787	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	788	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	789	\| (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	790
Kojto	98:8ab26030e058	791	/** Liquid crystal display clock. Please notice that FDIV prescaler
Kojto	98:8ab26030e058	792	* must be set by special API. */
Kojto	113:f141b2784e32	793	cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	794	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	795	\| (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	796	\| (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	797	\| (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	798	#endif
Kojto	98:8ab26030e058	799
Kojto	113:f141b2784e32	800	#if defined( CMU_PCNTCTRL_PCNT0CLKEN )
Kojto	98:8ab26030e058	801	/** Pulse counter 0 clock. */
Kojto	113:f141b2784e32	802	cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	803	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	804	\| (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	805	\| (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	806	\| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	807	#endif
Kojto	98:8ab26030e058	808
Kojto	113:f141b2784e32	809	#if defined( CMU_PCNTCTRL_PCNT1CLKEN )
Kojto	98:8ab26030e058	810	/** Pulse counter 1 clock. */
Kojto	113:f141b2784e32	811	cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	812	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	813	\| (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	814	\| (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	815	\| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	816	#endif
Kojto	98:8ab26030e058	817
Kojto	113:f141b2784e32	818	#if defined( CMU_PCNTCTRL_PCNT2CLKEN )
Kojto	98:8ab26030e058	819	/** Pulse counter 2 clock. */
Kojto	113:f141b2784e32	820	cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	821	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	822	\| (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	823	\| (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	824	\| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	825	#endif
Kojto	113:f141b2784e32	826	#if defined( CMU_LFACLKEN0_LESENSE )
Kojto	98:8ab26030e058	827	/** LESENSE clock. */
Kojto	113:f141b2784e32	828	cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	829	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	830	\| (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	831	\| (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	832	\| (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	833	#endif
Kojto	98:8ab26030e058	834
Kojto	98:8ab26030e058	835	/***************/
Kojto	98:8ab26030e058	836	/* LF B branch */
Kojto	98:8ab26030e058	837	/***************/
Kojto	98:8ab26030e058	838
Kojto	98:8ab26030e058	839	/** Low frequency B clock */
Kojto	113:f141b2784e32	840	cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	841	\| (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	842	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	843	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	844	\| (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	845
Kojto	113:f141b2784e32	846	#if defined( CMU_LFBCLKEN0_LEUART0 )
Kojto	98:8ab26030e058	847	/** Low energy universal asynchronous receiver/transmitter 0 clock. */
Kojto	113:f141b2784e32	848	cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	849	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	850	\| (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	851	\| (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	852	\| (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	853	#endif
Kojto	98:8ab26030e058	854
<>	128:9bcdf88f62b0	855	#if defined( CMU_LFBCLKEN0_CSEN )
<>	128:9bcdf88f62b0	856	/** Capacitive Sense LF clock. */
<>	128:9bcdf88f62b0	857	cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	858	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	859	\| (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	860	\| (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
<>	139:856d2700e60b	861	\| (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	862	#endif
<>	128:9bcdf88f62b0	863
Kojto	113:f141b2784e32	864	#if defined( CMU_LFBCLKEN0_LEUART1 )
Kojto	98:8ab26030e058	865	/** Low energy universal asynchronous receiver/transmitter 1 clock. */
Kojto	113:f141b2784e32	866	cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	867	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	868	\| (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	869	\| (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	870	\| (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	98:8ab26030e058	871	#endif
Kojto	98:8ab26030e058	872
<>	128:9bcdf88f62b0	873	#if defined( CMU_LFBCLKEN0_SYSTICK )
<>	128:9bcdf88f62b0	874	/** Cortex SYSTICK LF clock. */
<>	128:9bcdf88f62b0	875	cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
<>	128:9bcdf88f62b0	876	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
<>	128:9bcdf88f62b0	877	\| (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
<>	128:9bcdf88f62b0	878	\| (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS)
<>	128:9bcdf88f62b0	879	\| (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
<>	128:9bcdf88f62b0	880	#endif
<>	128:9bcdf88f62b0	881
Kojto	113:f141b2784e32	882	#if defined( _CMU_LFCCLKEN0_MASK )
Kojto	98:8ab26030e058	883	/***************/
Kojto	98:8ab26030e058	884	/* LF C branch */
Kojto	98:8ab26030e058	885	/***************/
Kojto	98:8ab26030e058	886
Kojto	98:8ab26030e058	887	/** Low frequency C clock */
Kojto	113:f141b2784e32	888	cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	889	\| (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	890	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	891	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	892	\| (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	893
Kojto	113:f141b2784e32	894	#if defined( CMU_LFCCLKEN0_USBLE )
Kojto	113:f141b2784e32	895	/** USB LE clock. */
Kojto	113:f141b2784e32	896	cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
Kojto	113:f141b2784e32	897	\| (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	898	\| (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	899	\| (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	900	\| (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	901	#endif
Kojto	98:8ab26030e058	902	#endif
Kojto	98:8ab26030e058	903
Kojto	113:f141b2784e32	904	#if defined( _CMU_LFECLKEN0_MASK )
Kojto	113:f141b2784e32	905	/***************/
Kojto	113:f141b2784e32	906	/* LF E branch */
Kojto	113:f141b2784e32	907	/***************/
Kojto	113:f141b2784e32	908
Kojto	113:f141b2784e32	909	/** Low frequency A clock */
Kojto	113:f141b2784e32	910	cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	911	\| (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	912	\| (CMU_NO_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	913	\| (0 << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	914	\| (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	915
Kojto	113:f141b2784e32	916	/** Real time counter and calendar clock. */
Kojto	113:f141b2784e32	917	#if defined ( CMU_LFECLKEN0_RTCC )
Kojto	113:f141b2784e32	918	cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
Kojto	113:f141b2784e32	919	\| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
Kojto	113:f141b2784e32	920	\| (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
Kojto	113:f141b2784e32	921	\| (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
Kojto	113:f141b2784e32	922	\| (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
Kojto	113:f141b2784e32	923	#endif
Kojto	98:8ab26030e058	924	#endif
Kojto	98:8ab26030e058	925
Kojto	98:8ab26030e058	926	} CMU_Clock_TypeDef;
Kojto	98:8ab26030e058	927
<>	128:9bcdf88f62b0	928	/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<>	128:9bcdf88f62b0	929	/* Deprecated CMU_Clock_TypeDef member */
<>	128:9bcdf88f62b0	930	#define cmuClock_CORELE cmuClock_HFLE
<>	128:9bcdf88f62b0	931	/** @endcond */
<>	128:9bcdf88f62b0	932
Kojto	98:8ab26030e058	933
Kojto	98:8ab26030e058	934	/** Oscillator types. */
Kojto	98:8ab26030e058	935	typedef enum
Kojto	98:8ab26030e058	936	{
Kojto	98:8ab26030e058	937	cmuOsc_LFXO, /*< Low frequency crystal oscillator. /
Kojto	98:8ab26030e058	938	cmuOsc_LFRCO, /*< Low frequency RC oscillator. /
Kojto	98:8ab26030e058	939	cmuOsc_HFXO, /*< High frequency crystal oscillator. /
Kojto	98:8ab26030e058	940	cmuOsc_HFRCO, /*< High frequency RC oscillator. /
Kojto	98:8ab26030e058	941	cmuOsc_AUXHFRCO, /*< Auxiliary high frequency RC oscillator. /
Kojto	98:8ab26030e058	942	#if defined( _CMU_STATUS_USHFRCOENS_MASK )
Kojto	98:8ab26030e058	943	cmuOsc_USHFRCO, /*< USB high frequency RC oscillator /
Kojto	98:8ab26030e058	944	#endif
Kojto	113:f141b2784e32	945	#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) \|\| defined( CMU_LFACLKSEL_LFA_ULFRCO )
<>	139:856d2700e60b	946	cmuOsc_ULFRCO, /*< Ultra low frequency RC oscillator. /
<>	139:856d2700e60b	947	#endif
<>	139:856d2700e60b	948	#if defined( _CMU_STATUS_PLFRCOENS_MASK )
<>	139:856d2700e60b	949	cmuOsc_PLFRCO, /*< Precision Low Frequency Oscillator. /
Kojto	98:8ab26030e058	950	#endif
Kojto	98:8ab26030e058	951	} CMU_Osc_TypeDef;
Kojto	98:8ab26030e058	952
<>	128:9bcdf88f62b0	953	/** Oscillator modes. */
<>	128:9bcdf88f62b0	954	typedef enum
<>	128:9bcdf88f62b0	955	{
<>	128:9bcdf88f62b0	956	cmuOscMode_Crystal, /*< Crystal oscillator. /
<>	128:9bcdf88f62b0	957	cmuOscMode_AcCoupled, /*< AC coupled buffer. /
<>	128:9bcdf88f62b0	958	cmuOscMode_External, /*< External digital clock. /
<>	128:9bcdf88f62b0	959	} CMU_OscMode_TypeDef;
Kojto	98:8ab26030e058	960
Kojto	98:8ab26030e058	961	/** Selectable clock sources. */
Kojto	98:8ab26030e058	962	typedef enum
Kojto	98:8ab26030e058	963	{
<>	139:856d2700e60b	964	cmuSelect_Error, /*< Usage error. /
<>	139:856d2700e60b	965	cmuSelect_Disabled, /*< Clock selector disabled. /
<>	139:856d2700e60b	966	cmuSelect_LFXO, /*< Low frequency crystal oscillator. /
<>	139:856d2700e60b	967	cmuSelect_LFRCO, /*< Low frequency RC oscillator. /
<>	139:856d2700e60b	968	cmuSelect_HFXO, /*< High frequency crystal oscillator. /
<>	139:856d2700e60b	969	cmuSelect_HFRCO, /*< High frequency RC oscillator. /
<>	139:856d2700e60b	970	cmuSelect_HFCLKLE, /*< High frequency LE clock divided by 2 or 4. /
<>	139:856d2700e60b	971	cmuSelect_AUXHFRCO, /*< Auxilliary clock source can be used for debug clock /
<>	139:856d2700e60b	972	cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
<>	139:856d2700e60b	973	Tiny Gecko and for USBC (not used on Gecko) */
Kojto	113:f141b2784e32	974	#if defined( CMU_STATUS_USHFRCOENS )
<>	139:856d2700e60b	975	cmuSelect_USHFRCO, /*< USB high frequency RC oscillator /
Kojto	98:8ab26030e058	976	#endif
Kojto	113:f141b2784e32	977	#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
<>	139:856d2700e60b	978	cmuSelect_USHFRCODIV2, /*< USB high frequency RC oscillator /
Kojto	98:8ab26030e058	979	#endif
Kojto	113:f141b2784e32	980	#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) \|\| defined( CMU_LFACLKSEL_LFA_ULFRCO )
<>	139:856d2700e60b	981	cmuSelect_ULFRCO, /*< Ultra low frequency RC oscillator. /
<>	139:856d2700e60b	982	#endif
<>	139:856d2700e60b	983	#if defined( _CMU_STATUS_PLFRCOENS_MASK )
<>	139:856d2700e60b	984	cmuSelect_PLFRCO, /*< Precision Low Frequency Oscillator. /
Kojto	98:8ab26030e058	985	#endif
Kojto	98:8ab26030e058	986	} CMU_Select_TypeDef;
Kojto	98:8ab26030e058	987
<>	128:9bcdf88f62b0	988	#if defined( CMU_HFCORECLKEN0_LE )
<>	128:9bcdf88f62b0	989	/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<>	128:9bcdf88f62b0	990	/* Deprecated CMU_Select_TypeDef member */
<>	128:9bcdf88f62b0	991	#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
<>	128:9bcdf88f62b0	992	/** @endcond */
<>	128:9bcdf88f62b0	993	#endif
<>	128:9bcdf88f62b0	994
<>	128:9bcdf88f62b0	995	#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
<>	128:9bcdf88f62b0	996	/** HFXO tuning modes */
<>	128:9bcdf88f62b0	997	typedef enum
<>	128:9bcdf88f62b0	998	{
<>	128:9bcdf88f62b0	999	cmuHFXOTuningMode_Auto = 0,
<>	128:9bcdf88f62b0	1000	cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /*< Run shunt current optimization only /
<>	128:9bcdf88f62b0	1001	cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /*< Run peak and shunt current optimization /
<>	128:9bcdf88f62b0	1002	\| CMU_CMD_HFXOSHUNTOPTSTART,
<>	128:9bcdf88f62b0	1003	} CMU_HFXOTuningMode_TypeDef;
<>	128:9bcdf88f62b0	1004	#endif
<>	128:9bcdf88f62b0	1005
<>	128:9bcdf88f62b0	1006	#if defined( _CMU_CTRL_LFXOBOOST_MASK )
<>	128:9bcdf88f62b0	1007	/** LFXO Boost values. */
<>	128:9bcdf88f62b0	1008	typedef enum
<>	128:9bcdf88f62b0	1009	{
<>	128:9bcdf88f62b0	1010	cmuLfxoBoost70 = 0x0,
<>	128:9bcdf88f62b0	1011	cmuLfxoBoost100 = 0x2,
<>	128:9bcdf88f62b0	1012	#if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
<>	128:9bcdf88f62b0	1013	cmuLfxoBoost70Reduced = 0x1,
<>	128:9bcdf88f62b0	1014	cmuLfxoBoost100Reduced = 0x3,
<>	128:9bcdf88f62b0	1015	#endif
<>	128:9bcdf88f62b0	1016	} CMU_LFXOBoost_TypeDef;
<>	128:9bcdf88f62b0	1017	#endif
Kojto	98:8ab26030e058	1018
Kojto	98:8ab26030e058	1019	/*******************************************************************************
Kojto	113:f141b2784e32	1020	***************************** STRUCTS *********************************
Kojto	113:f141b2784e32	1021	******************************************************************************/
Kojto	113:f141b2784e32	1022
Kojto	113:f141b2784e32	1023	/** LFXO initialization structure. Init values should be obtained from a configuration tool,
Kojto	113:f141b2784e32	1024	app note or xtal datasheet */
Kojto	113:f141b2784e32	1025	typedef struct
Kojto	113:f141b2784e32	1026	{
<>	128:9bcdf88f62b0	1027	#if defined( _CMU_LFXOCTRL_MASK )
Kojto	113:f141b2784e32	1028	uint8_t ctune; /*< CTUNE (load capacitance) value /
Kojto	113:f141b2784e32	1029	uint8_t gain; /*< Gain / max startup margin /
<>	128:9bcdf88f62b0	1030	#else
<>	128:9bcdf88f62b0	1031	CMU_LFXOBoost_TypeDef boost; /*< LFXO boost /
<>	128:9bcdf88f62b0	1032	#endif
Kojto	113:f141b2784e32	1033	uint8_t timeout; /*< Startup delay /
<>	128:9bcdf88f62b0	1034	CMU_OscMode_TypeDef mode; /*< Oscillator mode /
Kojto	113:f141b2784e32	1035	} CMU_LFXOInit_TypeDef;
Kojto	113:f141b2784e32	1036
<>	128:9bcdf88f62b0	1037	#if defined( _CMU_LFXOCTRL_MASK )
<>	128:9bcdf88f62b0	1038	/** Default LFXO initialization values for platform 2 devices which contain a
<>	128:9bcdf88f62b0	1039	* separate LFXOCTRL register. */
<>	128:9bcdf88f62b0	1040	#define CMU_LFXOINIT_DEFAULT \
<>	128:9bcdf88f62b0	1041	{ \
<>	128:9bcdf88f62b0	1042	_CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
<>	128:9bcdf88f62b0	1043	_CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
<>	128:9bcdf88f62b0	1044	_CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \
<>	128:9bcdf88f62b0	1045	cmuOscMode_Crystal, /* Crystal oscillator */ \
<>	128:9bcdf88f62b0	1046	}
<>	128:9bcdf88f62b0	1047	#define CMU_LFXOINIT_EXTERNAL_CLOCK \
<>	128:9bcdf88f62b0	1048	{ \
<>	128:9bcdf88f62b0	1049	0, /* No CTUNE value needed */ \
<>	128:9bcdf88f62b0	1050	0, /* No LFXO startup gain */ \
<>	128:9bcdf88f62b0	1051	_CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
<>	128:9bcdf88f62b0	1052	cmuOscMode_External, /* External digital clock */ \
<>	128:9bcdf88f62b0	1053	}
<>	128:9bcdf88f62b0	1054	#else
<>	128:9bcdf88f62b0	1055	/** Default LFXO initialization values for platform 1 devices. */
<>	128:9bcdf88f62b0	1056	#define CMU_LFXOINIT_DEFAULT \
<>	128:9bcdf88f62b0	1057	{ \
<>	128:9bcdf88f62b0	1058	cmuLfxoBoost70, \
<>	128:9bcdf88f62b0	1059	_CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
<>	128:9bcdf88f62b0	1060	cmuOscMode_Crystal, \
<>	128:9bcdf88f62b0	1061	}
<>	128:9bcdf88f62b0	1062	#define CMU_LFXOINIT_EXTERNAL_CLOCK \
<>	128:9bcdf88f62b0	1063	{ \
<>	128:9bcdf88f62b0	1064	cmuLfxoBoost70, \
<>	128:9bcdf88f62b0	1065	_CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
<>	128:9bcdf88f62b0	1066	cmuOscMode_External, \
Kojto	113:f141b2784e32	1067	}
Kojto	113:f141b2784e32	1068	#endif
Kojto	113:f141b2784e32	1069
Kojto	113:f141b2784e32	1070	/** HFXO initialization structure. Init values should be obtained from a configuration tool,
Kojto	113:f141b2784e32	1071	app note or xtal datasheet */
Kojto	113:f141b2784e32	1072	typedef struct
Kojto	113:f141b2784e32	1073	{
<>	128:9bcdf88f62b0	1074	#if defined( _CMU_HFXOCTRL_MASK )
Kojto	113:f141b2784e32	1075	bool lowPowerMode; /*< Enable low-power mode /
<>	128:9bcdf88f62b0	1076	bool autoStartEm01; /*< @deprecated Use @ref CMU_HFXOAutostartEnable instead. /
<>	128:9bcdf88f62b0	1077	bool autoSelEm01; /*< @deprecated Use @ref CMU_HFXOAutostartEnable instead. /
<>	128:9bcdf88f62b0	1078	bool autoStartSelOnRacWakeup; /*< @deprecated Use @ref CMU_HFXOAutostartEnable instead. /
Kojto	113:f141b2784e32	1079	uint16_t ctuneStartup; /*< Startup phase CTUNE (load capacitance) value /
Kojto	113:f141b2784e32	1080	uint16_t ctuneSteadyState; /*< Steady-state phase CTUNE (load capacitance) value /
Kojto	113:f141b2784e32	1081	uint8_t regIshSteadyState; /*< Shunt steady-state current /
Kojto	113:f141b2784e32	1082	uint8_t xoCoreBiasTrimStartup; /*< Startup XO core bias current trim /
Kojto	113:f141b2784e32	1083	uint8_t xoCoreBiasTrimSteadyState; /*< Steady-state XO core bias current trim /
Kojto	113:f141b2784e32	1084	uint8_t thresholdPeakDetect; /*< Peak detection threshold /
Kojto	113:f141b2784e32	1085	uint8_t timeoutShuntOptimization; /*< Timeout - shunt optimization /
Kojto	113:f141b2784e32	1086	uint8_t timeoutPeakDetect; /*< Timeout - peak detection /
Kojto	113:f141b2784e32	1087	uint8_t timeoutSteady; /*< Timeout - steady-state /
Kojto	113:f141b2784e32	1088	uint8_t timeoutStartup; /*< Timeout - startup /
<>	128:9bcdf88f62b0	1089	#else
<>	128:9bcdf88f62b0	1090	uint8_t boost; /*< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% /
<>	128:9bcdf88f62b0	1091	uint8_t timeout; /*< Startup delay /
<>	128:9bcdf88f62b0	1092	bool glitchDetector; /*< Enable/disable glitch detector /
<>	128:9bcdf88f62b0	1093	#endif
<>	128:9bcdf88f62b0	1094	CMU_OscMode_TypeDef mode; /*< Oscillator mode /
Kojto	113:f141b2784e32	1095	} CMU_HFXOInit_TypeDef;
Kojto	113:f141b2784e32	1096
<>	128:9bcdf88f62b0	1097	#if defined( _CMU_HFXOCTRL_MASK )
<>	128:9bcdf88f62b0	1098	/**
<>	128:9bcdf88f62b0	1099	* Default HFXO initialization values for Platform 2 devices which contain a
<>	128:9bcdf88f62b0	1100	* separate HFXOCTRL register.
<>	128:9bcdf88f62b0	1101	*/
Kojto	113:f141b2784e32	1102	#if defined( _EFR_DEVICE )
Kojto	113:f141b2784e32	1103	#define CMU_HFXOINIT_DEFAULT \
Kojto	113:f141b2784e32	1104	{ \
Kojto	113:f141b2784e32	1105	false, /* Low-noise mode for EFR32 */ \
<>	128:9bcdf88f62b0	1106	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1107	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1108	false, /* @deprecated no longer in use */ \
Kojto	113:f141b2784e32	1109	_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
Kojto	113:f141b2784e32	1110	_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
Kojto	113:f141b2784e32	1111	_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
<>	128:9bcdf88f62b0	1112	0x20, /* Matching errata fix in CHIP_Init() */ \
Kojto	113:f141b2784e32	1113	0x7, /* Recommended steady-state XO core bias current */ \
Kojto	113:f141b2784e32	1114	0x6, /* Recommended peak detection threshold */ \
Kojto	113:f141b2784e32	1115	_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
Kojto	113:f141b2784e32	1116	0xA, /* Recommended peak detection timeout */ \
<>	128:9bcdf88f62b0	1117	0x4, /* Recommended steady timeout */ \
Kojto	113:f141b2784e32	1118	_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
<>	128:9bcdf88f62b0	1119	cmuOscMode_Crystal, \
Kojto	113:f141b2784e32	1120	}
<>	128:9bcdf88f62b0	1121	#else /* EFM32 device */
Kojto	113:f141b2784e32	1122	#define CMU_HFXOINIT_DEFAULT \
Kojto	113:f141b2784e32	1123	{ \
Kojto	113:f141b2784e32	1124	true, /* Low-power mode for EFM32 */ \
<>	128:9bcdf88f62b0	1125	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1126	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1127	false, /* @deprecated no longer in use */ \
Kojto	113:f141b2784e32	1128	_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
Kojto	113:f141b2784e32	1129	_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
Kojto	113:f141b2784e32	1130	_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
<>	128:9bcdf88f62b0	1131	0x20, /* Matching errata fix in CHIP_Init() */ \
Kojto	113:f141b2784e32	1132	0x7, /* Recommended steady-state osc core bias current */ \
Kojto	113:f141b2784e32	1133	0x6, /* Recommended peak detection threshold */ \
Kojto	113:f141b2784e32	1134	_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
Kojto	113:f141b2784e32	1135	0xA, /* Recommended peak detection timeout */ \
<>	128:9bcdf88f62b0	1136	0x4, /* Recommended steady timeout */ \
Kojto	113:f141b2784e32	1137	_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
<>	128:9bcdf88f62b0	1138	cmuOscMode_Crystal, \
Kojto	113:f141b2784e32	1139	}
<>	128:9bcdf88f62b0	1140	#endif /* _EFR_DEVICE */
<>	128:9bcdf88f62b0	1141	#define CMU_HFXOINIT_EXTERNAL_CLOCK \
<>	128:9bcdf88f62b0	1142	{ \
<>	128:9bcdf88f62b0	1143	true, /* Low-power mode */ \
<>	128:9bcdf88f62b0	1144	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1145	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1146	false, /* @deprecated no longer in use */ \
<>	128:9bcdf88f62b0	1147	0, /* Startup CTUNE=0 recommended for external clock */ \
<>	128:9bcdf88f62b0	1148	0, /* Steady CTUNE=0 recommended for external clock */ \
<>	128:9bcdf88f62b0	1149	_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
<>	128:9bcdf88f62b0	1150	0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
<>	128:9bcdf88f62b0	1151	0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
<>	128:9bcdf88f62b0	1152	0x6, /* Recommended peak detection threshold */ \
<>	128:9bcdf88f62b0	1153	_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
<>	128:9bcdf88f62b0	1154	0x0, /* Peak-detect not recommended for external clock usage */ \
<>	128:9bcdf88f62b0	1155	_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
<>	128:9bcdf88f62b0	1156	_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
<>	128:9bcdf88f62b0	1157	cmuOscMode_External, \
<>	128:9bcdf88f62b0	1158	}
<>	128:9bcdf88f62b0	1159	#else /* _CMU_HFXOCTRL_MASK */
<>	128:9bcdf88f62b0	1160	/**
<>	128:9bcdf88f62b0	1161	* Default HFXO initialization values for Platform 1 devices.
<>	128:9bcdf88f62b0	1162	*/
<>	128:9bcdf88f62b0	1163	#define CMU_HFXOINIT_DEFAULT \
<>	128:9bcdf88f62b0	1164	{ \
<>	128:9bcdf88f62b0	1165	_CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
<>	128:9bcdf88f62b0	1166	_CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16k startup delay */ \
<>	128:9bcdf88f62b0	1167	false, /* Disable glitch detector */ \
<>	128:9bcdf88f62b0	1168	cmuOscMode_Crystal, /* Crystal oscillator */ \
<>	128:9bcdf88f62b0	1169	}
<>	128:9bcdf88f62b0	1170	#define CMU_HFXOINIT_EXTERNAL_CLOCK \
<>	128:9bcdf88f62b0	1171	{ \
<>	128:9bcdf88f62b0	1172	0, /* Minimal HFXO boost, 50% */ \
<>	128:9bcdf88f62b0	1173	_CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
<>	128:9bcdf88f62b0	1174	false, /* Disable glitch detector */ \
<>	128:9bcdf88f62b0	1175	cmuOscMode_External, /* External digital clock */ \
<>	128:9bcdf88f62b0	1176	}
Kojto	113:f141b2784e32	1177	#endif /* _CMU_HFXOCTRL_MASK */
Kojto	113:f141b2784e32	1178
Kojto	113:f141b2784e32	1179
Kojto	113:f141b2784e32	1180	/*******************************************************************************
Kojto	98:8ab26030e058	1181	*************************** PROTOTYPES ********************************
Kojto	98:8ab26030e058	1182	******************************************************************************/
Kojto	98:8ab26030e058	1183
Kojto	113:f141b2784e32	1184	#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
Kojto	113:f141b2784e32	1185	CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
Kojto	113:f141b2784e32	1186	void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
Kojto	113:f141b2784e32	1187
Kojto	113:f141b2784e32	1188	#elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<>	128:9bcdf88f62b0	1189	CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
<>	128:9bcdf88f62b0	1190	void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
Kojto	113:f141b2784e32	1191	#endif
Kojto	113:f141b2784e32	1192
Kojto	113:f141b2784e32	1193	uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
Kojto	98:8ab26030e058	1194
Kojto	113:f141b2784e32	1195	#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
Kojto	113:f141b2784e32	1196	void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
Kojto	113:f141b2784e32	1197	CMU_Osc_TypeDef upSel);
Kojto	113:f141b2784e32	1198	#endif
Kojto	98:8ab26030e058	1199
Kojto	113:f141b2784e32	1200	uint32_t CMU_CalibrateCountGet(void);
Kojto	113:f141b2784e32	1201	void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
Kojto	113:f141b2784e32	1202	CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
Kojto	113:f141b2784e32	1203	void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
Kojto	113:f141b2784e32	1204	uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
Kojto	113:f141b2784e32	1205
<>	139:856d2700e60b	1206	#if defined( _SILICON_LABS_32B_SERIES_1 )
Kojto	113:f141b2784e32	1207	void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);
Kojto	113:f141b2784e32	1208	uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
Kojto	98:8ab26030e058	1209	#endif
Kojto	98:8ab26030e058	1210
Kojto	113:f141b2784e32	1211	void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
Kojto	113:f141b2784e32	1212	CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
Kojto	113:f141b2784e32	1213	void CMU_FreezeEnable(bool enable);
Kojto	113:f141b2784e32	1214
Kojto	113:f141b2784e32	1215	#if defined( _CMU_HFRCOCTRL_BAND_MASK )
Kojto	113:f141b2784e32	1216	CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
Kojto	113:f141b2784e32	1217	void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
Kojto	113:f141b2784e32	1218
Kojto	113:f141b2784e32	1219	#elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
<>	128:9bcdf88f62b0	1220	CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
<>	128:9bcdf88f62b0	1221	void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
Kojto	113:f141b2784e32	1222	#endif
Kojto	113:f141b2784e32	1223
Kojto	113:f141b2784e32	1224	uint32_t CMU_HFRCOStartupDelayGet(void);
Kojto	113:f141b2784e32	1225	void CMU_HFRCOStartupDelaySet(uint32_t delay);
Kojto	113:f141b2784e32	1226
<>	128:9bcdf88f62b0	1227	#if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
<>	128:9bcdf88f62b0	1228	void CMU_HFXOAutostartEnable(uint32_t userSel,
Kojto	113:f141b2784e32	1229	bool enEM0EM1Start,
Kojto	113:f141b2784e32	1230	bool enEM0EM1StartSel);
Kojto	113:f141b2784e32	1231	#endif
Kojto	113:f141b2784e32	1232
<>	128:9bcdf88f62b0	1233	void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
Kojto	113:f141b2784e32	1234
Kojto	113:f141b2784e32	1235
Kojto	113:f141b2784e32	1236	uint32_t CMU_LCDClkFDIVGet(void);
Kojto	113:f141b2784e32	1237	void CMU_LCDClkFDIVSet(uint32_t div);
<>	128:9bcdf88f62b0	1238	void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
Kojto	98:8ab26030e058	1239
Kojto	113:f141b2784e32	1240	void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
Kojto	113:f141b2784e32	1241	uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
Kojto	113:f141b2784e32	1242	void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
<>	128:9bcdf88f62b0	1243
<>	128:9bcdf88f62b0	1244	#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
<>	128:9bcdf88f62b0	1245	bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
<>	128:9bcdf88f62b0	1246	bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
<>	128:9bcdf88f62b0	1247	CMU_HFXOTuningMode_TypeDef mode,
<>	128:9bcdf88f62b0	1248	bool wait);
<>	128:9bcdf88f62b0	1249	#endif
<>	128:9bcdf88f62b0	1250
Kojto	113:f141b2784e32	1251	bool CMU_PCNTClockExternalGet(unsigned int instance);
Kojto	113:f141b2784e32	1252	void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
Kojto	113:f141b2784e32	1253
Kojto	113:f141b2784e32	1254	#if defined( _CMU_USHFRCOCONF_BAND_MASK )
Kojto	113:f141b2784e32	1255	CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
Kojto	113:f141b2784e32	1256	void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
Kojto	113:f141b2784e32	1257	#endif
Kojto	113:f141b2784e32	1258
Kojto	98:8ab26030e058	1259
Kojto	113:f141b2784e32	1260	#if defined( CMU_CALCTRL_CONT )
Kojto	113:f141b2784e32	1261	/*************************************************************************//
Kojto	113:f141b2784e32	1262	* @brief
Kojto	113:f141b2784e32	1263	* Configures continuous calibration mode
Kojto	113:f141b2784e32	1264	* @param[in] enable
Kojto	113:f141b2784e32	1265	* If true, enables continuous calibration, if false disables continuous
Kojto	113:f141b2784e32	1266	* calibrartion
Kojto	113:f141b2784e32	1267	******************************************************************************/
Kojto	113:f141b2784e32	1268	__STATIC_INLINE void CMU_CalibrateCont(bool enable)
Kojto	113:f141b2784e32	1269	{
Kojto	113:f141b2784e32	1270	BUS_RegBitWrite(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
Kojto	113:f141b2784e32	1271	}
Kojto	113:f141b2784e32	1272	#endif
Kojto	98:8ab26030e058	1273
Kojto	98:8ab26030e058	1274
Kojto	113:f141b2784e32	1275	/*************************************************************************//
Kojto	113:f141b2784e32	1276	* @brief
Kojto	113:f141b2784e32	1277	* Starts calibration
Kojto	113:f141b2784e32	1278	* @note
Kojto	113:f141b2784e32	1279	* This call is usually invoked after CMU_CalibrateConfig() and possibly
Kojto	113:f141b2784e32	1280	* CMU_CalibrateCont()
Kojto	113:f141b2784e32	1281	******************************************************************************/
Kojto	113:f141b2784e32	1282	__STATIC_INLINE void CMU_CalibrateStart(void)
Kojto	113:f141b2784e32	1283	{
Kojto	113:f141b2784e32	1284	CMU->CMD = CMU_CMD_CALSTART;
Kojto	113:f141b2784e32	1285	}
Kojto	113:f141b2784e32	1286
Kojto	113:f141b2784e32	1287
Kojto	113:f141b2784e32	1288	#if defined( CMU_CMD_CALSTOP )
Kojto	113:f141b2784e32	1289	/*************************************************************************//
Kojto	113:f141b2784e32	1290	* @brief
Kojto	113:f141b2784e32	1291	* Stop the calibration counters
Kojto	113:f141b2784e32	1292	******************************************************************************/
Kojto	113:f141b2784e32	1293	__STATIC_INLINE void CMU_CalibrateStop(void)
Kojto	113:f141b2784e32	1294	{
Kojto	113:f141b2784e32	1295	CMU->CMD = CMU_CMD_CALSTOP;
Kojto	113:f141b2784e32	1296	}
Kojto	113:f141b2784e32	1297	#endif
Kojto	113:f141b2784e32	1298
Kojto	98:8ab26030e058	1299
Kojto	113:f141b2784e32	1300	/*************************************************************************//
Kojto	113:f141b2784e32	1301	* @brief
Kojto	113:f141b2784e32	1302	* Convert dividend to logarithmic value. Only works for even
Kojto	113:f141b2784e32	1303	* numbers equal to 2^n.
Kojto	113:f141b2784e32	1304	*
Kojto	113:f141b2784e32	1305	* @param[in] div
Kojto	113:f141b2784e32	1306	* Unscaled dividend.
Kojto	113:f141b2784e32	1307	*
Kojto	113:f141b2784e32	1308	* @return
Kojto	113:f141b2784e32	1309	* Logarithm of 2, as used by fixed prescalers.
Kojto	113:f141b2784e32	1310	******************************************************************************/
Kojto	113:f141b2784e32	1311	__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Kojto	113:f141b2784e32	1312	{
Kojto	113:f141b2784e32	1313	uint32_t log2;
Kojto	98:8ab26030e058	1314
Kojto	113:f141b2784e32	1315	/* Fixed 2^n prescalers take argument of 32768 or less. */
Kojto	113:f141b2784e32	1316	EFM_ASSERT((div > 0U) && (div <= 32768U));
Kojto	113:f141b2784e32	1317
Kojto	113:f141b2784e32	1318	/* Count leading zeroes and "reverse" result */
Kojto	113:f141b2784e32	1319	log2 = (31U - __CLZ(div));
Kojto	113:f141b2784e32	1320
Kojto	113:f141b2784e32	1321	return log2;
Kojto	113:f141b2784e32	1322	}
Kojto	113:f141b2784e32	1323
Kojto	98:8ab26030e058	1324
Kojto	98:8ab26030e058	1325	/*************************************************************************//
Kojto	98:8ab26030e058	1326	* @brief
Kojto	98:8ab26030e058	1327	* Clear one or more pending CMU interrupts.
Kojto	98:8ab26030e058	1328	*
Kojto	98:8ab26030e058	1329	* @param[in] flags
Kojto	98:8ab26030e058	1330	* CMU interrupt sources to clear.
Kojto	98:8ab26030e058	1331	******************************************************************************/
Kojto	98:8ab26030e058	1332	__STATIC_INLINE void CMU_IntClear(uint32_t flags)
Kojto	98:8ab26030e058	1333	{
Kojto	98:8ab26030e058	1334	CMU->IFC = flags;
Kojto	98:8ab26030e058	1335	}
Kojto	98:8ab26030e058	1336
Kojto	98:8ab26030e058	1337
Kojto	98:8ab26030e058	1338	/*************************************************************************//
Kojto	98:8ab26030e058	1339	* @brief
Kojto	98:8ab26030e058	1340	* Disable one or more CMU interrupts.
Kojto	98:8ab26030e058	1341	*
Kojto	98:8ab26030e058	1342	* @param[in] flags
Kojto	98:8ab26030e058	1343	* CMU interrupt sources to disable.
Kojto	98:8ab26030e058	1344	******************************************************************************/
Kojto	98:8ab26030e058	1345	__STATIC_INLINE void CMU_IntDisable(uint32_t flags)
Kojto	98:8ab26030e058	1346	{
Kojto	98:8ab26030e058	1347	CMU->IEN &= ~flags;
Kojto	98:8ab26030e058	1348	}
Kojto	98:8ab26030e058	1349
Kojto	98:8ab26030e058	1350
Kojto	98:8ab26030e058	1351	/*************************************************************************//
Kojto	98:8ab26030e058	1352	* @brief
Kojto	98:8ab26030e058	1353	* Enable one or more CMU interrupts.
Kojto	98:8ab26030e058	1354	*
Kojto	98:8ab26030e058	1355	* @note
Kojto	98:8ab26030e058	1356	* Depending on the use, a pending interrupt may already be set prior to
Kojto	98:8ab26030e058	1357	* enabling the interrupt. Consider using CMU_IntClear() prior to enabling
Kojto	98:8ab26030e058	1358	* if such a pending interrupt should be ignored.
Kojto	98:8ab26030e058	1359	*
Kojto	98:8ab26030e058	1360	* @param[in] flags
Kojto	98:8ab26030e058	1361	* CMU interrupt sources to enable.
Kojto	98:8ab26030e058	1362	******************************************************************************/
Kojto	98:8ab26030e058	1363	__STATIC_INLINE void CMU_IntEnable(uint32_t flags)
Kojto	98:8ab26030e058	1364	{
Kojto	98:8ab26030e058	1365	CMU->IEN \|= flags;
Kojto	98:8ab26030e058	1366	}
Kojto	98:8ab26030e058	1367
Kojto	98:8ab26030e058	1368
Kojto	98:8ab26030e058	1369	/*************************************************************************//
Kojto	98:8ab26030e058	1370	* @brief
Kojto	98:8ab26030e058	1371	* Get pending CMU interrupts.
Kojto	98:8ab26030e058	1372	*
Kojto	98:8ab26030e058	1373	* @return
Kojto	98:8ab26030e058	1374	* CMU interrupt sources pending.
Kojto	98:8ab26030e058	1375	******************************************************************************/
Kojto	98:8ab26030e058	1376	__STATIC_INLINE uint32_t CMU_IntGet(void)
Kojto	98:8ab26030e058	1377	{
Kojto	98:8ab26030e058	1378	return CMU->IF;
Kojto	98:8ab26030e058	1379	}
Kojto	98:8ab26030e058	1380
Kojto	98:8ab26030e058	1381
Kojto	98:8ab26030e058	1382	/*************************************************************************//
Kojto	98:8ab26030e058	1383	* @brief
Kojto	98:8ab26030e058	1384	* Get enabled and pending CMU interrupt flags.
Kojto	98:8ab26030e058	1385	*
Kojto	98:8ab26030e058	1386	* @details
Kojto	98:8ab26030e058	1387	* Useful for handling more interrupt sources in the same interrupt handler.
Kojto	98:8ab26030e058	1388	*
Kojto	98:8ab26030e058	1389	* @note
Kojto	98:8ab26030e058	1390	* The event bits are not cleared by the use of this function.
Kojto	98:8ab26030e058	1391	*
Kojto	98:8ab26030e058	1392	* @return
Kojto	113:f141b2784e32	1393	* Pending and enabled CMU interrupt sources
Kojto	113:f141b2784e32	1394	* The return value is the bitwise AND of
Kojto	113:f141b2784e32	1395	* - the enabled interrupt sources in CMU_IEN and
Kojto	113:f141b2784e32	1396	* - the pending interrupt flags CMU_IF
Kojto	98:8ab26030e058	1397	******************************************************************************/
Kojto	98:8ab26030e058	1398	__STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
Kojto	98:8ab26030e058	1399	{
Kojto	113:f141b2784e32	1400	uint32_t ien;
Kojto	98:8ab26030e058	1401
Kojto	113:f141b2784e32	1402	ien = CMU->IEN;
Kojto	113:f141b2784e32	1403	return CMU->IF & ien;
Kojto	98:8ab26030e058	1404	}
Kojto	98:8ab26030e058	1405
Kojto	98:8ab26030e058	1406
Kojto	98:8ab26030e058	1407	/************************************************************************//
Kojto	98:8ab26030e058	1408	* @brief
Kojto	113:f141b2784e32	1409	* Set one or more pending CMU interrupts.
Kojto	98:8ab26030e058	1410	*
Kojto	98:8ab26030e058	1411	* @param[in] flags
Kojto	98:8ab26030e058	1412	* CMU interrupt sources to set to pending.
Kojto	98:8ab26030e058	1413	*****************************************************************************/
Kojto	98:8ab26030e058	1414	__STATIC_INLINE void CMU_IntSet(uint32_t flags)
Kojto	98:8ab26030e058	1415	{
Kojto	98:8ab26030e058	1416	CMU->IFS = flags;
Kojto	98:8ab26030e058	1417	}
Kojto	98:8ab26030e058	1418
Kojto	98:8ab26030e058	1419
Kojto	98:8ab26030e058	1420	/*************************************************************************//
Kojto	98:8ab26030e058	1421	* @brief
Kojto	98:8ab26030e058	1422	* Lock the CMU in order to protect some of its registers against unintended
Kojto	98:8ab26030e058	1423	* modification.
Kojto	98:8ab26030e058	1424	*
Kojto	98:8ab26030e058	1425	* @details
Kojto	98:8ab26030e058	1426	* Please refer to the reference manual for CMU registers that will be
Kojto	98:8ab26030e058	1427	* locked.
Kojto	98:8ab26030e058	1428	*
Kojto	98:8ab26030e058	1429	* @note
Kojto	98:8ab26030e058	1430	* If locking the CMU registers, they must be unlocked prior to using any
Kojto	98:8ab26030e058	1431	* CMU API functions modifying CMU registers protected by the lock.
Kojto	98:8ab26030e058	1432	******************************************************************************/
Kojto	98:8ab26030e058	1433	__STATIC_INLINE void CMU_Lock(void)
Kojto	98:8ab26030e058	1434	{
Kojto	98:8ab26030e058	1435	CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
Kojto	98:8ab26030e058	1436	}
Kojto	98:8ab26030e058	1437
Kojto	98:8ab26030e058	1438
Kojto	98:8ab26030e058	1439	/*************************************************************************//
Kojto	98:8ab26030e058	1440	* @brief
Kojto	113:f141b2784e32	1441	* Convert logarithm of 2 prescaler to division factor.
Kojto	113:f141b2784e32	1442	*
Kojto	113:f141b2784e32	1443	* @param[in] log2
Kojto	113:f141b2784e32	1444	* Logarithm of 2, as used by fixed prescalers.
Kojto	113:f141b2784e32	1445	*
Kojto	113:f141b2784e32	1446	* @return
Kojto	113:f141b2784e32	1447	* Dividend.
Kojto	113:f141b2784e32	1448	******************************************************************************/
Kojto	113:f141b2784e32	1449	__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Kojto	113:f141b2784e32	1450	{
Kojto	113:f141b2784e32	1451	return 1 << log2;
Kojto	113:f141b2784e32	1452	}
Kojto	113:f141b2784e32	1453
Kojto	113:f141b2784e32	1454
<>	139:856d2700e60b	1455	#if defined( _SILICON_LABS_32B_SERIES_1 )
Kojto	113:f141b2784e32	1456	/*************************************************************************//
Kojto	113:f141b2784e32	1457	* @brief
Kojto	113:f141b2784e32	1458	* Convert prescaler dividend to logarithmic value. Only works for even
Kojto	113:f141b2784e32	1459	* numbers equal to 2^n.
Kojto	113:f141b2784e32	1460	*
Kojto	113:f141b2784e32	1461	* @param[in] presc
Kojto	113:f141b2784e32	1462	* Unscaled dividend (dividend = presc + 1).
Kojto	113:f141b2784e32	1463	*
Kojto	113:f141b2784e32	1464	* @return
Kojto	113:f141b2784e32	1465	* Logarithm of 2, as used by fixed 2^n prescalers.
Kojto	113:f141b2784e32	1466	******************************************************************************/
Kojto	113:f141b2784e32	1467	__STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
Kojto	113:f141b2784e32	1468	{
Kojto	113:f141b2784e32	1469	uint32_t log2;
Kojto	113:f141b2784e32	1470
Kojto	113:f141b2784e32	1471	/* Integer prescalers take argument less than 32768. */
Kojto	113:f141b2784e32	1472	EFM_ASSERT(presc < 32768U);
Kojto	113:f141b2784e32	1473
Kojto	113:f141b2784e32	1474	/* Count leading zeroes and "reverse" result */
Kojto	113:f141b2784e32	1475	log2 = (31U - __CLZ(presc + 1));
Kojto	113:f141b2784e32	1476
Kojto	113:f141b2784e32	1477	/* Check that presc is a 2^n number */
Kojto	113:f141b2784e32	1478	EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1));
Kojto	113:f141b2784e32	1479
Kojto	113:f141b2784e32	1480	return log2;
Kojto	113:f141b2784e32	1481	}
Kojto	113:f141b2784e32	1482	#endif
Kojto	113:f141b2784e32	1483
Kojto	113:f141b2784e32	1484
Kojto	113:f141b2784e32	1485	/*************************************************************************//
Kojto	113:f141b2784e32	1486	* @brief
Kojto	98:8ab26030e058	1487	* Unlock the CMU so that writing to locked registers again is possible.
Kojto	98:8ab26030e058	1488	******************************************************************************/
Kojto	98:8ab26030e058	1489	__STATIC_INLINE void CMU_Unlock(void)
Kojto	98:8ab26030e058	1490	{
Kojto	98:8ab26030e058	1491	CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
Kojto	98:8ab26030e058	1492	}
Kojto	98:8ab26030e058	1493
<>	128:9bcdf88f62b0	1494
<>	128:9bcdf88f62b0	1495	#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
<>	128:9bcdf88f62b0	1496	/*************************************************************************//
<>	128:9bcdf88f62b0	1497	* @brief
<>	128:9bcdf88f62b0	1498	* Get current HFRCO frequency.
<>	128:9bcdf88f62b0	1499	*
<>	128:9bcdf88f62b0	1500	* @deprecated
<>	128:9bcdf88f62b0	1501	* Deprecated function. New code should use @ref CMU_HFRCOBandGet().
<>	128:9bcdf88f62b0	1502	*
<>	128:9bcdf88f62b0	1503	* @return
<>	128:9bcdf88f62b0	1504	* HFRCO frequency
<>	128:9bcdf88f62b0	1505	******************************************************************************/
<>	128:9bcdf88f62b0	1506	__STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
<>	128:9bcdf88f62b0	1507	{
<>	128:9bcdf88f62b0	1508	return CMU_HFRCOBandGet();
<>	128:9bcdf88f62b0	1509	}
<>	128:9bcdf88f62b0	1510
<>	128:9bcdf88f62b0	1511
<>	128:9bcdf88f62b0	1512	/*************************************************************************//
<>	128:9bcdf88f62b0	1513	* @brief
<>	128:9bcdf88f62b0	1514	* Set HFRCO calibration for the selected target frequency
<>	128:9bcdf88f62b0	1515	*
<>	128:9bcdf88f62b0	1516	* @deprecated
<>	128:9bcdf88f62b0	1517	* Deprecated function. New code should use @ref CMU_HFRCOBandSet().
<>	128:9bcdf88f62b0	1518	*
<>	128:9bcdf88f62b0	1519	* @param[in] setFreq
<>	128:9bcdf88f62b0	1520	* HFRCO frequency to set
<>	128:9bcdf88f62b0	1521	******************************************************************************/
<>	128:9bcdf88f62b0	1522	__STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
<>	128:9bcdf88f62b0	1523	{
<>	128:9bcdf88f62b0	1524	CMU_HFRCOBandSet(setFreq);
<>	128:9bcdf88f62b0	1525	}
<>	128:9bcdf88f62b0	1526	#endif
<>	128:9bcdf88f62b0	1527
<>	128:9bcdf88f62b0	1528
<>	128:9bcdf88f62b0	1529	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
<>	128:9bcdf88f62b0	1530	/*************************************************************************//
<>	128:9bcdf88f62b0	1531	* @brief
<>	128:9bcdf88f62b0	1532	* Get current AUXHFRCO frequency.
<>	128:9bcdf88f62b0	1533	*
<>	128:9bcdf88f62b0	1534	* @deprecated
<>	128:9bcdf88f62b0	1535	* Deprecated function. New code should use @ref CMU_AUXHFRCOBandGet().
<>	128:9bcdf88f62b0	1536	*
<>	128:9bcdf88f62b0	1537	* @return
<>	128:9bcdf88f62b0	1538	* AUXHFRCO frequency
<>	128:9bcdf88f62b0	1539	******************************************************************************/
<>	128:9bcdf88f62b0	1540	__STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
<>	128:9bcdf88f62b0	1541	{
<>	128:9bcdf88f62b0	1542	return CMU_AUXHFRCOBandGet();
<>	128:9bcdf88f62b0	1543	}
<>	128:9bcdf88f62b0	1544
<>	128:9bcdf88f62b0	1545
<>	128:9bcdf88f62b0	1546	/*************************************************************************//
<>	128:9bcdf88f62b0	1547	* @brief
<>	128:9bcdf88f62b0	1548	* Set AUXHFRCO calibration for the selected target frequency
<>	128:9bcdf88f62b0	1549	*
<>	128:9bcdf88f62b0	1550	* @deprecated
<>	128:9bcdf88f62b0	1551	* Deprecated function. New code should use @ref CMU_AUXHFRCOBandSet().
<>	128:9bcdf88f62b0	1552	*
<>	128:9bcdf88f62b0	1553	* @param[in] setFreq
<>	128:9bcdf88f62b0	1554	* AUXHFRCO frequency to set
<>	128:9bcdf88f62b0	1555	******************************************************************************/
<>	128:9bcdf88f62b0	1556	__STATIC_INLINE void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
<>	128:9bcdf88f62b0	1557	{
<>	128:9bcdf88f62b0	1558	CMU_AUXHFRCOBandSet(setFreq);
<>	128:9bcdf88f62b0	1559	}
<>	128:9bcdf88f62b0	1560	#endif
<>	128:9bcdf88f62b0	1561
Kojto	98:8ab26030e058	1562	/** @} (end addtogroup CMU) */
<>	128:9bcdf88f62b0	1563	/** @} (end addtogroup emlib) */
Kojto	98:8ab26030e058	1564
Kojto	98:8ab26030e058	1565	#ifdef __cplusplus
Kojto	98:8ab26030e058	1566	}
Kojto	98:8ab26030e058	1567	#endif
Kojto	98:8ab26030e058	1568
Kojto	98:8ab26030e058	1569	#endif /* defined( CMU_PRESENT ) */
<>	128:9bcdf88f62b0	1570	#endif /* EM_CMU_H */