mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARCH_MAX/stm32f4xx_hal_pwr_ex.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
110:165afa46840b 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_pwr_ex.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
bogdanm 89:552587b429a1 7 * @brief Header file of PWR HAL Extension module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_PWR_EX_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_PWR_EX_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup PWREx
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 59 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
Kojto 110:165afa46840b 62 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 63 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 92:4fc01daae5a5 64
Kojto 99:dbbf35b96557 65 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
bogdanm 92:4fc01daae5a5 66 * @{
bogdanm 92:4fc01daae5a5 67 */
bogdanm 92:4fc01daae5a5 68 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
bogdanm 92:4fc01daae5a5 69 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
bogdanm 92:4fc01daae5a5 70 /**
bogdanm 92:4fc01daae5a5 71 * @}
bogdanm 92:4fc01daae5a5 72 */
bogdanm 92:4fc01daae5a5 73
Kojto 99:dbbf35b96557 74 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
bogdanm 89:552587b429a1 75 * @{
bogdanm 89:552587b429a1 76 */
bogdanm 89:552587b429a1 77 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
bogdanm 89:552587b429a1 78 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
bogdanm 89:552587b429a1 79 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
bogdanm 89:552587b429a1 80 /**
bogdanm 89:552587b429a1 81 * @}
bogdanm 89:552587b429a1 82 */
Kojto 110:165afa46840b 83 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 84
Kojto 110:165afa46840b 85 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
Kojto 99:dbbf35b96557 86 * @{
Kojto 99:dbbf35b96557 87 */
Kojto 106:ba1f97679dad 88 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 89 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
Kojto 122:f9eeca106725 90 #define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000U) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
Kojto 99:dbbf35b96557 91 #else
Kojto 99:dbbf35b96557 92 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
Kojto 99:dbbf35b96557 93 180 MHz by activating the over-drive mode. */
Kojto 99:dbbf35b96557 94 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
Kojto 99:dbbf35b96557 95 168 MHz by activating the over-drive mode. */
Kojto 99:dbbf35b96557 96 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
Kojto 99:dbbf35b96557 97 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 99:dbbf35b96557 98 /**
Kojto 99:dbbf35b96557 99 * @}
Kojto 99:dbbf35b96557 100 */
Kojto 122:f9eeca106725 101 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
Kojto 122:f9eeca106725 102 defined(STM32F412Rx) || defined(STM32F412Cx)
Kojto 110:165afa46840b 103 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
Kojto 110:165afa46840b 104 * @{
Kojto 110:165afa46840b 105 */
Kojto 122:f9eeca106725 106 #define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 107 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
Kojto 122:f9eeca106725 108 defined(STM32F412Rx) || defined(STM32F412Cx)
Kojto 122:f9eeca106725 109 #define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 110 #endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
Kojto 122:f9eeca106725 111 STM32F412Rx || STM32F412Cx */
Kojto 110:165afa46840b 112 /**
Kojto 110:165afa46840b 113 * @}
Kojto 110:165afa46840b 114 */
Kojto 122:f9eeca106725 115 #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
Kojto 110:165afa46840b 116
bogdanm 89:552587b429a1 117 /**
bogdanm 89:552587b429a1 118 * @}
bogdanm 89:552587b429a1 119 */
bogdanm 89:552587b429a1 120
bogdanm 89:552587b429a1 121 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 122 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
Kojto 99:dbbf35b96557 123 * @{
Kojto 99:dbbf35b96557 124 */
Kojto 110:165afa46840b 125
Kojto 110:165afa46840b 126 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 110:165afa46840b 127 /** @brief macros configure the main internal regulator output voltage.
Kojto 110:165afa46840b 128 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 110:165afa46840b 129 * a tradeoff between performance and power consumption when the device does
Kojto 110:165afa46840b 130 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 110:165afa46840b 131 * This parameter can be one of the following values:
Kojto 110:165afa46840b 132 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 110:165afa46840b 133 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 110:165afa46840b 134 * @retval None
Kojto 110:165afa46840b 135 */
Kojto 110:165afa46840b 136 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 122:f9eeca106725 137 __IO uint32_t tmpreg = 0x00U; \
Kojto 110:165afa46840b 138 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 110:165afa46840b 139 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 140 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 110:165afa46840b 141 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 142 } while(0)
Kojto 110:165afa46840b 143 #else
Kojto 110:165afa46840b 144 /** @brief macros configure the main internal regulator output voltage.
Kojto 110:165afa46840b 145 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 110:165afa46840b 146 * a tradeoff between performance and power consumption when the device does
Kojto 110:165afa46840b 147 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 110:165afa46840b 148 * This parameter can be one of the following values:
Kojto 110:165afa46840b 149 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 110:165afa46840b 150 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 110:165afa46840b 151 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
Kojto 110:165afa46840b 152 * @retval None
Kojto 110:165afa46840b 153 */
Kojto 110:165afa46840b 154 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 122:f9eeca106725 155 __IO uint32_t tmpreg = 0x00U; \
Kojto 110:165afa46840b 156 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 110:165afa46840b 157 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 158 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 110:165afa46840b 159 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 160 } while(0)
Kojto 110:165afa46840b 161 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 110:165afa46840b 162
Kojto 110:165afa46840b 163 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 164 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 89:552587b429a1 165 /** @brief Macros to enable or disable the Over drive mode.
bogdanm 89:552587b429a1 166 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
bogdanm 89:552587b429a1 167 */
bogdanm 89:552587b429a1 168 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
bogdanm 89:552587b429a1 169 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
bogdanm 89:552587b429a1 170
bogdanm 89:552587b429a1 171 /** @brief Macros to enable or disable the Over drive switching.
bogdanm 89:552587b429a1 172 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
bogdanm 89:552587b429a1 173 */
bogdanm 89:552587b429a1 174 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
bogdanm 89:552587b429a1 175 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
bogdanm 89:552587b429a1 176
bogdanm 89:552587b429a1 177 /** @brief Macros to enable or disable the Under drive mode.
bogdanm 89:552587b429a1 178 * @note This mode is enabled only with STOP low power mode.
bogdanm 89:552587b429a1 179 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
bogdanm 89:552587b429a1 180 * mode is only available when the main regulator or the low power regulator
bogdanm 89:552587b429a1 181 * is in low voltage mode.
bogdanm 89:552587b429a1 182 * @note If the Under-drive mode was enabled, it is automatically disabled after
bogdanm 89:552587b429a1 183 * exiting Stop mode.
bogdanm 89:552587b429a1 184 * When the voltage regulator operates in Under-drive mode, an additional
bogdanm 89:552587b429a1 185 * startup delay is induced when waking up from Stop mode.
bogdanm 89:552587b429a1 186 */
bogdanm 89:552587b429a1 187 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
bogdanm 89:552587b429a1 188 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
bogdanm 89:552587b429a1 189
bogdanm 89:552587b429a1 190 /** @brief Check PWR flag is set or not.
bogdanm 89:552587b429a1 191 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
bogdanm 89:552587b429a1 192 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 193 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 194 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
bogdanm 89:552587b429a1 195 * is ready
bogdanm 89:552587b429a1 196 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
bogdanm 89:552587b429a1 197 * switching is ready
bogdanm 89:552587b429a1 198 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
bogdanm 89:552587b429a1 199 * is enabled in Stop mode
bogdanm 89:552587b429a1 200 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 89:552587b429a1 201 */
bogdanm 89:552587b429a1 202 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 89:552587b429a1 203
bogdanm 89:552587b429a1 204 /** @brief Clear the Under-Drive Ready flag.
bogdanm 89:552587b429a1 205 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
bogdanm 89:552587b429a1 206 */
bogdanm 89:552587b429a1 207 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
bogdanm 89:552587b429a1 208
Kojto 110:165afa46840b 209 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 210 /**
Kojto 99:dbbf35b96557 211 * @}
Kojto 99:dbbf35b96557 212 */
bogdanm 89:552587b429a1 213
bogdanm 89:552587b429a1 214 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 215 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
Kojto 99:dbbf35b96557 216 * @{
Kojto 99:dbbf35b96557 217 */
Kojto 99:dbbf35b96557 218
Kojto 99:dbbf35b96557 219 /** @addtogroup PWREx_Exported_Functions_Group1
Kojto 99:dbbf35b96557 220 * @{
Kojto 99:dbbf35b96557 221 */
Kojto 99:dbbf35b96557 222 void HAL_PWREx_EnableFlashPowerDown(void);
Kojto 99:dbbf35b96557 223 void HAL_PWREx_DisableFlashPowerDown(void);
bogdanm 89:552587b429a1 224 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
bogdanm 89:552587b429a1 225 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
Kojto 99:dbbf35b96557 226 uint32_t HAL_PWREx_GetVoltageRange(void);
Kojto 99:dbbf35b96557 227 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
bogdanm 89:552587b429a1 228
Kojto 110:165afa46840b 229 #if defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 230 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
Kojto 110:165afa46840b 231 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
Kojto 110:165afa46840b 232 #endif /* STM32F469xx || STM32F479xx */
Kojto 110:165afa46840b 233
Kojto 110:165afa46840b 234 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
Kojto 122:f9eeca106725 235 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
Kojto 122:f9eeca106725 236 defined(STM32F412Rx) || defined(STM32F412Cx)
bogdanm 92:4fc01daae5a5 237 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
bogdanm 92:4fc01daae5a5 238 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
bogdanm 92:4fc01daae5a5 239 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
bogdanm 92:4fc01daae5a5 240 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
Kojto 122:f9eeca106725 241 #endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
Kojto 122:f9eeca106725 242 STM32F412Rx || STM32F412Cx */
bogdanm 92:4fc01daae5a5 243
Kojto 110:165afa46840b 244 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
Kojto 110:165afa46840b 245 defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 246 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
Kojto 99:dbbf35b96557 247 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
bogdanm 92:4fc01daae5a5 248 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
Kojto 110:165afa46840b 249 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 250
Kojto 99:dbbf35b96557 251 /**
Kojto 99:dbbf35b96557 252 * @}
Kojto 99:dbbf35b96557 253 */
Kojto 99:dbbf35b96557 254
Kojto 99:dbbf35b96557 255 /**
Kojto 99:dbbf35b96557 256 * @}
Kojto 99:dbbf35b96557 257 */
Kojto 99:dbbf35b96557 258 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 259 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 260 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 261 /** @defgroup PWREx_Private_Constants PWREx Private Constants
Kojto 99:dbbf35b96557 262 * @{
Kojto 99:dbbf35b96557 263 */
Kojto 99:dbbf35b96557 264
Kojto 99:dbbf35b96557 265 /** @defgroup PWREx_register_alias_address PWREx Register alias address
Kojto 99:dbbf35b96557 266 * @{
Kojto 99:dbbf35b96557 267 */
Kojto 99:dbbf35b96557 268 /* ------------- PWR registers bit address in the alias region ---------------*/
Kojto 99:dbbf35b96557 269 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 270 /* Alias word address of FPDS bit */
Kojto 99:dbbf35b96557 271 #define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
Kojto 122:f9eeca106725 272 #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 273
Kojto 99:dbbf35b96557 274 /* Alias word address of ODEN bit */
Kojto 99:dbbf35b96557 275 #define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
Kojto 122:f9eeca106725 276 #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 277
Kojto 99:dbbf35b96557 278 /* Alias word address of ODSWEN bit */
Kojto 99:dbbf35b96557 279 #define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
Kojto 122:f9eeca106725 280 #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 281
Kojto 99:dbbf35b96557 282 /* Alias word address of MRLVDS bit */
Kojto 99:dbbf35b96557 283 #define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
Kojto 122:f9eeca106725 284 #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 285
Kojto 99:dbbf35b96557 286 /* Alias word address of LPLVDS bit */
Kojto 99:dbbf35b96557 287 #define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
Kojto 122:f9eeca106725 288 #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 289
Kojto 99:dbbf35b96557 290 /**
Kojto 99:dbbf35b96557 291 * @}
Kojto 99:dbbf35b96557 292 */
Kojto 99:dbbf35b96557 293
Kojto 99:dbbf35b96557 294 /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
Kojto 99:dbbf35b96557 295 * @{
Kojto 99:dbbf35b96557 296 */
Kojto 99:dbbf35b96557 297 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 298 /* Alias word address of BRE bit */
Kojto 99:dbbf35b96557 299 #define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
Kojto 122:f9eeca106725 300 #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
Kojto 110:165afa46840b 301
Kojto 110:165afa46840b 302 #if defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 303 /* Alias word address of WUPP bit */
Kojto 110:165afa46840b 304 #define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP)
Kojto 122:f9eeca106725 305 #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
Kojto 110:165afa46840b 306 #endif /* STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 307 /**
Kojto 99:dbbf35b96557 308 * @}
Kojto 99:dbbf35b96557 309 */
Kojto 99:dbbf35b96557 310
Kojto 99:dbbf35b96557 311 /**
Kojto 99:dbbf35b96557 312 * @}
Kojto 99:dbbf35b96557 313 */
Kojto 99:dbbf35b96557 314
Kojto 99:dbbf35b96557 315 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 316 /** @defgroup PWREx_Private_Macros PWREx Private Macros
Kojto 99:dbbf35b96557 317 * @{
Kojto 99:dbbf35b96557 318 */
Kojto 99:dbbf35b96557 319
Kojto 99:dbbf35b96557 320 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
Kojto 99:dbbf35b96557 321 * @{
Kojto 99:dbbf35b96557 322 */
Kojto 110:165afa46840b 323 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 324 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 325 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
Kojto 99:dbbf35b96557 326 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
Kojto 110:165afa46840b 327 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 328
Kojto 106:ba1f97679dad 329 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 330 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 99:dbbf35b96557 331 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
Kojto 99:dbbf35b96557 332 #else
Kojto 99:dbbf35b96557 333 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 99:dbbf35b96557 334 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
Kojto 99:dbbf35b96557 335 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
Kojto 99:dbbf35b96557 336 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 99:dbbf35b96557 337
Kojto 110:165afa46840b 338 #if defined(STM32F446xx)
Kojto 110:165afa46840b 339 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
Kojto 122:f9eeca106725 340 #elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
Kojto 122:f9eeca106725 341 defined(STM32F412Rx) || defined(STM32F412Cx)
Kojto 110:165afa46840b 342 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 110:165afa46840b 343 ((PIN) == PWR_WAKEUP_PIN3))
Kojto 110:165afa46840b 344 #else
Kojto 110:165afa46840b 345 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
Kojto 110:165afa46840b 346 #endif /* STM32F446xx */
Kojto 99:dbbf35b96557 347 /**
Kojto 99:dbbf35b96557 348 * @}
Kojto 99:dbbf35b96557 349 */
Kojto 99:dbbf35b96557 350
Kojto 99:dbbf35b96557 351 /**
Kojto 99:dbbf35b96557 352 * @}
Kojto 99:dbbf35b96557 353 */
bogdanm 89:552587b429a1 354
bogdanm 89:552587b429a1 355 /**
bogdanm 89:552587b429a1 356 * @}
bogdanm 89:552587b429a1 357 */
bogdanm 89:552587b429a1 358
bogdanm 89:552587b429a1 359 /**
bogdanm 89:552587b429a1 360 * @}
bogdanm 89:552587b429a1 361 */
bogdanm 89:552587b429a1 362
bogdanm 89:552587b429a1 363 #ifdef __cplusplus
bogdanm 89:552587b429a1 364 }
bogdanm 89:552587b429a1 365 #endif
bogdanm 89:552587b429a1 366
bogdanm 89:552587b429a1 367
bogdanm 89:552587b429a1 368 #endif /* __STM32F4xx_HAL_PWR_EX_H */
bogdanm 89:552587b429a1 369
bogdanm 89:552587b429a1 370 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/