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TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 135:176b8275d35d

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f3xx_hal_tim.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
bogdanm	86:04dd9b1680ae	7	* @brief Header file of TIM HAL module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F3xx_HAL_TIM_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F3xx_HAL_TIM_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	47	#include "stm32f3xx_hal_def.h"
bogdanm	86:04dd9b1680ae	48
bogdanm	86:04dd9b1680ae	49	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	86:04dd9b1680ae	50	* @{
bogdanm	86:04dd9b1680ae	51	*/
bogdanm	86:04dd9b1680ae	52
bogdanm	86:04dd9b1680ae	53	/** @addtogroup TIM
bogdanm	86:04dd9b1680ae	54	* @{
bogdanm	86:04dd9b1680ae	55	*/
bogdanm	86:04dd9b1680ae	56
bogdanm	86:04dd9b1680ae	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58	/** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm	92:4fc01daae5a5	59	* @{
bogdanm	92:4fc01daae5a5	60	*/
bogdanm	86:04dd9b1680ae	61	/**
bogdanm	86:04dd9b1680ae	62	* @brief TIM Time base Configuration Structure definition
bogdanm	86:04dd9b1680ae	63	*/
bogdanm	86:04dd9b1680ae	64	typedef struct
bogdanm	86:04dd9b1680ae	65	{
bogdanm	86:04dd9b1680ae	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	135:176b8275d35d	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
bogdanm	86:04dd9b1680ae	68
bogdanm	86:04dd9b1680ae	69	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	86:04dd9b1680ae	70	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	86:04dd9b1680ae	71
bogdanm	86:04dd9b1680ae	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	86:04dd9b1680ae	73	Auto-Reload Register at the next update event.
bogdanm	86:04dd9b1680ae	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	86:04dd9b1680ae	75
bogdanm	86:04dd9b1680ae	76	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	86:04dd9b1680ae	77	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	86:04dd9b1680ae	78
bogdanm	86:04dd9b1680ae	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	86:04dd9b1680ae	80	reaches zero, an update event is generated and counting restarts
bogdanm	86:04dd9b1680ae	81	from the RCR value (N).
<>	135:176b8275d35d	82	This means in PWM mode that (N+1U) corresponds to:
bogdanm	86:04dd9b1680ae	83	- the number of PWM periods in edge-aligned mode
bogdanm	86:04dd9b1680ae	84	- the number of half PWM period in center-aligned mode
Kojto	122:f9eeca106725	85	GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Kojto	122:f9eeca106725	86	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<>	135:176b8275d35d	87
<>	135:176b8275d35d	88	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
<>	135:176b8275d35d	89	This parameter can be a value of @ref TIM_AutoReloadPreload */
bogdanm	86:04dd9b1680ae	90	} TIM_Base_InitTypeDef;
bogdanm	86:04dd9b1680ae	91
bogdanm	86:04dd9b1680ae	92	/**
bogdanm	86:04dd9b1680ae	93	* @brief TIM Output Compare Configuration Structure definition
bogdanm	86:04dd9b1680ae	94	*/
bogdanm	86:04dd9b1680ae	95	typedef struct
bogdanm	86:04dd9b1680ae	96	{
bogdanm	86:04dd9b1680ae	97	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	86:04dd9b1680ae	98	This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
bogdanm	86:04dd9b1680ae	99
bogdanm	86:04dd9b1680ae	100	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	135:176b8275d35d	101	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
bogdanm	86:04dd9b1680ae	102
bogdanm	86:04dd9b1680ae	103	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	86:04dd9b1680ae	104	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	86:04dd9b1680ae	105
bogdanm	86:04dd9b1680ae	106	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	86:04dd9b1680ae	107	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	86:04dd9b1680ae	108	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	86:04dd9b1680ae	109
bogdanm	86:04dd9b1680ae	110	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	86:04dd9b1680ae	111	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	86:04dd9b1680ae	112	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	86:04dd9b1680ae	113
bogdanm	86:04dd9b1680ae	114
bogdanm	86:04dd9b1680ae	115	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	86:04dd9b1680ae	116	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	86:04dd9b1680ae	117	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	86:04dd9b1680ae	118
bogdanm	86:04dd9b1680ae	119	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	86:04dd9b1680ae	120	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	86:04dd9b1680ae	121	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	86:04dd9b1680ae	122	} TIM_OC_InitTypeDef;
bogdanm	86:04dd9b1680ae	123
bogdanm	86:04dd9b1680ae	124	/**
bogdanm	86:04dd9b1680ae	125	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	86:04dd9b1680ae	126	*/
bogdanm	86:04dd9b1680ae	127	typedef struct
bogdanm	86:04dd9b1680ae	128	{
bogdanm	86:04dd9b1680ae	129	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	86:04dd9b1680ae	130	This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
bogdanm	86:04dd9b1680ae	131
bogdanm	86:04dd9b1680ae	132	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	135:176b8275d35d	133	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
bogdanm	86:04dd9b1680ae	134
bogdanm	86:04dd9b1680ae	135	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	86:04dd9b1680ae	136	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	86:04dd9b1680ae	137
bogdanm	86:04dd9b1680ae	138	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	86:04dd9b1680ae	139	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	86:04dd9b1680ae	140	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	86:04dd9b1680ae	141
bogdanm	86:04dd9b1680ae	142	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	86:04dd9b1680ae	143	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	86:04dd9b1680ae	144	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	86:04dd9b1680ae	145
bogdanm	86:04dd9b1680ae	146	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	86:04dd9b1680ae	147	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	86:04dd9b1680ae	148	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	86:04dd9b1680ae	149
bogdanm	86:04dd9b1680ae	150	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	86:04dd9b1680ae	151	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	86:04dd9b1680ae	152
bogdanm	86:04dd9b1680ae	153	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	86:04dd9b1680ae	154	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	86:04dd9b1680ae	155
bogdanm	86:04dd9b1680ae	156	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	135:176b8275d35d	157	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	158	} TIM_OnePulse_InitTypeDef;
bogdanm	86:04dd9b1680ae	159
bogdanm	86:04dd9b1680ae	160
bogdanm	86:04dd9b1680ae	161	/**
bogdanm	86:04dd9b1680ae	162	* @brief TIM Input Capture Configuration Structure definition
bogdanm	86:04dd9b1680ae	163	*/
bogdanm	86:04dd9b1680ae	164	typedef struct
bogdanm	86:04dd9b1680ae	165	{
bogdanm	86:04dd9b1680ae	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	86:04dd9b1680ae	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	86:04dd9b1680ae	168
bogdanm	86:04dd9b1680ae	169	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	86:04dd9b1680ae	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	86:04dd9b1680ae	171
bogdanm	86:04dd9b1680ae	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	86:04dd9b1680ae	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	86:04dd9b1680ae	174
bogdanm	86:04dd9b1680ae	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	135:176b8275d35d	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	177	} TIM_IC_InitTypeDef;
bogdanm	86:04dd9b1680ae	178
bogdanm	86:04dd9b1680ae	179	/**
bogdanm	86:04dd9b1680ae	180	* @brief TIM Encoder Configuration Structure definition
bogdanm	86:04dd9b1680ae	181	*/
bogdanm	86:04dd9b1680ae	182	typedef struct
bogdanm	86:04dd9b1680ae	183	{
bogdanm	86:04dd9b1680ae	184	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	86:04dd9b1680ae	185	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	86:04dd9b1680ae	186
bogdanm	86:04dd9b1680ae	187	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	86:04dd9b1680ae	188	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	86:04dd9b1680ae	189
bogdanm	86:04dd9b1680ae	190	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	86:04dd9b1680ae	191	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	86:04dd9b1680ae	192
bogdanm	86:04dd9b1680ae	193	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	86:04dd9b1680ae	194	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	86:04dd9b1680ae	195
bogdanm	86:04dd9b1680ae	196	uint32_t IC1Filter; /*!< Specifies the input capture filter.
<>	135:176b8275d35d	197	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	198
bogdanm	86:04dd9b1680ae	199	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	86:04dd9b1680ae	200	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	86:04dd9b1680ae	201
bogdanm	86:04dd9b1680ae	202	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	86:04dd9b1680ae	203	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	86:04dd9b1680ae	204
bogdanm	86:04dd9b1680ae	205	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	86:04dd9b1680ae	206	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	86:04dd9b1680ae	207
bogdanm	86:04dd9b1680ae	208	uint32_t IC2Filter; /*!< Specifies the input capture filter.
<>	135:176b8275d35d	209	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	210	} TIM_Encoder_InitTypeDef;
bogdanm	86:04dd9b1680ae	211
bogdanm	86:04dd9b1680ae	212
bogdanm	86:04dd9b1680ae	213	/**
Kojto	122:f9eeca106725	214	* @brief TIM Clock Configuration Handle Structure definition
bogdanm	86:04dd9b1680ae	215	*/
bogdanm	86:04dd9b1680ae	216	typedef struct
bogdanm	86:04dd9b1680ae	217	{
bogdanm	86:04dd9b1680ae	218	uint32_t ClockSource; /*!< TIM clock sources
bogdanm	86:04dd9b1680ae	219	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	86:04dd9b1680ae	220	uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm	86:04dd9b1680ae	221	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	86:04dd9b1680ae	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm	86:04dd9b1680ae	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	86:04dd9b1680ae	224	uint32_t ClockFilter; /*!< TIM clock filter
<>	135:176b8275d35d	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	226	}TIM_ClockConfigTypeDef;
bogdanm	86:04dd9b1680ae	227
bogdanm	86:04dd9b1680ae	228	/**
Kojto	122:f9eeca106725	229	* @brief TIM Clear Input Configuration Handle Structure definition
bogdanm	86:04dd9b1680ae	230	*/
bogdanm	86:04dd9b1680ae	231	typedef struct
bogdanm	86:04dd9b1680ae	232	{
bogdanm	86:04dd9b1680ae	233	uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm	86:04dd9b1680ae	234	This parameter can be ENABLE or DISABLE */
bogdanm	86:04dd9b1680ae	235	uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm	86:04dd9b1680ae	236	This parameter can be a value of @ref TIMEx_ClearInput_Source */
bogdanm	86:04dd9b1680ae	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm	86:04dd9b1680ae	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	86:04dd9b1680ae	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm	86:04dd9b1680ae	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	86:04dd9b1680ae	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
<>	135:176b8275d35d	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	243	}TIM_ClearInputConfigTypeDef;
bogdanm	86:04dd9b1680ae	244
bogdanm	86:04dd9b1680ae	245	/**
bogdanm	86:04dd9b1680ae	246	* @brief TIM Slave configuration Structure definition
bogdanm	86:04dd9b1680ae	247	*/
bogdanm	86:04dd9b1680ae	248	typedef struct {
bogdanm	86:04dd9b1680ae	249	uint32_t SlaveMode; /*!< Slave mode selection
bogdanm	86:04dd9b1680ae	250	This parameter can be a value of @ref TIMEx_Slave_Mode */
bogdanm	86:04dd9b1680ae	251	uint32_t InputTrigger; /*!< Input Trigger source
bogdanm	86:04dd9b1680ae	252	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	86:04dd9b1680ae	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm	86:04dd9b1680ae	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	86:04dd9b1680ae	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm	86:04dd9b1680ae	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	86:04dd9b1680ae	257	uint32_t TriggerFilter; /*!< Input trigger filter
<>	135:176b8275d35d	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
bogdanm	86:04dd9b1680ae	259
bogdanm	86:04dd9b1680ae	260	}TIM_SlaveConfigTypeDef;
bogdanm	86:04dd9b1680ae	261
bogdanm	86:04dd9b1680ae	262	/**
bogdanm	86:04dd9b1680ae	263	* @brief HAL State structures definition
bogdanm	86:04dd9b1680ae	264	*/
bogdanm	86:04dd9b1680ae	265	typedef enum
bogdanm	86:04dd9b1680ae	266	{
<>	135:176b8275d35d	267	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
<>	135:176b8275d35d	268	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
<>	135:176b8275d35d	269	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
<>	135:176b8275d35d	270	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
bogdanm	86:04dd9b1680ae	271	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	86:04dd9b1680ae	272	}HAL_TIM_StateTypeDef;
bogdanm	86:04dd9b1680ae	273
bogdanm	86:04dd9b1680ae	274	/**
bogdanm	86:04dd9b1680ae	275	* @brief HAL Active channel structures definition
bogdanm	86:04dd9b1680ae	276	*/
bogdanm	86:04dd9b1680ae	277	typedef enum
bogdanm	86:04dd9b1680ae	278	{
<>	135:176b8275d35d	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
<>	135:176b8275d35d	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
<>	135:176b8275d35d	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
<>	135:176b8275d35d	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
bogdanm	86:04dd9b1680ae	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	86:04dd9b1680ae	284	}HAL_TIM_ActiveChannel;
bogdanm	86:04dd9b1680ae	285
bogdanm	86:04dd9b1680ae	286	/**
bogdanm	86:04dd9b1680ae	287	* @brief TIM Time Base Handle Structure definition
bogdanm	86:04dd9b1680ae	288	*/
bogdanm	86:04dd9b1680ae	289	typedef struct
bogdanm	86:04dd9b1680ae	290	{
bogdanm	86:04dd9b1680ae	291	TIM_TypeDef Instance; /!< Register base address */
bogdanm	86:04dd9b1680ae	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	86:04dd9b1680ae	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	86:04dd9b1680ae	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
Kojto	122:f9eeca106725	295	This array is accessed by a @ref TIM_DMA_Handle_index */
bogdanm	86:04dd9b1680ae	296	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	86:04dd9b1680ae	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	86:04dd9b1680ae	298	}TIM_HandleTypeDef;
bogdanm	86:04dd9b1680ae	299
bogdanm	92:4fc01daae5a5	300	/**
bogdanm	92:4fc01daae5a5	301	* @}
bogdanm	92:4fc01daae5a5	302	*/
Kojto	122:f9eeca106725	303	/* End of exported types -----------------------------------------------------*/
bogdanm	92:4fc01daae5a5	304
bogdanm	86:04dd9b1680ae	305	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	306	/** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm	86:04dd9b1680ae	307	* @{
bogdanm	86:04dd9b1680ae	308	*/
bogdanm	86:04dd9b1680ae	309
Kojto	122:f9eeca106725	310	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
bogdanm	86:04dd9b1680ae	311	* @{
bogdanm	86:04dd9b1680ae	312	*/
<>	135:176b8275d35d	313	#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /!< Polarity for TIx source /
bogdanm	86:04dd9b1680ae	314	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	86:04dd9b1680ae	315	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	86:04dd9b1680ae	316	/**
bogdanm	86:04dd9b1680ae	317	* @}
bogdanm	86:04dd9b1680ae	318	*/
bogdanm	86:04dd9b1680ae	319
bogdanm	92:4fc01daae5a5	320	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm	86:04dd9b1680ae	321	* @{
bogdanm	86:04dd9b1680ae	322	*/
bogdanm	86:04dd9b1680ae	323	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
<>	135:176b8275d35d	324	#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /!< Polarity for ETR source /
bogdanm	86:04dd9b1680ae	325	/**
bogdanm	86:04dd9b1680ae	326	* @}
bogdanm	86:04dd9b1680ae	327	*/
bogdanm	86:04dd9b1680ae	328
bogdanm	92:4fc01daae5a5	329	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm	86:04dd9b1680ae	330	* @{
bogdanm	86:04dd9b1680ae	331	*/
<>	135:176b8275d35d	332	#define TIM_ETRPRESCALER_DIV1 (0x0000U) /!< No prescaler is used /
<>	135:176b8275d35d	333	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2U /
<>	135:176b8275d35d	334	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4U /
<>	135:176b8275d35d	335	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8U /
bogdanm	86:04dd9b1680ae	336	/**
bogdanm	86:04dd9b1680ae	337	* @}
bogdanm	86:04dd9b1680ae	338	*/
bogdanm	86:04dd9b1680ae	339
bogdanm	92:4fc01daae5a5	340	/** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm	86:04dd9b1680ae	341	* @{
bogdanm	86:04dd9b1680ae	342	*/
<>	135:176b8275d35d	343	#define TIM_COUNTERMODE_UP (0x0000U)
bogdanm	86:04dd9b1680ae	344	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	86:04dd9b1680ae	345	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	86:04dd9b1680ae	346	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	86:04dd9b1680ae	347	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	86:04dd9b1680ae	348	/**
bogdanm	86:04dd9b1680ae	349	* @}
bogdanm	86:04dd9b1680ae	350	*/
bogdanm	86:04dd9b1680ae	351
bogdanm	92:4fc01daae5a5	352	/** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm	86:04dd9b1680ae	353	* @{
bogdanm	86:04dd9b1680ae	354	*/
<>	135:176b8275d35d	355	#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
bogdanm	86:04dd9b1680ae	356	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	86:04dd9b1680ae	357	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	86:04dd9b1680ae	358	/**
bogdanm	86:04dd9b1680ae	359	* @}
bogdanm	86:04dd9b1680ae	360	*/
bogdanm	86:04dd9b1680ae	361
<>	135:176b8275d35d	362	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
<>	135:176b8275d35d	363	* @{
<>	135:176b8275d35d	364	*/
<>	135:176b8275d35d	365	#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /!< TIMx_ARR register is not buffered /
<>	135:176b8275d35d	366	#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /!< TIMx_ARR register is buffered /
<>	135:176b8275d35d	367
<>	135:176b8275d35d	368	/**
<>	135:176b8275d35d	369	* @}
<>	135:176b8275d35d	370	*/
<>	135:176b8275d35d	371
bogdanm	92:4fc01daae5a5	372	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm	86:04dd9b1680ae	373	* @{
bogdanm	86:04dd9b1680ae	374	*/
<>	135:176b8275d35d	375	#define TIM_OCFAST_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	376	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	86:04dd9b1680ae	377	/**
bogdanm	86:04dd9b1680ae	378	* @}
bogdanm	86:04dd9b1680ae	379	*/
bogdanm	86:04dd9b1680ae	380
bogdanm	92:4fc01daae5a5	381	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm	86:04dd9b1680ae	382	* @{
bogdanm	86:04dd9b1680ae	383	*/
<>	135:176b8275d35d	384	#define TIM_OCPOLARITY_HIGH (0x0000U)
bogdanm	86:04dd9b1680ae	385	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	86:04dd9b1680ae	386	/**
bogdanm	86:04dd9b1680ae	387	* @}
bogdanm	86:04dd9b1680ae	388	*/
bogdanm	86:04dd9b1680ae	389
bogdanm	92:4fc01daae5a5	390	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm	86:04dd9b1680ae	391	* @{
bogdanm	86:04dd9b1680ae	392	*/
<>	135:176b8275d35d	393	#define TIM_OCNPOLARITY_HIGH (0x0000U)
bogdanm	86:04dd9b1680ae	394	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm	86:04dd9b1680ae	395	/**
bogdanm	86:04dd9b1680ae	396	* @}
bogdanm	86:04dd9b1680ae	397	*/
bogdanm	86:04dd9b1680ae	398
bogdanm	92:4fc01daae5a5	399	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm	86:04dd9b1680ae	400	* @{
bogdanm	86:04dd9b1680ae	401	*/
bogdanm	86:04dd9b1680ae	402	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
<>	135:176b8275d35d	403	#define TIM_OCIDLESTATE_RESET (0x0000U)
bogdanm	86:04dd9b1680ae	404	/**
bogdanm	86:04dd9b1680ae	405	* @}
bogdanm	86:04dd9b1680ae	406	*/
bogdanm	86:04dd9b1680ae	407
bogdanm	92:4fc01daae5a5	408	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm	86:04dd9b1680ae	409	* @{
bogdanm	86:04dd9b1680ae	410	*/
bogdanm	86:04dd9b1680ae	411	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
<>	135:176b8275d35d	412	#define TIM_OCNIDLESTATE_RESET (0x0000U)
bogdanm	86:04dd9b1680ae	413	/**
bogdanm	86:04dd9b1680ae	414	* @}
bogdanm	86:04dd9b1680ae	415	*/
bogdanm	86:04dd9b1680ae	416
bogdanm	92:4fc01daae5a5	417	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm	86:04dd9b1680ae	418	* @{
bogdanm	86:04dd9b1680ae	419	*/
bogdanm	86:04dd9b1680ae	420	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	86:04dd9b1680ae	421	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	86:04dd9b1680ae	422	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	86:04dd9b1680ae	423	/**
bogdanm	86:04dd9b1680ae	424	* @}
bogdanm	86:04dd9b1680ae	425	*/
bogdanm	86:04dd9b1680ae	426
bogdanm	92:4fc01daae5a5	427	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm	86:04dd9b1680ae	428	* @{
bogdanm	86:04dd9b1680ae	429	*/
<>	135:176b8275d35d	430	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
bogdanm	86:04dd9b1680ae	431	connected to IC1, IC2, IC3 or IC4, respectively */
<>	135:176b8275d35d	432	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
bogdanm	86:04dd9b1680ae	433	connected to IC2, IC1, IC4 or IC3, respectively */
<>	135:176b8275d35d	434	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC /
bogdanm	86:04dd9b1680ae	435	/**
bogdanm	86:04dd9b1680ae	436	* @}
bogdanm	86:04dd9b1680ae	437	*/
bogdanm	86:04dd9b1680ae	438
bogdanm	92:4fc01daae5a5	439	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm	86:04dd9b1680ae	440	* @{
bogdanm	86:04dd9b1680ae	441	*/
<>	135:176b8275d35d	442	#define TIM_ICPSC_DIV1 (0x0000U) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	86:04dd9b1680ae	443	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	86:04dd9b1680ae	444	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	86:04dd9b1680ae	445	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	86:04dd9b1680ae	446	/**
bogdanm	86:04dd9b1680ae	447	* @}
bogdanm	86:04dd9b1680ae	448	*/
bogdanm	86:04dd9b1680ae	449
bogdanm	92:4fc01daae5a5	450	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm	86:04dd9b1680ae	451	* @{
bogdanm	86:04dd9b1680ae	452	*/
bogdanm	86:04dd9b1680ae	453	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
<>	135:176b8275d35d	454	#define TIM_OPMODE_REPETITIVE (0x0000U)
bogdanm	86:04dd9b1680ae	455	/**
bogdanm	86:04dd9b1680ae	456	* @}
bogdanm	86:04dd9b1680ae	457	*/
Kojto	122:f9eeca106725	458
bogdanm	92:4fc01daae5a5	459	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm	86:04dd9b1680ae	460	* @{
bogdanm	86:04dd9b1680ae	461	*/
bogdanm	86:04dd9b1680ae	462	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	86:04dd9b1680ae	463	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	86:04dd9b1680ae	464	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	86:04dd9b1680ae	465	/**
bogdanm	86:04dd9b1680ae	466	* @}
bogdanm	86:04dd9b1680ae	467	*/
Kojto	122:f9eeca106725	468
Kojto	122:f9eeca106725	469	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
bogdanm	86:04dd9b1680ae	470	* @{
bogdanm	86:04dd9b1680ae	471	*/
bogdanm	86:04dd9b1680ae	472	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	86:04dd9b1680ae	473	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	86:04dd9b1680ae	474	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	86:04dd9b1680ae	475	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	86:04dd9b1680ae	476	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	86:04dd9b1680ae	477	#define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm	86:04dd9b1680ae	478	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	86:04dd9b1680ae	479	#define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm	86:04dd9b1680ae	480	/**
bogdanm	86:04dd9b1680ae	481	* @}
bogdanm	86:04dd9b1680ae	482	*/
Kojto	122:f9eeca106725	483
Kojto	122:f9eeca106725	484	/** @defgroup TIM_Commutation_Source TIM Commutation Source
Kojto	122:f9eeca106725	485	* @{
Kojto	122:f9eeca106725	486	*/
bogdanm	86:04dd9b1680ae	487	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
<>	135:176b8275d35d	488	#define TIM_COMMUTATION_SOFTWARE (0x0000U)
bogdanm	86:04dd9b1680ae	489
Kojto	122:f9eeca106725	490	/**
Kojto	122:f9eeca106725	491	* @}
Kojto	122:f9eeca106725	492	*/
Kojto	122:f9eeca106725	493
bogdanm	92:4fc01daae5a5	494	/** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm	86:04dd9b1680ae	495	* @{
bogdanm	86:04dd9b1680ae	496	*/
bogdanm	86:04dd9b1680ae	497	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	86:04dd9b1680ae	498	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	86:04dd9b1680ae	499	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	86:04dd9b1680ae	500	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	86:04dd9b1680ae	501	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	86:04dd9b1680ae	502	#define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm	86:04dd9b1680ae	503	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	86:04dd9b1680ae	504	/**
bogdanm	86:04dd9b1680ae	505	* @}
Kojto	122:f9eeca106725	506	*/
bogdanm	86:04dd9b1680ae	507
bogdanm	92:4fc01daae5a5	508	/** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm	86:04dd9b1680ae	509	* @{
bogdanm	86:04dd9b1680ae	510	*/
bogdanm	86:04dd9b1680ae	511	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	86:04dd9b1680ae	512	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	86:04dd9b1680ae	513	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	86:04dd9b1680ae	514	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	86:04dd9b1680ae	515	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	86:04dd9b1680ae	516	#define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm	86:04dd9b1680ae	517	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	86:04dd9b1680ae	518	#define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm	86:04dd9b1680ae	519	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	86:04dd9b1680ae	520	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	86:04dd9b1680ae	521	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	86:04dd9b1680ae	522	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	86:04dd9b1680ae	523	/**
bogdanm	86:04dd9b1680ae	524	* @}
bogdanm	86:04dd9b1680ae	525	*/
bogdanm	86:04dd9b1680ae	526
bogdanm	92:4fc01daae5a5	527	/** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm	86:04dd9b1680ae	528	* @{
bogdanm	86:04dd9b1680ae	529	*/
Kojto	122:f9eeca106725	530	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
Kojto	122:f9eeca106725	531	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<>	135:176b8275d35d	532	#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
Kojto	122:f9eeca106725	533	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
Kojto	122:f9eeca106725	534	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
Kojto	122:f9eeca106725	535	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
Kojto	122:f9eeca106725	536	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
Kojto	122:f9eeca106725	537	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
Kojto	122:f9eeca106725	538	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
Kojto	122:f9eeca106725	539	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	86:04dd9b1680ae	540	/**
bogdanm	86:04dd9b1680ae	541	* @}
bogdanm	86:04dd9b1680ae	542	*/
bogdanm	86:04dd9b1680ae	543
bogdanm	92:4fc01daae5a5	544	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm	86:04dd9b1680ae	545	* @{
bogdanm	86:04dd9b1680ae	546	*/
bogdanm	86:04dd9b1680ae	547	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	86:04dd9b1680ae	548	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	86:04dd9b1680ae	549	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	86:04dd9b1680ae	550	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	86:04dd9b1680ae	551	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	86:04dd9b1680ae	552	/**
bogdanm	86:04dd9b1680ae	553	* @}
bogdanm	86:04dd9b1680ae	554	*/
Kojto	122:f9eeca106725	555
bogdanm	92:4fc01daae5a5	556	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm	86:04dd9b1680ae	557	* @{
bogdanm	86:04dd9b1680ae	558	*/
bogdanm	86:04dd9b1680ae	559	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	86:04dd9b1680ae	560	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	86:04dd9b1680ae	561	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	86:04dd9b1680ae	562	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	86:04dd9b1680ae	563	/**
bogdanm	86:04dd9b1680ae	564	* @}
bogdanm	86:04dd9b1680ae	565	*/
bogdanm	86:04dd9b1680ae	566
bogdanm	92:4fc01daae5a5	567	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm	86:04dd9b1680ae	568	* @{
bogdanm	86:04dd9b1680ae	569	*/
bogdanm	86:04dd9b1680ae	570	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	86:04dd9b1680ae	571	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	86:04dd9b1680ae	572	/**
bogdanm	86:04dd9b1680ae	573	* @}
bogdanm	86:04dd9b1680ae	574	*/
bogdanm	86:04dd9b1680ae	575
bogdanm	92:4fc01daae5a5	576	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm	86:04dd9b1680ae	577	* @{
bogdanm	86:04dd9b1680ae	578	*/
bogdanm	86:04dd9b1680ae	579	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	86:04dd9b1680ae	580	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	86:04dd9b1680ae	581	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	86:04dd9b1680ae	582	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	86:04dd9b1680ae	583	/**
bogdanm	86:04dd9b1680ae	584	* @}
bogdanm	86:04dd9b1680ae	585	*/
bogdanm	86:04dd9b1680ae	586
Kojto	122:f9eeca106725	587	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
bogdanm	86:04dd9b1680ae	588	* @{
bogdanm	86:04dd9b1680ae	589	*/
Kojto	122:f9eeca106725	590	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
<>	135:176b8275d35d	591	#define TIM_OSSR_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	592	/**
bogdanm	86:04dd9b1680ae	593	* @}
bogdanm	86:04dd9b1680ae	594	*/
bogdanm	86:04dd9b1680ae	595
Kojto	122:f9eeca106725	596	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
bogdanm	86:04dd9b1680ae	597	* @{
bogdanm	86:04dd9b1680ae	598	*/
Kojto	122:f9eeca106725	599	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
<>	135:176b8275d35d	600	#define TIM_OSSI_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	601	/**
bogdanm	86:04dd9b1680ae	602	* @}
bogdanm	86:04dd9b1680ae	603	*/
Kojto	122:f9eeca106725	604
Kojto	122:f9eeca106725	605	/** @defgroup TIM_Lock_level TIM Lock level
bogdanm	86:04dd9b1680ae	606	* @{
bogdanm	86:04dd9b1680ae	607	*/
<>	135:176b8275d35d	608	#define TIM_LOCKLEVEL_OFF (0x0000U)
bogdanm	86:04dd9b1680ae	609	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm	86:04dd9b1680ae	610	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm	86:04dd9b1680ae	611	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm	86:04dd9b1680ae	612	/**
bogdanm	86:04dd9b1680ae	613	* @}
bogdanm	86:04dd9b1680ae	614	*/
Kojto	122:f9eeca106725	615
Kojto	122:f9eeca106725	616	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
bogdanm	86:04dd9b1680ae	617	* @{
bogdanm	86:04dd9b1680ae	618	*/
bogdanm	86:04dd9b1680ae	619	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
<>	135:176b8275d35d	620	#define TIM_BREAK_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	621	/**
bogdanm	86:04dd9b1680ae	622	* @}
bogdanm	86:04dd9b1680ae	623	*/
Kojto	122:f9eeca106725	624
bogdanm	92:4fc01daae5a5	625	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm	86:04dd9b1680ae	626	* @{
bogdanm	86:04dd9b1680ae	627	*/
<>	135:176b8275d35d	628	#define TIM_BREAKPOLARITY_LOW (0x0000U)
bogdanm	86:04dd9b1680ae	629	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm	86:04dd9b1680ae	630	/**
bogdanm	86:04dd9b1680ae	631	* @}
bogdanm	86:04dd9b1680ae	632	*/
bogdanm	92:4fc01daae5a5	633	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm	86:04dd9b1680ae	634	* @{
bogdanm	86:04dd9b1680ae	635	*/
bogdanm	86:04dd9b1680ae	636	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
<>	135:176b8275d35d	637	#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	638	/**
bogdanm	86:04dd9b1680ae	639	* @}
bogdanm	86:04dd9b1680ae	640	*/
bogdanm	86:04dd9b1680ae	641
bogdanm	92:4fc01daae5a5	642	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm	86:04dd9b1680ae	643	* @{
bogdanm	86:04dd9b1680ae	644	*/
<>	135:176b8275d35d	645	#define TIM_TRGO_RESET (0x0000U)
Kojto	122:f9eeca106725	646	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
Kojto	122:f9eeca106725	647	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
Kojto	122:f9eeca106725	648	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
Kojto	122:f9eeca106725	649	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
Kojto	122:f9eeca106725	650	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
Kojto	122:f9eeca106725	651	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
Kojto	122:f9eeca106725	652	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	86:04dd9b1680ae	653	/**
bogdanm	86:04dd9b1680ae	654	* @}
Kojto	122:f9eeca106725	655	*/
Kojto	122:f9eeca106725	656
Kojto	122:f9eeca106725	657	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
bogdanm	86:04dd9b1680ae	658	* @{
bogdanm	86:04dd9b1680ae	659	*/
<>	135:176b8275d35d	660	#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
<>	135:176b8275d35d	661	#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	662	/**
bogdanm	86:04dd9b1680ae	663	* @}
bogdanm	86:04dd9b1680ae	664	*/
Kojto	122:f9eeca106725	665
bogdanm	92:4fc01daae5a5	666	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm	86:04dd9b1680ae	667	* @{
bogdanm	86:04dd9b1680ae	668	*/
<>	135:176b8275d35d	669	#define TIM_TS_ITR0 (0x0000U)
<>	135:176b8275d35d	670	#define TIM_TS_ITR1 (0x0010U)
<>	135:176b8275d35d	671	#define TIM_TS_ITR2 (0x0020U)
<>	135:176b8275d35d	672	#define TIM_TS_ITR3 (0x0030U)
<>	135:176b8275d35d	673	#define TIM_TS_TI1F_ED (0x0040U)
<>	135:176b8275d35d	674	#define TIM_TS_TI1FP1 (0x0050U)
<>	135:176b8275d35d	675	#define TIM_TS_TI2FP2 (0x0060U)
<>	135:176b8275d35d	676	#define TIM_TS_ETRF (0x0070U)
<>	135:176b8275d35d	677	#define TIM_TS_NONE (0xFFFFU)
bogdanm	86:04dd9b1680ae	678	/**
bogdanm	86:04dd9b1680ae	679	* @}
bogdanm	86:04dd9b1680ae	680	*/
bogdanm	86:04dd9b1680ae	681
bogdanm	92:4fc01daae5a5	682	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm	86:04dd9b1680ae	683	* @{
bogdanm	86:04dd9b1680ae	684	*/
bogdanm	86:04dd9b1680ae	685	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	86:04dd9b1680ae	686	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	86:04dd9b1680ae	687	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	86:04dd9b1680ae	688	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	86:04dd9b1680ae	689	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	86:04dd9b1680ae	690	/**
bogdanm	86:04dd9b1680ae	691	* @}
bogdanm	86:04dd9b1680ae	692	*/
bogdanm	86:04dd9b1680ae	693
bogdanm	92:4fc01daae5a5	694	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm	86:04dd9b1680ae	695	* @{
bogdanm	86:04dd9b1680ae	696	*/
bogdanm	86:04dd9b1680ae	697	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	86:04dd9b1680ae	698	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	86:04dd9b1680ae	699	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	86:04dd9b1680ae	700	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	86:04dd9b1680ae	701	/**
bogdanm	86:04dd9b1680ae	702	* @}
bogdanm	86:04dd9b1680ae	703	*/
bogdanm	86:04dd9b1680ae	704
bogdanm	92:4fc01daae5a5	705	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm	86:04dd9b1680ae	706	* @{
bogdanm	86:04dd9b1680ae	707	*/
<>	135:176b8275d35d	708	#define TIM_TI1SELECTION_CH1 (0x0000U)
bogdanm	86:04dd9b1680ae	709	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	86:04dd9b1680ae	710	/**
bogdanm	86:04dd9b1680ae	711	* @}
bogdanm	86:04dd9b1680ae	712	*/
bogdanm	86:04dd9b1680ae	713
bogdanm	92:4fc01daae5a5	714	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm	86:04dd9b1680ae	715	* @{
bogdanm	86:04dd9b1680ae	716	*/
<>	135:176b8275d35d	717	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
<>	135:176b8275d35d	718	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
<>	135:176b8275d35d	719	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
<>	135:176b8275d35d	720	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
<>	135:176b8275d35d	721	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
<>	135:176b8275d35d	722	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
<>	135:176b8275d35d	723	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
<>	135:176b8275d35d	724	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
<>	135:176b8275d35d	725	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
<>	135:176b8275d35d	726	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
<>	135:176b8275d35d	727	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
<>	135:176b8275d35d	728	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
<>	135:176b8275d35d	729	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
<>	135:176b8275d35d	730	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
<>	135:176b8275d35d	731	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
<>	135:176b8275d35d	732	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
<>	135:176b8275d35d	733	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
<>	135:176b8275d35d	734	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
bogdanm	86:04dd9b1680ae	735	/**
bogdanm	86:04dd9b1680ae	736	* @}
bogdanm	86:04dd9b1680ae	737	*/
bogdanm	86:04dd9b1680ae	738
Kojto	122:f9eeca106725	739	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
bogdanm	86:04dd9b1680ae	740	* @{
bogdanm	86:04dd9b1680ae	741	*/
<>	135:176b8275d35d	742	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /!< Index of the DMA handle used for Update DMA requests /
<>	135:176b8275d35d	743	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
<>	135:176b8275d35d	744	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
<>	135:176b8275d35d	745	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
<>	135:176b8275d35d	746	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
<>	135:176b8275d35d	747	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /!< Index of the DMA handle used for Commutation DMA requests /
<>	135:176b8275d35d	748	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	86:04dd9b1680ae	749	/**
bogdanm	86:04dd9b1680ae	750	* @}
bogdanm	86:04dd9b1680ae	751	*/
bogdanm	86:04dd9b1680ae	752
Kojto	122:f9eeca106725	753	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
bogdanm	86:04dd9b1680ae	754	* @{
bogdanm	86:04dd9b1680ae	755	*/
<>	135:176b8275d35d	756	#define TIM_CCx_ENABLE (0x0001U)
<>	135:176b8275d35d	757	#define TIM_CCx_DISABLE (0x0000U)
<>	135:176b8275d35d	758	#define TIM_CCxN_ENABLE (0x0004U)
<>	135:176b8275d35d	759	#define TIM_CCxN_DISABLE (0x0000U)
bogdanm	86:04dd9b1680ae	760	/**
bogdanm	86:04dd9b1680ae	761	* @}
Kojto	122:f9eeca106725	762	*/
bogdanm	86:04dd9b1680ae	763
bogdanm	86:04dd9b1680ae	764	/**
bogdanm	86:04dd9b1680ae	765	* @}
Kojto	122:f9eeca106725	766	*/
Kojto	122:f9eeca106725	767	/* End of exported constants -------------------------------------------------*/
Kojto	122:f9eeca106725	768
bogdanm	86:04dd9b1680ae	769	/* Exported macros -----------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	770	/** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm	86:04dd9b1680ae	771	* @{
bogdanm	86:04dd9b1680ae	772	*/
bogdanm	86:04dd9b1680ae	773
bogdanm	86:04dd9b1680ae	774	/** @brief Reset TIM handle state
bogdanm	86:04dd9b1680ae	775	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	776	* @retval None
bogdanm	86:04dd9b1680ae	777	*/
bogdanm	86:04dd9b1680ae	778	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	86:04dd9b1680ae	779
bogdanm	86:04dd9b1680ae	780	/**
bogdanm	86:04dd9b1680ae	781	* @brief Enable the TIM peripheral.
bogdanm	86:04dd9b1680ae	782	* @param __HANDLE__: TIM handle
bogdanm	86:04dd9b1680ae	783	* @retval None
bogdanm	86:04dd9b1680ae	784	*/
bogdanm	86:04dd9b1680ae	785	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	86:04dd9b1680ae	786
bogdanm	86:04dd9b1680ae	787	/**
bogdanm	86:04dd9b1680ae	788	* @brief Enable the TIM main Output.
bogdanm	86:04dd9b1680ae	789	* @param __HANDLE__: TIM handle
bogdanm	86:04dd9b1680ae	790	* @retval None
bogdanm	86:04dd9b1680ae	791	*/
bogdanm	86:04dd9b1680ae	792	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
bogdanm	86:04dd9b1680ae	793
bogdanm	86:04dd9b1680ae	794	/**
bogdanm	86:04dd9b1680ae	795	* @brief Disable the TIM peripheral.
bogdanm	86:04dd9b1680ae	796	* @param __HANDLE__: TIM handle
bogdanm	86:04dd9b1680ae	797	* @retval None
bogdanm	86:04dd9b1680ae	798	*/
bogdanm	86:04dd9b1680ae	799	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	86:04dd9b1680ae	800	do { \
<>	135:176b8275d35d	801	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
bogdanm	86:04dd9b1680ae	802	{ \
<>	135:176b8275d35d	803	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
bogdanm	86:04dd9b1680ae	804	{ \
bogdanm	86:04dd9b1680ae	805	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	86:04dd9b1680ae	806	} \
bogdanm	86:04dd9b1680ae	807	} \
<>	135:176b8275d35d	808	} while(0U)
bogdanm	86:04dd9b1680ae	809	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
bogdanm	86:04dd9b1680ae	810	channels have been disabled */
bogdanm	86:04dd9b1680ae	811	/**
bogdanm	86:04dd9b1680ae	812	* @brief Disable the TIM main Output.
bogdanm	86:04dd9b1680ae	813	* @param __HANDLE__: TIM handle
bogdanm	86:04dd9b1680ae	814	* @retval None
Kojto	122:f9eeca106725	815	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
bogdanm	86:04dd9b1680ae	816	*/
bogdanm	86:04dd9b1680ae	817	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm	86:04dd9b1680ae	818	do { \
<>	135:176b8275d35d	819	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
bogdanm	86:04dd9b1680ae	820	{ \
<>	135:176b8275d35d	821	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
bogdanm	86:04dd9b1680ae	822	{ \
bogdanm	86:04dd9b1680ae	823	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm	86:04dd9b1680ae	824	} \
bogdanm	86:04dd9b1680ae	825	} \
<>	135:176b8275d35d	826	} while(0U)
<>	135:176b8275d35d	827
<>	135:176b8275d35d	828	/* The Main Output Enable of a timer instance is disabled unconditionally */
<>	135:176b8275d35d	829	/**
<>	135:176b8275d35d	830	* @brief Disable the TIM main Output.
<>	135:176b8275d35d	831	* @param __HANDLE__: TIM handle
<>	135:176b8275d35d	832	* @retval None
<>	135:176b8275d35d	833	* @note The Main Output Enable of a timer instance is disabled uncondiotionally
<>	135:176b8275d35d	834	*/
<>	135:176b8275d35d	835	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
bogdanm	86:04dd9b1680ae	836
Kojto	122:f9eeca106725	837	/**
Kojto	122:f9eeca106725	838	* @brief Enables the specified TIM interrupt.
Kojto	122:f9eeca106725	839	* @param __HANDLE__: specifies the TIM Handle.
Kojto	122:f9eeca106725	840	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
Kojto	122:f9eeca106725	841	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	842	* @arg TIM_IT_UPDATE: Update interrupt
Kojto	122:f9eeca106725	843	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
Kojto	122:f9eeca106725	844	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
Kojto	122:f9eeca106725	845	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
Kojto	122:f9eeca106725	846	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
Kojto	122:f9eeca106725	847	* @arg TIM_IT_COM: Commutation interrupt
Kojto	122:f9eeca106725	848	* @arg TIM_IT_TRIGGER: Trigger interrupt
Kojto	122:f9eeca106725	849	* @arg TIM_IT_BREAK: Break interrupt
Kojto	122:f9eeca106725	850	* @retval None
Kojto	122:f9eeca106725	851	*/
bogdanm	86:04dd9b1680ae	852	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
Kojto	122:f9eeca106725	853
Kojto	122:f9eeca106725	854	/**
Kojto	122:f9eeca106725	855	* @brief Disables the specified TIM interrupt.
Kojto	122:f9eeca106725	856	* @param __HANDLE__: specifies the TIM Handle.
Kojto	122:f9eeca106725	857	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
Kojto	122:f9eeca106725	858	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	859	* @arg TIM_IT_UPDATE: Update interrupt
Kojto	122:f9eeca106725	860	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
Kojto	122:f9eeca106725	861	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
Kojto	122:f9eeca106725	862	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
Kojto	122:f9eeca106725	863	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
Kojto	122:f9eeca106725	864	* @arg TIM_IT_COM: Commutation interrupt
Kojto	122:f9eeca106725	865	* @arg TIM_IT_TRIGGER: Trigger interrupt
Kojto	122:f9eeca106725	866	* @arg TIM_IT_BREAK: Break interrupt
Kojto	122:f9eeca106725	867	* @retval None
Kojto	122:f9eeca106725	868	*/
bogdanm	86:04dd9b1680ae	869	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Kojto	122:f9eeca106725	870
Kojto	122:f9eeca106725	871	/**
Kojto	122:f9eeca106725	872	* @brief Enables the specified DMA request.
Kojto	122:f9eeca106725	873	* @param __HANDLE__: specifies the TIM Handle.
Kojto	122:f9eeca106725	874	* @param __DMA__: specifies the TIM DMA request to enable.
Kojto	122:f9eeca106725	875	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	876	* @arg TIM_DMA_UPDATE: Update DMA request
Kojto	122:f9eeca106725	877	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
Kojto	122:f9eeca106725	878	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
Kojto	122:f9eeca106725	879	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
Kojto	122:f9eeca106725	880	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
Kojto	122:f9eeca106725	881	* @arg TIM_DMA_COM: Commutation DMA request
Kojto	122:f9eeca106725	882	* @arg TIM_DMA_TRIGGER: Trigger DMA request
Kojto	122:f9eeca106725	883	* @retval None
Kojto	122:f9eeca106725	884	*/
Kojto	122:f9eeca106725	885	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
Kojto	122:f9eeca106725	886
Kojto	122:f9eeca106725	887	/**
Kojto	122:f9eeca106725	888	* @brief Disables the specified DMA request.
Kojto	122:f9eeca106725	889	* @param __HANDLE__: specifies the TIM Handle.
Kojto	122:f9eeca106725	890	* @param __DMA__: specifies the TIM DMA request to disable.
Kojto	122:f9eeca106725	891	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	892	* @arg TIM_DMA_UPDATE: Update DMA request
Kojto	122:f9eeca106725	893	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
Kojto	122:f9eeca106725	894	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
Kojto	122:f9eeca106725	895	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
Kojto	122:f9eeca106725	896	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
Kojto	122:f9eeca106725	897	* @arg TIM_DMA_COM: Commutation DMA request
Kojto	122:f9eeca106725	898	* @arg TIM_DMA_TRIGGER: Trigger DMA request
Kojto	122:f9eeca106725	899	* @retval None
Kojto	122:f9eeca106725	900	*/
bogdanm	86:04dd9b1680ae	901	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Kojto	122:f9eeca106725	902
Kojto	122:f9eeca106725	903	/**
Kojto	122:f9eeca106725	904	* @brief Checks whether the specified TIM interrupt flag is set or not.
Kojto	122:f9eeca106725	905	* @param __HANDLE__: specifies the TIM Handle.
Kojto	122:f9eeca106725	906	* @param __FLAG__: specifies the TIM interrupt flag to check.
Kojto	122:f9eeca106725	907	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	908	* @arg TIM_FLAG_UPDATE: Update interrupt flag
Kojto	122:f9eeca106725	909	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
Kojto	122:f9eeca106725	910	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
Kojto	122:f9eeca106725	911	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
Kojto	122:f9eeca106725	912	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
Kojto	122:f9eeca106725	913	* @arg TIM_FLAG_COM: Commutation interrupt flag
Kojto	122:f9eeca106725	914	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
Kojto	122:f9eeca106725	915	* @arg TIM_FLAG_BREAK: Break interrupt flag
Kojto	122:f9eeca106725	916	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
Kojto	122:f9eeca106725	917	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
Kojto	122:f9eeca106725	918	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
Kojto	122:f9eeca106725	919	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Kojto	122:f9eeca106725	920	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	122:f9eeca106725	921	*/
bogdanm	86:04dd9b1680ae	922	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Kojto	122:f9eeca106725	923
Kojto	122:f9eeca106725	924	/**
Kojto	122:f9eeca106725	925	* @brief Clears the specified TIM interrupt flag.
Kojto	122:f9eeca106725	926	* @param __HANDLE__: specifies the TIM Handle.
Kojto	122:f9eeca106725	927	* @param __FLAG__: specifies the TIM interrupt flag to clear.
Kojto	122:f9eeca106725	928	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	929	* @arg TIM_FLAG_UPDATE: Update interrupt flag
Kojto	122:f9eeca106725	930	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
Kojto	122:f9eeca106725	931	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
Kojto	122:f9eeca106725	932	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
Kojto	122:f9eeca106725	933	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
Kojto	122:f9eeca106725	934	* @arg TIM_FLAG_COM: Commutation interrupt flag
Kojto	122:f9eeca106725	935	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
Kojto	122:f9eeca106725	936	* @arg TIM_FLAG_BREAK: Break interrupt flag
Kojto	122:f9eeca106725	937	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
Kojto	122:f9eeca106725	938	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
Kojto	122:f9eeca106725	939	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
Kojto	122:f9eeca106725	940	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Kojto	122:f9eeca106725	941	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	122:f9eeca106725	942	*/
bogdanm	86:04dd9b1680ae	943	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	86:04dd9b1680ae	944
Kojto	122:f9eeca106725	945	/**
Kojto	122:f9eeca106725	946	* @brief Checks whether the specified TIM interrupt has occurred or not.
Kojto	122:f9eeca106725	947	* @param __HANDLE__: TIM handle
Kojto	122:f9eeca106725	948	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
Kojto	122:f9eeca106725	949	* @retval The state of TIM_IT (SET or RESET).
Kojto	122:f9eeca106725	950	*/
Kojto	122:f9eeca106725	951	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto	122:f9eeca106725	952
Kojto	122:f9eeca106725	953	/**
Kojto	122:f9eeca106725	954	* @brief Clear the TIM interrupt pending bits
Kojto	122:f9eeca106725	955	* @param __HANDLE__: TIM handle
Kojto	122:f9eeca106725	956	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	122:f9eeca106725	957	* @retval None
Kojto	122:f9eeca106725	958	*/
bogdanm	86:04dd9b1680ae	959	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	86:04dd9b1680ae	960
Kojto	122:f9eeca106725	961	/**
Kojto	122:f9eeca106725	962	* @brief Indicates whether or not the TIM Counter is used as downcounter
Kojto	122:f9eeca106725	963	* @param __HANDLE__: TIM handle.
Kojto	122:f9eeca106725	964	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
Kojto	122:f9eeca106725	965	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.
Kojto	122:f9eeca106725	966	*/
Kojto	122:f9eeca106725	967	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	86:04dd9b1680ae	968
Kojto	122:f9eeca106725	969	/**
Kojto	122:f9eeca106725	970	* @brief Sets the TIM active prescaler register value on update event.
Kojto	122:f9eeca106725	971	* @param __HANDLE__: TIM handle.
Kojto	122:f9eeca106725	972	* @param __PRESC__: specifies the active prescaler register new value.
Kojto	122:f9eeca106725	973	* @retval None
Kojto	122:f9eeca106725	974	*/
Kojto	122:f9eeca106725	975	#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	86:04dd9b1680ae	976
bogdanm	86:04dd9b1680ae	977	/**
bogdanm	86:04dd9b1680ae	978	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	86:04dd9b1680ae	979	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	980	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	86:04dd9b1680ae	981	* @retval None
bogdanm	86:04dd9b1680ae	982	*/
Kojto	122:f9eeca106725	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	86:04dd9b1680ae	984
bogdanm	86:04dd9b1680ae	985	/**
bogdanm	86:04dd9b1680ae	986	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	86:04dd9b1680ae	987	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	988	* @retval None
bogdanm	86:04dd9b1680ae	989	*/
Kojto	122:f9eeca106725	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
bogdanm	86:04dd9b1680ae	991	((__HANDLE__)->Instance->CNT)
bogdanm	86:04dd9b1680ae	992
bogdanm	86:04dd9b1680ae	993	/**
bogdanm	86:04dd9b1680ae	994	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	86:04dd9b1680ae	995	* another time any Init function.
bogdanm	86:04dd9b1680ae	996	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	997	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	86:04dd9b1680ae	998	* @retval None
bogdanm	86:04dd9b1680ae	999	*/
Kojto	122:f9eeca106725	1000	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
bogdanm	86:04dd9b1680ae	1001	do{ \
bogdanm	86:04dd9b1680ae	1002	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	86:04dd9b1680ae	1003	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<>	135:176b8275d35d	1004	} while(0U)
bogdanm	86:04dd9b1680ae	1005
bogdanm	86:04dd9b1680ae	1006	/**
bogdanm	86:04dd9b1680ae	1007	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	86:04dd9b1680ae	1008	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	1009	* @retval None
bogdanm	86:04dd9b1680ae	1010	*/
Kojto	122:f9eeca106725	1011	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
bogdanm	86:04dd9b1680ae	1012	((__HANDLE__)->Instance->ARR)
bogdanm	86:04dd9b1680ae	1013
bogdanm	86:04dd9b1680ae	1014	/**
bogdanm	86:04dd9b1680ae	1015	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	86:04dd9b1680ae	1016	* another time any Init function.
bogdanm	86:04dd9b1680ae	1017	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	1018	* @param __CKD__: specifies the clock division value.
bogdanm	86:04dd9b1680ae	1019	* This parameter can be one of the following value:
bogdanm	86:04dd9b1680ae	1020	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	86:04dd9b1680ae	1021	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	86:04dd9b1680ae	1022	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	86:04dd9b1680ae	1023	* @retval None
bogdanm	86:04dd9b1680ae	1024	*/
Kojto	122:f9eeca106725	1025	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
bogdanm	86:04dd9b1680ae	1026	do{ \
bogdanm	86:04dd9b1680ae	1027	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	86:04dd9b1680ae	1028	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	86:04dd9b1680ae	1029	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
<>	135:176b8275d35d	1030	} while(0U)
bogdanm	86:04dd9b1680ae	1031
bogdanm	86:04dd9b1680ae	1032	/**
bogdanm	86:04dd9b1680ae	1033	* @brief Gets the TIM Clock Division value on runtime
bogdanm	86:04dd9b1680ae	1034	* @param __HANDLE__: TIM handle.
bogdanm	86:04dd9b1680ae	1035	* @retval None
bogdanm	86:04dd9b1680ae	1036	*/
Kojto	122:f9eeca106725	1037	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
bogdanm	86:04dd9b1680ae	1038	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	86:04dd9b1680ae	1039
bogdanm	86:04dd9b1680ae	1040	/**
bogdanm	86:04dd9b1680ae	1041	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	86:04dd9b1680ae	1042	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	86:04dd9b1680ae	1043	* @param __HANDLE__: TIM handle.
Kojto	122:f9eeca106725	1044	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	86:04dd9b1680ae	1045	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1046	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	86:04dd9b1680ae	1047	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	86:04dd9b1680ae	1048	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	86:04dd9b1680ae	1049	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	86:04dd9b1680ae	1050	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	86:04dd9b1680ae	1051	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1052	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	86:04dd9b1680ae	1053	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	86:04dd9b1680ae	1054	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	86:04dd9b1680ae	1055	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	86:04dd9b1680ae	1056	* @retval None
bogdanm	86:04dd9b1680ae	1057	*/
Kojto	122:f9eeca106725	1058	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	86:04dd9b1680ae	1059	do{ \
Kojto	122:f9eeca106725	1060	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
Kojto	122:f9eeca106725	1061	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<>	135:176b8275d35d	1062	} while(0U)
bogdanm	86:04dd9b1680ae	1063
bogdanm	86:04dd9b1680ae	1064	/**
bogdanm	86:04dd9b1680ae	1065	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	86:04dd9b1680ae	1066	* @param __HANDLE__: TIM handle.
Kojto	122:f9eeca106725	1067	* @param __CHANNEL__: TIM Channels to be configured.
bogdanm	86:04dd9b1680ae	1068	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1069	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	86:04dd9b1680ae	1070	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	86:04dd9b1680ae	1071	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	86:04dd9b1680ae	1072	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	86:04dd9b1680ae	1073	* @retval None
bogdanm	86:04dd9b1680ae	1074	*/
Kojto	122:f9eeca106725	1075	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
bogdanm	86:04dd9b1680ae	1076	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<>	135:176b8275d35d	1077	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
bogdanm	86:04dd9b1680ae	1078	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<>	135:176b8275d35d	1079	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
bogdanm	86:04dd9b1680ae	1080
bogdanm	86:04dd9b1680ae	1081	/**
bogdanm	92:4fc01daae5a5	1082	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	92:4fc01daae5a5	1083	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1084	* @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm	92:4fc01daae5a5	1085	* overflow/underflow generates an update interrupt or DMA request (if
bogdanm	92:4fc01daae5a5	1086	* enabled)
bogdanm	92:4fc01daae5a5	1087	* @retval None
bogdanm	92:4fc01daae5a5	1088	*/
bogdanm	92:4fc01daae5a5	1089	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1090	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
bogdanm	92:4fc01daae5a5	1091
bogdanm	92:4fc01daae5a5	1092	/**
bogdanm	92:4fc01daae5a5	1093	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm	92:4fc01daae5a5	1094	* @param __HANDLE__: TIM handle.
bogdanm	92:4fc01daae5a5	1095	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm	92:4fc01daae5a5	1096	* following events generate an update interrupt or DMA request (if
bogdanm	92:4fc01daae5a5	1097	* enabled):
Kojto	122:f9eeca106725	1098	* (+) Counter overflow/underflow
Kojto	122:f9eeca106725	1099	* (+) Setting the UG bit
Kojto	122:f9eeca106725	1100	* (+) Update generation through the slave mode controller
bogdanm	92:4fc01daae5a5	1101	* @retval None
bogdanm	92:4fc01daae5a5	1102	*/
bogdanm	92:4fc01daae5a5	1103	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm	92:4fc01daae5a5	1104	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm	92:4fc01daae5a5	1105
bogdanm	92:4fc01daae5a5	1106	/**
Kojto	122:f9eeca106725	1107	* @brief Sets the TIM Capture x input polarity on runtime.
Kojto	122:f9eeca106725	1108	* @param __HANDLE__: TIM handle.
Kojto	122:f9eeca106725	1109	* @param __CHANNEL__: TIM Channels to be configured.
Kojto	122:f9eeca106725	1110	* This parameter can be one of the following values:
Kojto	122:f9eeca106725	1111	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
Kojto	122:f9eeca106725	1112	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
Kojto	122:f9eeca106725	1113	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
Kojto	122:f9eeca106725	1114	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
Kojto	122:f9eeca106725	1115	* @param __POLARITY__: Polarity for TIx source
Kojto	122:f9eeca106725	1116	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
Kojto	122:f9eeca106725	1117	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
Kojto	122:f9eeca106725	1118	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Kojto	122:f9eeca106725	1119	* @retval None
Kojto	122:f9eeca106725	1120	*/
Kojto	122:f9eeca106725	1121	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto	122:f9eeca106725	1122	do{ \
Kojto	122:f9eeca106725	1123	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
Kojto	122:f9eeca106725	1124	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<>	135:176b8275d35d	1125	}while(0U)
Kojto	122:f9eeca106725	1126
Kojto	122:f9eeca106725	1127	/**
Kojto	122:f9eeca106725	1128	* @}
Kojto	122:f9eeca106725	1129	*/
Kojto	122:f9eeca106725	1130	/* End of exported macros ----------------------------------------------------*/
Kojto	122:f9eeca106725	1131
Kojto	122:f9eeca106725	1132	/* Private Constants -----------------------------------------------------------*/
Kojto	122:f9eeca106725	1133	/** @defgroup TIM_Private_Constants TIM Private Constants
Kojto	122:f9eeca106725	1134	* @{
Kojto	122:f9eeca106725	1135	*/
Kojto	122:f9eeca106725	1136
Kojto	122:f9eeca106725	1137	/* The counter of a timer instance is disabled only if all the CCx and CCxN
Kojto	122:f9eeca106725	1138	channels have been disabled */
Kojto	122:f9eeca106725	1139	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
Kojto	122:f9eeca106725	1140	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
Kojto	122:f9eeca106725	1141
Kojto	122:f9eeca106725	1142	/**
bogdanm	86:04dd9b1680ae	1143	* @}
bogdanm	86:04dd9b1680ae	1144	*/
Kojto	122:f9eeca106725	1145	/* End of private constants --------------------------------------------------*/
Kojto	122:f9eeca106725	1146
Kojto	122:f9eeca106725	1147	/* Private Macros -----------------------------------------------------------*/
Kojto	122:f9eeca106725	1148	/** @defgroup TIM_Private_Macros TIM Private Macros
Kojto	122:f9eeca106725	1149	* @{
Kojto	122:f9eeca106725	1150	*/
Kojto	122:f9eeca106725	1151
Kojto	122:f9eeca106725	1152	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
Kojto	122:f9eeca106725	1153	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
Kojto	122:f9eeca106725	1154	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
Kojto	122:f9eeca106725	1155	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
Kojto	122:f9eeca106725	1156	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
Kojto	122:f9eeca106725	1157
Kojto	122:f9eeca106725	1158	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
Kojto	122:f9eeca106725	1159	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
Kojto	122:f9eeca106725	1160	((DIV) == TIM_CLOCKDIVISION_DIV4))
Kojto	122:f9eeca106725	1161
<>	135:176b8275d35d	1162	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
<>	135:176b8275d35d	1163	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
Kojto	122:f9eeca106725	1164
Kojto	122:f9eeca106725	1165	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
Kojto	122:f9eeca106725	1166	((STATE) == TIM_OCFAST_ENABLE))
Kojto	122:f9eeca106725	1167
Kojto	122:f9eeca106725	1168	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
Kojto	122:f9eeca106725	1169	((POLARITY) == TIM_OCPOLARITY_LOW))
Kojto	122:f9eeca106725	1170
Kojto	122:f9eeca106725	1171	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
Kojto	122:f9eeca106725	1172	((POLARITY) == TIM_OCNPOLARITY_LOW))
Kojto	122:f9eeca106725	1173
Kojto	122:f9eeca106725	1174	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
Kojto	122:f9eeca106725	1175	((STATE) == TIM_OCIDLESTATE_RESET))
Kojto	122:f9eeca106725	1176
Kojto	122:f9eeca106725	1177	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
Kojto	122:f9eeca106725	1178	((STATE) == TIM_OCNIDLESTATE_RESET))
Kojto	122:f9eeca106725	1179
Kojto	122:f9eeca106725	1180
Kojto	122:f9eeca106725	1181	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
Kojto	122:f9eeca106725	1182	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
Kojto	122:f9eeca106725	1183	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
Kojto	122:f9eeca106725	1184
Kojto	122:f9eeca106725	1185	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
Kojto	122:f9eeca106725	1186	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
Kojto	122:f9eeca106725	1187	((SELECTION) == TIM_ICSELECTION_TRC))
Kojto	122:f9eeca106725	1188
Kojto	122:f9eeca106725	1189	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
Kojto	122:f9eeca106725	1190	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
Kojto	122:f9eeca106725	1191	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
Kojto	122:f9eeca106725	1192	((PRESCALER) == TIM_ICPSC_DIV8))
Kojto	122:f9eeca106725	1193
Kojto	122:f9eeca106725	1194	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
Kojto	122:f9eeca106725	1195	((MODE) == TIM_OPMODE_REPETITIVE))
Kojto	122:f9eeca106725	1196
Kojto	122:f9eeca106725	1197	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
Kojto	122:f9eeca106725	1198	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
Kojto	122:f9eeca106725	1199	((MODE) == TIM_ENCODERMODE_TI12))
Kojto	122:f9eeca106725	1200
<>	135:176b8275d35d	1201	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
Kojto	122:f9eeca106725	1202
Kojto	122:f9eeca106725	1203
Kojto	122:f9eeca106725	1204	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
Kojto	122:f9eeca106725	1205	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
Kojto	122:f9eeca106725	1206	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
Kojto	122:f9eeca106725	1207	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
Kojto	122:f9eeca106725	1208	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
Kojto	122:f9eeca106725	1209	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
Kojto	122:f9eeca106725	1210	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
Kojto	122:f9eeca106725	1211	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
Kojto	122:f9eeca106725	1212	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
Kojto	122:f9eeca106725	1213	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
Kojto	122:f9eeca106725	1214
Kojto	122:f9eeca106725	1215	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
Kojto	122:f9eeca106725	1216	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
Kojto	122:f9eeca106725	1217	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
Kojto	122:f9eeca106725	1218	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
Kojto	122:f9eeca106725	1219	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
Kojto	122:f9eeca106725	1220
Kojto	122:f9eeca106725	1221	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
Kojto	122:f9eeca106725	1222	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
Kojto	122:f9eeca106725	1223	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
Kojto	122:f9eeca106725	1224	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
Kojto	122:f9eeca106725	1225
<>	135:176b8275d35d	1226	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	122:f9eeca106725	1227
Kojto	122:f9eeca106725	1228	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
Kojto	122:f9eeca106725	1229	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
Kojto	122:f9eeca106725	1230
Kojto	122:f9eeca106725	1231	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
Kojto	122:f9eeca106725	1232	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
Kojto	122:f9eeca106725	1233	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
Kojto	122:f9eeca106725	1234	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
Kojto	122:f9eeca106725	1235
<>	135:176b8275d35d	1236	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	122:f9eeca106725	1237
Kojto	122:f9eeca106725	1238	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
Kojto	122:f9eeca106725	1239	((STATE) == TIM_OSSR_DISABLE))
Kojto	122:f9eeca106725	1240
Kojto	122:f9eeca106725	1241	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
Kojto	122:f9eeca106725	1242	((STATE) == TIM_OSSI_DISABLE))
Kojto	122:f9eeca106725	1243
Kojto	122:f9eeca106725	1244	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
Kojto	122:f9eeca106725	1245	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
Kojto	122:f9eeca106725	1246	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
Kojto	122:f9eeca106725	1247	((LEVEL) == TIM_LOCKLEVEL_3))
Kojto	122:f9eeca106725	1248
Kojto	122:f9eeca106725	1249	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
Kojto	122:f9eeca106725	1250	((STATE) == TIM_BREAK_DISABLE))
Kojto	122:f9eeca106725	1251
Kojto	122:f9eeca106725	1252	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
Kojto	122:f9eeca106725	1253	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
Kojto	122:f9eeca106725	1254
Kojto	122:f9eeca106725	1255	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
Kojto	122:f9eeca106725	1256	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
Kojto	122:f9eeca106725	1257
Kojto	122:f9eeca106725	1258	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
Kojto	122:f9eeca106725	1259	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
Kojto	122:f9eeca106725	1260	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
Kojto	122:f9eeca106725	1261	((SOURCE) == TIM_TRGO_OC1) \|\| \
Kojto	122:f9eeca106725	1262	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
Kojto	122:f9eeca106725	1263	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
Kojto	122:f9eeca106725	1264	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
Kojto	122:f9eeca106725	1265	((SOURCE) == TIM_TRGO_OC4REF))
Kojto	122:f9eeca106725	1266
Kojto	122:f9eeca106725	1267	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
Kojto	122:f9eeca106725	1268	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
Kojto	122:f9eeca106725	1269
Kojto	122:f9eeca106725	1270	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	122:f9eeca106725	1271	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	122:f9eeca106725	1272	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	122:f9eeca106725	1273	((SELECTION) == TIM_TS_ITR3) \|\| \
Kojto	122:f9eeca106725	1274	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
Kojto	122:f9eeca106725	1275	((SELECTION) == TIM_TS_TI1FP1) \|\| \
Kojto	122:f9eeca106725	1276	((SELECTION) == TIM_TS_TI2FP2) \|\| \
Kojto	122:f9eeca106725	1277	((SELECTION) == TIM_TS_ETRF))
Kojto	122:f9eeca106725	1278
Kojto	122:f9eeca106725	1279	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	122:f9eeca106725	1280	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	122:f9eeca106725	1281	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	122:f9eeca106725	1282	((SELECTION) == TIM_TS_ITR3) \|\| \
Kojto	122:f9eeca106725	1283	((SELECTION) == TIM_TS_NONE))
Kojto	122:f9eeca106725	1284
Kojto	122:f9eeca106725	1285	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
Kojto	122:f9eeca106725	1286	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
Kojto	122:f9eeca106725	1287	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
Kojto	122:f9eeca106725	1288	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
Kojto	122:f9eeca106725	1289	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
Kojto	122:f9eeca106725	1290
Kojto	122:f9eeca106725	1291	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
Kojto	122:f9eeca106725	1292	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
Kojto	122:f9eeca106725	1293	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
Kojto	122:f9eeca106725	1294	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
Kojto	122:f9eeca106725	1295
<>	135:176b8275d35d	1296	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	122:f9eeca106725	1297
Kojto	122:f9eeca106725	1298	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
Kojto	122:f9eeca106725	1299	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
Kojto	122:f9eeca106725	1300
Kojto	122:f9eeca106725	1301	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
Kojto	122:f9eeca106725	1302	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1303	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1304	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1305	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1306	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1307	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1308	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1309	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1310	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1311	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1312	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1313	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1314	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1315	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1316	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1317	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
Kojto	122:f9eeca106725	1318	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
Kojto	122:f9eeca106725	1319
<>	135:176b8275d35d	1320	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
Kojto	122:f9eeca106725	1321
Kojto	122:f9eeca106725	1322	/** @brief Set TIM IC prescaler
Kojto	122:f9eeca106725	1323	* @param __HANDLE__: TIM handle
Kojto	122:f9eeca106725	1324	* @param __CHANNEL__: specifies TIM Channel
Kojto	122:f9eeca106725	1325	* @param __ICPSC__: specifies the prescaler value.
Kojto	122:f9eeca106725	1326	* @retval None
Kojto	122:f9eeca106725	1327	*/
Kojto	122:f9eeca106725	1328	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
Kojto	122:f9eeca106725	1329	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
<>	135:176b8275d35d	1330	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
Kojto	122:f9eeca106725	1331	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
<>	135:176b8275d35d	1332	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
Kojto	122:f9eeca106725	1333
Kojto	122:f9eeca106725	1334	/** @brief Reset TIM IC prescaler
Kojto	122:f9eeca106725	1335	* @param __HANDLE__: TIM handle
Kojto	122:f9eeca106725	1336	* @param __CHANNEL__: specifies TIM Channel
Kojto	122:f9eeca106725	1337	* @retval None
Kojto	122:f9eeca106725	1338	*/
Kojto	122:f9eeca106725	1339	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
Kojto	122:f9eeca106725	1340	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
Kojto	122:f9eeca106725	1341	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
Kojto	122:f9eeca106725	1342	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
Kojto	122:f9eeca106725	1343	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
Kojto	122:f9eeca106725	1344
Kojto	122:f9eeca106725	1345	/** @brief Set TIM IC polarity
Kojto	122:f9eeca106725	1346	* @param __HANDLE__: TIM handle
Kojto	122:f9eeca106725	1347	* @param __CHANNEL__: specifies TIM Channel
Kojto	122:f9eeca106725	1348	* @param __POLARITY__: specifies TIM Channel Polarity
Kojto	122:f9eeca106725	1349	* @retval None
Kojto	122:f9eeca106725	1350	*/
Kojto	122:f9eeca106725	1351	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
Kojto	122:f9eeca106725	1352	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
<>	135:176b8275d35d	1353	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
<>	135:176b8275d35d	1354	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
<>	135:176b8275d35d	1355	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
Kojto	122:f9eeca106725	1356
Kojto	122:f9eeca106725	1357	/** @brief Reset TIM IC polarity
Kojto	122:f9eeca106725	1358	* @param __HANDLE__: TIM handle
Kojto	122:f9eeca106725	1359	* @param __CHANNEL__: specifies TIM Channel
Kojto	122:f9eeca106725	1360	* @retval None
Kojto	122:f9eeca106725	1361	*/
Kojto	122:f9eeca106725	1362	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
Kojto	122:f9eeca106725	1363	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
Kojto	122:f9eeca106725	1364	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
Kojto	122:f9eeca106725	1365	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
Kojto	122:f9eeca106725	1366	((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
Kojto	122:f9eeca106725	1367	/**
Kojto	122:f9eeca106725	1368	* @}
Kojto	122:f9eeca106725	1369	*/
Kojto	122:f9eeca106725	1370	/* End of private macros -----------------------------------------------------*/
bogdanm	86:04dd9b1680ae	1371
bogdanm	92:4fc01daae5a5	1372	/* Include TIM HAL Extended module */
bogdanm	86:04dd9b1680ae	1373	#include "stm32f3xx_hal_tim_ex.h"
bogdanm	86:04dd9b1680ae	1374
bogdanm	86:04dd9b1680ae	1375	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	1376	/** @addtogroup TIM_Exported_Functions
bogdanm	92:4fc01daae5a5	1377	* @{
bogdanm	92:4fc01daae5a5	1378	*/
bogdanm	86:04dd9b1680ae	1379
Kojto	122:f9eeca106725	1380	/** @addtogroup TIM_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	1381	* @{
bogdanm	92:4fc01daae5a5	1382	*/
bogdanm	86:04dd9b1680ae	1383	/* Time Base functions ********************************************************/
bogdanm	86:04dd9b1680ae	1384	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1385	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1386	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1387	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1388	/* Blocking mode: Polling */
bogdanm	86:04dd9b1680ae	1389	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1390	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1391	/* Non-Blocking mode: Interrupt */
bogdanm	86:04dd9b1680ae	1392	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1393	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1394	/* Non-Blocking mode: DMA */
bogdanm	86:04dd9b1680ae	1395	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	86:04dd9b1680ae	1396	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1397	/**
bogdanm	92:4fc01daae5a5	1398	* @}
bogdanm	92:4fc01daae5a5	1399	*/
bogdanm	86:04dd9b1680ae	1400
Kojto	122:f9eeca106725	1401	/** @addtogroup TIM_Exported_Functions_Group2
bogdanm	92:4fc01daae5a5	1402	* @{
bogdanm	92:4fc01daae5a5	1403	*/
bogdanm	86:04dd9b1680ae	1404	/* Timer Output Compare functions **********************************************/
bogdanm	86:04dd9b1680ae	1405	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1406	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1407	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1408	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1409	/* Blocking mode: Polling */
bogdanm	86:04dd9b1680ae	1410	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1411	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1412	/* Non-Blocking mode: Interrupt */
bogdanm	86:04dd9b1680ae	1413	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1414	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1415	/* Non-Blocking mode: DMA */
bogdanm	86:04dd9b1680ae	1416	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	86:04dd9b1680ae	1417	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto	122:f9eeca106725	1418
bogdanm	92:4fc01daae5a5	1419	/**
bogdanm	92:4fc01daae5a5	1420	* @}
bogdanm	92:4fc01daae5a5	1421	*/
bogdanm	92:4fc01daae5a5	1422
Kojto	122:f9eeca106725	1423	/** @addtogroup TIM_Exported_Functions_Group3
bogdanm	92:4fc01daae5a5	1424	* @{
bogdanm	92:4fc01daae5a5	1425	*/
bogdanm	86:04dd9b1680ae	1426	/* Timer PWM functions *********************************************************/
bogdanm	86:04dd9b1680ae	1427	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1428	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1429	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1430	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1431	/* Blocking mode: Polling */
bogdanm	86:04dd9b1680ae	1432	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1433	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1434	/* Non-Blocking mode: Interrupt */
bogdanm	86:04dd9b1680ae	1435	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1436	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1437	/* Non-Blocking mode: DMA */
bogdanm	86:04dd9b1680ae	1438	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	86:04dd9b1680ae	1439	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1440	/**
bogdanm	92:4fc01daae5a5	1441	* @}
bogdanm	92:4fc01daae5a5	1442	*/
bogdanm	92:4fc01daae5a5	1443
Kojto	122:f9eeca106725	1444	/** @addtogroup TIM_Exported_Functions_Group4
bogdanm	92:4fc01daae5a5	1445	* @{
bogdanm	92:4fc01daae5a5	1446	*/
bogdanm	86:04dd9b1680ae	1447	/* Timer Input Capture functions ***********************************************/
bogdanm	86:04dd9b1680ae	1448	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1449	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1450	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1451	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1452	/* Blocking mode: Polling */
bogdanm	86:04dd9b1680ae	1453	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1454	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1455	/* Non-Blocking mode: Interrupt */
bogdanm	86:04dd9b1680ae	1456	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1457	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1458	/* Non-Blocking mode: DMA */
bogdanm	86:04dd9b1680ae	1459	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	86:04dd9b1680ae	1460	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	92:4fc01daae5a5	1461	/**
bogdanm	92:4fc01daae5a5	1462	* @}
bogdanm	92:4fc01daae5a5	1463	*/
bogdanm	92:4fc01daae5a5	1464
Kojto	122:f9eeca106725	1465	/** @addtogroup TIM_Exported_Functions_Group5
bogdanm	92:4fc01daae5a5	1466	* @{
bogdanm	92:4fc01daae5a5	1467	*/
bogdanm	86:04dd9b1680ae	1468	/* Timer One Pulse functions ***************************************************/
bogdanm	86:04dd9b1680ae	1469	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	86:04dd9b1680ae	1470	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1471	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1472	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1473	/* Blocking mode: Polling */
bogdanm	86:04dd9b1680ae	1474	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	86:04dd9b1680ae	1475	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	86:04dd9b1680ae	1476	/* Non-Blocking mode: Interrupt */
bogdanm	86:04dd9b1680ae	1477	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	86:04dd9b1680ae	1478	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	92:4fc01daae5a5	1479	/**
bogdanm	92:4fc01daae5a5	1480	* @}
bogdanm	92:4fc01daae5a5	1481	*/
bogdanm	86:04dd9b1680ae	1482
Kojto	122:f9eeca106725	1483	/** @addtogroup TIM_Exported_Functions_Group6
bogdanm	92:4fc01daae5a5	1484	* @{
bogdanm	92:4fc01daae5a5	1485	*/
bogdanm	86:04dd9b1680ae	1486	/* Timer Encoder functions *****************************************************/
bogdanm	86:04dd9b1680ae	1487	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	86:04dd9b1680ae	1488	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1489	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1490	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1491	/* Blocking mode: Polling */
bogdanm	86:04dd9b1680ae	1492	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1493	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1494	/* Non-Blocking mode: Interrupt */
bogdanm	86:04dd9b1680ae	1495	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1496	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1497	/* Non-Blocking mode: DMA */
bogdanm	86:04dd9b1680ae	1498	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	86:04dd9b1680ae	1499	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto	122:f9eeca106725	1500
bogdanm	92:4fc01daae5a5	1501	/**
bogdanm	92:4fc01daae5a5	1502	* @}
bogdanm	92:4fc01daae5a5	1503	*/
bogdanm	86:04dd9b1680ae	1504
Kojto	122:f9eeca106725	1505	/** @addtogroup TIM_Exported_Functions_Group7
bogdanm	92:4fc01daae5a5	1506	* @{
bogdanm	92:4fc01daae5a5	1507	*/
bogdanm	86:04dd9b1680ae	1508	/* Interrupt Handler functions **********************************************/
bogdanm	86:04dd9b1680ae	1509	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1510	/**
bogdanm	92:4fc01daae5a5	1511	* @}
bogdanm	92:4fc01daae5a5	1512	*/
bogdanm	86:04dd9b1680ae	1513
Kojto	122:f9eeca106725	1514	/** @addtogroup TIM_Exported_Functions_Group8
bogdanm	92:4fc01daae5a5	1515	* @{
bogdanm	92:4fc01daae5a5	1516	*/
bogdanm	86:04dd9b1680ae	1517	/* Control functions *********************************************************/
bogdanm	86:04dd9b1680ae	1518	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1519	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1520	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1521	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	86:04dd9b1680ae	1522	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	86:04dd9b1680ae	1523	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	86:04dd9b1680ae	1524	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	86:04dd9b1680ae	1525	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
Kojto	122:f9eeca106725	1526	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	86:04dd9b1680ae	1527	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	86:04dd9b1680ae	1528	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	86:04dd9b1680ae	1529	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	86:04dd9b1680ae	1530	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	86:04dd9b1680ae	1531	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	86:04dd9b1680ae	1532	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	86:04dd9b1680ae	1533	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	86:04dd9b1680ae	1534	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
Kojto	122:f9eeca106725	1535
bogdanm	92:4fc01daae5a5	1536	/**
bogdanm	92:4fc01daae5a5	1537	* @}
bogdanm	92:4fc01daae5a5	1538	*/
bogdanm	86:04dd9b1680ae	1539
Kojto	122:f9eeca106725	1540	/** @addtogroup TIM_Exported_Functions_Group9
bogdanm	92:4fc01daae5a5	1541	* @{
bogdanm	92:4fc01daae5a5	1542	*/
bogdanm	86:04dd9b1680ae	1543	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	86:04dd9b1680ae	1544	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1545	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1546	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1547	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1548	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1549	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	92:4fc01daae5a5	1550	/**
bogdanm	92:4fc01daae5a5	1551	* @}
bogdanm	92:4fc01daae5a5	1552	*/
bogdanm	86:04dd9b1680ae	1553
Kojto	122:f9eeca106725	1554	/** @addtogroup TIM_Exported_Functions_Group10
bogdanm	92:4fc01daae5a5	1555	* @{
bogdanm	92:4fc01daae5a5	1556	*/
bogdanm	86:04dd9b1680ae	1557	/* Peripheral State functions **************************************************/
bogdanm	86:04dd9b1680ae	1558	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1559	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1560	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1561	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1562	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	86:04dd9b1680ae	1563	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
Kojto	122:f9eeca106725	1564
bogdanm	92:4fc01daae5a5	1565	/**
bogdanm	92:4fc01daae5a5	1566	* @}
bogdanm	92:4fc01daae5a5	1567	*/
bogdanm	92:4fc01daae5a5	1568
bogdanm	92:4fc01daae5a5	1569	/**
bogdanm	92:4fc01daae5a5	1570	* @}
bogdanm	92:4fc01daae5a5	1571	*/
Kojto	122:f9eeca106725	1572	/* End of exported functions -------------------------------------------------*/
bogdanm	86:04dd9b1680ae	1573
Kojto	122:f9eeca106725	1574	/* Private Functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	1575	/** @addtogroup TIM_Private_Functions
Kojto	122:f9eeca106725	1576	* @{
Kojto	122:f9eeca106725	1577	*/
bogdanm	86:04dd9b1680ae	1578	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
bogdanm	86:04dd9b1680ae	1579	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm	86:04dd9b1680ae	1580	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	86:04dd9b1680ae	1581	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	86:04dd9b1680ae	1582	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	86:04dd9b1680ae	1583	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
bogdanm	86:04dd9b1680ae	1584	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm	86:04dd9b1680ae	1585	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
Kojto	122:f9eeca106725	1586	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	1587	void TIM_DMAError(DMA_HandleTypeDef *hdma);
Kojto	122:f9eeca106725	1588	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	86:04dd9b1680ae	1589	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
Kojto	122:f9eeca106725	1590	/**
Kojto	122:f9eeca106725	1591	* @}
Kojto	122:f9eeca106725	1592	*/
Kojto	122:f9eeca106725	1593	/* End of private functions --------------------------------------------------*/
bogdanm	86:04dd9b1680ae	1594
bogdanm	86:04dd9b1680ae	1595	/**
bogdanm	86:04dd9b1680ae	1596	* @}
bogdanm	92:4fc01daae5a5	1597	*/
bogdanm	86:04dd9b1680ae	1598
bogdanm	86:04dd9b1680ae	1599	/**
bogdanm	86:04dd9b1680ae	1600	* @}
bogdanm	86:04dd9b1680ae	1601	*/
bogdanm	86:04dd9b1680ae	1602
bogdanm	86:04dd9b1680ae	1603	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	1604	}
bogdanm	86:04dd9b1680ae	1605	#endif
bogdanm	86:04dd9b1680ae	1606
bogdanm	86:04dd9b1680ae	1607	#endif /* __STM32F3xx_HAL_TIM_H */
bogdanm	86:04dd9b1680ae	1608
bogdanm	86:04dd9b1680ae	1609	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/