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drivers/QSPI.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /* mbed Microcontroller Library
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2006-2018 ARM Limited
AnnaBridge 172:65be27845400 3 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 171:3a7713b1edbc 6 * you may not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 7 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 12 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 171:3a7713b1edbc 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 14 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 15 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 16 */
AnnaBridge 171:3a7713b1edbc 17 #ifndef MBED_QSPI_H
AnnaBridge 171:3a7713b1edbc 18 #define MBED_QSPI_H
AnnaBridge 171:3a7713b1edbc 19
AnnaBridge 171:3a7713b1edbc 20 #include "platform/platform.h"
AnnaBridge 171:3a7713b1edbc 21
AnnaBridge 172:65be27845400 22 #if DEVICE_QSPI || defined(DOXYGEN_ONLY)
AnnaBridge 171:3a7713b1edbc 23
AnnaBridge 171:3a7713b1edbc 24 #include "hal/qspi_api.h"
AnnaBridge 171:3a7713b1edbc 25 #include "platform/PlatformMutex.h"
AnnaBridge 171:3a7713b1edbc 26 #include "platform/SingletonPtr.h"
AnnaBridge 171:3a7713b1edbc 27 #include "platform/NonCopyable.h"
AnnaBridge 171:3a7713b1edbc 28
AnnaBridge 171:3a7713b1edbc 29 #define ONE_MHZ 1000000
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 namespace mbed {
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 /** \addtogroup drivers */
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /** A QSPI Driver, used for communicating with QSPI slave devices
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
AnnaBridge 171:3a7713b1edbc 38 * Most QSPI devices will also require Chip Select which is indicated by ssel.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * @note Synchronization level: Thread safe
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 * Example:
AnnaBridge 171:3a7713b1edbc 43 * @code
AnnaBridge 171:3a7713b1edbc 44 * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
AnnaBridge 171:3a7713b1edbc 45 *
AnnaBridge 171:3a7713b1edbc 46 * #include "mbed.h"
AnnaBridge 171:3a7713b1edbc 47 *
AnnaBridge 171:3a7713b1edbc 48 * #define CMD_WRITE 0x02
AnnaBridge 171:3a7713b1edbc 49 * #define CMD_READ 0x03
AnnaBridge 171:3a7713b1edbc 50 * #define ADDRESS 0x1000
AnnaBridge 171:3a7713b1edbc 51 *
AnnaBridge 171:3a7713b1edbc 52 * // hardware ssel (where applicable)
AnnaBridge 171:3a7713b1edbc 53 * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
AnnaBridge 171:3a7713b1edbc 54 *
AnnaBridge 171:3a7713b1edbc 55 *
AnnaBridge 171:3a7713b1edbc 56 * int main() {
AnnaBridge 171:3a7713b1edbc 57 * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
AnnaBridge 171:3a7713b1edbc 58 * char rx_buf[4];
AnnaBridge 171:3a7713b1edbc 59 * int buf_len = sizeof(tx_buf);
AnnaBridge 171:3a7713b1edbc 60 *
AnnaBridge 171:3a7713b1edbc 61 * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
AnnaBridge 171:3a7713b1edbc 62 * if (result != QSPI_STATUS_OK) {
AnnaBridge 171:3a7713b1edbc 63 * printf("Write failed");
AnnaBridge 171:3a7713b1edbc 64 * }
AnnaBridge 171:3a7713b1edbc 65 * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
AnnaBridge 171:3a7713b1edbc 66 * if (result != QSPI_STATUS_OK) {
AnnaBridge 171:3a7713b1edbc 67 * printf("Read failed");
AnnaBridge 171:3a7713b1edbc 68 * }
AnnaBridge 171:3a7713b1edbc 69 *
AnnaBridge 171:3a7713b1edbc 70 * }
AnnaBridge 171:3a7713b1edbc 71 * @endcode
AnnaBridge 171:3a7713b1edbc 72 * @ingroup drivers
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74 class QSPI : private NonCopyable<QSPI> {
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 public:
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /** Create a QSPI master connected to the specified pins
AnnaBridge 171:3a7713b1edbc 79 *
AnnaBridge 171:3a7713b1edbc 80 * io0-io3 is used to specify the Pins used for Quad SPI mode
AnnaBridge 171:3a7713b1edbc 81 *
AnnaBridge 171:3a7713b1edbc 82 * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 83 * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 84 * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 85 * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 86 * @param sclk QSPI Clock pin
AnnaBridge 171:3a7713b1edbc 87 * @param ssel QSPI chip select pin
AnnaBridge 171:3a7713b1edbc 88 * @param mode Clock polarity and phase mode (0 - 3) of SPI
AnnaBridge 171:3a7713b1edbc 89 * (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
AnnaBridge 171:3a7713b1edbc 90 *
AnnaBridge 171:3a7713b1edbc 91 */
AnnaBridge 171:3a7713b1edbc 92 QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
AnnaBridge 171:3a7713b1edbc 93 virtual ~QSPI()
AnnaBridge 171:3a7713b1edbc 94 {
AnnaBridge 171:3a7713b1edbc 95 }
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /** Configure the data transmission format
AnnaBridge 171:3a7713b1edbc 98 *
AnnaBridge 171:3a7713b1edbc 99 * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 100 * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 101 * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
AnnaBridge 171:3a7713b1edbc 102 * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 103 * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
AnnaBridge 171:3a7713b1edbc 104 * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 105 * @param dummy_cycles Number of dummy clock cycles to be used after alt phase
AnnaBridge 171:3a7713b1edbc 106 *
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108 qspi_status_t configure_format(qspi_bus_width_t inst_width,
AnnaBridge 171:3a7713b1edbc 109 qspi_bus_width_t address_width,
AnnaBridge 171:3a7713b1edbc 110 qspi_address_size_t address_size,
AnnaBridge 171:3a7713b1edbc 111 qspi_bus_width_t alt_width,
AnnaBridge 171:3a7713b1edbc 112 qspi_alt_size_t alt_size,
AnnaBridge 171:3a7713b1edbc 113 qspi_bus_width_t data_width,
AnnaBridge 171:3a7713b1edbc 114 int dummy_cycles);
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /** Set the qspi bus clock frequency
AnnaBridge 171:3a7713b1edbc 117 *
AnnaBridge 171:3a7713b1edbc 118 * @param hz SCLK frequency in hz (default = 1MHz)
AnnaBridge 171:3a7713b1edbc 119 * @returns
AnnaBridge 171:3a7713b1edbc 120 * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
AnnaBridge 171:3a7713b1edbc 121 */
AnnaBridge 171:3a7713b1edbc 122 qspi_status_t set_frequency(int hz = ONE_MHZ);
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /** Read from QSPI peripheral with the preset read_instruction and alt_value
AnnaBridge 171:3a7713b1edbc 125 *
AnnaBridge 171:3a7713b1edbc 126 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 127 * @param rx_buffer Buffer for data to be read from the peripheral
AnnaBridge 171:3a7713b1edbc 128 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
AnnaBridge 171:3a7713b1edbc 129 *
AnnaBridge 171:3a7713b1edbc 130 * @returns
AnnaBridge 171:3a7713b1edbc 131 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133 qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /** Write to QSPI peripheral using custom write instruction
AnnaBridge 171:3a7713b1edbc 136 *
AnnaBridge 171:3a7713b1edbc 137 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 138 * @param tx_buffer Buffer containing data to be sent to peripheral
AnnaBridge 171:3a7713b1edbc 139 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
AnnaBridge 171:3a7713b1edbc 140 *
AnnaBridge 171:3a7713b1edbc 141 * @returns
AnnaBridge 171:3a7713b1edbc 142 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 143 */
AnnaBridge 171:3a7713b1edbc 144 qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 /** Read from QSPI peripheral using custom read instruction, alt values
AnnaBridge 171:3a7713b1edbc 147 *
AnnaBridge 171:3a7713b1edbc 148 * @param instruction Instruction value to be used in instruction phase
AnnaBridge 171:3a7713b1edbc 149 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
AnnaBridge 171:3a7713b1edbc 150 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 151 * @param rx_buffer Buffer for data to be read from the peripheral
AnnaBridge 171:3a7713b1edbc 152 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
AnnaBridge 171:3a7713b1edbc 153 *
AnnaBridge 171:3a7713b1edbc 154 * @returns
AnnaBridge 171:3a7713b1edbc 155 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157 qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /** Write to QSPI peripheral using custom write instruction, alt values
AnnaBridge 171:3a7713b1edbc 160 *
AnnaBridge 171:3a7713b1edbc 161 * @param instruction Instruction value to be used in instruction phase
AnnaBridge 171:3a7713b1edbc 162 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
AnnaBridge 171:3a7713b1edbc 163 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 164 * @param tx_buffer Buffer containing data to be sent to peripheral
AnnaBridge 171:3a7713b1edbc 165 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
AnnaBridge 171:3a7713b1edbc 166 *
AnnaBridge 171:3a7713b1edbc 167 * @returns
AnnaBridge 171:3a7713b1edbc 168 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 169 */
AnnaBridge 171:3a7713b1edbc 170 qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /** Perform a transaction to write to an address(a control register) and get the status results
AnnaBridge 171:3a7713b1edbc 173 *
AnnaBridge 171:3a7713b1edbc 174 * @param instruction Instruction value to be used in instruction phase
AnnaBridge 171:3a7713b1edbc 175 * @param address Some instruction might require address. Use -1 if no address
AnnaBridge 171:3a7713b1edbc 176 * @param tx_buffer Buffer containing data to be sent to peripheral
AnnaBridge 171:3a7713b1edbc 177 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
AnnaBridge 171:3a7713b1edbc 178 * @param rx_buffer Buffer for data to be read from the peripheral
AnnaBridge 171:3a7713b1edbc 179 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
AnnaBridge 171:3a7713b1edbc 180 *
AnnaBridge 171:3a7713b1edbc 181 * @returns
AnnaBridge 171:3a7713b1edbc 182 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 #if !defined(DOXYGEN_ONLY)
AnnaBridge 171:3a7713b1edbc 187 protected:
AnnaBridge 171:3a7713b1edbc 188 /** Acquire exclusive access to this SPI bus
AnnaBridge 171:3a7713b1edbc 189 */
AnnaBridge 171:3a7713b1edbc 190 virtual void lock(void);
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 /** Release exclusive access to this SPI bus
AnnaBridge 171:3a7713b1edbc 193 */
AnnaBridge 171:3a7713b1edbc 194 virtual void unlock(void);
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 qspi_t _qspi;
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 bool acquire(void);
AnnaBridge 171:3a7713b1edbc 199 static QSPI *_owner;
AnnaBridge 171:3a7713b1edbc 200 static SingletonPtr<PlatformMutex> _mutex;
AnnaBridge 171:3a7713b1edbc 201 qspi_bus_width_t _inst_width; //Bus width for Instruction phase
AnnaBridge 171:3a7713b1edbc 202 qspi_bus_width_t _address_width; //Bus width for Address phase
AnnaBridge 171:3a7713b1edbc 203 qspi_address_size_t _address_size;
AnnaBridge 171:3a7713b1edbc 204 qspi_bus_width_t _alt_width; //Bus width for Alt phase
AnnaBridge 171:3a7713b1edbc 205 qspi_alt_size_t _alt_size;
AnnaBridge 171:3a7713b1edbc 206 qspi_bus_width_t _data_width; //Bus width for Data phase
AnnaBridge 171:3a7713b1edbc 207 qspi_command_t _qspi_command; //QSPI Hal command struct
AnnaBridge 171:3a7713b1edbc 208 unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
AnnaBridge 171:3a7713b1edbc 209 int _hz; //Bus Frequency
AnnaBridge 171:3a7713b1edbc 210 int _mode; //SPI mode
AnnaBridge 171:3a7713b1edbc 211 bool _initialized;
AnnaBridge 171:3a7713b1edbc 212 PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 private:
AnnaBridge 171:3a7713b1edbc 215 /* Private acquire function without locking/unlocking
AnnaBridge 171:3a7713b1edbc 216 * Implemented in order to avoid duplicate locking and boost performance
AnnaBridge 171:3a7713b1edbc 217 */
AnnaBridge 171:3a7713b1edbc 218 bool _acquire(void);
AnnaBridge 171:3a7713b1edbc 219 bool _initialize();
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /*
AnnaBridge 171:3a7713b1edbc 222 * This function builds the qspi command struct to be send to Hal
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224 inline void _build_qspi_command(int instruction, int address, int alt);
AnnaBridge 171:3a7713b1edbc 225 #endif
AnnaBridge 171:3a7713b1edbc 226 };
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 } // namespace mbed
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 #endif
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 #endif