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drivers/QSPI.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Child:
172:65be27845400
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /* mbed Microcontroller Library
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2006-2018 ARM Limited
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 171:3a7713b1edbc 5 * you may not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 6 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 171:3a7713b1edbc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 13 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 14 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 15 */
AnnaBridge 171:3a7713b1edbc 16 #ifndef MBED_QSPI_H
AnnaBridge 171:3a7713b1edbc 17 #define MBED_QSPI_H
AnnaBridge 171:3a7713b1edbc 18
AnnaBridge 171:3a7713b1edbc 19 #include "platform/platform.h"
AnnaBridge 171:3a7713b1edbc 20
AnnaBridge 171:3a7713b1edbc 21 #if defined (DEVICE_QSPI) || defined(DOXYGEN_ONLY)
AnnaBridge 171:3a7713b1edbc 22
AnnaBridge 171:3a7713b1edbc 23 #include "hal/qspi_api.h"
AnnaBridge 171:3a7713b1edbc 24 #include "platform/PlatformMutex.h"
AnnaBridge 171:3a7713b1edbc 25 #include "platform/SingletonPtr.h"
AnnaBridge 171:3a7713b1edbc 26 #include "platform/NonCopyable.h"
AnnaBridge 171:3a7713b1edbc 27
AnnaBridge 171:3a7713b1edbc 28 #define ONE_MHZ 1000000
AnnaBridge 171:3a7713b1edbc 29
AnnaBridge 171:3a7713b1edbc 30 namespace mbed {
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 /** \addtogroup drivers */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 /** A QSPI Driver, used for communicating with QSPI slave devices
AnnaBridge 171:3a7713b1edbc 35 *
AnnaBridge 171:3a7713b1edbc 36 * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
AnnaBridge 171:3a7713b1edbc 37 * Most QSPI devices will also require Chip Select which is indicated by ssel.
AnnaBridge 171:3a7713b1edbc 38 *
AnnaBridge 171:3a7713b1edbc 39 * @note Synchronization level: Thread safe
AnnaBridge 171:3a7713b1edbc 40 *
AnnaBridge 171:3a7713b1edbc 41 * Example:
AnnaBridge 171:3a7713b1edbc 42 * @code
AnnaBridge 171:3a7713b1edbc 43 * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
AnnaBridge 171:3a7713b1edbc 44 *
AnnaBridge 171:3a7713b1edbc 45 * #include "mbed.h"
AnnaBridge 171:3a7713b1edbc 46 *
AnnaBridge 171:3a7713b1edbc 47 * #define CMD_WRITE 0x02
AnnaBridge 171:3a7713b1edbc 48 * #define CMD_READ 0x03
AnnaBridge 171:3a7713b1edbc 49 * #define ADDRESS 0x1000
AnnaBridge 171:3a7713b1edbc 50 *
AnnaBridge 171:3a7713b1edbc 51 * // hardware ssel (where applicable)
AnnaBridge 171:3a7713b1edbc 52 * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
AnnaBridge 171:3a7713b1edbc 53 *
AnnaBridge 171:3a7713b1edbc 54 *
AnnaBridge 171:3a7713b1edbc 55 * int main() {
AnnaBridge 171:3a7713b1edbc 56 * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
AnnaBridge 171:3a7713b1edbc 57 * char rx_buf[4];
AnnaBridge 171:3a7713b1edbc 58 * int buf_len = sizeof(tx_buf);
AnnaBridge 171:3a7713b1edbc 59 *
AnnaBridge 171:3a7713b1edbc 60 * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
AnnaBridge 171:3a7713b1edbc 61 * if (result != QSPI_STATUS_OK) {
AnnaBridge 171:3a7713b1edbc 62 * printf("Write failed");
AnnaBridge 171:3a7713b1edbc 63 * }
AnnaBridge 171:3a7713b1edbc 64 * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
AnnaBridge 171:3a7713b1edbc 65 * if (result != QSPI_STATUS_OK) {
AnnaBridge 171:3a7713b1edbc 66 * printf("Read failed");
AnnaBridge 171:3a7713b1edbc 67 * }
AnnaBridge 171:3a7713b1edbc 68 *
AnnaBridge 171:3a7713b1edbc 69 * }
AnnaBridge 171:3a7713b1edbc 70 * @endcode
AnnaBridge 171:3a7713b1edbc 71 * @ingroup drivers
AnnaBridge 171:3a7713b1edbc 72 */
AnnaBridge 171:3a7713b1edbc 73 class QSPI : private NonCopyable<QSPI> {
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 public:
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /** Create a QSPI master connected to the specified pins
AnnaBridge 171:3a7713b1edbc 78 *
AnnaBridge 171:3a7713b1edbc 79 * io0-io3 is used to specify the Pins used for Quad SPI mode
AnnaBridge 171:3a7713b1edbc 80 *
AnnaBridge 171:3a7713b1edbc 81 * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 82 * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 83 * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 84 * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
AnnaBridge 171:3a7713b1edbc 85 * @param sclk QSPI Clock pin
AnnaBridge 171:3a7713b1edbc 86 * @param ssel QSPI chip select pin
AnnaBridge 171:3a7713b1edbc 87 * @param mode Clock polarity and phase mode (0 - 3) of SPI
AnnaBridge 171:3a7713b1edbc 88 * (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
AnnaBridge 171:3a7713b1edbc 89 *
AnnaBridge 171:3a7713b1edbc 90 */
AnnaBridge 171:3a7713b1edbc 91 QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
AnnaBridge 171:3a7713b1edbc 92 virtual ~QSPI()
AnnaBridge 171:3a7713b1edbc 93 {
AnnaBridge 171:3a7713b1edbc 94 }
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 /** Configure the data transmission format
AnnaBridge 171:3a7713b1edbc 97 *
AnnaBridge 171:3a7713b1edbc 98 * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 99 * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 100 * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
AnnaBridge 171:3a7713b1edbc 101 * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 102 * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
AnnaBridge 171:3a7713b1edbc 103 * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
AnnaBridge 171:3a7713b1edbc 104 * @param dummy_cycles Number of dummy clock cycles to be used after alt phase
AnnaBridge 171:3a7713b1edbc 105 *
AnnaBridge 171:3a7713b1edbc 106 */
AnnaBridge 171:3a7713b1edbc 107 qspi_status_t configure_format(qspi_bus_width_t inst_width,
AnnaBridge 171:3a7713b1edbc 108 qspi_bus_width_t address_width,
AnnaBridge 171:3a7713b1edbc 109 qspi_address_size_t address_size,
AnnaBridge 171:3a7713b1edbc 110 qspi_bus_width_t alt_width,
AnnaBridge 171:3a7713b1edbc 111 qspi_alt_size_t alt_size,
AnnaBridge 171:3a7713b1edbc 112 qspi_bus_width_t data_width,
AnnaBridge 171:3a7713b1edbc 113 int dummy_cycles);
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /** Set the qspi bus clock frequency
AnnaBridge 171:3a7713b1edbc 116 *
AnnaBridge 171:3a7713b1edbc 117 * @param hz SCLK frequency in hz (default = 1MHz)
AnnaBridge 171:3a7713b1edbc 118 * @returns
AnnaBridge 171:3a7713b1edbc 119 * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
AnnaBridge 171:3a7713b1edbc 120 */
AnnaBridge 171:3a7713b1edbc 121 qspi_status_t set_frequency(int hz = ONE_MHZ);
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 /** Read from QSPI peripheral with the preset read_instruction and alt_value
AnnaBridge 171:3a7713b1edbc 124 *
AnnaBridge 171:3a7713b1edbc 125 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 126 * @param rx_buffer Buffer for data to be read from the peripheral
AnnaBridge 171:3a7713b1edbc 127 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
AnnaBridge 171:3a7713b1edbc 128 *
AnnaBridge 171:3a7713b1edbc 129 * @returns
AnnaBridge 171:3a7713b1edbc 130 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 131 */
AnnaBridge 171:3a7713b1edbc 132 qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 /** Write to QSPI peripheral using custom write instruction
AnnaBridge 171:3a7713b1edbc 135 *
AnnaBridge 171:3a7713b1edbc 136 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 137 * @param tx_buffer Buffer containing data to be sent to peripheral
AnnaBridge 171:3a7713b1edbc 138 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
AnnaBridge 171:3a7713b1edbc 139 *
AnnaBridge 171:3a7713b1edbc 140 * @returns
AnnaBridge 171:3a7713b1edbc 141 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 142 */
AnnaBridge 171:3a7713b1edbc 143 qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 /** Read from QSPI peripheral using custom read instruction, alt values
AnnaBridge 171:3a7713b1edbc 146 *
AnnaBridge 171:3a7713b1edbc 147 * @param instruction Instruction value to be used in instruction phase
AnnaBridge 171:3a7713b1edbc 148 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
AnnaBridge 171:3a7713b1edbc 149 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 150 * @param rx_buffer Buffer for data to be read from the peripheral
AnnaBridge 171:3a7713b1edbc 151 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
AnnaBridge 171:3a7713b1edbc 152 *
AnnaBridge 171:3a7713b1edbc 153 * @returns
AnnaBridge 171:3a7713b1edbc 154 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 155 */
AnnaBridge 171:3a7713b1edbc 156 qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /** Write to QSPI peripheral using custom write instruction, alt values
AnnaBridge 171:3a7713b1edbc 159 *
AnnaBridge 171:3a7713b1edbc 160 * @param instruction Instruction value to be used in instruction phase
AnnaBridge 171:3a7713b1edbc 161 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
AnnaBridge 171:3a7713b1edbc 162 * @param address Address to be accessed in QSPI peripheral
AnnaBridge 171:3a7713b1edbc 163 * @param tx_buffer Buffer containing data to be sent to peripheral
AnnaBridge 171:3a7713b1edbc 164 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
AnnaBridge 171:3a7713b1edbc 165 *
AnnaBridge 171:3a7713b1edbc 166 * @returns
AnnaBridge 171:3a7713b1edbc 167 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169 qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /** Perform a transaction to write to an address(a control register) and get the status results
AnnaBridge 171:3a7713b1edbc 172 *
AnnaBridge 171:3a7713b1edbc 173 * @param instruction Instruction value to be used in instruction phase
AnnaBridge 171:3a7713b1edbc 174 * @param address Some instruction might require address. Use -1 if no address
AnnaBridge 171:3a7713b1edbc 175 * @param tx_buffer Buffer containing data to be sent to peripheral
AnnaBridge 171:3a7713b1edbc 176 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
AnnaBridge 171:3a7713b1edbc 177 * @param rx_buffer Buffer for data to be read from the peripheral
AnnaBridge 171:3a7713b1edbc 178 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
AnnaBridge 171:3a7713b1edbc 179 *
AnnaBridge 171:3a7713b1edbc 180 * @returns
AnnaBridge 171:3a7713b1edbc 181 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
AnnaBridge 171:3a7713b1edbc 182 */
AnnaBridge 171:3a7713b1edbc 183 qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 #if !defined(DOXYGEN_ONLY)
AnnaBridge 171:3a7713b1edbc 186 protected:
AnnaBridge 171:3a7713b1edbc 187 /** Acquire exclusive access to this SPI bus
AnnaBridge 171:3a7713b1edbc 188 */
AnnaBridge 171:3a7713b1edbc 189 virtual void lock(void);
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /** Release exclusive access to this SPI bus
AnnaBridge 171:3a7713b1edbc 192 */
AnnaBridge 171:3a7713b1edbc 193 virtual void unlock(void);
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 qspi_t _qspi;
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 bool acquire(void);
AnnaBridge 171:3a7713b1edbc 198 static QSPI *_owner;
AnnaBridge 171:3a7713b1edbc 199 static SingletonPtr<PlatformMutex> _mutex;
AnnaBridge 171:3a7713b1edbc 200 qspi_bus_width_t _inst_width; //Bus width for Instruction phase
AnnaBridge 171:3a7713b1edbc 201 qspi_bus_width_t _address_width; //Bus width for Address phase
AnnaBridge 171:3a7713b1edbc 202 qspi_address_size_t _address_size;
AnnaBridge 171:3a7713b1edbc 203 qspi_bus_width_t _alt_width; //Bus width for Alt phase
AnnaBridge 171:3a7713b1edbc 204 qspi_alt_size_t _alt_size;
AnnaBridge 171:3a7713b1edbc 205 qspi_bus_width_t _data_width; //Bus width for Data phase
AnnaBridge 171:3a7713b1edbc 206 qspi_command_t _qspi_command; //QSPI Hal command struct
AnnaBridge 171:3a7713b1edbc 207 unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
AnnaBridge 171:3a7713b1edbc 208 int _hz; //Bus Frequency
AnnaBridge 171:3a7713b1edbc 209 int _mode; //SPI mode
AnnaBridge 171:3a7713b1edbc 210 bool _initialized;
AnnaBridge 171:3a7713b1edbc 211 PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 private:
AnnaBridge 171:3a7713b1edbc 214 /* Private acquire function without locking/unlocking
AnnaBridge 171:3a7713b1edbc 215 * Implemented in order to avoid duplicate locking and boost performance
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217 bool _acquire(void);
AnnaBridge 171:3a7713b1edbc 218 bool _initialize();
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /*
AnnaBridge 171:3a7713b1edbc 221 * This function builds the qspi command struct to be send to Hal
AnnaBridge 171:3a7713b1edbc 222 */
AnnaBridge 171:3a7713b1edbc 223 inline void _build_qspi_command(int instruction, int address, int alt);
AnnaBridge 171:3a7713b1edbc 224 #endif
AnnaBridge 171:3a7713b1edbc 225 };
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 } // namespace mbed
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 #endif
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 #endif