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vendor/NXP/LPC812/hal/gpio_api.c@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "gpio_api.h"
emilmont 10:3bc89ef62ce7 17 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 static int gpio_enabled = 0;
emilmont 10:3bc89ef62ce7 20 static void gpio_enable(void) {
emilmont 10:3bc89ef62ce7 21 gpio_enabled = 1;
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 /* Enable AHB clock to the GPIO domain. */
emilmont 10:3bc89ef62ce7 24 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
emilmont 10:3bc89ef62ce7 27 LPC_SYSCON->PRESETCTRL &= ~(0x1<<10);
emilmont 10:3bc89ef62ce7 28 LPC_SYSCON->PRESETCTRL |= (0x1<<10);
emilmont 10:3bc89ef62ce7 29 }
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 uint32_t gpio_set(PinName pin) {
emilmont 10:3bc89ef62ce7 32 int f = 0;
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 if (!gpio_enabled)
emilmont 10:3bc89ef62ce7 35 gpio_enable();
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 pin_function(pin, f);
emilmont 10:3bc89ef62ce7 38
emilmont 10:3bc89ef62ce7 39 return (1 << ((int)pin & 0x1F));
emilmont 10:3bc89ef62ce7 40 }
emilmont 10:3bc89ef62ce7 41
emilmont 10:3bc89ef62ce7 42 void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
emilmont 10:3bc89ef62ce7 43 if(pin == NC) return;
emilmont 10:3bc89ef62ce7 44
emilmont 10:3bc89ef62ce7 45 obj->pin = pin;
emilmont 10:3bc89ef62ce7 46 obj->mask = gpio_set(pin);
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 obj->reg_set = &LPC_GPIO_PORT->SET0;
emilmont 10:3bc89ef62ce7 49 obj->reg_clr = &LPC_GPIO_PORT->CLR0;
emilmont 10:3bc89ef62ce7 50 obj->reg_in = &LPC_GPIO_PORT->PIN0;
emilmont 10:3bc89ef62ce7 51 obj->reg_dir = &LPC_GPIO_PORT->DIR0;
emilmont 10:3bc89ef62ce7 52
emilmont 10:3bc89ef62ce7 53 gpio_dir(obj, direction);
emilmont 10:3bc89ef62ce7 54 switch (direction) {
emilmont 10:3bc89ef62ce7 55 case PIN_OUTPUT: pin_mode(pin, PullNone); break;
emilmont 10:3bc89ef62ce7 56 case PIN_INPUT : pin_mode(pin, PullDown); break;
emilmont 10:3bc89ef62ce7 57 }
emilmont 10:3bc89ef62ce7 58 }
emilmont 10:3bc89ef62ce7 59
emilmont 10:3bc89ef62ce7 60 void gpio_mode(gpio_t *obj, PinMode mode) {
emilmont 10:3bc89ef62ce7 61 pin_mode(obj->pin, mode);
emilmont 10:3bc89ef62ce7 62 }
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64 void gpio_dir(gpio_t *obj, PinDirection direction) {
emilmont 10:3bc89ef62ce7 65 switch (direction) {
emilmont 10:3bc89ef62ce7 66 case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
emilmont 10:3bc89ef62ce7 67 case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
emilmont 10:3bc89ef62ce7 68 }
emilmont 10:3bc89ef62ce7 69 }