Diff: targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c

Revision:

324:406fd2029f23

Parent:

149:1fb5f62b92bd

--- a/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c	Mon Sep 15 15:30:06 2014 +0100
+++ b/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c	Thu Sep 18 14:00:17 2014 +0100
@@ -35,173 +35,53 @@
  ******************************************************************************/
 
 /*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
  * Code
  ******************************************************************************/
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_master_init
- * Description   : Configure the DSPI peripheral in master mode.
- * This function will initialize the module to user defined settings and default settings in master
- * mode.  Here is an example demonstrating how to define the dspi_master_config_t structure and call
- * the dspi_hal_master_init function:
- *    dspi_master_config_t dspiConfig;
- *    dspiConfig.isEnabled = false;
- *    dspiConfig.whichCtar = kDspiCtar0;
- *    dspiConfig.bitsPerSec = 0;
- *    dspiConfig.sourceClockInHz = dspiSourceClock;
- *    dspiConfig.isSckContinuous = false;
- *    dspiConfig.whichPcs = kDspiPcs0;
- *    dspiConfig.pcsPolarity = kDspiPcs_ActiveLow;
- *    dspiConfig.masterInSample = kDspiSckToSin_0Clock;
- *    dspiConfig.isModifiedTimingFormatEnabled = false;
- *    dspiConfig.isTxFifoDisabled = false;
- *    dspiConfig.isRxFifoDisabled = false;
- *    dspiConfig.dataConfig.bitsPerFrame = 16;
- *    dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
- *    dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
- *    dspiConfig.dataConfig.direction = kDspiMsbFirst;
- *    dspi_hal_master_init(instance, &dspiConfig, calculatedBaudRate);
- *
- *END**************************************************************************/
-dspi_status_t dspi_hal_master_init(uint32_t instance, const dspi_master_config_t * config,
-                       uint32_t * calculatedBaudRate)
-{
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
-    /* Enable or disable the module. */
-    /* Note, to enable the module, MDIS must be cleared.  However, the member isEnabled*/
-    /* must be true (1) to enable module, hence we negate the value of isEnabled to properly*/
-    /* configure the MDIS bit*/
-    BW_SPI_MCR_MDIS(instance, ~(config->isEnabled == true));
-
-    /* Configure baud rate if a value is provided.*/
-    if (config->bitsPerSec != 0U)
-    {
-        *calculatedBaudRate = dspi_hal_set_baud(instance, config->whichCtar, config->bitsPerSec,
-                                               config->sourceClockInHz);
-    }
-    else
-    {
-        *calculatedBaudRate = 0;
-    }
-
-    /* Set master or slave mode.*/
-    dspi_hal_set_master_slave(instance, kDspiMaster);
-
-    /* Configure data format.*/
-    if (dspi_hal_configure_data_format(instance, config->whichCtar, &config->dataConfig)
-        != kStatus_DSPI_Success)
-    {
-        return kStatus_DSPI_InvalidBitCount;
-    }
-
-    /* Configure for continuous SCK operation*/
-    dspi_hal_configure_continuous_sck(instance, config->isSckContinuous);
-
-    /* Configure for peripheral chip select polarity*/
-    dspi_hal_configure_pcs_polarity(instance, config->whichPcs,config->pcsPolarity);
-
-    /* Configure sample point for data in, master mode*/
-    dspi_hal_set_datain_samplepoint(instance, config->masterInSample);
-
-    /* Configure for modified timing format*/
-    dspi_hal_configure_modified_timing_format(instance, config->isModifiedTimingFormatEnabled);
-
-    /* Configure for fifo operation*/
-    dspi_hal_configure_fifos(instance, config->isTxFifoDisabled, config->isRxFifoDisabled);
-
-    /* finally, clear the DSPI CONFIGURATION (DCONF), even though this is cleared in some IPs*/
-    /* by default and other bit settings are reserved*/
-    HW_SPI_MCR_CLR(instance, BM_SPI_MCR_DCONF);
-
-    return kStatus_DSPI_Success;
-}
-
-/*FUNCTION**********************************************************************
- *
- * Function Name : dspi_hal_slave_init
- * Description   : Configure the DSPI peripheral in slave mode.
- * This function initializes the DSPI module for slave mode. Here is an example demonstrating how
- * to define the dspi_slave_config_t structure and call the dspi_hal_slave_init function:
- *    dspi_slave_config_t dspiConfig;
- *    dspiConfig.isEnabled = false;
- *    dspiConfig.isTxFifoDisabled = false;
- *    dspiConfig.isRxFifoDisabled = false;
- *    dspiConfig.dataConfig.bitsPerFrame = 16;
- *    dspiConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
- *    dspiConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
- *    dspi_hal_slave_init(instance, &dspiConfig);
- *
- *END**************************************************************************/
-dspi_status_t dspi_hal_slave_init(uint32_t instance, const dspi_slave_config_t * config)
-{
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
-    /* Enable or disable the module.
-     * Note, to enable the module, MDIS must be cleared.  However, the member isEnabled
-     * must be true (1) to enable module, hence we negate the value of isEnabled to properly
-     * configure the MDIS bit
-     */
-    BW_SPI_MCR_MDIS(instance, ~(config->isEnabled == true));
-
-    /* Set master or slave moe. */
-    dspi_hal_set_master_slave(instance, kDspiSlave);
-
-    /* Configure data format. For slave mode, only CTAR0 is available for use */
-    if (dspi_hal_configure_data_format(instance, kDspiCtar0, &config->dataConfig)
-        != kStatus_DSPI_Success)
-    {
-        return kStatus_DSPI_InvalidBitCount;
-    }
-
-    /* Configure for fifo operation */
-    dspi_hal_configure_fifos(instance, config->isTxFifoDisabled, config->isRxFifoDisabled);
-
-    /* finally, clear the DSPI CONFIGURATION (DCONF), even though this is cleared in some IPs
-     * by default and other bit settings are reserved
-     */
-    HW_SPI_MCR_CLR(instance, BM_SPI_MCR_DCONF);
-
-    return kStatus_DSPI_Success;
-}
-
-/*FUNCTION**********************************************************************
- *
- * Function Name : dspi_hal_reset
+ * Function Name : DSPI_HAL_Init
  * Description   : Restore DSPI to reset configuration.
  * This function basically resets all of the DSPI registers to their default setting including
  * disabling the module.
  *
  *END**************************************************************************/
-void dspi_hal_reset(uint32_t instance)
+void DSPI_HAL_Init(uint32_t baseAddr)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     /* first, make sure the module is enabled to allow writes to certain registers*/
-    dspi_hal_enable(instance);
+    DSPI_HAL_Enable(baseAddr);
 
     /* Halt all transfers*/
-    HW_SPI_MCR_WR(instance, BM_SPI_MCR_HALT);
-
-    /* flush the fifos*/
-    dspi_hal_flush_fifos(instance, true, true);
+    DSPI_HAL_StopTransfer(baseAddr);
 
     /* set the registers to their default states*/
     /* clear the status bits (write-1-to-clear)*/
-    HW_SPI_SR_WR(instance, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF | BM_SPI_SR_TFFF |
-                           BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
-    HW_SPI_TCR_WR(instance, 0);
-    HW_SPI_CTARn_WR(instance, 0, 0); /* CTAR0*/
-    HW_SPI_CTARn_WR(instance, 1, 0); /* CTAR1*/
-    HW_SPI_RSER_WR(instance, 0);
-    /* disable the module*/
-    HW_SPI_MCR_WR(instance, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
+    HW_SPI_SR_WR(baseAddr, BM_SPI_SR_TCF | BM_SPI_SR_EOQF | BM_SPI_SR_TFUF |
+                                          BM_SPI_SR_TFFF | BM_SPI_SR_RFOF | BM_SPI_SR_RFDF);
+    HW_SPI_TCR_WR(baseAddr, 0);
+    HW_SPI_CTARn_WR(baseAddr, 0, 0x78000000); /* CTAR0*/
+    HW_SPI_CTARn_WR(baseAddr, 1, 0x78000000); /* CTAR1*/
+    HW_SPI_RSER_WR(baseAddr, 0);
+
+    /* Clear out PUSHR register. Since DSPI is halted, nothing should be transmitted. Be
+     * sure the flush the FIFOs afterwards
+     */
+    HW_SPI_PUSHR_WR(baseAddr, 0);
+
+    /* flush the fifos*/
+    DSPI_HAL_SetFlushFifoCmd(baseAddr, true, true);
+
+    /* Now set MCR to default value, which disables module: set MDIS and HALT, clear other bits */
+    HW_SPI_MCR_WR(baseAddr, BM_SPI_MCR_MDIS | BM_SPI_MCR_HALT);
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_set_baud
+ * Function Name : DSPI_HAL_SetBaudRate
  * Description   : Set the DSPI baud rate in bits per second.
  * This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
  * possible baud rate without exceeding the desired baud rate, and will return the calculated
@@ -209,13 +89,11 @@
  * module source clock (in Hz).
  *
  *END**************************************************************************/
-uint32_t dspi_hal_set_baud(uint32_t instance, dspi_ctar_selection_t whichCtar, uint32_t bitsPerSec,
-                        uint32_t sourceClockInHz)
+uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
+                              uint32_t bitsPerSec, uint32_t sourceClockInHz)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     /* for master mode configuration, if slave mode detected, return 0*/
-    if (HW_SPI_MCR(instance).B.MSTR != 1)
+    if (!DSPI_HAL_IsMaster(baseAddr))
     {
         return 0;
     }
@@ -264,14 +142,10 @@
         }
     }
 
-    uint32_t temp;
     /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
-    temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
-    temp &= ~(BM_SPI_CTARn_DBR| BM_SPI_CTARn_PBR | BM_SPI_CTARn_BR);
-    temp |= BF_SPI_CTARn_DBR(bestDbr - 1) |
-            BF_SPI_CTARn_PBR(bestPrescaler) |
-            BF_SPI_CTARn_BR(bestScaler);
-    HW_SPI_CTARn_WR(instance, whichCtar, temp);
+    BW_SPI_CTARn_DBR(baseAddr, whichCtar, (bestDbr - 1));
+    BW_SPI_CTARn_PBR(baseAddr, whichCtar, bestPrescaler);
+    BW_SPI_CTARn_BR(baseAddr, whichCtar, bestScaler);
 
     /* return the actual calculated baud rate*/
     return bestBaudrate;
@@ -279,49 +153,40 @@
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_set_baud_divisors
+ * Function Name : DSPI_HAL_SetBaudDivisors
  * Description   : Configure the baud rate divisors manually.
  * This function allows the caller to manually set the baud rate divisors in the event that
- * these dividers are known and the caller does not wish to call the dspi_hal_set_baud function.
+ * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
  *
  *END**************************************************************************/
-void dspi_hal_set_baud_divisors(uint32_t instance,
-                                dspi_ctar_selection_t whichCtar,
-                                const dspi_baud_rate_divisors_t * divisors)
+void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
+                              dspi_ctar_selection_t whichCtar,
+                              const dspi_baud_rate_divisors_t * divisors)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
-    uint32_t temp;
-
     /* these settings are only relevant in master mode*/
-    if (HW_SPI_MCR(instance).B.MSTR == 1)
+    if (DSPI_HAL_IsMaster(baseAddr))
     {
-        temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
-        temp &= ~(BM_SPI_CTARn_DBR | BM_SPI_CTARn_PBR | BM_SPI_CTARn_BR); /* clear dividers*/
-        temp |= BF_SPI_CTARn_DBR(divisors->doubleBaudRate) |
-                BF_SPI_CTARn_PBR(divisors->prescaleDivisor) |
-                BF_SPI_CTARn_BR(divisors->baudRateDivisor);
-        HW_SPI_CTARn_WR(instance, whichCtar, temp);
+        BW_SPI_CTARn_DBR(baseAddr, whichCtar, divisors->doubleBaudRate);
+        BW_SPI_CTARn_PBR(baseAddr, whichCtar, divisors->prescaleDivisor);
+        BW_SPI_CTARn_BR(baseAddr, whichCtar, divisors->baudRateDivisor);
     }
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_configure_pcs_polarity
+ * Function Name : DSPI_HAL_SetPcsPolarityMode
  * Description   : Configure DSPI peripheral chip select polarity.
  * This function will take in the desired peripheral chip select (PCS) and it's
  * corresponding desired polarity and will configure the PCS signal to operate with the
  * desired characteristic.
  *
  *END**************************************************************************/
-void dspi_hal_configure_pcs_polarity(uint32_t instance, dspi_which_pcs_config_t pcs,
-                                     dspi_pcs_polarity_config_t activeLowOrHigh)
+void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
+                                 dspi_pcs_polarity_config_t activeLowOrHigh)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     uint32_t temp;
 
-    temp = BR_SPI_MCR_PCSIS(instance);
+    temp = BR_SPI_MCR_PCSIS(baseAddr);
 
     if (activeLowOrHigh == kDspiPcs_ActiveLow)
     {
@@ -332,60 +197,59 @@
         temp &= ~(unsigned)pcs;
     }
 
-    BW_SPI_MCR_PCSIS(instance, temp);
+    BW_SPI_MCR_PCSIS(baseAddr, temp);
 }
 
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_configure_fifos
- * Description   : Configure DSPI fifos.
+ * Function Name : DSPI_HAL_SetFifoCmd
+ * Description   : Enables (or disables) the DSPI FIFOs.
  * This function with allow the caller to disable/enable the TX and RX FIFOs (independently).
- * Note that to disable, the caller must pass in a logic 1 (true) for the particular FIFO
- * configuration.  To enable, the caller must pass in a logic 0 (false).  For example, to enable
- * both the TX and RX FIFOs, the caller will make this function call (where instance is the
+ * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
+ * configuration.  To enable, the caller must pass in a logic 1 (true).
  *
  *END**************************************************************************/
-void dspi_hal_configure_fifos(uint32_t instance, bool disableTxFifo, bool disableRxFifo)
+void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     /* first see if MDIS is set or cleared */
-    uint32_t isMdisSet = HW_SPI_MCR(instance).B.MDIS;
+    uint32_t isMdisSet = BR_SPI_MCR_MDIS(baseAddr);
 
     if (isMdisSet)
     {
-        /* clear the MDIS bit to allow us to write to the fifo disables */
-        HW_SPI_MCR_CLR(instance, BM_SPI_MCR_MDIS);
+        /* clear the MDIS bit (enable DSPI) to allow us to write to the fifo disables */
+        DSPI_HAL_Enable(baseAddr);
     }
 
-    BW_SPI_MCR_DIS_TXF(instance, (disableTxFifo == true));
-    BW_SPI_MCR_DIS_RXF(instance, (disableRxFifo == true));
+    /* Note, the bit definition is "disable FIFO", so a "1" would disable. If user wants to enable
+     * the FIFOs, they pass in true, which we must logically negate (turn to false) to enable the
+     * FIFO
+     */
+    BW_SPI_MCR_DIS_TXF(baseAddr, ~(enableTxFifo == true));
+    BW_SPI_MCR_DIS_RXF(baseAddr, ~(enableRxFifo == true));
 
-    /* set MDIS if it was set to begin with */
+    /* set MDIS (disable DSPI) if it was set to begin with */
     if (isMdisSet)
     {
-        HW_SPI_MCR_SET(instance, BM_SPI_MCR_MDIS);
+        DSPI_HAL_Disable(baseAddr);
     }
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_flush_fifos
+ * Function Name : DSPI_HAL_SetFlushFifoCmd
  * Description   : Flush DSPI fifos.
  *
  *END**************************************************************************/
-void dspi_hal_flush_fifos(uint32_t instance, bool enableFlushTxFifo, bool enableFlushRxFifo)
+void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
-    BW_SPI_MCR_CLR_TXF(instance, (enableFlushTxFifo == true));
-    BW_SPI_MCR_CLR_RXF(instance, (enableFlushRxFifo == true));
+    BW_SPI_MCR_CLR_TXF(baseAddr, (enableFlushTxFifo == true));
+    BW_SPI_MCR_CLR_RXF(baseAddr, (enableFlushRxFifo == true));
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_configure_data_format
+ * Function Name : DSPI_HAL_SetDataFormat
  * Description   : Configure the data format for a particular CTAR.
  * This function configures the bits-per-frame, polarity, phase, and shift direction for a
  * particular CTAR. An example use case is as follows:
@@ -394,169 +258,267 @@
  *    dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
  *    dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
  *    dataFormat.direction = kDspiMsbFirst;
- *    dspi_hal_configure_data_format(instance, kDspiCtar0, &dataFormat);
+ *    DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &dataFormat);
  *
  *END**************************************************************************/
-dspi_status_t dspi_hal_configure_data_format(uint32_t instance,
-                                        dspi_ctar_selection_t whichCtar,
-                                        const dspi_data_format_config_t * config)
+dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
+                                     dspi_ctar_selection_t whichCtar,
+                                     const dspi_data_format_config_t * config)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     /* check bits-per-frame value to make sure it it within the proper range*/
     /* in either master or slave mode*/
     if ((config->bitsPerFrame < 4) ||
-        ((config->bitsPerFrame > 16) && (HW_SPI_MCR(instance).B.MSTR == 1)) ||
-        ((config->bitsPerFrame > 32) && (HW_SPI_MCR(instance).B.MSTR == 0)))
+        ((config->bitsPerFrame > 16) && (HW_SPI_MCR(baseAddr).B.MSTR == 1)) ||
+        ((config->bitsPerFrame > 32) && (HW_SPI_MCR(baseAddr).B.MSTR == 0)))
     {
         return kStatus_DSPI_InvalidBitCount;
     }
 
-    uint32_t temp;
-
     /* for master mode configuration*/
-    if (HW_SPI_MCR(instance).B.MSTR == 1)
+    if (DSPI_HAL_IsMaster(baseAddr))
     {
-        temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
-        temp &= ~(BM_SPI_CTARn_FMSZ| BM_SPI_CTARn_CPOL | BM_SPI_CTARn_CPHA | BM_SPI_CTARn_LSBFE);
-        temp |= BF_SPI_CTARn_FMSZ(config->bitsPerFrame - 1) |
-                BF_SPI_CTARn_CPOL(config->clkPolarity) |
-                BF_SPI_CTARn_CPHA(config->clkPhase) |
-                BF_SPI_CTARn_LSBFE(config->direction);
-        HW_SPI_CTARn_WR(instance, whichCtar, temp);
+        BW_SPI_CTARn_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
+        BW_SPI_CTARn_CPOL(baseAddr, whichCtar, config->clkPolarity);
+        BW_SPI_CTARn_CPHA(baseAddr, whichCtar, config->clkPhase);
+        BW_SPI_CTARn_LSBFE(baseAddr, whichCtar, config->direction);
     }
     else /* for slave mode configuration*/
     {
-        temp = HW_SPI_CTARn_SLAVE_RD(instance, whichCtar); /* save register contents*/
-        temp &= ~(BM_SPI_CTARn_SLAVE_FMSZ| BM_SPI_CTARn_SLAVE_CPOL | BM_SPI_CTARn_SLAVE_CPHA);
-        temp |= BF_SPI_CTARn_SLAVE_FMSZ(config->bitsPerFrame - 1) |
-                BF_SPI_CTARn_SLAVE_CPOL(config->clkPolarity) |
-                BF_SPI_CTARn_SLAVE_CPHA(config->clkPhase);
-        HW_SPI_CTARn_SLAVE_WR(instance, whichCtar, temp);
+        BW_SPI_CTARn_SLAVE_FMSZ(baseAddr, whichCtar, (config->bitsPerFrame - 1));
+        BW_SPI_CTARn_SLAVE_CPOL(baseAddr, whichCtar, config->clkPolarity);
+        BW_SPI_CTARn_SLAVE_CPHA(baseAddr, whichCtar, config->clkPhase);
     }
     return kStatus_DSPI_Success;
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_configure_delays
- * Description   : Configure the delays for a particular CTAR, master mode only.
- * This function configures the PCS to SCK delay prescalar (PCSSCK),
- * the PCS to SCK Delay scalar (CSSCK),
- * the After SCK delay prescalar (PASC),
- * the After SCK delay scalar (ASC),
- * the Delay after transfer prescalar (PDT),
- * and the Delay after transfer scalar (DT).
- * The following is an example use case of this function:
- *    dspi_delay_settings_config_t delayConfig;
- *    delayConfig.pcsToSckPre = 0x3;
- *    delayConfig.pcsToSck = 0xF;
- *    delayConfig.afterSckPre = 0x2;
- *    delayConfig.afterSck = 0xA;
- *    delayConfig.afterTransferPre = 0x1;
- *    delayConfig.afterTransfer = 0x5;
- *    dspi_hal_configure_delays(instance, kDspiCtar0, &delayConfig);
+ * Function Name : DSPI_HAL_SetDelay
+ * Description   : Manually configures the delay prescaler and scaler for a particular CTAR.
+ * This function configures the:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
+ * After SCK delay pre-scalar (PASC) and scalar (ASC),
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
  *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the prescaler and scaler value.
+ * This basically allows the user to directly set the prescaler/scaler values if they have
+ * pre-calculated them or if they simply wish to manually increment either value.
  *END**************************************************************************/
-void dspi_hal_configure_delays(uint32_t instance,
-                               dspi_ctar_selection_t whichCtar,
-                               const dspi_delay_settings_config_t * config)
+void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
+                       uint32_t scaler, dspi_delay_type_t whichDelay)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
-    uint32_t temp;
-
     /* these settings are only relevant in master mode*/
-    if (HW_SPI_MCR(instance).B.MSTR == 1)
+    if (DSPI_HAL_IsMaster(baseAddr))
     {
-        temp = HW_SPI_CTARn_RD(instance, whichCtar); /* save register contents*/
-        temp &= ~(BM_SPI_CTARn_PCSSCK | BM_SPI_CTARn_PASC | BM_SPI_CTARn_PDT |
-                  BM_SPI_CTARn_CSSCK| BM_SPI_CTARn_ASC | BM_SPI_CTARn_DT);
-        temp |= BF_SPI_CTARn_PCSSCK(config->pcsToSckPre) |
-                BF_SPI_CTARn_PASC(config->afterSckPre) |
-                BF_SPI_CTARn_PDT(config->afterTransferPre) |
-                BF_SPI_CTARn_CSSCK(config->pcsToSck) |
-                BF_SPI_CTARn_ASC(config->afterSck) |
-                BF_SPI_CTARn_DT(config->afterTransfer);
-        HW_SPI_CTARn_WR(instance, whichCtar, temp);
+        if (whichDelay == kDspiPcsToSck)
+        {
+            BW_SPI_CTARn_PCSSCK(baseAddr, whichCtar, prescaler);
+            BW_SPI_CTARn_CSSCK(baseAddr, whichCtar, scaler);
+        }
+
+        if (whichDelay == kDspiLastSckToPcs)
+        {
+            BW_SPI_CTARn_PASC(baseAddr, whichCtar, prescaler);
+            BW_SPI_CTARn_ASC(baseAddr, whichCtar, scaler);
+        }
+
+        if (whichDelay == kDspiAfterTransfer)
+        {
+            BW_SPI_CTARn_PDT(baseAddr, whichCtar, prescaler);
+            BW_SPI_CTARn_DT(baseAddr, whichCtar, scaler);
+        }
     }
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_configure_dma
- * Description   : Configure transmit and receive DMA requests.
- * This function configures the FIFOs to generate a DMA or interrupt request. Note that the
- * corresponding request enable must also be set.  For the Transmit FIFO Fill, in order
- * to generate a DMA request, the Transmit FIFO Fill Request Enable (TFFF_RE) must also be set.
- * Similarly for the Receive FIFO Drain Request, to generate a DMA request, the Receive FIFO Drain
- * Request Enable (RFDF_RE) must also be set.  These request enables can be configured via
- * the function dspi_hal_configure_interrupt().  So basically to enable DMA operation, first enable
- * the desired request enable using the dspi_hal_configure_interrupt() function and then use
- * the dspi_hal_configure_dma() to configure the request to generate a DMA reuqest.
+ * Function Name : DSPI_HAL_CalculateDelay
+ * Description   : Calculates the delay prescaler and scaler based on desired delay input in
+ *                 nano-seconds.
+ *
+ * This function calculates the values for:
+ * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
+ * After SCK delay pre-scalar (PASC) and scalar (ASC), or
+ * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ *
+ * These delay names are available in type dspi_delay_type_t.
+ *
+ * The user passes which delay they want to configure along with the desired delay value in
+ * nano-seconds.  The function will calculate the values needed for the prescaler and scaler and
+ * will return the actual calculated delay as an exact delay match may not be acheivable. In this
+ * case, the closest match will be calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay will be returned. It will be up to the higher level
+ * peripheral driver to alert the user of an out of range delay input.
+ *END**************************************************************************/
+uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
+                                 dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
+                                 uint32_t delayInNanoSec)
+{
+    /* for master mode configuration, if slave mode detected, return 0*/
+    if (!DSPI_HAL_IsMaster(baseAddr))
+    {
+        return 0;
+    }
+
+    uint32_t prescaler, bestPrescaler;
+    uint32_t scaler, bestScaler;
+    uint32_t realDelay, bestDelay;
+    uint32_t diff, min_diff;
+    uint32_t initialDelayNanoSec;
+
+    /* find combination of prescaler and scaler resulting in the delay closest to the
+     * requested value
+     */
+    min_diff = 0xFFFFFFFFU;
+    /* Initialize prescaler and scaler to their max values to generate the max delay */
+    bestPrescaler = 0x3;
+    bestScaler = 0xF;
+    bestDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[bestPrescaler] *
+                 s_delayScaler[bestScaler];
+
+    /* First calculate the initial, default delay */
+    initialDelayNanoSec = 1000000000/sourceClockInHz * 2;
+
+    /* If the initial, default delay is already greater than the desired delay, then
+     * set the delays to their initial value (0) and return the delay. In other words,
+     * there is no way to decrease the delay value further.
+     */
+    if (initialDelayNanoSec >= delayInNanoSec)
+    {
+        DSPI_HAL_SetDelay(baseAddr, whichCtar, 0, 0, whichDelay);
+        return initialDelayNanoSec;
+    }
+
+
+    /* In all for loops, if min_diff = 0, the exit for loop*/
+    for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
+    {
+        for (scaler = 0; (scaler < 16) && min_diff; scaler++)
+        {
+            realDelay = (1000000000/sourceClockInHz) * s_delayPrescaler[prescaler] *
+                         s_delayScaler[scaler];
+
+            /* calculate the delay difference based on the conditional statement
+             * that states that the calculated delay must not be less then the desired delay
+             */
+            if (realDelay >= delayInNanoSec)
+            {
+                diff = realDelay-delayInNanoSec;
+                if (min_diff > diff)
+                {
+                    /* a better match found */
+                    min_diff = diff;
+                    bestPrescaler = prescaler;
+                    bestScaler = scaler;
+                    bestDelay = realDelay;
+                }
+            }
+        }
+    }
+
+    /* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
+    DSPI_HAL_SetDelay(baseAddr, whichCtar, bestPrescaler, bestScaler, whichDelay);
+
+    /* return the actual calculated baud rate*/
+    return bestDelay;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetTxFifoFillDmaIntMode
+ * Description   : Configures the DSPI Tx FIFO Fill request to generate DMA or interrupt requests.
+ * This function configures the DSPI Tx FIFO Fill flag to generate either
+ * an interrupt or DMA request.  The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
+ *
+ *  DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
+ *  DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
+ *  DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
  *
  *END**************************************************************************/
-void dspi_hal_configure_dma(uint32_t instance, bool enableTransmit, bool enableReceive)
+void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
-    BW_SPI_RSER_TFFF_DIRS(instance, enableTransmit);
-    BW_SPI_RSER_RFDF_DIRS(instance, enableReceive);
+    BW_SPI_RSER_TFFF_DIRS(baseAddr, mode);  /* Configure as DMA or interrupt */
+    BW_SPI_RSER_TFFF_RE(baseAddr, (enable == true));  /* Enable or disable the request */
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_configure_interrupt
- * Description   : Configure DSPI interrupts.
- * This function will configure the various interrupt sources of the DSPI.  The parameters to pass
- * in are instance, interrupt source, and enable/disable setting.
- * The interrupt source will be of a typedef enum whose value will be the bit position of the
- * interrupt source setting within the RSER register.  In the DSPI, all of the interrupt
- * configuration settings reside within the one register.  The typedef enum will equate each
- * interrupt source to the bit position defined in the device header file.
- * The function will use these bit positions in its algorithm to enable/disable the
- * interrupt source, where interrupt source is of type dspi_status_and_interrupt_request_t.
- *    temp = (HW_SPI_RSER_RD(instance) & ~interruptSrc) | (enable << interruptSrc);
- *    HW_SPI_RSER_WR(instance, temp);
+ * Function Name : DSPI_HAL_SetRxFifoDrainDmaIntMode
+ * Description   : Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
+ * This function configures the DSPI Rx FIFO Drain flag to generate either
+ * an interrupt or DMA request.  The user passes in which request they'd like to generate
+ * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
+ * Note, when disabling the request, the request type is don't care.
  *
- *    dspi_hal_configure_interrupt(instance, kDspiTxComplete, true); <- example use-case
+ *  DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
+ *  DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
+ *  DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
  *
  *END**************************************************************************/
-void dspi_hal_configure_interrupt(uint32_t instance,
+void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable)
+{
+    BW_SPI_RSER_RFDF_DIRS(baseAddr, mode);  /* Configure as DMA or interrupt */
+    BW_SPI_RSER_RFDF_RE(baseAddr, (enable == true));  /* Enable or disable the request */
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_SetIntMode
+ * Description   : Configure DSPI interrupts.
+ * This function configures the various interrupt sources of the DSPI.  The parameters are
+ * baseAddr, interrupt source, and enable/disable setting.
+ * The interrupt source is a typedef enum whose value is the bit position of the
+ * interrupt source setting within the RSER register.  In the DSPI, all interrupt
+ * configuration settings are in  one register.  The typedef enum  equates each
+ * interrupt source to the bit position defined in the device header file.
+ * The function  uses these bit positions in its algorithm to enable/disable the
+ * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
+ * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
+ * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
+ * these requests can generate either an interrupt or DMA request.
+ *
+ *   DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
+ *
+ *END**************************************************************************/
+void DSPI_HAL_SetIntMode(uint32_t baseAddr,
                                   dspi_status_and_interrupt_request_t interruptSrc,
                                   bool enable)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     uint32_t temp;
 
-    temp = (HW_SPI_RSER_RD(instance) & ~(0x1U << interruptSrc)) | ((uint32_t)enable << interruptSrc);
-    HW_SPI_RSER_WR(instance, temp);
+    temp = (HW_SPI_RSER_RD(baseAddr) & ~(0x1U << interruptSrc)) |
+                          ((uint32_t)enable << interruptSrc);
+    HW_SPI_RSER_WR(baseAddr, temp);
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_get_fifo_data
+ * Function Name : DSPI_HAL_GetFifoData
  * Description   : Read fifo registers for debug purposes.
  *
  *END**************************************************************************/
-uint32_t dspi_hal_get_fifo_data(uint32_t instance, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
+uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     if (whichFifo == kDspiTxFifo)
     {
-        return HW_SPI_TXFRn_RD(instance, whichFifoEntry);
+        return HW_SPI_TXFRn_RD(baseAddr, whichFifoEntry);
     }
     else
     {
-        return HW_SPI_RXFRn_RD(instance, whichFifoEntry);
+        return HW_SPI_RXFRn_RD(baseAddr, whichFifoEntry);
     }
 }
 
 /*FUNCTION**********************************************************************
  *
- * Function Name : dspi_hal_write_data_master_mode
+ * Function Name : DSPI_HAL_WriteDataMastermode
  * Description   : Write data into the data buffer, master mode.
  * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
  * provides characteristics of the data being sent such as: optional continuous chip select
@@ -570,17 +532,16 @@
  *    commandConfig.whichPcs = kDspiPcs1;
  *    commandConfig.clearTransferCount = false;
  *    commandConfig.isEndOfQueue = false;
- *    dspi_hal_write_data_master_mode(instance, &commandConfig, dataWord);
+ *    DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
  *
  *END**************************************************************************/
-void dspi_hal_write_data_master_mode(uint32_t instance,
-                                     dspi_command_config_t * command,
-                                     uint16_t data)
+void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
+                                  dspi_command_config_t * command,
+                                  uint16_t data)
 {
-    assert(instance < HW_SPI_INSTANCE_COUNT);
-
     uint32_t temp;
 
+    /* First, build up the 32-bit word then write it to the PUSHR */
     temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
            BF_SPI_PUSHR_CTAS(command->whichCtar) |
            BF_SPI_PUSHR_PCS(command->whichPcs) |
@@ -588,7 +549,53 @@
            BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
            BF_SPI_PUSHR_TXDATA(data);
 
-    HW_SPI_PUSHR_WR(instance, temp);
+    HW_SPI_PUSHR_WR(baseAddr, temp);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DSPI_HAL_WriteDataMastermode
+ * Description   : Write data into the data buffer, master mode and waits till complete to return.
+ * In master mode, the 16-bit data is appended with the 16-bit command info. The command portion
+ * provides characteristics of the data being sent such as: optional continuous chip select
+ * operation between transfers, the desired Clock and Transfer Attributes register to use for the
+ * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
+ * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
+ * sending the first frame of a data packet). An example use case is as follows:
+ *    dspi_command_config_t commandConfig;
+ *    commandConfig.isChipSelectContinuous = true;
+ *    commandConfig.whichCtar = kDspiCtar0;
+ *    commandConfig.whichPcs = kDspiPcs1;
+ *    commandConfig.clearTransferCount = false;
+ *    commandConfig.isEndOfQueue = false;
+ *    DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
+ *
+ * Note that this function will not return until after the transmit is complete. Also note that
+ * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
+ * Since the SPI is a synchronous protocol, receive data will be available when transmit completes.
+ *
+ *END**************************************************************************/
+void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
+                                          dspi_command_config_t * command,
+                                          uint16_t data)
+{
+    uint32_t temp;
+
+    /* First, clear Transmit Complete Flag (TCF) */
+    BW_SPI_SR_TCF(baseAddr, 1);
+
+    /* First, build up the 32-bit word then write it to the PUSHR */
+    temp = BF_SPI_PUSHR_CONT(command->isChipSelectContinuous) |
+           BF_SPI_PUSHR_CTAS(command->whichCtar) |
+           BF_SPI_PUSHR_PCS(command->whichPcs) |
+           BF_SPI_PUSHR_EOQ(command->isEndOfQueue) |
+           BF_SPI_PUSHR_CTCNT(command->clearTransferCount) |
+           BF_SPI_PUSHR_TXDATA(data);
+
+    HW_SPI_PUSHR_WR(baseAddr, temp);
+
+    /* Wait till TCF sets */
+    while(BR_SPI_SR_TCF(baseAddr) == 0) { }
 }
 
 /*******************************************************************************