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Last commit 20 Feb 2019 by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.c
- Revision:
- 369:2e96f1b71984
- Parent:
- 226:b062af740e40
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.c Mon Oct 27 08:00:06 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.c Mon Oct 27 09:45:07 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nand.c
* @author MCD Application Team
- * @version V1.1.0RC2
- * @date 14-May-2014
+ * @version V1.1.0
+ * @date 19-June-2014
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -330,17 +330,17 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x90;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
/* Read the electronic signature from NAND flash */
data = *(__IO uint32_t *)deviceAddress;
/* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data);
+ pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data);
+ pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data);
+ pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data);
+ pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -410,7 +410,7 @@
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0;
- uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
+ uint32_t deviceAddress = 0, numPagesRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -434,33 +434,30 @@
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize)))
+ /* Page(s) read loop */
+ while((NumPageToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
{
- /* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
+ /* NAND raw address calculation */
+ nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr > 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for(; index < size; index++)
+ for(index = 0 ; index < hnand->Info.PageSize; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
}
@@ -472,7 +469,7 @@
NumPageToRead--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
+ HAL_NAND_Address_Inc(hnand, pAddress);
}
@@ -497,9 +494,9 @@
*/
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
- __IO uint32_t index = 0;
- uint32_t timeout = 0;
- uint32_t deviceAddress = 0, size = 0 , numPagesWritten = 0, nandAddress = 0;
+ __IO uint32_t index = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceAddress = 0 , numPagesWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -523,45 +520,42 @@
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
-
/* Page(s) write loop */
- while((NumPageToWrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize)))
+ while((NumPageToWrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
{
- /* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
+ /* NAND raw address calculation */
+ nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr > 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
}
/* Write data to memory */
- for(; index < size; index++)
+ for(index = 0 ; index < hnand->Info.PageSize; index++)
{
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Check for timeout value */
- timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -574,7 +568,7 @@
NumPageToWrite--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
+ HAL_NAND_Address_Inc(hnand, pAddress);
}
@@ -600,7 +594,7 @@
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
+ uint32_t deviceAddress = 0, numSpareAreaRead = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -622,36 +616,32 @@
}
/* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ hnand->State = HAL_NAND_STATE_BUSY;
/* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize)))
- {
-
- /* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaRead);
-
+ while((NumSpareAreaToRead != 0) && (addressStatus == NAND_VALID_ADDRESS))
+ {
+ /* NAND raw address calculation */
+ nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
+
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
+
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr > 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
- for ( ;index < size; index++)
+ for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
}
@@ -663,7 +653,7 @@
NumSpareAreaToRead--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
+ HAL_NAND_Address_Inc(hnand, pAddress);
}
/* Update the NAND controller state */
@@ -687,8 +677,8 @@
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
- uint32_t timeout = 0;
- uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceAddress = 0, numSpareAreaWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -710,48 +700,45 @@
}
/* Update the FMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ hnand->State = HAL_NAND_STATE_BUSY;
/* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize)))
+ while((NumSpareAreaTowrite != 0) && (addressStatus == NAND_VALID_ADDRESS))
{
- /* update the buffer size */
- size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaWritten);
-
+ /* NAND raw address calculation */
+ nandAddress = __ARRAY_ADDRESS(pAddress, hnand);
+
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress);
}
/* Write data to memory */
- for(; index < size; index++)
+ for(index = 0 ; index < hnand->Info.SpareAreaSize; index++)
{
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10;
+ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Check for timeout value */
- timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -764,7 +751,7 @@
NumSpareAreaTowrite--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
+ HAL_NAND_Address_Inc(hnand, pAddress);
}
@@ -811,19 +798,19 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x60;
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
}
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0xD0;
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -857,7 +844,7 @@
}
/* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x70;
+ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
data = *(__IO uint8_t *)DeviceAddress;
