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Last commit 20 Feb 2019 by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h
- Revision:
- 489:119543c9f674
- Parent:
- 382:ee426a420dbb
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h Thu Mar 05 13:15:07 2015 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h Thu Mar 12 14:30:49 2015 +0000
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 18-June-2014
+ * @version V1.2.0
+ * @date 06-February-2015
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -101,66 +101,66 @@
section in Reference manual */
} SMBUS_InitTypeDef;
-/**
- * @brief HAL State structures definition
+/** @defgroup SMBUS_State SMBUS State
+ * @brief HAL States definition
+ * @{
+ */
+
+#define HAL_SMBUS_STATE_RESET 0x00 /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY 0x01 /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY 0x02 /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX 0x12 /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX 0x22 /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX 0x32 /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX 0x42 /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT 0x03 /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR 0x04 /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_LISTEN 0x08 /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Error_Code SMBUS Error Code
+ * @brief SMBUS Error Code
+ * @{
*/
-typedef enum
-{
- HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */
- HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */
- HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */
- HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
- HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
- HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
- HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
- HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */
- HAL_SMBUS_STATE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */
-/* Aliases for inter STM32 series compatibility */
- HAL_SMBUS_STATE_SLAVE_LISTEN = HAL_SMBUS_STATE_LISTEN
-}HAL_SMBUS_StateTypeDef;
-
+#define HAL_SMBUS_ERROR_NONE 0x00 /*!< No error */
+#define HAL_SMBUS_ERROR_BERR 0x01 /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO 0x02 /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF 0x04 /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR 0x08 /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT 0x10 /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT 0x20 /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT 0x40 /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR 0x80 /*!< PEC error */
/**
- * @brief HAL SMBUS Error Code structure definition
- */
-typedef enum
-{
- HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */
- HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */
- HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */
- HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */
- HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */
- HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */
- HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */
- HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */
- HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */
-
-}HAL_SMBUS_ErrorTypeDef;
+ * @}
+ */
/**
* @brief SMBUS handle Structure definition
*/
typedef struct
{
- I2C_TypeDef *Instance; /*!< SMBUS registers base address */
-
- SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
-
- uint16_t XferSize; /*!< SMBUS transfer size */
-
- __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
+
+ SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< SMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< SMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous tate */
+
+ HAL_LockTypeDef Lock; /*!< SMBUS locking object */
+
+ __IO uint32_t State; /*!< SMBUS communication state */
- __IO uint32_t XferOptions; /*!< SMBUS transfer options */
-
- __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */
-
- HAL_LockTypeDef Lock; /*!< SMBUS locking object */
-
- __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
-
- __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code , see SMBUS_Error_Code */
}SMBUS_HandleTypeDef;
@@ -173,11 +173,11 @@
/** @defgroup SMBUS_Analog_Filter
* @{
*/
-#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
-#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
+#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
-#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
- ((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
/**
* @}
*/
@@ -198,11 +198,11 @@
* @{
*/
-#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
+#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
-#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
- ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
/**
* @}
*/
@@ -236,11 +236,11 @@
/** @defgroup SMBUS_general_call_addressing_mode
* @{
*/
-#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN
+#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
-#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
- ((CALL) == SMBUS_GENERALCALL_ENABLED))
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLE))
/**
* @}
*/
@@ -248,11 +248,11 @@
/** @defgroup SMBUS_nostretch_mode
* @{
*/
-#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
+#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
- ((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
/**
* @}
*/
@@ -260,11 +260,11 @@
/** @defgroup SMBUS_packet_error_check_mode
* @{
*/
-#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_PEC_ENABLED I2C_CR1_PECEN
+#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
-#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \
- ((PEC) == SMBUS_PEC_ENABLED))
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
+ ((PEC) == SMBUS_PEC_ENABLE))
/**
* @}
*/
@@ -487,17 +487,17 @@
#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
-#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define __SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define __SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+#define __SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
-#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
-#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
-#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+#define __SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
+#define __SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define __SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define __SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define __SMBUS_GET_ALERT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
@@ -516,7 +516,7 @@
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
/* Aliases for inter STM32 series compatibility */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_EnableListen_IT
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
@@ -538,14 +538,14 @@
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
/* Aliases for inter STM32 series compatibility */
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+#define HAL_SMBUS_AddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_ListenCpltCallback
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
/* Peripheral State and Errors functions *************************************/
-HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
@@ -563,3 +563,5 @@
#endif /* __STM32L0xx_HAL_SMBUS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
