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Last commit 20 Feb 2019 by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h
- Revision:
- 489:119543c9f674
- Parent:
- 382:ee426a420dbb
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h Thu Mar 05 13:15:07 2015 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h Thu Mar 12 14:30:49 2015 +0000
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 18-June-2014
+ * @version V1.2.0
+ * @date 06-February-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup RCCEx
+/** @defgroup RCCEx
* @{
*/
@@ -58,7 +58,7 @@
/**
* @brief RCC extended clocks structure definition
*/
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -74,9 +74,17 @@
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
+#if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+#endif
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCCEx_RTC_Clock_Source */
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+#endif
uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
@@ -85,16 +93,18 @@
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
-#endif /* !(STM32L051xx) && !(STM32L061xx) */
+
-#if defined(STM32L051xx) || defined(STM32L061xx)
+#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+#if !defined (STM32L031xx) && !defined (STM32L041xx)
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
-
+#endif
uint32_t Usart2ClockSelection; /*!< USART2 clock source
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
@@ -104,30 +114,41 @@
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
+#if defined (STM32L071xx) || defined(STM32L081xx)
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+#endif
+
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
- This parameter can be a value of @ref RCCEx_RTC_Clock_Source */
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t LptimClockSelection; /*!< LPTIM1 clock source
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32L051xx || STM32L061xx */
+
+#endif /* STM32L0x1xx */
+
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+/** @defgroup RCCEx_Exported_Constants
+ * @{
+ */
/**
- * @brief RCC CRS Status structures definition
+ * @brief RCC CRS Status definition
*/
-typedef enum
-{
- RCC_CRS_NONE = 0x00,
- RCC_CRS_TIMEOUT = 0x01,
- RCC_CRS_SYNCOK = 0x02,
- RCC_CRS_SYNCWARM = 0x04,
- RCC_CRS_SYNCERR = 0x08,
- RCC_CRS_SYNCMISS = 0x10,
- RCC_CRS_TRIMOV = 0x20
-} RCC_CRSStatusTypeDef;
+#define RCC_CRS_NONE ((uint32_t) 0x00000000)
+#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
+#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
+#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
+#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
+#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
+#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
+
+/**
+ * @}
+ */
/**
* @brief RCC_CRS Init structure definition
*/
@@ -175,17 +196,18 @@
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
}RCC_CRSSynchroInfoTypeDef;
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants
+/** @addtogroup RCCEx_Exported_Constants
* @{
*/
/** @defgroup RCCEx_Periph_Clock_Selection
* @{
*/
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
@@ -194,31 +216,67 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
-
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
+#endif
+#if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
+#endif
-#define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
-#endif /* !(STM32L051xx) && !(STM32L061xx) */
+#if defined (STM32L052xx) || defined(STM32L062xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
+#elif defined (STM32L053xx) || defined(STM32L063xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
+#elif defined (STM32L072xx) || defined(STM32L082xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 ))
+#elif defined (STM32L073xx) || defined(STM32L083xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LCD))
+#endif
-#if defined(STM32L051xx) || defined(STM32L061xx)
+#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+
+#if !defined(STM32L031xx) && !defined(STM32L041xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#endif
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
+#if !defined(STM32L031xx) && !defined(STM32L041xx)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
+#endif
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
-
+#if defined(STM32L071xx) || defined(STM32L081xx)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
+#endif
-#define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_LPTIM1))
-#endif /* !(STM32L051xx) && !(STM32L061xx) */
+#if defined(STM32L031xx) || defined(STM32L041xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC ))
+#elif defined(STM32L051xx) || defined(STM32L061xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_LPTIM1))
+#elif defined(STM32L071xx) || defined(STM32L081xx)
+#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
+#endif
+
+#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
/**
* @}
*/
-
+
/** @defgroup RCCEx_USART1_Clock_Source
* @{
*/
@@ -226,10 +284,10 @@
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
/**
* @}
*/
@@ -241,10 +299,10 @@
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
/**
* @}
*/
@@ -256,10 +314,10 @@
#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
/**
* @}
*/
@@ -270,9 +328,26 @@
#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
-#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
- ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
+
+/** @defgroup RCCEx_I2C3_Clock_Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
+#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+#endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
+
/**
* @}
*/
@@ -286,15 +361,15 @@
* @}
*/
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/** @defgroup RCCEx_USB_Clock_Source
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
#define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
- ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
/**
* @}
*/
@@ -305,8 +380,8 @@
#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
-#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48) || \
- ((SOURCE) == RCC_RNGCLKSOURCE_PLLCLK))
+#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
+ ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
/**
* @}
*/
@@ -314,16 +389,39 @@
/** @defgroup RCCEx_HSI48M_Clock_Source
* @{
*/
+#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
-#define RCC_HSI48M_RC48 RCC_CCIPR_HSI48SEL
+#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
-#define IS_RCC_HSI48MCLKSOURCE(HSI48MCLK) (((HSI48MCLK) == RCC_HSI48M_PLL) || ((HSI48MCLK) == RCC_HSI48M_RC48))
+#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
/**
* @}
*/
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+/** @defgroup RCC_HSI_Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint8_t)0x00)
+#define RCC_HSI_ON RCC_CR_HSION
+#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
+
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
+ ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))
+#else
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
+ ((__HSI__) == RCC_HSI_DIV4))
+#endif
+
+/**
+ * @}
+ */
/** @defgroup RCCEx_LPTIM1_Clock_Source
* @{
@@ -333,10 +431,10 @@
#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
-#define IS_RCC_LPTIMCLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_PCLK) || \
- ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSI) || \
- ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_HSI) || \
- ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSE))
+#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
+ ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \
+ ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
/**
* @}
*/
@@ -345,11 +443,11 @@
* @{
*/
-#define RCC_StopWakeUpClock_MSI ((uint32_t)0x00)
-#define RCC_StopWakeUpClock_HSI RCC_CFGR_STOPWUCK
+#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
+#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
-#define IS_RCC_STOPWAKEUP_CLOCK(SOURCE) (((SOURCE) == RCC_StopWakeUpClock_MSI) || \
- ((SOURCE) == RCC_StopWakeUpClock_HSI))
+#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
+ ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
/**
* @}
*/
@@ -362,13 +460,13 @@
#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
- ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((DRIVE) == RCC_LSEDRIVE_HIGH))
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
/**
* @}
*/
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/** @defgroup RCCEx_CRS_SynchroSource
* @{
*/
@@ -376,9 +474,9 @@
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) ||\
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
/**
* @}
*/
@@ -395,10 +493,10 @@
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) ||\
- ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
+#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\
+ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
/**
* @}
*/
@@ -409,8 +507,8 @@
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
/**
* @}
*/
@@ -421,7 +519,7 @@
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
/**
* @}
*/
@@ -431,7 +529,7 @@
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
-#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
/**
* @}
*/
@@ -443,7 +541,7 @@
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
-#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
/**
* @}
*/
@@ -454,8 +552,8 @@
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
-#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
- ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
/**
* @}
*/
@@ -490,13 +588,13 @@
* @}
*/
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros
+/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
* @{
*/
@@ -506,18 +604,41 @@
* using it.
*/
-#if defined(STM32L062xx) || defined(STM32L063xx)
-#define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN))
-#define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
-#endif /* STM32L062xx || STM32L063xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
+#define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN))
+#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN))
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
-#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+/** @brief Enable or disable the IOPORT peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN))
-#define __RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
+
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx */
/** @brief Enable or disable the APB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
@@ -525,150 +646,260 @@
* using it.
*/
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
-#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
-#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-#if defined(STM32L053xx) || defined(STM32L063xx)
-#define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
-#define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
-#endif /* STM32L053xx || STM32L063xx */
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+#define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
+#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
+#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
#if defined(STM32L053xx) || defined(STM32L063xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || \
defined(STM32L051xx) || defined(STM32L061xx)
-#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32L051xx || STM32L061xx || */
+ /* STM32L052xx || STM32L062xx || */
+ /* STM32L053xx || STM32L063xx || */
+
+#if defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32L031xx || STM32L041xx || */
+
-#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
-#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
-#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
-#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
-#define __LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
-#endif /* STM32L051xx || STM32L061xx || */
- /* STM32L052xx || STM32L062xx || */
- /* STM32L053xx || STM32L063xx || */
-
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx */
+
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
+ defined(STM32L031xx) || defined(STM32L041xx)
+
/** @brief Enable or disable the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
+#define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN))
+#define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN))
+#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN))
+#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-#if defined(STM32L053xx) || defined(STM32L063xx) || \
- defined(STM32L052xx) || defined(STM32L062xx) || \
- defined(STM32L051xx) || defined(STM32L061xx)
-#define __TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN))
-#define __TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN))
-#define __FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN))
-#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-
-#define __TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
-#define __TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
-#define __FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
-#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
-#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
-#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
-#endif /* STM32L051xx || STM32L061xx || */
- /* STM32L052xx || STM32L062xx || */
- /* STM32L053xx || STM32L063xx || */
+#define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
+#define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
+#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
+#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
+ /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
+ /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
/** @brief Force or release AHB peripheral reset.
*/
-#if defined(STM32L062xx) || defined(STM32L063xx)
-#define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST))
-#define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
-#endif /* STM32L062xx || STM32L063xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
+#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST))
+#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
-#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
-#define __RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST))
-#define __RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+/** @brief Force or release IOPORT peripheral reset.
+ */
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
+
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx */
+
/** @brief Force or release APB1 peripheral reset.
*/
+
#if defined(STM32L053xx) || defined(STM32L063xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || \
- defined(STM32L051xx) || defined(STM32L061xx)
-#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
-#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+ defined(STM32L051xx) || defined(STM32L061xx)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
-#define __LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
-#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
-#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
#endif /* STM32L051xx || STM32L061xx || */
/* STM32L052xx || STM32L062xx || */
- /* STM32L053xx || STM32L063xx || */
-
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+ /* STM32L053xx || STM32L063xx */
+#if defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
+#endif /* STM32L031xx || STM32L041xx || */
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
-#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
-
-#if defined(STM32L053xx) || defined(STM32L063xx)
-#define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
-#define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
-#endif /* STM32L053xx || STM32L063xx */
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-/** @brief Force or release APB2 peripheral reset.
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx || */
+
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
+#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
+#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
+
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
+ /** @brief Force or release APB2 peripheral reset.
*/
-#if defined(STM32L053xx) || defined(STM32L063xx) || \
- defined(STM32L052xx) || defined(STM32L062xx) || \
- defined(STM32L051xx) || defined(STM32L061xx)
-#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST))
-#define __TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST))
+#define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST))
-#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
-#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
-#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
-#define __TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
-#define __TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
-#endif /* STM32L051xx || STM32L061xx || */
- /* STM32L052xx || STM32L062xx || */
- /* STM32L053xx || STM32L063xx || */
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
+#define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
+#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
+ /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
+ /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -677,18 +908,34 @@
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN))
-#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN))
-#define __TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
-#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN))
+#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-#if defined(STM32L062xx) || defined(STM32L063xx)
-#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN))
-#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
-#endif /* STM32L062xx || STM32L063xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN))
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOESMEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
+
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx || */
/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -699,66 +946,101 @@
#if defined(STM32L053xx) || defined(STM32L063xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || \
- defined(STM32L051xx) || defined(STM32L061xx)
-#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
-#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
-#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
-#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
-#define __LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
-#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
-#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
-#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
-#define __LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
+ defined(STM32L051xx) || defined(STM32L061xx)
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
-#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
-#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
-#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
-#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
-#define __LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
-#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
-#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
-#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
-#define __LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
#endif /* STM32L051xx || STM32L061xx || */
/* STM32L052xx || STM32L062xx || */
- /* STM32L053xx || STM32L063xx || */
+ /* STM32L053xx || STM32L063xx */
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
-#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN))
-#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM3SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM7SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART4SMEN))
+#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART5SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C3SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
-#define __CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN))
-#define __CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
+#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx || */
+
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN))
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN))
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-#if defined(STM32L053xx) || defined(STM32L063xx)
-#define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN))
-#define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
-#endif /* STM32L053xx || STM32L063xx */
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN))
+#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
+#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
*/
-#if defined(STM32L053xx) || defined(STM32L063xx) || \
- defined(STM32L052xx) || defined(STM32L062xx) || \
- defined(STM32L051xx) || defined(STM32L061xx)
-#define __TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN))
-#define __TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN))
-#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN))
-#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN))
-#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN))
+#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN))
+#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN))
-#define __TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
-#define __TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
-#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
-#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
-#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
-#endif /* STM32L051xx || STM32L061xx || */
- /* STM32L052xx || STM32L062xx || */
- /* STM32L053xx || STM32L063xx || */
+#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
+#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
+#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
+ /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
+ /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
/** @brief macro to configure the I2C1 clock (I2C1CLK).
*
@@ -779,6 +1061,32 @@
*/
#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
+#if defined (STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+/** @brief macro to configure the I2C3 clock (I2C3CLK).
+ *
+ * @param __I2C3CLKSource__: specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
+
+/** @brief macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
+
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx || */
+
/** @brief macro to configure the USART1 clock (USART1CLK).
*
* @param __USART1CLKSource__: specifies the USART1 clock source.
@@ -863,7 +1171,7 @@
*/
#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
* This parameter can be one of the following values:
@@ -904,7 +1212,7 @@
* USB an RNG peripherals.
* This parameter can be one of the following values:
* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
- * @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator.
+ * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
*/
#define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
@@ -914,10 +1222,10 @@
* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
* @retval The clock source can be one of the following values:
* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
- * @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator.
+ * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
*/
#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
-#endif /* !(STM32L051xx ) && !(STM32L061xx ) */
+#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
/**
* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
@@ -946,14 +1254,14 @@
* @brief Macro to configures the wake up from stop clock.
* @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
* This parameter can be one of the following values:
- * @arg RCC_StopWakeUpClock_MSI: MSI selected as system clock source
- * @arg RCC_StopWakeUpClock_HSI: HSI selected as system clock source
+ * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
+ * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
* @retval None
*/
#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/**
* @brief Enables the specified CRS interrupts.
* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
@@ -978,7 +1286,7 @@
*/
#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
-/** @brief Check the CRS's interrupt has occurred or not.
+/** @brief Check the CRS interrupt has occurred or not.
* @param __INTERRUPT__: specifies the CRS interrupt source to check.
* This parameter can be one of the following values:
* @arg RCC_CRS_IT_SYNCOK
@@ -989,7 +1297,7 @@
*/
#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
-/** @brief Clear the CRS's interrupt pending bits
+/** @brief Clear the CRS interrupt pending bits
* bits to clear the selected interrupt pending bits.
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
@@ -1002,7 +1310,7 @@
* @arg RCC_CRS_IT_SYNCMISS
*/
/* CRS IT Error Mask */
-#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
(CRS->ICR = (__INTERRUPT__)))
@@ -1020,7 +1328,7 @@
* @arg RCC_CRS_FLAG_SYNCMISS
* @retval The new state of _FLAG_ (TRUE or FALSE).
*/
-#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clears the CRS specified FLAG.
@@ -1037,7 +1345,7 @@
*/
/* CRS Flag Error Mask */
-#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
(CRS->ICR = (__FLAG__)))
@@ -1083,27 +1391,84 @@
* @param _FSYNC_ Synchronization signal frequency (value in Hz)
* @retval None
*/
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
+
+#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+/** @brief Enable or disable the HSI OUT .
+ * @note After reset, the HSI output is not available
+ */
+
+#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
+#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
+
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx */
+
+#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) ||\
+ defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx)
-#endif /* !(STM32L051xx) && !(STM32L061xx) */
+/**
+ * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
+ * @note After enabling the HSI48, the application software should wait on
+ * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+ * be used to clock the USB.
+ * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
+ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \
+ SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \
+ } while (0)
+#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
+ SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \
+ } while (0)
+/** @brief Enable or disable the HSI48M DIV6 OUT .
+ * @note After reset, the HSI48Mhz (divided by 6) output is not available
+ */
+#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
+#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
+
+#endif /* STM32L071xx || STM32L081xx || */
+ /* STM32L072xx || STM32L082xx || */
+ /* STM32L073xx || STM32L083xx */
+
/**
* @}
*/
-
-/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+
+ * @{
+ */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_EnableLSECSS(void);
-void HAL_RCCEx_DisableLSECSS(void);
-#if !defined(STM32L051xx) && !defined(STM32L061xx)
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
-RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
-#endif /* !(STM32L051xx) && !(STM32L061xx) */
-
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void HAL_RCCEx_EnableHSI48_VREFINT(void);
+void HAL_RCCEx_DisableHSI48_VREFINT(void);
+#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1119,3 +1484,4 @@
#endif /* __STM32L0xx_HAL_RCC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
