Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c

Revision:

489:119543c9f674

Parent:

382:ee426a420dbb

Child:

520:7182721120da

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c	Thu Mar 05 13:15:07 2015 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c	Thu Mar 12 14:30:49 2015 +0000
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32l0xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    18-June-2014
+  * @version V1.2.0
+  * @date    06-February-2015
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -30,11 +30,31 @@
          (+) Enable the clock for the peripheral(s) to be used
          (+) Configure the clock source(s) for peripherals whose clocks are not
              derived from the System clock (ADC, RTC/LCD, RNG and IWDG)
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]  
+      A delay between an RCC peripheral clock enable and the effective peripheral 
+      enabling should be taken into account in order to manage the peripheral read/write 
+      from/to registeres.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle 
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle 
+          after the clock enable bit is set on the hardware register
+
+    [..]  
+      Possible Workarounds:
+      (#) Enable the peripheral clock sometimes before the peripheral read/write 
+          register is required.
+      (#) For AHB peripheral, insert two dummy read to the peripheral register.
+      (#) For APB peripheral, insert a dummy read to the peripheral register.
+             
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -68,42 +88,48 @@
   * @{
   */
 
-/** @defgroup RCC 
+/** @addtogroup RCC 
   * @brief RCC HAL module driver
   * @{
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
 
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define HSI48_TIMEOUT_VALUE        ((uint32_t)100)  /* 100 ms */
-#define MSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */    
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
+/** @defgroup RCC_Private_Constants RCC Private constants
+  * @{
+  */ 
+#define RCC_HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define RCC_HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define RCC_LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define RCC_PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define RCC_HSI48_TIMEOUT_VALUE        ((uint32_t)100)  /* 100 ms */
+#define RCC_MSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */    
+#define RCC_CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
 
-/* Private macro -------------------------------------------------------------*/
-#define __MCO1_CLK_ENABLE()   __GPIOA_CLK_ENABLE()
+#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
 #define MCO1_GPIO_PORT        GPIOA
 #define MCO1_PIN              GPIO_PIN_8
 #define MCO2_PIN              GPIO_PIN_9
 
-/* Private variables ---------------------------------------------------------*/
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_Private_Vatiables RCC Private Data
+  * @{
+  */ 
 static __IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 static __IO const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000};
 
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */ 
 
-/** @defgroup RCC_Private_Functions
+/** @addtogroup RCC_Exported_Functions
   * @{
   */
 
-/** @defgroup RCC_Group1 Initialization and de-initialization functions 
+/** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 
  *  @brief    Initialization and Configuration functions 
  *
 @verbatim    
@@ -183,28 +209,15 @@
   *           - AHB, APB1 and APB2 prescaler set to 1.
   *           - CSS and MCO OFF
   *           - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
+  * @note   This function does not modify the configuration of the
   * @note      -Peripheral clocks
   * @note      -HSI48, LSI, LSE and RTC clocks                  
   * @param  None
   * @retval None
   */
-void HAL_RCC_DeInit(void)
+__weak void HAL_RCC_DeInit(void)
 {
-  /* Set MSION bit */
-  SET_BIT(RCC->CR, RCC_CR_MSION); 
-  
-  /* Reset HSION, HSEON, CSSON, PLLON */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_CSSHSEON | RCC_CR_PLLON); 
-  
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-  
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-  
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIER); 
+  /* This function is now defined in the file stm32L0xx_rcc_ex.c */
 }
 
 /**
@@ -228,9 +241,9 @@
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE)))
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE)))
     {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
       {
         return HAL_ERROR;
       }
@@ -246,7 +259,7 @@
       /* Wait till HSE is disabled */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
       {
-        if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
@@ -256,7 +269,7 @@
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
       
       /* Check the HSE State */
-      if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
+      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
       {
         /* Get timeout */
         tickstart = HAL_GetTick();
@@ -264,7 +277,7 @@
         /* Wait till HSE is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
         {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -275,10 +288,10 @@
         /* Get timeout */
         tickstart = HAL_GetTick();
       
-        /* Wait till HSE is  bypassed or disabled */  
+        /* Wait till HSE is disabled */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
         {
-           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+           if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -294,7 +307,7 @@
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
     
     /* When the HSI is used as system clock it will not disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI)))
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI)))
     {
       /* When HSI is used as system clock it will not disabled */
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
@@ -322,7 +335,7 @@
         /* Wait till HSI is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
         {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -342,7 +355,7 @@
         /* Wait till HSI is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
         {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -389,7 +402,7 @@
         /* Wait till MSI is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
         {
-          if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -411,7 +424,7 @@
         /* Wait till MSI is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET)
         {
-          if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -437,7 +450,7 @@
       /* Wait till LSI is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
       {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
@@ -454,7 +467,7 @@
       /* Wait till LSI is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
       {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
@@ -462,7 +475,7 @@
     }
   }
   
-  
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)  
    /*------------------------------ HSI48 Configuration -------------------------*/ 
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
   {
@@ -481,7 +494,7 @@
       /* Wait till HSI48 is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
       {
-        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
@@ -498,13 +511,15 @@
       /* Wait till HSI48 is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
       {
-        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
       } 
     }
   }
+#endif /* !(STM32L031xx) && !(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)*/  
+  
   /*------------------------------ LSE Configuration -------------------------*/ 
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
   {
@@ -512,7 +527,7 @@
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 
     /* Enable Power Clock*/
-    __PWR_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
 
     /* Enable write access to Backup domain */
     PWR->CR |= PWR_CR_DBP;
@@ -522,7 +537,7 @@
  
     while((PWR->CR & PWR_CR_DBP) == RESET)
     {
-      if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }
@@ -537,7 +552,7 @@
     /* Wait till LSE is ready */  
     while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
     {
-      if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+      if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }      
@@ -546,7 +561,7 @@
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
     /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
     {     
       /* Get timeout */
       tickstart = HAL_GetTick();
@@ -554,7 +569,7 @@
       /* Wait till LSE is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
       {
-        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
@@ -568,7 +583,7 @@
       /* Wait till LSE is ready */  
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
       {
-        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }      
@@ -581,7 +596,7 @@
   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
   {
     /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
     { 
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
       {
@@ -600,7 +615,7 @@
         /* Wait till PLL is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
         {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -619,7 +634,7 @@
         /* Wait till PLL is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
         {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -635,7 +650,7 @@
         /* Wait till PLL is ready */  
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
         {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }      
@@ -753,9 +768,9 @@
       
       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
       {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           } 
@@ -763,9 +778,9 @@
       }
       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
       {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           } 
@@ -775,7 +790,7 @@
       {
         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           } 
@@ -783,9 +798,9 @@
       }
       else
       {
-        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -852,9 +867,9 @@
       
       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
       {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           } 
@@ -862,9 +877,9 @@
       }
       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
       {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           } 
@@ -874,7 +889,7 @@
       {
         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           } 
@@ -882,9 +897,9 @@
       }
       else
       {
-        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
         {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }  
@@ -927,7 +942,7 @@
   * @}
   */
 
-/** @defgroup RCC_Group2 Peripheral Control functions 
+/** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions 
  *  @brief   RCC clocks control functions 
  *
 @verbatim   
@@ -958,7 +973,9 @@
   *     @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
   *     @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected
   *     @arg RCC_MCO1SOURCE_LSI: LSI clock selected
-  *     @arg RCC_MCO1SOURCE_LSE: LSE clock selected    
+  *     @arg RCC_MCO1SOURCE_LSE: LSE clock selected
+  *     and in STM32L052xx,STM32L053xx,STM32L062xx, STM32L063xx
+  *            STM32L072xx,STM32L073xx,STM32L082xx, STM32L083xx 
   *     @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected
   * @param  RCC_MCODIV: specifies the MCO DIV.
   *     This parameter can be one of the following values: 
@@ -996,7 +1013,7 @@
     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
     
     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource << 24 | RCC_MCODiv )));
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource | RCC_MCODiv )));
 }
 
 /**
@@ -1057,16 +1074,15 @@
  
   /*MSI frequency range in HZ*/
   msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-  msirange = MSIRangeTable[msirange];
   
   switch (RCC->CFGR & RCC_CFGR_SWS)
   {
     case RCC_CFGR_SWS_MSI: /* MSI used as system clock */ 
     {  
-      sysclockfreq = msirange;
+      sysclockfreq = (32768 * (1 << (msirange + 1)));
       break;
     }
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
+    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock */
     {
       if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
       {
@@ -1078,12 +1094,12 @@
       }
       break;
     }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
+    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
     {
       sysclockfreq = HSE_VALUE;
       break;
     }
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
+    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
     {
       /* Get PLL clock source and multiplication factor ----------------------*/
       pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
@@ -1096,7 +1112,14 @@
       if (pllsource == RCC_CFGR_PLLSRC_HSI)
       {
         /* HSI oscillator clock selected as PLL clock source */
-        sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv);
+        if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
+        {
+          sysclockfreq = (HSI_VALUE >> 2) * (pllmul / plldiv);
+        }
+        else 
+        {
+          sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv);
+        }
       }
       else
       {
@@ -1107,7 +1130,7 @@
     }
     default: /* MSI used as system clock */
     {
-      sysclockfreq =  msirange;
+      sysclockfreq = (32768 * (1 << (msirange + 1)));
       break;
     }
   }
@@ -1171,8 +1194,11 @@
 {
   /* Set all possible values for the Oscillator type parameter ---------------*/
   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | \
-                                      RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-  
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+  RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+#endif
+
   /* Get the HSE configuration -----------------------------------------------*/
   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
   {
@@ -1199,7 +1225,8 @@
   
   RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24); 
   RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13); 
-  
+
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)  
   /* Get the HSI48 configuration -----------------------------------------------*/
   if((RCC->CRRCR &RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
   {
@@ -1209,6 +1236,7 @@
   {
     RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
   }
+#endif
   
   /* Get the HSI configuration -----------------------------------------------*/
   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
@@ -1299,10 +1327,10 @@
 void HAL_RCC_NMI_IRQHandler(void)
 {
   /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  if(__HAL_RCC_GET_IT_SOURCE(RCC_IT_CSS))
   {
     /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CCSCallback();
+    HAL_RCC_CSSCallback();
 
     /* Clear RCC CSS pending bit */
     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
@@ -1314,10 +1342,10 @@
   * @param  none 
   * @retval none
   */
-__weak void HAL_RCC_CCSCallback(void)
+__weak void HAL_RCC_CSSCallback(void)
 {
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RCC_CCSCallback could be implemented in the user file
+            the HAL_RCC_CSSCallback could be implemented in the user file
    */ 
 }
 
@@ -1339,3 +1367,4 @@
   */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+