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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h@612:fba1c7dc54c0, 2015-08-18 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Aug 18 15:00:09 2015 +0100
- Revision:
- 612:fba1c7dc54c0
- Parent:
- 592:a274ee790e56
Synchronized with git revision 0d637743c77c4a5e3c30f9636c78d19ec3e10f34
Full URL: https://github.com/mbedmicro/mbed/commit/0d637743c77c4a5e3c30f9636c78d19ec3e10f34/
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_PM_INSTANCE_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_PM_INSTANCE_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========== Register definition for PM peripheral ========== */ |
| mbed_official | 579:53297373a894 | 5 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 6 | #define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ |
| mbed_official | 579:53297373a894 | 7 | #define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ |
| mbed_official | 579:53297373a894 | 8 | #define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ |
| mbed_official | 579:53297373a894 | 9 | #define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ |
| mbed_official | 579:53297373a894 | 10 | #define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ |
| mbed_official | 579:53297373a894 | 11 | #define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ |
| mbed_official | 579:53297373a894 | 12 | #define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ |
| mbed_official | 579:53297373a894 | 13 | #define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ |
| mbed_official | 579:53297373a894 | 14 | #define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ |
| mbed_official | 579:53297373a894 | 15 | #define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ |
| mbed_official | 579:53297373a894 | 16 | #define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 17 | #define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 18 | #define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 19 | #define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ |
| mbed_official | 579:53297373a894 | 20 | #else |
| mbed_official | 579:53297373a894 | 21 | #define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ |
| mbed_official | 579:53297373a894 | 22 | #define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ |
| mbed_official | 579:53297373a894 | 23 | #define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ |
| mbed_official | 579:53297373a894 | 24 | #define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ |
| mbed_official | 579:53297373a894 | 25 | #define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ |
| mbed_official | 579:53297373a894 | 26 | #define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ |
| mbed_official | 579:53297373a894 | 27 | #define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ |
| mbed_official | 579:53297373a894 | 28 | #define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ |
| mbed_official | 579:53297373a894 | 29 | #define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ |
| mbed_official | 579:53297373a894 | 30 | #define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ |
| mbed_official | 579:53297373a894 | 31 | #define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 32 | #define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 33 | #define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 34 | #define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ |
| mbed_official | 579:53297373a894 | 35 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 36 | |
| mbed_official | 579:53297373a894 | 37 | /* ========== Instance parameters for PM peripheral ========== */ |
| mbed_official | 579:53297373a894 | 38 | #define PM_CTRL_MCSEL_DFLL48M 3 |
| mbed_official | 579:53297373a894 | 39 | #define PM_CTRL_MCSEL_GCLK 0 |
| mbed_official | 579:53297373a894 | 40 | #define PM_CTRL_MCSEL_OSC8M 1 |
| mbed_official | 579:53297373a894 | 41 | #define PM_CTRL_MCSEL_XOSC 2 |
| mbed_official | 579:53297373a894 | 42 | #define PM_PM_CLK_APB_NUM 2 |
| mbed_official | 579:53297373a894 | 43 | |
| mbed_official | 579:53297373a894 | 44 | #endif /* _SAMD21_PM_INSTANCE_ */ |
