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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c@482:d9a48e768ce0, 2015-02-27 (annotated)

Committer:
mbed_official
Date:
Fri Feb 27 10:00:08 2015 +0000
Revision:
482:d9a48e768ce0
Parent:
460:3bcf9be0332c
Child:
506:520a30fd3bde
Synchronized with git revision 43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c



Full URL: https://github.com/mbedmicro/mbed/commit/43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c/



RZ/A1H - Modify to support GCC and Fix some bugs of driver.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include "i2c_api.h"
mbed_official 390:35c2c1cf29cd 18 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 19 #include "pinmap.h"
mbed_official 441:d2c15dda23c1 20 #include "r_typedefs.h"
mbed_official 390:35c2c1cf29cd 21
mbed_official 390:35c2c1cf29cd 22 #include "riic_iodefine.h"
mbed_official 422:a032ac66f24e 23 #include "RZ_A1_Init.h"
mbed_official 422:a032ac66f24e 24 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 25
mbed_official 390:35c2c1cf29cd 26 volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 27
mbed_official 390:35c2c1cf29cd 28 #define REG(N) \
mbed_official 390:35c2c1cf29cd 29 RIIC[obj->i2c]->RIICn##N
mbed_official 390:35c2c1cf29cd 30
mbed_official 441:d2c15dda23c1 31 /* RIICnCR1 */
mbed_official 441:d2c15dda23c1 32 #define CR1_RST (1 << 6)
mbed_official 441:d2c15dda23c1 33 #define CR1_ICE (1 << 7)
mbed_official 441:d2c15dda23c1 34
mbed_official 441:d2c15dda23c1 35 /* RIICnCR2 */
mbed_official 441:d2c15dda23c1 36 #define CR2_ST (1 << 1)
mbed_official 460:3bcf9be0332c 37 #define CR2_RS (1 << 2)
mbed_official 441:d2c15dda23c1 38 #define CR2_SP (1 << 3)
mbed_official 460:3bcf9be0332c 39 #define CR2_TRS (1 << 5)
mbed_official 441:d2c15dda23c1 40 #define CR2_BBSY (1 << 7)
mbed_official 441:d2c15dda23c1 41
mbed_official 441:d2c15dda23c1 42 /* RIICnMR3 */
mbed_official 441:d2c15dda23c1 43 #define MR3_ACKBT (1 << 3)
mbed_official 441:d2c15dda23c1 44 #define MR3_ACKWP (1 << 4)
mbed_official 441:d2c15dda23c1 45 #define MR3_WAIT (1 << 6)
mbed_official 441:d2c15dda23c1 46
mbed_official 460:3bcf9be0332c 47 /* RIICnSER */
mbed_official 460:3bcf9be0332c 48 #define SER_SAR0E (1 << 0)
mbed_official 460:3bcf9be0332c 49
mbed_official 460:3bcf9be0332c 50 /* RIICnSR1 */
mbed_official 460:3bcf9be0332c 51 #define SR1_AAS0 (1 << 0)
mbed_official 460:3bcf9be0332c 52
mbed_official 441:d2c15dda23c1 53 /* RIICnSR2 */
mbed_official 460:3bcf9be0332c 54 #define SR2_START (1 << 2)
mbed_official 441:d2c15dda23c1 55 #define SR2_STOP (1 << 3)
mbed_official 441:d2c15dda23c1 56 #define SR2_NACKF (1 << 4)
mbed_official 441:d2c15dda23c1 57 #define SR2_RDRF (1 << 5)
mbed_official 441:d2c15dda23c1 58 #define SR2_TEND (1 << 6)
mbed_official 441:d2c15dda23c1 59 #define SR2_TDRE (1 << 7)
mbed_official 441:d2c15dda23c1 60
mbed_official 441:d2c15dda23c1 61 #define TIMEOUT_1S (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
mbed_official 390:35c2c1cf29cd 62
mbed_official 390:35c2c1cf29cd 63 static const PinMap PinMap_I2C_SDA[] = {
mbed_official 390:35c2c1cf29cd 64 {P1_1 , I2C_0, 1},
mbed_official 390:35c2c1cf29cd 65 {P1_3 , I2C_1, 1},
mbed_official 390:35c2c1cf29cd 66 {P1_7 , I2C_3, 1},
mbed_official 390:35c2c1cf29cd 67 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 68 };
mbed_official 390:35c2c1cf29cd 69
mbed_official 390:35c2c1cf29cd 70 static const PinMap PinMap_I2C_SCL[] = {
mbed_official 390:35c2c1cf29cd 71 {P1_0 , I2C_0, 1},
mbed_official 390:35c2c1cf29cd 72 {P1_2 , I2C_1, 1},
mbed_official 390:35c2c1cf29cd 73 {P1_6 , I2C_3, 1},
mbed_official 390:35c2c1cf29cd 74 {NC , NC, 0}
mbed_official 390:35c2c1cf29cd 75 };
mbed_official 390:35c2c1cf29cd 76
mbed_official 441:d2c15dda23c1 77
mbed_official 390:35c2c1cf29cd 78 static inline int i2c_status(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 79 return REG(SR2.UINT8[0]);
mbed_official 390:35c2c1cf29cd 80 }
mbed_official 390:35c2c1cf29cd 81
mbed_official 441:d2c15dda23c1 82 static void i2c_reg_reset(i2c_t *obj) {
mbed_official 441:d2c15dda23c1 83 /* full reset */
mbed_official 441:d2c15dda23c1 84 REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
mbed_official 441:d2c15dda23c1 85 REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
mbed_official 441:d2c15dda23c1 86 REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
mbed_official 441:d2c15dda23c1 87
mbed_official 441:d2c15dda23c1 88 REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
mbed_official 441:d2c15dda23c1 89 REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
mbed_official 441:d2c15dda23c1 90
mbed_official 441:d2c15dda23c1 91 /* set frequency */
mbed_official 441:d2c15dda23c1 92 REG(MR1.UINT8[0]) |= obj->pclk_bit;
mbed_official 441:d2c15dda23c1 93 REG(BRL.UINT8[0]) = obj->width_low;
mbed_official 441:d2c15dda23c1 94 REG(BRH.UINT8[0]) = obj->width_hi;
mbed_official 441:d2c15dda23c1 95
mbed_official 441:d2c15dda23c1 96 REG(MR2.UINT8[0]) = 0x07;
mbed_official 441:d2c15dda23c1 97 REG(MR3.UINT8[0]) = 0x00;
mbed_official 441:d2c15dda23c1 98
mbed_official 441:d2c15dda23c1 99 REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
mbed_official 441:d2c15dda23c1 100 REG(IER.UINT8[0]) = 0x00; // no interrupt
mbed_official 441:d2c15dda23c1 101
mbed_official 441:d2c15dda23c1 102 REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
mbed_official 441:d2c15dda23c1 103 }
mbed_official 441:d2c15dda23c1 104
mbed_official 460:3bcf9be0332c 105 static inline int i2c_wait_RDRF(i2c_t *obj) {
mbed_official 460:3bcf9be0332c 106 int timeout = 0;
mbed_official 460:3bcf9be0332c 107
mbed_official 460:3bcf9be0332c 108 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 460:3bcf9be0332c 109 while (!(i2c_status(obj) & SR2_RDRF)) {
mbed_official 460:3bcf9be0332c 110 timeout ++;
mbed_official 460:3bcf9be0332c 111 if (timeout >= TIMEOUT_1S) {
mbed_official 460:3bcf9be0332c 112 return -1;
mbed_official 460:3bcf9be0332c 113 }
mbed_official 460:3bcf9be0332c 114 }
mbed_official 460:3bcf9be0332c 115
mbed_official 460:3bcf9be0332c 116 return 0;
mbed_official 460:3bcf9be0332c 117 }
mbed_official 460:3bcf9be0332c 118
mbed_official 441:d2c15dda23c1 119 static int i2c_wait_TDRE(i2c_t *obj) {
mbed_official 409:a95c696104d3 120 int timeout = 0;
mbed_official 409:a95c696104d3 121
mbed_official 441:d2c15dda23c1 122 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 441:d2c15dda23c1 123 while (!(i2c_status(obj) & SR2_TDRE)) {
mbed_official 409:a95c696104d3 124 timeout ++;
mbed_official 441:d2c15dda23c1 125 if (timeout >= TIMEOUT_1S) {
mbed_official 441:d2c15dda23c1 126 return -1;
mbed_official 441:d2c15dda23c1 127 }
mbed_official 441:d2c15dda23c1 128 }
mbed_official 441:d2c15dda23c1 129
mbed_official 441:d2c15dda23c1 130 return 0;
mbed_official 441:d2c15dda23c1 131 }
mbed_official 441:d2c15dda23c1 132
mbed_official 441:d2c15dda23c1 133 static int i2c_wait_TEND(i2c_t *obj) {
mbed_official 441:d2c15dda23c1 134 int timeout = 0;
mbed_official 441:d2c15dda23c1 135
mbed_official 441:d2c15dda23c1 136 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 441:d2c15dda23c1 137 while (!(i2c_status(obj) & SR2_TEND)) {
mbed_official 441:d2c15dda23c1 138 timeout ++;
mbed_official 441:d2c15dda23c1 139 if (timeout >= TIMEOUT_1S) {
mbed_official 441:d2c15dda23c1 140 return -1;
mbed_official 441:d2c15dda23c1 141 }
mbed_official 409:a95c696104d3 142 }
mbed_official 409:a95c696104d3 143
mbed_official 409:a95c696104d3 144 return 0;
mbed_official 409:a95c696104d3 145 }
mbed_official 409:a95c696104d3 146
mbed_official 409:a95c696104d3 147
mbed_official 460:3bcf9be0332c 148 static int i2c_wait_START(i2c_t *obj) {
mbed_official 460:3bcf9be0332c 149 int timeout = 0;
mbed_official 460:3bcf9be0332c 150
mbed_official 460:3bcf9be0332c 151 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 460:3bcf9be0332c 152 while (!(i2c_status(obj) & SR2_START)) {
mbed_official 460:3bcf9be0332c 153 timeout ++;
mbed_official 460:3bcf9be0332c 154 if (timeout >= TIMEOUT_1S) {
mbed_official 460:3bcf9be0332c 155 return -1;
mbed_official 460:3bcf9be0332c 156 }
mbed_official 460:3bcf9be0332c 157 }
mbed_official 460:3bcf9be0332c 158
mbed_official 460:3bcf9be0332c 159 return 0;
mbed_official 460:3bcf9be0332c 160 }
mbed_official 460:3bcf9be0332c 161
mbed_official 430:d406b7919023 162 static int i2c_wait_STOP(i2c_t *obj) {
mbed_official 441:d2c15dda23c1 163 int timeout = 0;
mbed_official 441:d2c15dda23c1 164
mbed_official 441:d2c15dda23c1 165 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 441:d2c15dda23c1 166 while (!(i2c_status(obj) & SR2_STOP)) {
mbed_official 441:d2c15dda23c1 167 timeout ++;
mbed_official 441:d2c15dda23c1 168 if (timeout >= TIMEOUT_1S) {
mbed_official 441:d2c15dda23c1 169 return -1;
mbed_official 441:d2c15dda23c1 170 }
mbed_official 441:d2c15dda23c1 171 }
mbed_official 430:d406b7919023 172
mbed_official 430:d406b7919023 173 return 0;
mbed_official 430:d406b7919023 174 }
mbed_official 430:d406b7919023 175
mbed_official 460:3bcf9be0332c 176 static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
mbed_official 441:d2c15dda23c1 177 /* SR2.NACKF = 0 */
mbed_official 441:d2c15dda23c1 178 REG(SR2.UINT32) &= ~SR2_NACKF;
mbed_official 460:3bcf9be0332c 179 /* SR2.STOP = 0 */
mbed_official 441:d2c15dda23c1 180 REG(SR2.UINT32) &= ~SR2_STOP;
mbed_official 441:d2c15dda23c1 181 }
mbed_official 441:d2c15dda23c1 182
mbed_official 460:3bcf9be0332c 183 static void i2c_set_MR3_NACK(i2c_t *obj) {
mbed_official 460:3bcf9be0332c 184 /* send a NOT ACK */
mbed_official 460:3bcf9be0332c 185 REG(MR3.UINT32) |= MR3_ACKWP;
mbed_official 460:3bcf9be0332c 186 REG(MR3.UINT32) |= MR3_ACKBT;
mbed_official 460:3bcf9be0332c 187 REG(MR3.UINT32) &= ~MR3_ACKWP;
mbed_official 460:3bcf9be0332c 188 }
mbed_official 460:3bcf9be0332c 189
mbed_official 460:3bcf9be0332c 190 static void i2c_set_MR3_ACK(i2c_t *obj) {
mbed_official 460:3bcf9be0332c 191 /* send a ACK */
mbed_official 460:3bcf9be0332c 192 REG(MR3.UINT32) |= MR3_ACKWP;
mbed_official 460:3bcf9be0332c 193 REG(MR3.UINT32) &= ~MR3_ACKBT;
mbed_official 460:3bcf9be0332c 194 REG(MR3.UINT32) &= ~MR3_ACKWP;
mbed_official 441:d2c15dda23c1 195 }
mbed_official 430:d406b7919023 196
mbed_official 390:35c2c1cf29cd 197 static inline void i2c_power_enable(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 198 volatile uint8_t dummy;
mbed_official 390:35c2c1cf29cd 199 switch ((int)obj->i2c) {
mbed_official 460:3bcf9be0332c 200 case I2C_0:
mbed_official 460:3bcf9be0332c 201 CPGSTBCR9 &= ~(0x80);
mbed_official 460:3bcf9be0332c 202 break;
mbed_official 460:3bcf9be0332c 203 case I2C_1:
mbed_official 460:3bcf9be0332c 204 CPGSTBCR9 &= ~(0x40);
mbed_official 460:3bcf9be0332c 205 break;
mbed_official 460:3bcf9be0332c 206 case I2C_2:
mbed_official 460:3bcf9be0332c 207 CPGSTBCR9 &= ~(0x20);
mbed_official 460:3bcf9be0332c 208 break;
mbed_official 460:3bcf9be0332c 209 case I2C_3:
mbed_official 460:3bcf9be0332c 210 CPGSTBCR9 &= ~(0x10);
mbed_official 460:3bcf9be0332c 211 break;
mbed_official 390:35c2c1cf29cd 212 }
mbed_official 390:35c2c1cf29cd 213 dummy = CPGSTBCR9;
mbed_official 390:35c2c1cf29cd 214 }
mbed_official 390:35c2c1cf29cd 215
mbed_official 390:35c2c1cf29cd 216 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
mbed_official 441:d2c15dda23c1 217 /* determine the I2C to use */
mbed_official 390:35c2c1cf29cd 218 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
mbed_official 390:35c2c1cf29cd 219 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
mbed_official 390:35c2c1cf29cd 220 obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
mbed_official 390:35c2c1cf29cd 221 MBED_ASSERT((int)obj->i2c != NC);
mbed_official 409:a95c696104d3 222
mbed_official 441:d2c15dda23c1 223 /* enable power */
mbed_official 390:35c2c1cf29cd 224 i2c_power_enable(obj);
mbed_official 390:35c2c1cf29cd 225
mbed_official 441:d2c15dda23c1 226 /* set default frequency at 100k */
mbed_official 427:8eeb5157dee4 227 i2c_frequency(obj, 100000);
mbed_official 427:8eeb5157dee4 228
mbed_official 390:35c2c1cf29cd 229 pinmap_pinout(sda, PinMap_I2C_SDA);
mbed_official 390:35c2c1cf29cd 230 pinmap_pinout(scl, PinMap_I2C_SCL);
mbed_official 460:3bcf9be0332c 231
mbed_official 460:3bcf9be0332c 232 obj->last_stop_flag = 1;
mbed_official 390:35c2c1cf29cd 233 }
mbed_official 390:35c2c1cf29cd 234
mbed_official 390:35c2c1cf29cd 235 inline int i2c_start(i2c_t *obj) {
mbed_official 441:d2c15dda23c1 236 int timeout = 0;
mbed_official 441:d2c15dda23c1 237
mbed_official 441:d2c15dda23c1 238 while (REG(CR2.UINT32) & CR2_BBSY) {
mbed_official 441:d2c15dda23c1 239 timeout ++;
mbed_official 441:d2c15dda23c1 240 if (timeout >= obj->bbsy_wait_cnt) {
mbed_official 460:3bcf9be0332c 241 break;
mbed_official 441:d2c15dda23c1 242 }
mbed_official 390:35c2c1cf29cd 243 }
mbed_official 441:d2c15dda23c1 244 /* Start Condition */
mbed_official 441:d2c15dda23c1 245 REG(CR2.UINT8[0]) |= CR2_ST;
mbed_official 390:35c2c1cf29cd 246
mbed_official 441:d2c15dda23c1 247 return 0;
mbed_official 390:35c2c1cf29cd 248 }
mbed_official 390:35c2c1cf29cd 249
mbed_official 482:d9a48e768ce0 250 static inline int i2c_restart(i2c_t *obj) {
mbed_official 460:3bcf9be0332c 251 /* SR2.START = 0 */
mbed_official 460:3bcf9be0332c 252 REG(SR2.UINT32) &= ~SR2_START;
mbed_official 460:3bcf9be0332c 253 /* ReStart condition */
mbed_official 460:3bcf9be0332c 254 REG(CR2.UINT32) |= CR2_RS;
mbed_official 460:3bcf9be0332c 255
mbed_official 460:3bcf9be0332c 256 return 0;
mbed_official 460:3bcf9be0332c 257 }
mbed_official 460:3bcf9be0332c 258
mbed_official 390:35c2c1cf29cd 259 inline int i2c_stop(i2c_t *obj) {
mbed_official 460:3bcf9be0332c 260 /* SR2.STOP = 0 */
mbed_official 441:d2c15dda23c1 261 REG(SR2.UINT32) &= ~SR2_STOP;
mbed_official 441:d2c15dda23c1 262 /* Stop condition */
mbed_official 441:d2c15dda23c1 263 REG(CR2.UINT32) |= CR2_SP;
mbed_official 409:a95c696104d3 264
mbed_official 390:35c2c1cf29cd 265 return 0;
mbed_official 390:35c2c1cf29cd 266 }
mbed_official 390:35c2c1cf29cd 267
mbed_official 460:3bcf9be0332c 268 static void i2c_set_err_noslave(i2c_t *obj, int stop) {
mbed_official 460:3bcf9be0332c 269 if (stop) {
mbed_official 460:3bcf9be0332c 270 (void)i2c_stop(obj);
mbed_official 460:3bcf9be0332c 271 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 272 i2c_set_SR2_NACKF_STOP(obj);
mbed_official 460:3bcf9be0332c 273 } else {
mbed_official 460:3bcf9be0332c 274 (void)i2c_restart(obj);
mbed_official 460:3bcf9be0332c 275 (void)i2c_wait_START(obj);
mbed_official 460:3bcf9be0332c 276 /* SR2.START = 0 */
mbed_official 460:3bcf9be0332c 277 REG(SR2.UINT32) &= ~SR2_START;
mbed_official 460:3bcf9be0332c 278 }
mbed_official 460:3bcf9be0332c 279 }
mbed_official 460:3bcf9be0332c 280
mbed_official 390:35c2c1cf29cd 281 static inline int i2c_do_write(i2c_t *obj, int value) {
mbed_official 441:d2c15dda23c1 282 int timeout = 0;
mbed_official 441:d2c15dda23c1 283
mbed_official 441:d2c15dda23c1 284 if (!(i2c_status(obj) & SR2_NACKF)) {
mbed_official 441:d2c15dda23c1 285 /* RIICnSR2.NACKF=0 */
mbed_official 441:d2c15dda23c1 286 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 441:d2c15dda23c1 287 while (!(i2c_status(obj) & SR2_TDRE)) {
mbed_official 441:d2c15dda23c1 288 /* RIICnSR2.TDRE=0 */
mbed_official 441:d2c15dda23c1 289 timeout ++;
mbed_official 441:d2c15dda23c1 290 if (timeout >= TIMEOUT_1S) {
mbed_official 441:d2c15dda23c1 291 return -1;
mbed_official 441:d2c15dda23c1 292 }
mbed_official 441:d2c15dda23c1 293 if (i2c_status(obj) & SR2_NACKF) {
mbed_official 441:d2c15dda23c1 294 /* RIICnSR2.NACKF=1 */
mbed_official 441:d2c15dda23c1 295 return -1;
mbed_official 441:d2c15dda23c1 296 }
mbed_official 441:d2c15dda23c1 297 }
mbed_official 441:d2c15dda23c1 298 /* write the data */
mbed_official 390:35c2c1cf29cd 299 REG(DRT.UINT32) = value;
mbed_official 441:d2c15dda23c1 300 } else {
mbed_official 441:d2c15dda23c1 301 return -1;
mbed_official 390:35c2c1cf29cd 302 }
mbed_official 441:d2c15dda23c1 303
mbed_official 441:d2c15dda23c1 304 return 0;
mbed_official 441:d2c15dda23c1 305 }
mbed_official 441:d2c15dda23c1 306
mbed_official 441:d2c15dda23c1 307 static inline int i2c_read_address_write(i2c_t *obj, int value) {
mbed_official 441:d2c15dda23c1 308 int status;
mbed_official 460:3bcf9be0332c 309
mbed_official 441:d2c15dda23c1 310 status = i2c_wait_TDRE(obj);
mbed_official 441:d2c15dda23c1 311 if (status == 0) {
mbed_official 441:d2c15dda23c1 312 /* write the data */
mbed_official 441:d2c15dda23c1 313 REG(DRT.UINT32) = value;
mbed_official 441:d2c15dda23c1 314 }
mbed_official 460:3bcf9be0332c 315
mbed_official 460:3bcf9be0332c 316 return status;
mbed_official 441:d2c15dda23c1 317
mbed_official 390:35c2c1cf29cd 318 }
mbed_official 390:35c2c1cf29cd 319
mbed_official 390:35c2c1cf29cd 320 static inline int i2c_do_read(i2c_t *obj, int last) {
mbed_official 409:a95c696104d3 321 if (last == 2) {
mbed_official 409:a95c696104d3 322 /* this time is befor last byte read */
mbed_official 441:d2c15dda23c1 323 /* Set MR3 WAIT bit is 1 */;
mbed_official 441:d2c15dda23c1 324 REG(MR3.UINT32) |= MR3_WAIT;
mbed_official 409:a95c696104d3 325 } else if (last == 1) {
mbed_official 460:3bcf9be0332c 326 i2c_set_MR3_NACK(obj);
mbed_official 390:35c2c1cf29cd 327 } else {
mbed_official 460:3bcf9be0332c 328 i2c_set_MR3_ACK(obj);
mbed_official 390:35c2c1cf29cd 329 }
mbed_official 409:a95c696104d3 330
mbed_official 441:d2c15dda23c1 331 /* return the data */
mbed_official 390:35c2c1cf29cd 332 return (REG(DRR.UINT32) & 0xFF);
mbed_official 390:35c2c1cf29cd 333 }
mbed_official 390:35c2c1cf29cd 334
mbed_official 390:35c2c1cf29cd 335 void i2c_frequency(i2c_t *obj, int hz) {
mbed_official 441:d2c15dda23c1 336 float64_t pclk_val;
mbed_official 441:d2c15dda23c1 337 float64_t wait_utime;
mbed_official 441:d2c15dda23c1 338 volatile float64_t bps;
mbed_official 441:d2c15dda23c1 339 volatile float64_t L_time; /* H Width period */
mbed_official 441:d2c15dda23c1 340 volatile float64_t H_time; /* L Width period */
mbed_official 441:d2c15dda23c1 341 uint32_t tmp_L_width;
mbed_official 441:d2c15dda23c1 342 uint32_t tmp_H_width;
mbed_official 441:d2c15dda23c1 343 uint32_t remainder;
mbed_official 441:d2c15dda23c1 344 uint32_t wk_cks = 0;
mbed_official 427:8eeb5157dee4 345
mbed_official 422:a032ac66f24e 346 /* set PCLK */
mbed_official 427:8eeb5157dee4 347 if (false == RZ_A1_IsClockMode0()) {
mbed_official 441:d2c15dda23c1 348 pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
mbed_official 422:a032ac66f24e 349 } else {
mbed_official 441:d2c15dda23c1 350 pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
mbed_official 422:a032ac66f24e 351 }
mbed_official 427:8eeb5157dee4 352
mbed_official 422:a032ac66f24e 353 /* Min 10kHz, Max 400kHz */
mbed_official 422:a032ac66f24e 354 if (hz < 10000) {
mbed_official 441:d2c15dda23c1 355 bps = 10000;
mbed_official 422:a032ac66f24e 356 } else if (hz > 400000) {
mbed_official 441:d2c15dda23c1 357 bps = 400000;
mbed_official 422:a032ac66f24e 358 } else {
mbed_official 441:d2c15dda23c1 359 bps = (float64_t)hz;
mbed_official 422:a032ac66f24e 360 }
mbed_official 427:8eeb5157dee4 361
mbed_official 441:d2c15dda23c1 362 /* Calculation L width time */
mbed_official 441:d2c15dda23c1 363 L_time = (1 / (2 * bps)); /* Harf period of frequency */
mbed_official 441:d2c15dda23c1 364 H_time = L_time;
mbed_official 441:d2c15dda23c1 365
mbed_official 441:d2c15dda23c1 366 /* Check I2C mode of Speed */
mbed_official 441:d2c15dda23c1 367 if (bps > 100000) {
mbed_official 441:d2c15dda23c1 368 /* Fast-mode */
mbed_official 441:d2c15dda23c1 369 L_time -= 102E-9; /* Falling time of SCL clock. */
mbed_official 441:d2c15dda23c1 370 H_time -= 138E-9; /* Rising time of SCL clock. */
mbed_official 441:d2c15dda23c1 371 /* Check L wideth */
mbed_official 441:d2c15dda23c1 372 if (L_time < 1.3E-6) {
mbed_official 441:d2c15dda23c1 373 /* Wnen L width less than 1.3us */
mbed_official 441:d2c15dda23c1 374 /* Subtract Rise up and down time for SCL from H/L width */
mbed_official 441:d2c15dda23c1 375 L_time = 1.3E-6;
mbed_official 441:d2c15dda23c1 376 H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
mbed_official 422:a032ac66f24e 377 }
mbed_official 422:a032ac66f24e 378 }
mbed_official 409:a95c696104d3 379
mbed_official 441:d2c15dda23c1 380 tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
mbed_official 441:d2c15dda23c1 381 tmp_L_width >>= 1;
mbed_official 441:d2c15dda23c1 382 wk_cks++;
mbed_official 441:d2c15dda23c1 383 while (tmp_L_width >= 341) {
mbed_official 441:d2c15dda23c1 384 tmp_L_width >>= 1;
mbed_official 441:d2c15dda23c1 385 wk_cks++;
mbed_official 441:d2c15dda23c1 386 }
mbed_official 441:d2c15dda23c1 387 remainder = tmp_L_width % 10;
mbed_official 441:d2c15dda23c1 388 tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
mbed_official 441:d2c15dda23c1 389
mbed_official 441:d2c15dda23c1 390 tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
mbed_official 441:d2c15dda23c1 391 tmp_H_width >>= wk_cks;
mbed_official 441:d2c15dda23c1 392 if (remainder == 0) {
mbed_official 441:d2c15dda23c1 393 tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
mbed_official 422:a032ac66f24e 394 } else {
mbed_official 441:d2c15dda23c1 395 remainder += tmp_H_width % 10;
mbed_official 441:d2c15dda23c1 396 tmp_H_width = (tmp_H_width / 10) - 3;
mbed_official 441:d2c15dda23c1 397 if (remainder > 10) {
mbed_official 441:d2c15dda23c1 398 tmp_H_width += 1; /* fine adjustment */
mbed_official 441:d2c15dda23c1 399 }
mbed_official 422:a032ac66f24e 400 }
mbed_official 441:d2c15dda23c1 401 /* timeout of BBSY bit is minimum low width by frequency */
mbed_official 441:d2c15dda23c1 402 /* so timeout calculates "(low width) * 2" by frequency */
mbed_official 441:d2c15dda23c1 403 wait_utime = (L_time * 2) * 1000000;
mbed_official 441:d2c15dda23c1 404 /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
mbed_official 441:d2c15dda23c1 405 if (wait_utime <= 0.3) {
mbed_official 441:d2c15dda23c1 406 obj->bbsy_wait_cnt = 1;
mbed_official 441:d2c15dda23c1 407 } else {
mbed_official 441:d2c15dda23c1 408 obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
mbed_official 441:d2c15dda23c1 409 }
mbed_official 441:d2c15dda23c1 410
mbed_official 441:d2c15dda23c1 411
mbed_official 441:d2c15dda23c1 412 /* I2C Rate */
mbed_official 441:d2c15dda23c1 413 obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
mbed_official 441:d2c15dda23c1 414 obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
mbed_official 441:d2c15dda23c1 415 obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
mbed_official 441:d2c15dda23c1 416
mbed_official 441:d2c15dda23c1 417 /* full reset */
mbed_official 441:d2c15dda23c1 418 i2c_reg_reset(obj);
mbed_official 390:35c2c1cf29cd 419 }
mbed_official 390:35c2c1cf29cd 420
mbed_official 390:35c2c1cf29cd 421 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
mbed_official 409:a95c696104d3 422 int count = 0;
mbed_official 409:a95c696104d3 423 int status;
mbed_official 409:a95c696104d3 424 int value;
mbed_official 409:a95c696104d3 425 volatile uint32_t work_reg = 0;
mbed_official 409:a95c696104d3 426
mbed_official 460:3bcf9be0332c 427 if(length <= 0) {
mbed_official 460:3bcf9be0332c 428 return 0;
mbed_official 390:35c2c1cf29cd 429 }
mbed_official 460:3bcf9be0332c 430 i2c_set_MR3_ACK(obj);
mbed_official 460:3bcf9be0332c 431 /* There is a STOP condition for last processing */
mbed_official 460:3bcf9be0332c 432 if (obj->last_stop_flag != 0) {
mbed_official 460:3bcf9be0332c 433 status = i2c_start(obj);
mbed_official 460:3bcf9be0332c 434 if (status != 0) {
mbed_official 460:3bcf9be0332c 435 i2c_set_err_noslave(obj, stop);
mbed_official 460:3bcf9be0332c 436 return I2C_ERROR_BUS_BUSY;
mbed_official 460:3bcf9be0332c 437 }
mbed_official 460:3bcf9be0332c 438 }
mbed_official 460:3bcf9be0332c 439 obj->last_stop_flag = stop;
mbed_official 441:d2c15dda23c1 440 /* Send Slave address */
mbed_official 441:d2c15dda23c1 441 status = i2c_read_address_write(obj, (address | 0x01));
mbed_official 441:d2c15dda23c1 442 if (status != 0) {
mbed_official 460:3bcf9be0332c 443 i2c_set_err_noslave(obj, stop);
mbed_official 390:35c2c1cf29cd 444 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 445 }
mbed_official 460:3bcf9be0332c 446 /* wait RDRF */
mbed_official 441:d2c15dda23c1 447 status = i2c_wait_RDRF(obj);
mbed_official 409:a95c696104d3 448 /* check ACK/NACK */
mbed_official 460:3bcf9be0332c 449 if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) {
mbed_official 409:a95c696104d3 450 /* Slave sends NACK */
mbed_official 460:3bcf9be0332c 451 /* If not repeated start, send stop. */
mbed_official 460:3bcf9be0332c 452 if (stop) {
mbed_official 460:3bcf9be0332c 453 i2c_stop(obj);
mbed_official 460:3bcf9be0332c 454 /* dummy read */
mbed_official 460:3bcf9be0332c 455 value = REG(DRR.UINT32);
mbed_official 460:3bcf9be0332c 456 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 457 i2c_set_SR2_NACKF_STOP(obj);
mbed_official 460:3bcf9be0332c 458 } else {
mbed_official 460:3bcf9be0332c 459 (void)i2c_restart(obj);
mbed_official 460:3bcf9be0332c 460 /* dummy read */
mbed_official 460:3bcf9be0332c 461 value = REG(DRR.UINT32);
mbed_official 460:3bcf9be0332c 462 (void)i2c_wait_START(obj);
mbed_official 460:3bcf9be0332c 463 /* SR2.START = 0 */
mbed_official 460:3bcf9be0332c 464 REG(SR2.UINT32) &= ~SR2_START;
mbed_official 460:3bcf9be0332c 465 }
mbed_official 409:a95c696104d3 466 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 467 }
mbed_official 441:d2c15dda23c1 468 /* Read in all except last byte */
mbed_official 430:d406b7919023 469 if (length > 2) {
mbed_official 441:d2c15dda23c1 470 /* dummy read */
mbed_official 441:d2c15dda23c1 471 value = REG(DRR.UINT32);
mbed_official 409:a95c696104d3 472 for (count = 0; count < (length - 1); count++) {
mbed_official 441:d2c15dda23c1 473 /* wait for it to arrive */
mbed_official 441:d2c15dda23c1 474 status = i2c_wait_RDRF(obj);
mbed_official 441:d2c15dda23c1 475 if (status != 0) {
mbed_official 460:3bcf9be0332c 476 i2c_set_err_noslave(obj, stop);
mbed_official 441:d2c15dda23c1 477 return I2C_ERROR_NO_SLAVE;
mbed_official 441:d2c15dda23c1 478 }
mbed_official 441:d2c15dda23c1 479 /* Recieve the data */
mbed_official 409:a95c696104d3 480 if (count == (length - 2)) {
mbed_official 409:a95c696104d3 481 value = i2c_do_read(obj, 1);
mbed_official 409:a95c696104d3 482 } else if ((length >= 3) && (count == (length - 3))) {
mbed_official 409:a95c696104d3 483 value = i2c_do_read(obj, 2);
mbed_official 409:a95c696104d3 484 } else {
mbed_official 409:a95c696104d3 485 value = i2c_do_read(obj, 0);
mbed_official 409:a95c696104d3 486 }
mbed_official 441:d2c15dda23c1 487 data[count] = (char)value;
mbed_official 409:a95c696104d3 488 }
mbed_official 430:d406b7919023 489 } else if (length == 2) {
mbed_official 460:3bcf9be0332c 490 /* Set MR3 WATI bit is 1 */
mbed_official 441:d2c15dda23c1 491 REG(MR3.UINT32) |= MR3_WAIT;
mbed_official 441:d2c15dda23c1 492 /* dummy read */
mbed_official 430:d406b7919023 493 value = REG(DRR.UINT32);
mbed_official 441:d2c15dda23c1 494 /* wait for it to arrive */
mbed_official 441:d2c15dda23c1 495 status = i2c_wait_RDRF(obj);
mbed_official 441:d2c15dda23c1 496 if (status != 0) {
mbed_official 460:3bcf9be0332c 497 i2c_set_err_noslave(obj, stop);
mbed_official 441:d2c15dda23c1 498 return I2C_ERROR_NO_SLAVE;
mbed_official 441:d2c15dda23c1 499 }
mbed_official 460:3bcf9be0332c 500 i2c_set_MR3_NACK(obj);
mbed_official 430:d406b7919023 501 data[count] = (char)REG(DRR.UINT32);
mbed_official 430:d406b7919023 502 count++;
mbed_official 460:3bcf9be0332c 503 } else {
mbed_official 460:3bcf9be0332c 504 /* length == 1 */
mbed_official 430:d406b7919023 505 /* Set MR3 WATI bit is 1 */;
mbed_official 441:d2c15dda23c1 506 REG(MR3.UINT32) |= MR3_WAIT;
mbed_official 460:3bcf9be0332c 507 i2c_set_MR3_NACK(obj);
mbed_official 441:d2c15dda23c1 508 /* dummy read */
mbed_official 430:d406b7919023 509 value = REG(DRR.UINT32);
mbed_official 441:d2c15dda23c1 510 }
mbed_official 441:d2c15dda23c1 511 /* wait for it to arrive */
mbed_official 441:d2c15dda23c1 512 status = i2c_wait_RDRF(obj);
mbed_official 441:d2c15dda23c1 513 if (status != 0) {
mbed_official 460:3bcf9be0332c 514 i2c_set_err_noslave(obj, stop);
mbed_official 441:d2c15dda23c1 515 return I2C_ERROR_NO_SLAVE;
mbed_official 409:a95c696104d3 516 }
mbed_official 460:3bcf9be0332c 517
mbed_official 443:ed48b4122bfb 518 /* If not repeated start, send stop. */
mbed_official 443:ed48b4122bfb 519 if (stop) {
mbed_official 460:3bcf9be0332c 520 (void)i2c_stop(obj);
mbed_official 443:ed48b4122bfb 521 /* RIICnDRR read */
mbed_official 443:ed48b4122bfb 522 value = REG(DRR.UINT32) & 0xFF;
mbed_official 443:ed48b4122bfb 523 data[count] = (char)value;
mbed_official 443:ed48b4122bfb 524 /* RIICnMR3.WAIT = 0 */
mbed_official 443:ed48b4122bfb 525 REG(MR3.UINT32) &= ~MR3_WAIT;
mbed_official 443:ed48b4122bfb 526 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 527 i2c_set_SR2_NACKF_STOP(obj);
mbed_official 443:ed48b4122bfb 528 } else {
mbed_official 460:3bcf9be0332c 529 (void)i2c_restart(obj);
mbed_official 443:ed48b4122bfb 530 /* RIICnDRR read */
mbed_official 443:ed48b4122bfb 531 value = REG(DRR.UINT32) & 0xFF;
mbed_official 443:ed48b4122bfb 532 data[count] = (char)value;
mbed_official 443:ed48b4122bfb 533 /* RIICnMR3.WAIT = 0 */
mbed_official 443:ed48b4122bfb 534 REG(MR3.UINT32) &= ~MR3_WAIT;
mbed_official 460:3bcf9be0332c 535 (void)i2c_wait_START(obj);
mbed_official 460:3bcf9be0332c 536 /* SR2.START = 0 */
mbed_official 460:3bcf9be0332c 537 REG(SR2.UINT32) &= ~SR2_START;
mbed_official 443:ed48b4122bfb 538 }
mbed_official 409:a95c696104d3 539
mbed_official 390:35c2c1cf29cd 540 return length;
mbed_official 390:35c2c1cf29cd 541 }
mbed_official 390:35c2c1cf29cd 542
mbed_official 390:35c2c1cf29cd 543 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
mbed_official 441:d2c15dda23c1 544 int cnt;
mbed_official 441:d2c15dda23c1 545 int status;
mbed_official 409:a95c696104d3 546
mbed_official 460:3bcf9be0332c 547 if(length <= 0) {
mbed_official 460:3bcf9be0332c 548 return 0;
mbed_official 390:35c2c1cf29cd 549 }
mbed_official 460:3bcf9be0332c 550
mbed_official 460:3bcf9be0332c 551 /* There is a STOP condition for last processing */
mbed_official 460:3bcf9be0332c 552 if (obj->last_stop_flag != 0) {
mbed_official 460:3bcf9be0332c 553 status = i2c_start(obj);
mbed_official 460:3bcf9be0332c 554 if (status != 0) {
mbed_official 460:3bcf9be0332c 555 i2c_set_err_noslave(obj, stop);
mbed_official 460:3bcf9be0332c 556 return I2C_ERROR_BUS_BUSY;
mbed_official 460:3bcf9be0332c 557 }
mbed_official 460:3bcf9be0332c 558 }
mbed_official 460:3bcf9be0332c 559 obj->last_stop_flag = stop;
mbed_official 441:d2c15dda23c1 560 /* Send Slave address */
mbed_official 390:35c2c1cf29cd 561 status = i2c_do_write(obj, address);
mbed_official 441:d2c15dda23c1 562 if (status != 0) {
mbed_official 460:3bcf9be0332c 563 i2c_set_err_noslave(obj, stop);
mbed_official 390:35c2c1cf29cd 564 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 565 }
mbed_official 441:d2c15dda23c1 566 /* Send Write data */
mbed_official 441:d2c15dda23c1 567 for (cnt=0; cnt<length; cnt++) {
mbed_official 441:d2c15dda23c1 568 status = i2c_do_write(obj, data[cnt]);
mbed_official 441:d2c15dda23c1 569 if(status != 0) {
mbed_official 460:3bcf9be0332c 570 i2c_set_err_noslave(obj, stop);
mbed_official 441:d2c15dda23c1 571 return cnt;
mbed_official 390:35c2c1cf29cd 572 }
mbed_official 390:35c2c1cf29cd 573 }
mbed_official 441:d2c15dda23c1 574 /* Wait send end */
mbed_official 441:d2c15dda23c1 575 status = i2c_wait_TEND(obj);
mbed_official 441:d2c15dda23c1 576 if (status != 0) {
mbed_official 460:3bcf9be0332c 577 i2c_set_err_noslave(obj, stop);
mbed_official 441:d2c15dda23c1 578 return I2C_ERROR_NO_SLAVE;
mbed_official 390:35c2c1cf29cd 579 }
mbed_official 443:ed48b4122bfb 580 /* If not repeated start, send stop. */
mbed_official 443:ed48b4122bfb 581 if (stop) {
mbed_official 460:3bcf9be0332c 582 (void)i2c_stop(obj);
mbed_official 443:ed48b4122bfb 583 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 584 i2c_set_SR2_NACKF_STOP(obj);
mbed_official 460:3bcf9be0332c 585 } else {
mbed_official 460:3bcf9be0332c 586 (void)i2c_restart(obj);
mbed_official 460:3bcf9be0332c 587 (void)i2c_wait_START(obj);
mbed_official 460:3bcf9be0332c 588 /* SR2.START = 0 */
mbed_official 460:3bcf9be0332c 589 REG(SR2.UINT32) &= ~SR2_START;
mbed_official 460:3bcf9be0332c 590
mbed_official 443:ed48b4122bfb 591 }
mbed_official 441:d2c15dda23c1 592
mbed_official 390:35c2c1cf29cd 593 return length;
mbed_official 390:35c2c1cf29cd 594 }
mbed_official 390:35c2c1cf29cd 595
mbed_official 390:35c2c1cf29cd 596 void i2c_reset(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 597 i2c_stop(obj);
mbed_official 441:d2c15dda23c1 598 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 599 i2c_set_SR2_NACKF_STOP(obj);
mbed_official 390:35c2c1cf29cd 600 }
mbed_official 390:35c2c1cf29cd 601
mbed_official 390:35c2c1cf29cd 602 int i2c_byte_read(i2c_t *obj, int last) {
mbed_official 441:d2c15dda23c1 603 int status;
mbed_official 441:d2c15dda23c1 604
mbed_official 441:d2c15dda23c1 605 /* wait for it to arrive */
mbed_official 441:d2c15dda23c1 606 status = i2c_wait_RDRF(obj);
mbed_official 441:d2c15dda23c1 607 if (status != 0) {
mbed_official 460:3bcf9be0332c 608 i2c_set_err_noslave(obj, 1);
mbed_official 441:d2c15dda23c1 609 return I2C_ERROR_NO_SLAVE;
mbed_official 441:d2c15dda23c1 610 }
mbed_official 430:d406b7919023 611
mbed_official 460:3bcf9be0332c 612 return (i2c_do_read(obj, last));
mbed_official 390:35c2c1cf29cd 613 }
mbed_official 390:35c2c1cf29cd 614
mbed_official 390:35c2c1cf29cd 615 int i2c_byte_write(i2c_t *obj, int data) {
mbed_official 390:35c2c1cf29cd 616 int ack;
mbed_official 460:3bcf9be0332c 617 int status;
mbed_official 460:3bcf9be0332c 618
mbed_official 460:3bcf9be0332c 619 status = i2c_do_write(obj, (data & 0xFF));
mbed_official 441:d2c15dda23c1 620 if (status != 0) {
mbed_official 460:3bcf9be0332c 621 i2c_set_err_noslave(obj, 1);
mbed_official 390:35c2c1cf29cd 622 ack = 0;
mbed_official 390:35c2c1cf29cd 623 } else {
mbed_official 390:35c2c1cf29cd 624 ack = 1;
mbed_official 390:35c2c1cf29cd 625 }
mbed_official 409:a95c696104d3 626
mbed_official 390:35c2c1cf29cd 627 return ack;
mbed_official 390:35c2c1cf29cd 628 }
mbed_official 390:35c2c1cf29cd 629
mbed_official 390:35c2c1cf29cd 630 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
mbed_official 390:35c2c1cf29cd 631 if (enable_slave != 0) {
mbed_official 460:3bcf9be0332c 632 REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
mbed_official 390:35c2c1cf29cd 633 } else {
mbed_official 460:3bcf9be0332c 634 REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
mbed_official 390:35c2c1cf29cd 635 }
mbed_official 390:35c2c1cf29cd 636 }
mbed_official 390:35c2c1cf29cd 637
mbed_official 390:35c2c1cf29cd 638 int i2c_slave_receive(i2c_t *obj) {
mbed_official 390:35c2c1cf29cd 639 int status;
mbed_official 390:35c2c1cf29cd 640 int retval;
mbed_official 409:a95c696104d3 641
mbed_official 460:3bcf9be0332c 642 status = REG(SR1.UINT8[0]) & SR1_AAS0;
mbed_official 460:3bcf9be0332c 643 status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
mbed_official 460:3bcf9be0332c 644
mbed_official 390:35c2c1cf29cd 645 switch(status) {
mbed_official 460:3bcf9be0332c 646 case 0x01:
mbed_official 460:3bcf9be0332c 647 /* the master is writing to this slave */
mbed_official 460:3bcf9be0332c 648 retval = 3;
mbed_official 460:3bcf9be0332c 649 break;
mbed_official 460:3bcf9be0332c 650 case 0x02:
mbed_official 460:3bcf9be0332c 651 /* the master is writing to all slave */
mbed_official 460:3bcf9be0332c 652 retval = 2;
mbed_official 460:3bcf9be0332c 653 break;
mbed_official 460:3bcf9be0332c 654 case 0x03:
mbed_official 460:3bcf9be0332c 655 /* the master has requested a read from this slave */
mbed_official 460:3bcf9be0332c 656 retval = 1;
mbed_official 460:3bcf9be0332c 657 break;
mbed_official 460:3bcf9be0332c 658 default :
mbed_official 460:3bcf9be0332c 659 /* no data */
mbed_official 460:3bcf9be0332c 660 retval = 0;
mbed_official 460:3bcf9be0332c 661 break;
mbed_official 390:35c2c1cf29cd 662 }
mbed_official 409:a95c696104d3 663
mbed_official 460:3bcf9be0332c 664 return retval;
mbed_official 390:35c2c1cf29cd 665 }
mbed_official 390:35c2c1cf29cd 666
mbed_official 390:35c2c1cf29cd 667 int i2c_slave_read(i2c_t *obj, char *data, int length) {
mbed_official 460:3bcf9be0332c 668 int timeout = 0;
mbed_official 460:3bcf9be0332c 669 int count;
mbed_official 460:3bcf9be0332c 670 int break_flg = 0;
mbed_official 409:a95c696104d3 671
mbed_official 460:3bcf9be0332c 672 if(length <= 0) {
mbed_official 460:3bcf9be0332c 673 return 0;
mbed_official 460:3bcf9be0332c 674 }
mbed_official 460:3bcf9be0332c 675 for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
mbed_official 460:3bcf9be0332c 676 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
mbed_official 460:3bcf9be0332c 677 while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) {
mbed_official 460:3bcf9be0332c 678 /* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */
mbed_official 460:3bcf9be0332c 679 if (i2c_status(obj) & SR2_STOP) {
mbed_official 460:3bcf9be0332c 680 /* RIICnSR2.STOP = 1 */
mbed_official 460:3bcf9be0332c 681 break_flg = 1;
mbed_official 460:3bcf9be0332c 682 break;
mbed_official 460:3bcf9be0332c 683 }
mbed_official 460:3bcf9be0332c 684 timeout ++;
mbed_official 460:3bcf9be0332c 685 if (timeout >= TIMEOUT_1S) {
mbed_official 460:3bcf9be0332c 686 return -1;
mbed_official 460:3bcf9be0332c 687 }
mbed_official 460:3bcf9be0332c 688 }
mbed_official 460:3bcf9be0332c 689 if (break_flg == 0) {
mbed_official 460:3bcf9be0332c 690 if (count == 0) {
mbed_official 460:3bcf9be0332c 691 /* dummy read */
mbed_official 460:3bcf9be0332c 692 (void)REG(DRR.UINT32);
mbed_official 460:3bcf9be0332c 693 } else {
mbed_official 460:3bcf9be0332c 694 data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
mbed_official 460:3bcf9be0332c 695 }
mbed_official 390:35c2c1cf29cd 696 }
mbed_official 460:3bcf9be0332c 697 }
mbed_official 460:3bcf9be0332c 698 if (break_flg == 0) {
mbed_official 460:3bcf9be0332c 699 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 700 } else {
mbed_official 460:3bcf9be0332c 701 if (i2c_status(obj) & SR2_RDRF) {
mbed_official 460:3bcf9be0332c 702 if (count <= 1) {
mbed_official 460:3bcf9be0332c 703 /* fail safe */
mbed_official 460:3bcf9be0332c 704 /* dummy read */
mbed_official 460:3bcf9be0332c 705 (void)REG(DRR.UINT32);
mbed_official 460:3bcf9be0332c 706 } else {
mbed_official 460:3bcf9be0332c 707 data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
mbed_official 460:3bcf9be0332c 708 }
mbed_official 460:3bcf9be0332c 709 }
mbed_official 460:3bcf9be0332c 710 }
mbed_official 460:3bcf9be0332c 711 /* SR2.STOP = 0 */
mbed_official 460:3bcf9be0332c 712 REG(SR2.UINT32) &= ~SR2_STOP;
mbed_official 409:a95c696104d3 713
mbed_official 460:3bcf9be0332c 714 return (count - 1);
mbed_official 460:3bcf9be0332c 715 }
mbed_official 460:3bcf9be0332c 716
mbed_official 460:3bcf9be0332c 717 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
mbed_official 460:3bcf9be0332c 718 int count = 0;
mbed_official 460:3bcf9be0332c 719 int status = 0;
mbed_official 460:3bcf9be0332c 720
mbed_official 460:3bcf9be0332c 721 if(length <= 0) {
mbed_official 460:3bcf9be0332c 722 return 0;
mbed_official 390:35c2c1cf29cd 723 }
mbed_official 409:a95c696104d3 724
mbed_official 460:3bcf9be0332c 725 while ((count < length) && (status == 0)) {
mbed_official 460:3bcf9be0332c 726 status = i2c_do_write(obj, data[count]);
mbed_official 460:3bcf9be0332c 727 count++;
mbed_official 460:3bcf9be0332c 728 }
mbed_official 460:3bcf9be0332c 729 if (status == 0) {
mbed_official 460:3bcf9be0332c 730 /* Wait send end */
mbed_official 460:3bcf9be0332c 731 status = i2c_wait_TEND(obj);
mbed_official 460:3bcf9be0332c 732 if (status != 0) {
mbed_official 460:3bcf9be0332c 733 i2c_set_err_noslave(obj, 1);
mbed_official 460:3bcf9be0332c 734 return 0;
mbed_official 460:3bcf9be0332c 735 }
mbed_official 460:3bcf9be0332c 736 }
mbed_official 460:3bcf9be0332c 737 /* dummy read */
mbed_official 460:3bcf9be0332c 738 (void)REG(DRR.UINT32);
mbed_official 460:3bcf9be0332c 739 (void)i2c_wait_STOP(obj);
mbed_official 460:3bcf9be0332c 740 i2c_set_SR2_NACKF_STOP(obj);
mbed_official 409:a95c696104d3 741
mbed_official 390:35c2c1cf29cd 742 return count;
mbed_official 390:35c2c1cf29cd 743 }
mbed_official 390:35c2c1cf29cd 744
mbed_official 460:3bcf9be0332c 745 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
mbed_official 460:3bcf9be0332c 746 REG(SAR0.UINT32) = address & 0xfffffffe;
mbed_official 390:35c2c1cf29cd 747 }