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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Parent:
441:d2c15dda23c1 
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal_spi.c
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V1.3.0
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 340:28d1f895c6fe 7 * @brief SPI HAL module driver.
mbed_official 630:825f75ca301e 8 * This file provides firmware functions to manage the following
mbed_official 630:825f75ca301e 9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official 630:825f75ca301e 10 * + Initialization and de-initialization functions
mbed_official 630:825f75ca301e 11 * + IO operation functions
mbed_official 630:825f75ca301e 12 * + Peripheral Control functions
mbed_official 340:28d1f895c6fe 13 * + Peripheral State functions
mbed_official 630:825f75ca301e 14 *
mbed_official 340:28d1f895c6fe 15 @verbatim
mbed_official 630:825f75ca301e 16 ==============================================================================
mbed_official 630:825f75ca301e 17 ##### How to use this driver #####
mbed_official 630:825f75ca301e 18 ==============================================================================
mbed_official 340:28d1f895c6fe 19 [..]
mbed_official 630:825f75ca301e 20 The SPI HAL driver can be used as follows:
mbed_official 630:825f75ca301e 21
mbed_official 630:825f75ca301e 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official 630:825f75ca301e 23 SPI_HandleTypeDef hspi;
mbed_official 630:825f75ca301e 24
mbed_official 630:825f75ca301e 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
mbed_official 630:825f75ca301e 26 (##) Enable the SPIx interface clock
mbed_official 630:825f75ca301e 27 (##) SPI pins configuration
mbed_official 630:825f75ca301e 28 (+++) Enable the clock for the SPI GPIOs
mbed_official 630:825f75ca301e 29 (+++) Configure these SPI pins as alternate function push-pull
mbed_official 630:825f75ca301e 30 (##) NVIC configuration if you need to use interrupt process
mbed_official 630:825f75ca301e 31 (+++) Configure the SPIx interrupt priority
mbed_official 630:825f75ca301e 32 (+++) Enable the NVIC SPI IRQ handle
mbed_official 630:825f75ca301e 33 (##) DMA Configuration if you need to use DMA process
mbed_official 630:825f75ca301e 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
mbed_official 630:825f75ca301e 35 (+++) Enable the DMAx clock
mbed_official 630:825f75ca301e 36 (+++) Configure the DMA handle parameters
mbed_official 630:825f75ca301e 37 (+++) Configure the DMA Tx or Rx channel
mbed_official 630:825f75ca301e 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official 630:825f75ca301e 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
mbed_official 630:825f75ca301e 40
mbed_official 630:825f75ca301e 41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
mbed_official 630:825f75ca301e 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official 630:825f75ca301e 43
mbed_official 630:825f75ca301e 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official 630:825f75ca301e 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official 630:825f75ca301e 46 by calling the customized HAL_SPI_MspInit() API.
mbed_official 630:825f75ca301e 47 [..]
mbed_official 630:825f75ca301e 48 Circular mode restriction:
mbed_official 630:825f75ca301e 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
mbed_official 630:825f75ca301e 50 (##) Master 2Lines RxOnly
mbed_official 630:825f75ca301e 51 (##) Master 1Line Rx
mbed_official 630:825f75ca301e 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
mbed_official 630:825f75ca301e 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
mbed_official 630:825f75ca301e 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
mbed_official 630:825f75ca301e 55 [..]
mbed_official 630:825f75ca301e 56 Using the HAL it is not possible to reach all supported SPI frequency with the differents
mbed_official 630:825f75ca301e 57 the following table resume the max SPI frequency reached with data size 8bits/16bits,
mbed_official 630:825f75ca301e 58 according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
mbed_official 630:825f75ca301e 59 +-----------------------------------------------------------------------------------------
mbed_official 630:825f75ca301e 60 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line
mbed_official 630:825f75ca301e 61 | Process | Tranfert mode |---------------------|---------------------|------------------
mbed_official 630:825f75ca301e 62 | | | Master | Slave | Master | Slave | Master | Slave
mbed_official 630:825f75ca301e 63 |=========================================================================================
mbed_official 630:825f75ca301e 64 | T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
mbed_official 630:825f75ca301e 65 | X |----------------|----------|----------|----------|----------|----------|-------
mbed_official 630:825f75ca301e 66 | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
mbed_official 630:825f75ca301e 67 | R |----------------|----------|----------|----------|----------|----------|-------
mbed_official 630:825f75ca301e 68 | X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA
mbed_official 630:825f75ca301e 69 |=========|================|==========|==========|==========|==========|==========|=======
mbed_official 630:825f75ca301e 70 | | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
mbed_official 630:825f75ca301e 71 | |----------------|----------|----------|----------|----------|----------|-------
mbed_official 630:825f75ca301e 72 | R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
mbed_official 630:825f75ca301e 73 | X |----------------|----------|----------|----------|----------|----------|-------
mbed_official 630:825f75ca301e 74 | | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/
mbed_official 630:825f75ca301e 75 |=========|================|==========|==========|==========|==========|==========|=======
mbed_official 630:825f75ca301e 76 | | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
mbed_official 630:825f75ca301e 77 | |----------------|----------|----------|----------|----------|----------|-------
mbed_official 630:825f75ca301e 78 | T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
mbed_official 630:825f75ca301e 79 | X |----------------|----------|----------|----------|----------|----------|-------
mbed_official 630:825f75ca301e 80 | | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/
mbed_official 630:825f75ca301e 81 +-----------------------------------------------------------------------------------------
mbed_official 630:825f75ca301e 82 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
mbed_official 630:825f75ca301e 83 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
mbed_official 630:825f75ca301e 84 @note
mbed_official 630:825f75ca301e 85 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_S
mbed_official 630:825f75ca301e 86 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official 630:825f75ca301e 87 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official 630:825f75ca301e 88
mbed_official 340:28d1f895c6fe 89 @endverbatim
mbed_official 340:28d1f895c6fe 90 ******************************************************************************
mbed_official 340:28d1f895c6fe 91 * @attention
mbed_official 340:28d1f895c6fe 92 *
mbed_official 630:825f75ca301e 93 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 94 *
mbed_official 340:28d1f895c6fe 95 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 96 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 97 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 98 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 99 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 100 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 101 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 102 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 103 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 104 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 105 *
mbed_official 340:28d1f895c6fe 106 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 107 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 108 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 109 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 110 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 111 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 112 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 113 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 114 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 115 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 116 *
mbed_official 630:825f75ca301e 117 ******************************************************************************
mbed_official 340:28d1f895c6fe 118 */
mbed_official 630:825f75ca301e 119
mbed_official 340:28d1f895c6fe 120 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 121 #include "stm32f0xx_hal.h"
mbed_official 630:825f75ca301e 122
mbed_official 340:28d1f895c6fe 123 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 124 * @{
mbed_official 340:28d1f895c6fe 125 */
mbed_official 340:28d1f895c6fe 126
mbed_official 630:825f75ca301e 127 /** @defgroup SPI SPI
mbed_official 340:28d1f895c6fe 128 * @brief SPI HAL module driver
mbed_official 340:28d1f895c6fe 129 * @{
mbed_official 340:28d1f895c6fe 130 */
mbed_official 340:28d1f895c6fe 131 #ifdef HAL_SPI_MODULE_ENABLED
mbed_official 340:28d1f895c6fe 132
mbed_official 340:28d1f895c6fe 133 /* Private typedef -----------------------------------------------------------*/
mbed_official 630:825f75ca301e 134 /* Private defines -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 135 /** @defgroup SPI_Private_Constants SPI Private Constants
mbed_official 340:28d1f895c6fe 136 * @{
mbed_official 340:28d1f895c6fe 137 */
mbed_official 340:28d1f895c6fe 138 #define SPI_DEFAULT_TIMEOUT 50
mbed_official 340:28d1f895c6fe 139 /**
mbed_official 340:28d1f895c6fe 140 * @}
mbed_official 340:28d1f895c6fe 141 */
mbed_official 340:28d1f895c6fe 142
mbed_official 630:825f75ca301e 143 /* Private macros ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 144 /* Private variables ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 145 /* Private function prototypes -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 146 /** @defgroup SPI_Private_Functions SPI Private Functions
mbed_official 340:28d1f895c6fe 147 * @{
mbed_official 340:28d1f895c6fe 148 */
mbed_official 441:d2c15dda23c1 149 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 441:d2c15dda23c1 150 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 441:d2c15dda23c1 151 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 441:d2c15dda23c1 152 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 441:d2c15dda23c1 153 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 441:d2c15dda23c1 154 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 441:d2c15dda23c1 155 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 156 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official 340:28d1f895c6fe 157 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
mbed_official 340:28d1f895c6fe 158 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 159 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 160 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 161 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 162 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 163 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 164 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 165 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 166 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 167 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 168 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 169 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 170 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 171 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 172 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 340:28d1f895c6fe 173 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 630:825f75ca301e 174 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 340:28d1f895c6fe 175 /**
mbed_official 340:28d1f895c6fe 176 * @}
mbed_official 340:28d1f895c6fe 177 */
mbed_official 340:28d1f895c6fe 178
mbed_official 340:28d1f895c6fe 179 /* Exported functions ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 180
mbed_official 340:28d1f895c6fe 181 /** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official 340:28d1f895c6fe 182 * @{
mbed_official 340:28d1f895c6fe 183 */
mbed_official 340:28d1f895c6fe 184
mbed_official 630:825f75ca301e 185 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 630:825f75ca301e 186 * @brief Initialization and Configuration functions
mbed_official 340:28d1f895c6fe 187 *
mbed_official 630:825f75ca301e 188 @verbatim
mbed_official 340:28d1f895c6fe 189 ===============================================================================
mbed_official 630:825f75ca301e 190 ##### Initialization and de-initialization functions #####
mbed_official 340:28d1f895c6fe 191 ===============================================================================
mbed_official 630:825f75ca301e 192 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 630:825f75ca301e 193 de-initialize the SPIx peripheral:
mbed_official 340:28d1f895c6fe 194
mbed_official 630:825f75ca301e 195 (+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official 340:28d1f895c6fe 196 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 340:28d1f895c6fe 197
mbed_official 630:825f75ca301e 198 (+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official 340:28d1f895c6fe 199 the selected configuration:
mbed_official 340:28d1f895c6fe 200 (++) Mode
mbed_official 630:825f75ca301e 201 (++) Direction
mbed_official 340:28d1f895c6fe 202 (++) Data Size
mbed_official 340:28d1f895c6fe 203 (++) Clock Polarity and Phase
mbed_official 340:28d1f895c6fe 204 (++) NSS Management
mbed_official 340:28d1f895c6fe 205 (++) BaudRate Prescaler
mbed_official 340:28d1f895c6fe 206 (++) FirstBit
mbed_official 340:28d1f895c6fe 207 (++) TIMode
mbed_official 340:28d1f895c6fe 208 (++) CRC Calculation
mbed_official 340:28d1f895c6fe 209 (++) CRC Polynomial if CRC enabled
mbed_official 630:825f75ca301e 210 (++) CRC Length, used only with Data8 and Data16
mbed_official 340:28d1f895c6fe 211 (++) FIFO reception threshold
mbed_official 340:28d1f895c6fe 212
mbed_official 630:825f75ca301e 213 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official 630:825f75ca301e 214 of the selected SPIx peripheral.
mbed_official 630:825f75ca301e 215
mbed_official 340:28d1f895c6fe 216 @endverbatim
mbed_official 340:28d1f895c6fe 217 * @{
mbed_official 340:28d1f895c6fe 218 */
mbed_official 340:28d1f895c6fe 219
mbed_official 340:28d1f895c6fe 220 /**
mbed_official 630:825f75ca301e 221 * @brief Initialize the SPI according to the specified parameters
mbed_official 630:825f75ca301e 222 * in the SPI_InitTypeDef and initialize the associated handle.
mbed_official 630:825f75ca301e 223 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 224 * the configuration information for SPI module.
mbed_official 340:28d1f895c6fe 225 * @retval HAL status
mbed_official 340:28d1f895c6fe 226 */
mbed_official 340:28d1f895c6fe 227 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 228 {
mbed_official 340:28d1f895c6fe 229 uint32_t frxth;
mbed_official 630:825f75ca301e 230
mbed_official 340:28d1f895c6fe 231 /* Check the SPI handle allocation */
mbed_official 441:d2c15dda23c1 232 if(hspi == NULL)
mbed_official 630:825f75ca301e 233 {
mbed_official 340:28d1f895c6fe 234 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 235 }
mbed_official 630:825f75ca301e 236
mbed_official 340:28d1f895c6fe 237 /* Check the parameters */
mbed_official 340:28d1f895c6fe 238 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official 340:28d1f895c6fe 239 assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official 340:28d1f895c6fe 240 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
mbed_official 340:28d1f895c6fe 241 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official 340:28d1f895c6fe 242 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official 340:28d1f895c6fe 243 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official 340:28d1f895c6fe 244 assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official 340:28d1f895c6fe 245 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
mbed_official 340:28d1f895c6fe 246 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official 340:28d1f895c6fe 247 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official 340:28d1f895c6fe 248 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official 340:28d1f895c6fe 249 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official 340:28d1f895c6fe 250 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official 340:28d1f895c6fe 251 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
mbed_official 630:825f75ca301e 252
mbed_official 630:825f75ca301e 253 if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official 630:825f75ca301e 254 {
mbed_official 630:825f75ca301e 255 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 256 hspi->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 257
mbed_official 630:825f75ca301e 258 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official 630:825f75ca301e 259 HAL_SPI_MspInit(hspi);
mbed_official 630:825f75ca301e 260 }
mbed_official 630:825f75ca301e 261
mbed_official 340:28d1f895c6fe 262 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 630:825f75ca301e 263
mbed_official 340:28d1f895c6fe 264 /* Disable the selected SPI peripheral */
mbed_official 340:28d1f895c6fe 265 __HAL_SPI_DISABLE(hspi);
mbed_official 630:825f75ca301e 266
mbed_official 340:28d1f895c6fe 267 /* Align by default the rs fifo threshold on the data size */
mbed_official 340:28d1f895c6fe 268 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 269 {
mbed_official 340:28d1f895c6fe 270 frxth = SPI_RXFIFO_THRESHOLD_HF;
mbed_official 340:28d1f895c6fe 271 }
mbed_official 340:28d1f895c6fe 272 else
mbed_official 340:28d1f895c6fe 273 {
mbed_official 340:28d1f895c6fe 274 frxth = SPI_RXFIFO_THRESHOLD_QF;
mbed_official 340:28d1f895c6fe 275 }
mbed_official 630:825f75ca301e 276
mbed_official 340:28d1f895c6fe 277 /* CRC calculation is valid only for 16Bit and 8 Bit */
mbed_official 340:28d1f895c6fe 278 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
mbed_official 340:28d1f895c6fe 279 {
mbed_official 340:28d1f895c6fe 280 /* CRC must be disabled */
mbed_official 630:825f75ca301e 281 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
mbed_official 340:28d1f895c6fe 282 }
mbed_official 630:825f75ca301e 283
mbed_official 340:28d1f895c6fe 284 /* Align the CRC Length on the data size */
mbed_official 340:28d1f895c6fe 285 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
mbed_official 340:28d1f895c6fe 286 {
mbed_official 630:825f75ca301e 287 /* CRC Length aligned on the data size : value set by default */
mbed_official 340:28d1f895c6fe 288 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 289 {
mbed_official 340:28d1f895c6fe 290 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
mbed_official 340:28d1f895c6fe 291 }
mbed_official 340:28d1f895c6fe 292 else
mbed_official 340:28d1f895c6fe 293 {
mbed_official 340:28d1f895c6fe 294 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
mbed_official 340:28d1f895c6fe 295 }
mbed_official 340:28d1f895c6fe 296 }
mbed_official 630:825f75ca301e 297
mbed_official 340:28d1f895c6fe 298 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
mbed_official 340:28d1f895c6fe 299 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
mbed_official 340:28d1f895c6fe 300 Communication speed, First bit, CRC calculation state, CRC Length */
mbed_official 630:825f75ca301e 301 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
mbed_official 340:28d1f895c6fe 302 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
mbed_official 340:28d1f895c6fe 303 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
mbed_official 630:825f75ca301e 304
mbed_official 340:28d1f895c6fe 305 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 340:28d1f895c6fe 306 {
mbed_official 340:28d1f895c6fe 307 hspi->Instance->CR1|= SPI_CR1_CRCL;
mbed_official 340:28d1f895c6fe 308 }
mbed_official 630:825f75ca301e 309
mbed_official 340:28d1f895c6fe 310 /* Configure : NSS management */
mbed_official 340:28d1f895c6fe 311 /* Configure : Rx Fifo Threshold */
mbed_official 340:28d1f895c6fe 312 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
mbed_official 340:28d1f895c6fe 313 hspi->Init.DataSize ) | frxth;
mbed_official 630:825f75ca301e 314
mbed_official 340:28d1f895c6fe 315 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
mbed_official 340:28d1f895c6fe 316 /* Configure : CRC Polynomial */
mbed_official 340:28d1f895c6fe 317 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official 340:28d1f895c6fe 318
mbed_official 340:28d1f895c6fe 319 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official 340:28d1f895c6fe 320 hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official 340:28d1f895c6fe 321
mbed_official 340:28d1f895c6fe 322 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 323 hspi->State= HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 324
mbed_official 340:28d1f895c6fe 325 return HAL_OK;
mbed_official 340:28d1f895c6fe 326 }
mbed_official 340:28d1f895c6fe 327
mbed_official 340:28d1f895c6fe 328 /**
mbed_official 630:825f75ca301e 329 * @brief DeInitialize the SPI peripheral.
mbed_official 630:825f75ca301e 330 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 331 * the configuration information for SPI module.
mbed_official 340:28d1f895c6fe 332 * @retval HAL status
mbed_official 340:28d1f895c6fe 333 */
mbed_official 340:28d1f895c6fe 334 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 335 {
mbed_official 340:28d1f895c6fe 336 /* Check the SPI handle allocation */
mbed_official 441:d2c15dda23c1 337 if(hspi == NULL)
mbed_official 340:28d1f895c6fe 338 {
mbed_official 441:d2c15dda23c1 339 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 340 }
mbed_official 340:28d1f895c6fe 341
mbed_official 340:28d1f895c6fe 342 /* Check the parameters */
mbed_official 340:28d1f895c6fe 343 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official 340:28d1f895c6fe 344 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 630:825f75ca301e 345
mbed_official 340:28d1f895c6fe 346 /* Disable the SPI Peripheral Clock */
mbed_official 340:28d1f895c6fe 347 __HAL_SPI_DISABLE(hspi);
mbed_official 630:825f75ca301e 348
mbed_official 340:28d1f895c6fe 349 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 340:28d1f895c6fe 350 HAL_SPI_MspDeInit(hspi);
mbed_official 630:825f75ca301e 351
mbed_official 340:28d1f895c6fe 352 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 353 hspi->State = HAL_SPI_STATE_RESET;
mbed_official 630:825f75ca301e 354
mbed_official 340:28d1f895c6fe 355 __HAL_UNLOCK(hspi);
mbed_official 630:825f75ca301e 356
mbed_official 340:28d1f895c6fe 357 return HAL_OK;
mbed_official 340:28d1f895c6fe 358 }
mbed_official 340:28d1f895c6fe 359
mbed_official 340:28d1f895c6fe 360 /**
mbed_official 630:825f75ca301e 361 * @brief Initialize the SPI MSP.
mbed_official 630:825f75ca301e 362 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 363 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 364 * @retval None
mbed_official 340:28d1f895c6fe 365 */
mbed_official 630:825f75ca301e 366 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 367 {
mbed_official 630:825f75ca301e 368 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 369 the HAL_SPI_MspInit should be implemented in the user file
mbed_official 340:28d1f895c6fe 370 */
mbed_official 340:28d1f895c6fe 371 }
mbed_official 340:28d1f895c6fe 372
mbed_official 340:28d1f895c6fe 373 /**
mbed_official 630:825f75ca301e 374 * @brief DeInitialize the SPI MSP.
mbed_official 630:825f75ca301e 375 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 376 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 377 * @retval None
mbed_official 340:28d1f895c6fe 378 */
mbed_official 630:825f75ca301e 379 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 380 {
mbed_official 630:825f75ca301e 381 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 382 the HAL_SPI_MspDeInit should be implemented in the user file
mbed_official 340:28d1f895c6fe 383 */
mbed_official 340:28d1f895c6fe 384 }
mbed_official 340:28d1f895c6fe 385
mbed_official 340:28d1f895c6fe 386 /**
mbed_official 340:28d1f895c6fe 387 * @}
mbed_official 340:28d1f895c6fe 388 */
mbed_official 340:28d1f895c6fe 389
mbed_official 630:825f75ca301e 390 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
mbed_official 630:825f75ca301e 391 * @brief Data transfers functions
mbed_official 340:28d1f895c6fe 392 *
mbed_official 630:825f75ca301e 393 @verbatim
mbed_official 630:825f75ca301e 394 ==============================================================================
mbed_official 630:825f75ca301e 395 ##### IO operation functions #####
mbed_official 340:28d1f895c6fe 396 ===============================================================================
mbed_official 630:825f75ca301e 397 [..]
mbed_official 340:28d1f895c6fe 398 This subsection provides a set of functions allowing to manage the SPI
mbed_official 340:28d1f895c6fe 399 data transfers.
mbed_official 630:825f75ca301e 400
mbed_official 630:825f75ca301e 401 [..] The SPI supports master and slave mode :
mbed_official 340:28d1f895c6fe 402
mbed_official 340:28d1f895c6fe 403 (#) There are two modes of transfer:
mbed_official 630:825f75ca301e 404 (++) Blocking mode: The communication is performed in polling mode.
mbed_official 630:825f75ca301e 405 The HAL status of all data processing is returned by the same function
mbed_official 630:825f75ca301e 406 after finishing transfer.
mbed_official 630:825f75ca301e 407 (++) No-Blocking mode: The communication is performed using Interrupts
mbed_official 630:825f75ca301e 408 or DMA, These APIs return the HAL status.
mbed_official 630:825f75ca301e 409 The end of the data processing will be indicated through the
mbed_official 630:825f75ca301e 410 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 630:825f75ca301e 411 using DMA mode.
mbed_official 630:825f75ca301e 412 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official 630:825f75ca301e 413 will be executed respectively at the end of the transmit or Receive process
mbed_official 630:825f75ca301e 414 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official 441:d2c15dda23c1 415
mbed_official 630:825f75ca301e 416 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
mbed_official 630:825f75ca301e 417 exist for 1Line (simplex) and 2Lines (full duplex) modes.
mbed_official 340:28d1f895c6fe 418
mbed_official 340:28d1f895c6fe 419 @endverbatim
mbed_official 340:28d1f895c6fe 420 * @{
mbed_official 340:28d1f895c6fe 421 */
mbed_official 340:28d1f895c6fe 422
mbed_official 340:28d1f895c6fe 423 /**
mbed_official 630:825f75ca301e 424 * @brief Transmit an amount of data in blocking mode.
mbed_official 630:825f75ca301e 425 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 426 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 427 * @param pData: pointer to data buffer
mbed_official 630:825f75ca301e 428 * @param Size: amount of data to be sent
mbed_official 630:825f75ca301e 429 * @param Timeout: Timeout duration
mbed_official 340:28d1f895c6fe 430 * @retval HAL status
mbed_official 340:28d1f895c6fe 431 */
mbed_official 340:28d1f895c6fe 432 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 433 {
mbed_official 441:d2c15dda23c1 434 uint32_t tickstart = HAL_GetTick();
mbed_official 441:d2c15dda23c1 435 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 441:d2c15dda23c1 436
mbed_official 340:28d1f895c6fe 437 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 441:d2c15dda23c1 438
mbed_official 441:d2c15dda23c1 439 /* Process Locked */
mbed_official 441:d2c15dda23c1 440 __HAL_LOCK(hspi);
mbed_official 441:d2c15dda23c1 441
mbed_official 630:825f75ca301e 442 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 340:28d1f895c6fe 443 {
mbed_official 441:d2c15dda23c1 444 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 445 goto error;
mbed_official 340:28d1f895c6fe 446 }
mbed_official 630:825f75ca301e 447
mbed_official 441:d2c15dda23c1 448 if((pData == NULL ) || (Size == 0))
mbed_official 340:28d1f895c6fe 449 {
mbed_official 441:d2c15dda23c1 450 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 451 goto error;
mbed_official 340:28d1f895c6fe 452 }
mbed_official 441:d2c15dda23c1 453
mbed_official 630:825f75ca301e 454 /* Set the transaction information */
mbed_official 340:28d1f895c6fe 455 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 340:28d1f895c6fe 456 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 457 hspi->pTxBuffPtr = pData;
mbed_official 340:28d1f895c6fe 458 hspi->TxXferSize = Size;
mbed_official 340:28d1f895c6fe 459 hspi->TxXferCount = Size;
mbed_official 630:825f75ca301e 460 hspi->pRxBuffPtr = (uint8_t *)NULL;
mbed_official 340:28d1f895c6fe 461 hspi->RxXferSize = 0;
mbed_official 340:28d1f895c6fe 462 hspi->RxXferCount = 0;
mbed_official 340:28d1f895c6fe 463
mbed_official 441:d2c15dda23c1 464 /* Configure communication direction : 1Line */
mbed_official 441:d2c15dda23c1 465 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 441:d2c15dda23c1 466 {
mbed_official 630:825f75ca301e 467 SPI_1LINE_TX(hspi);
mbed_official 441:d2c15dda23c1 468 }
mbed_official 441:d2c15dda23c1 469
mbed_official 340:28d1f895c6fe 470 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 471 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 472 {
mbed_official 630:825f75ca301e 473 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 474 }
mbed_official 340:28d1f895c6fe 475
mbed_official 630:825f75ca301e 476 /* Check if the SPI is already enabled */
mbed_official 340:28d1f895c6fe 477 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 340:28d1f895c6fe 478 {
mbed_official 340:28d1f895c6fe 479 /* Enable SPI peripheral */
mbed_official 340:28d1f895c6fe 480 __HAL_SPI_ENABLE(hspi);
mbed_official 340:28d1f895c6fe 481 }
mbed_official 630:825f75ca301e 482
mbed_official 340:28d1f895c6fe 483 /* Transmit data in 16 Bit mode */
mbed_official 630:825f75ca301e 484 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 485 {
mbed_official 441:d2c15dda23c1 486 /* Transmit data in 16 Bit mode */
mbed_official 340:28d1f895c6fe 487 while (hspi->TxXferCount > 0)
mbed_official 340:28d1f895c6fe 488 {
mbed_official 340:28d1f895c6fe 489 /* Wait until TXE flag is set to send data */
mbed_official 441:d2c15dda23c1 490 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
mbed_official 340:28d1f895c6fe 491 {
mbed_official 441:d2c15dda23c1 492 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 441:d2c15dda23c1 493 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 441:d2c15dda23c1 494 hspi->TxXferCount--;
mbed_official 340:28d1f895c6fe 495 }
mbed_official 441:d2c15dda23c1 496 else
mbed_official 441:d2c15dda23c1 497 {
mbed_official 441:d2c15dda23c1 498 /* Timeout management */
mbed_official 630:825f75ca301e 499 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
mbed_official 441:d2c15dda23c1 500 {
mbed_official 441:d2c15dda23c1 501 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 502 goto error;
mbed_official 441:d2c15dda23c1 503 }
mbed_official 441:d2c15dda23c1 504 }
mbed_official 340:28d1f895c6fe 505 }
mbed_official 340:28d1f895c6fe 506 }
mbed_official 340:28d1f895c6fe 507 /* Transmit data in 8 Bit mode */
mbed_official 340:28d1f895c6fe 508 else
mbed_official 340:28d1f895c6fe 509 {
mbed_official 340:28d1f895c6fe 510 while (hspi->TxXferCount > 0)
mbed_official 340:28d1f895c6fe 511 {
mbed_official 441:d2c15dda23c1 512 /* Wait until TXE flag is set to send data */
mbed_official 441:d2c15dda23c1 513 if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
mbed_official 340:28d1f895c6fe 514 {
mbed_official 441:d2c15dda23c1 515 if(hspi->TxXferCount > 1)
mbed_official 340:28d1f895c6fe 516 {
mbed_official 630:825f75ca301e 517 /* write on the data register in packing mode */
mbed_official 441:d2c15dda23c1 518 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 441:d2c15dda23c1 519 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 441:d2c15dda23c1 520 hspi->TxXferCount -= 2;
mbed_official 340:28d1f895c6fe 521 }
mbed_official 441:d2c15dda23c1 522 else
mbed_official 441:d2c15dda23c1 523 {
mbed_official 441:d2c15dda23c1 524 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
mbed_official 630:825f75ca301e 525 hspi->TxXferCount--;
mbed_official 441:d2c15dda23c1 526 }
mbed_official 340:28d1f895c6fe 527 }
mbed_official 340:28d1f895c6fe 528 else
mbed_official 340:28d1f895c6fe 529 {
mbed_official 441:d2c15dda23c1 530 /* Timeout management */
mbed_official 630:825f75ca301e 531 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
mbed_official 340:28d1f895c6fe 532 {
mbed_official 441:d2c15dda23c1 533 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 534 goto error;
mbed_official 340:28d1f895c6fe 535 }
mbed_official 340:28d1f895c6fe 536 }
mbed_official 340:28d1f895c6fe 537 }
mbed_official 340:28d1f895c6fe 538 }
mbed_official 340:28d1f895c6fe 539
mbed_official 340:28d1f895c6fe 540 /* Enable CRC Transmission */
mbed_official 630:825f75ca301e 541 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 542 {
mbed_official 340:28d1f895c6fe 543 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 544 }
mbed_official 340:28d1f895c6fe 545
mbed_official 630:825f75ca301e 546 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 547 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 548 {
mbed_official 630:825f75ca301e 549 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 550 }
mbed_official 630:825f75ca301e 551
mbed_official 630:825f75ca301e 552 /* Clear overrun flag in 2 Lines communication mode because received is not read */
mbed_official 340:28d1f895c6fe 553 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 340:28d1f895c6fe 554 {
mbed_official 340:28d1f895c6fe 555 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 340:28d1f895c6fe 556 }
mbed_official 630:825f75ca301e 557
mbed_official 340:28d1f895c6fe 558 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 630:825f75ca301e 559 {
mbed_official 630:825f75ca301e 560 errorcode = HAL_ERROR;
mbed_official 340:28d1f895c6fe 561 }
mbed_official 441:d2c15dda23c1 562
mbed_official 441:d2c15dda23c1 563 error:
mbed_official 441:d2c15dda23c1 564 hspi->State = HAL_SPI_STATE_READY;
mbed_official 441:d2c15dda23c1 565 /* Process Unlocked */
mbed_official 441:d2c15dda23c1 566 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 567 return errorcode;
mbed_official 340:28d1f895c6fe 568 }
mbed_official 340:28d1f895c6fe 569
mbed_official 340:28d1f895c6fe 570 /**
mbed_official 630:825f75ca301e 571 * @brief Receive an amount of data in blocking mode.
mbed_official 630:825f75ca301e 572 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 573 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 574 * @param pData: pointer to data buffer
mbed_official 630:825f75ca301e 575 * @param Size: amount of data to be received
mbed_official 630:825f75ca301e 576 * @param Timeout: Timeout duration
mbed_official 340:28d1f895c6fe 577 * @retval HAL status
mbed_official 340:28d1f895c6fe 578 */
mbed_official 340:28d1f895c6fe 579 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 580 {
mbed_official 340:28d1f895c6fe 581 __IO uint16_t tmpreg;
mbed_official 441:d2c15dda23c1 582 uint32_t tickstart = HAL_GetTick();
mbed_official 441:d2c15dda23c1 583 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 340:28d1f895c6fe 584
mbed_official 340:28d1f895c6fe 585 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 340:28d1f895c6fe 586 {
mbed_official 340:28d1f895c6fe 587 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 630:825f75ca301e 588 /* in this case we call the TransmitReceive process */
mbed_official 441:d2c15dda23c1 589 /* Process Locked */
mbed_official 340:28d1f895c6fe 590 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
mbed_official 340:28d1f895c6fe 591 }
mbed_official 630:825f75ca301e 592
mbed_official 340:28d1f895c6fe 593 /* Process Locked */
mbed_official 340:28d1f895c6fe 594 __HAL_LOCK(hspi);
mbed_official 441:d2c15dda23c1 595
mbed_official 441:d2c15dda23c1 596 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 441:d2c15dda23c1 597 {
mbed_official 441:d2c15dda23c1 598 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 599 goto error;
mbed_official 441:d2c15dda23c1 600 }
mbed_official 441:d2c15dda23c1 601
mbed_official 441:d2c15dda23c1 602 if((pData == NULL ) || (Size == 0))
mbed_official 441:d2c15dda23c1 603 {
mbed_official 441:d2c15dda23c1 604 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 605 goto error;
mbed_official 441:d2c15dda23c1 606 }
mbed_official 630:825f75ca301e 607
mbed_official 340:28d1f895c6fe 608 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 340:28d1f895c6fe 609 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 610 hspi->pRxBuffPtr = pData;
mbed_official 340:28d1f895c6fe 611 hspi->RxXferSize = Size;
mbed_official 340:28d1f895c6fe 612 hspi->RxXferCount = Size;
mbed_official 630:825f75ca301e 613 hspi->pTxBuffPtr = (uint8_t *)NULL;
mbed_official 340:28d1f895c6fe 614 hspi->TxXferSize = 0;
mbed_official 340:28d1f895c6fe 615 hspi->TxXferCount = 0;
mbed_official 441:d2c15dda23c1 616
mbed_official 340:28d1f895c6fe 617 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 618 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 619 {
mbed_official 630:825f75ca301e 620 SPI_RESET_CRC(hspi);
mbed_official 441:d2c15dda23c1 621 /* this is done to handle the CRCNEXT before the latest data */
mbed_official 441:d2c15dda23c1 622 hspi->RxXferCount--;
mbed_official 340:28d1f895c6fe 623 }
mbed_official 340:28d1f895c6fe 624
mbed_official 630:825f75ca301e 625 /* Set the Rx Fido threshold */
mbed_official 340:28d1f895c6fe 626 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 627 {
mbed_official 630:825f75ca301e 628 /* set fiforxthresold according the reception data length: 16bit */
mbed_official 340:28d1f895c6fe 629 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 630 }
mbed_official 340:28d1f895c6fe 631 else
mbed_official 340:28d1f895c6fe 632 {
mbed_official 630:825f75ca301e 633 /* set fiforxthresold according the reception data length: 8bit */
mbed_official 340:28d1f895c6fe 634 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 635 }
mbed_official 340:28d1f895c6fe 636
mbed_official 340:28d1f895c6fe 637 /* Configure communication direction 1Line and enabled SPI if needed */
mbed_official 340:28d1f895c6fe 638 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 340:28d1f895c6fe 639 {
mbed_official 630:825f75ca301e 640 SPI_1LINE_RX(hspi);
mbed_official 340:28d1f895c6fe 641 }
mbed_official 340:28d1f895c6fe 642
mbed_official 441:d2c15dda23c1 643 /* Check if the SPI is already enabled */
mbed_official 340:28d1f895c6fe 644 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 340:28d1f895c6fe 645 {
mbed_official 441:d2c15dda23c1 646 /* Enable SPI peripheral */
mbed_official 340:28d1f895c6fe 647 __HAL_SPI_ENABLE(hspi);
mbed_official 340:28d1f895c6fe 648 }
mbed_official 340:28d1f895c6fe 649
mbed_official 340:28d1f895c6fe 650 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 651 {
mbed_official 630:825f75ca301e 652 /* Transfer loop */
mbed_official 441:d2c15dda23c1 653 while(hspi->RxXferCount > 0)
mbed_official 340:28d1f895c6fe 654 {
mbed_official 441:d2c15dda23c1 655 /* Check the RXNE flag */
mbed_official 441:d2c15dda23c1 656 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
mbed_official 340:28d1f895c6fe 657 {
mbed_official 441:d2c15dda23c1 658 /* read the received data */
mbed_official 441:d2c15dda23c1 659 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 441:d2c15dda23c1 660 hspi->RxXferCount--;
mbed_official 340:28d1f895c6fe 661 }
mbed_official 441:d2c15dda23c1 662 else
mbed_official 441:d2c15dda23c1 663 {
mbed_official 630:825f75ca301e 664 /* Timeout management */
mbed_official 441:d2c15dda23c1 665 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
mbed_official 441:d2c15dda23c1 666 {
mbed_official 441:d2c15dda23c1 667 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 668 goto error;
mbed_official 441:d2c15dda23c1 669 }
mbed_official 441:d2c15dda23c1 670 }
mbed_official 340:28d1f895c6fe 671 }
mbed_official 340:28d1f895c6fe 672 }
mbed_official 441:d2c15dda23c1 673 else
mbed_official 441:d2c15dda23c1 674 {
mbed_official 630:825f75ca301e 675 /* Transfer loop */
mbed_official 441:d2c15dda23c1 676 while(hspi->RxXferCount > 0)
mbed_official 340:28d1f895c6fe 677 {
mbed_official 441:d2c15dda23c1 678 /* Check the RXNE flag */
mbed_official 441:d2c15dda23c1 679 if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
mbed_official 340:28d1f895c6fe 680 {
mbed_official 441:d2c15dda23c1 681 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 441:d2c15dda23c1 682 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 441:d2c15dda23c1 683 hspi->RxXferCount--;
mbed_official 340:28d1f895c6fe 684 }
mbed_official 441:d2c15dda23c1 685 else
mbed_official 441:d2c15dda23c1 686 {
mbed_official 630:825f75ca301e 687 /* Timeout management */
mbed_official 630:825f75ca301e 688 if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
mbed_official 441:d2c15dda23c1 689 {
mbed_official 441:d2c15dda23c1 690 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 691 goto error;
mbed_official 441:d2c15dda23c1 692 }
mbed_official 441:d2c15dda23c1 693 }
mbed_official 441:d2c15dda23c1 694 }
mbed_official 340:28d1f895c6fe 695 }
mbed_official 340:28d1f895c6fe 696
mbed_official 441:d2c15dda23c1 697 /* Handle the CRC Transmission */
mbed_official 630:825f75ca301e 698 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 699 {
mbed_official 441:d2c15dda23c1 700 /* freeze the CRC before the latest data */
mbed_official 441:d2c15dda23c1 701 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
mbed_official 630:825f75ca301e 702
mbed_official 441:d2c15dda23c1 703 /* Read the latest data */
mbed_official 441:d2c15dda23c1 704 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 441:d2c15dda23c1 705 {
mbed_official 630:825f75ca301e 706 /* the latest data has not been received */
mbed_official 441:d2c15dda23c1 707 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 708 goto error;
mbed_official 441:d2c15dda23c1 709 }
mbed_official 630:825f75ca301e 710
mbed_official 441:d2c15dda23c1 711 /* Receive last data in 16 Bit mode */
mbed_official 441:d2c15dda23c1 712 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 713 {
mbed_official 441:d2c15dda23c1 714 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 441:d2c15dda23c1 715 }
mbed_official 441:d2c15dda23c1 716 /* Receive last data in 8 Bit mode */
mbed_official 441:d2c15dda23c1 717 else
mbed_official 441:d2c15dda23c1 718 {
mbed_official 441:d2c15dda23c1 719 *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 720 }
mbed_official 630:825f75ca301e 721
mbed_official 441:d2c15dda23c1 722 /* Wait until TXE flag */
mbed_official 441:d2c15dda23c1 723 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 441:d2c15dda23c1 724 {
mbed_official 441:d2c15dda23c1 725 /* Flag Error*/
mbed_official 630:825f75ca301e 726 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official 630:825f75ca301e 727 errorcode = HAL_TIMEOUT;
mbed_official 630:825f75ca301e 728 goto error;
mbed_official 441:d2c15dda23c1 729 }
mbed_official 630:825f75ca301e 730
mbed_official 441:d2c15dda23c1 731 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 441:d2c15dda23c1 732 {
mbed_official 340:28d1f895c6fe 733 tmpreg = hspi->Instance->DR;
mbed_official 630:825f75ca301e 734 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 735 UNUSED(tmpreg);
mbed_official 340:28d1f895c6fe 736 }
mbed_official 340:28d1f895c6fe 737 else
mbed_official 340:28d1f895c6fe 738 {
mbed_official 340:28d1f895c6fe 739 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 740 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 741 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 742
mbed_official 340:28d1f895c6fe 743 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 340:28d1f895c6fe 744 {
mbed_official 340:28d1f895c6fe 745 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 340:28d1f895c6fe 746 {
mbed_official 630:825f75ca301e 747 /* Error on the CRC reception */
mbed_official 630:825f75ca301e 748 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official 630:825f75ca301e 749 errorcode = HAL_TIMEOUT;
mbed_official 630:825f75ca301e 750 goto error;
mbed_official 340:28d1f895c6fe 751 }
mbed_official 340:28d1f895c6fe 752 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 753 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 754 UNUSED(tmpreg);
mbed_official 340:28d1f895c6fe 755 }
mbed_official 340:28d1f895c6fe 756 }
mbed_official 340:28d1f895c6fe 757 }
mbed_official 340:28d1f895c6fe 758
mbed_official 340:28d1f895c6fe 759 /* Check the end of the transaction */
mbed_official 340:28d1f895c6fe 760 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 340:28d1f895c6fe 761 {
mbed_official 630:825f75ca301e 762 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
mbed_official 340:28d1f895c6fe 763 }
mbed_official 630:825f75ca301e 764
mbed_official 340:28d1f895c6fe 765 /* Check if CRC error occurred */
mbed_official 340:28d1f895c6fe 766 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 340:28d1f895c6fe 767 {
mbed_official 340:28d1f895c6fe 768 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 340:28d1f895c6fe 769 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 340:28d1f895c6fe 770 }
mbed_official 630:825f75ca301e 771
mbed_official 441:d2c15dda23c1 772 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 441:d2c15dda23c1 773 {
mbed_official 441:d2c15dda23c1 774 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 775 }
mbed_official 630:825f75ca301e 776
mbed_official 441:d2c15dda23c1 777 error :
mbed_official 441:d2c15dda23c1 778 hspi->State = HAL_SPI_STATE_READY;
mbed_official 441:d2c15dda23c1 779 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 780 return errorcode;
mbed_official 340:28d1f895c6fe 781 }
mbed_official 340:28d1f895c6fe 782
mbed_official 340:28d1f895c6fe 783 /**
mbed_official 630:825f75ca301e 784 * @brief Transmit and Receive an amount of data in blocking mode.
mbed_official 630:825f75ca301e 785 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 786 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 787 * @param pTxData: pointer to transmission data buffer
mbed_official 630:825f75ca301e 788 * @param pRxData: pointer to reception data buffer
mbed_official 630:825f75ca301e 789 * @param Size: amount of data to be sent and received
mbed_official 630:825f75ca301e 790 * @param Timeout: Timeout duration
mbed_official 340:28d1f895c6fe 791 * @retval HAL status
mbed_official 340:28d1f895c6fe 792 */
mbed_official 340:28d1f895c6fe 793 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 794 {
mbed_official 441:d2c15dda23c1 795 __IO uint16_t tmpreg;
mbed_official 441:d2c15dda23c1 796 uint32_t tickstart = HAL_GetTick();
mbed_official 441:d2c15dda23c1 797 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 630:825f75ca301e 798
mbed_official 340:28d1f895c6fe 799 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 441:d2c15dda23c1 800
mbed_official 441:d2c15dda23c1 801 /* Process Locked */
mbed_official 441:d2c15dda23c1 802 __HAL_LOCK(hspi);
mbed_official 441:d2c15dda23c1 803
mbed_official 441:d2c15dda23c1 804 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 340:28d1f895c6fe 805 {
mbed_official 441:d2c15dda23c1 806 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 807 goto error;
mbed_official 340:28d1f895c6fe 808 }
mbed_official 630:825f75ca301e 809
mbed_official 441:d2c15dda23c1 810 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
mbed_official 340:28d1f895c6fe 811 {
mbed_official 441:d2c15dda23c1 812 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 813 goto error;
mbed_official 340:28d1f895c6fe 814 }
mbed_official 630:825f75ca301e 815
mbed_official 340:28d1f895c6fe 816 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 340:28d1f895c6fe 817 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 818 hspi->pRxBuffPtr = pRxData;
mbed_official 340:28d1f895c6fe 819 hspi->RxXferCount = Size;
mbed_official 340:28d1f895c6fe 820 hspi->RxXferSize = Size;
mbed_official 340:28d1f895c6fe 821 hspi->pTxBuffPtr = pTxData;
mbed_official 340:28d1f895c6fe 822 hspi->TxXferCount = Size;
mbed_official 630:825f75ca301e 823 hspi->TxXferSize = Size;
mbed_official 630:825f75ca301e 824
mbed_official 340:28d1f895c6fe 825 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 826 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 827 {
mbed_official 630:825f75ca301e 828 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 829 }
mbed_official 630:825f75ca301e 830
mbed_official 340:28d1f895c6fe 831 /* Set the Rx Fido threshold */
mbed_official 340:28d1f895c6fe 832 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
mbed_official 340:28d1f895c6fe 833 {
mbed_official 630:825f75ca301e 834 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 340:28d1f895c6fe 835 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 836 }
mbed_official 340:28d1f895c6fe 837 else
mbed_official 340:28d1f895c6fe 838 {
mbed_official 630:825f75ca301e 839 /* set fiforxthreshold according the reception data length: 8bit */
mbed_official 340:28d1f895c6fe 840 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 841 }
mbed_official 630:825f75ca301e 842
mbed_official 630:825f75ca301e 843 /* Check if the SPI is already enabled */
mbed_official 340:28d1f895c6fe 844 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 340:28d1f895c6fe 845 {
mbed_official 630:825f75ca301e 846 /* Enable SPI peripheral */
mbed_official 340:28d1f895c6fe 847 __HAL_SPI_ENABLE(hspi);
mbed_official 340:28d1f895c6fe 848 }
mbed_official 630:825f75ca301e 849
mbed_official 340:28d1f895c6fe 850 /* Transmit and Receive data in 16 Bit mode */
mbed_official 340:28d1f895c6fe 851 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 630:825f75ca301e 852 {
mbed_official 340:28d1f895c6fe 853 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
mbed_official 340:28d1f895c6fe 854 {
mbed_official 441:d2c15dda23c1 855 /* Check TXE flag */
mbed_official 340:28d1f895c6fe 856 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 340:28d1f895c6fe 857 {
mbed_official 340:28d1f895c6fe 858 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 340:28d1f895c6fe 859 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 860 hspi->TxXferCount--;
mbed_official 630:825f75ca301e 861
mbed_official 340:28d1f895c6fe 862 /* Enable CRC Transmission */
mbed_official 630:825f75ca301e 863 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 340:28d1f895c6fe 864 {
mbed_official 441:d2c15dda23c1 865 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
mbed_official 630:825f75ca301e 866 }
mbed_official 340:28d1f895c6fe 867 }
mbed_official 630:825f75ca301e 868
mbed_official 441:d2c15dda23c1 869 /* Check RXNE flag */
mbed_official 340:28d1f895c6fe 870 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 340:28d1f895c6fe 871 {
mbed_official 340:28d1f895c6fe 872 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 873 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 874 hspi->RxXferCount--;
mbed_official 340:28d1f895c6fe 875 }
mbed_official 441:d2c15dda23c1 876 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
mbed_official 340:28d1f895c6fe 877 {
mbed_official 441:d2c15dda23c1 878 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 879 goto error;
mbed_official 340:28d1f895c6fe 880 }
mbed_official 630:825f75ca301e 881 }
mbed_official 340:28d1f895c6fe 882 }
mbed_official 340:28d1f895c6fe 883 /* Transmit and Receive data in 8 Bit mode */
mbed_official 340:28d1f895c6fe 884 else
mbed_official 630:825f75ca301e 885 {
mbed_official 340:28d1f895c6fe 886 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
mbed_official 340:28d1f895c6fe 887 {
mbed_official 441:d2c15dda23c1 888 /* check TXE flag */
mbed_official 340:28d1f895c6fe 889 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 340:28d1f895c6fe 890 {
mbed_official 441:d2c15dda23c1 891 if(hspi->TxXferCount > 1)
mbed_official 340:28d1f895c6fe 892 {
mbed_official 340:28d1f895c6fe 893 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 340:28d1f895c6fe 894 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 895 hspi->TxXferCount -= 2;
mbed_official 630:825f75ca301e 896 }
mbed_official 340:28d1f895c6fe 897 else
mbed_official 340:28d1f895c6fe 898 {
mbed_official 340:28d1f895c6fe 899 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 340:28d1f895c6fe 900 hspi->TxXferCount--;
mbed_official 340:28d1f895c6fe 901 }
mbed_official 630:825f75ca301e 902
mbed_official 340:28d1f895c6fe 903 /* Enable CRC Transmission */
mbed_official 630:825f75ca301e 904 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 340:28d1f895c6fe 905 {
mbed_official 441:d2c15dda23c1 906 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 907 }
mbed_official 340:28d1f895c6fe 908 }
mbed_official 630:825f75ca301e 909
mbed_official 340:28d1f895c6fe 910 /* Wait until RXNE flag is reset */
mbed_official 340:28d1f895c6fe 911 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 340:28d1f895c6fe 912 {
mbed_official 340:28d1f895c6fe 913 if(hspi->RxXferCount > 1)
mbed_official 340:28d1f895c6fe 914 {
mbed_official 340:28d1f895c6fe 915 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 916 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 917 hspi->RxXferCount -= 2;
mbed_official 340:28d1f895c6fe 918 if(hspi->RxXferCount <= 1)
mbed_official 340:28d1f895c6fe 919 {
mbed_official 340:28d1f895c6fe 920 /* set fiforxthresold before to switch on 8 bit data size */
mbed_official 340:28d1f895c6fe 921 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 922 }
mbed_official 340:28d1f895c6fe 923 }
mbed_official 340:28d1f895c6fe 924 else
mbed_official 340:28d1f895c6fe 925 {
mbed_official 340:28d1f895c6fe 926 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 927 hspi->RxXferCount--;
mbed_official 340:28d1f895c6fe 928 }
mbed_official 340:28d1f895c6fe 929 }
mbed_official 441:d2c15dda23c1 930 if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
mbed_official 340:28d1f895c6fe 931 {
mbed_official 441:d2c15dda23c1 932 errorcode = HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 933 goto error;
mbed_official 441:d2c15dda23c1 934 }
mbed_official 340:28d1f895c6fe 935 }
mbed_official 340:28d1f895c6fe 936 }
mbed_official 630:825f75ca301e 937
mbed_official 340:28d1f895c6fe 938 /* Read CRC from DR to close CRC calculation process */
mbed_official 630:825f75ca301e 939 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 940 {
mbed_official 340:28d1f895c6fe 941 /* Wait until TXE flag */
mbed_official 340:28d1f895c6fe 942 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 943 {
mbed_official 630:825f75ca301e 944 /* Error on the CRC reception */
mbed_official 340:28d1f895c6fe 945 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 630:825f75ca301e 946 errorcode = HAL_TIMEOUT;
mbed_official 630:825f75ca301e 947 goto error;
mbed_official 340:28d1f895c6fe 948 }
mbed_official 630:825f75ca301e 949
mbed_official 340:28d1f895c6fe 950 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 340:28d1f895c6fe 951 {
mbed_official 340:28d1f895c6fe 952 tmpreg = hspi->Instance->DR;
mbed_official 630:825f75ca301e 953 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 954 UNUSED(tmpreg);
mbed_official 340:28d1f895c6fe 955 }
mbed_official 340:28d1f895c6fe 956 else
mbed_official 340:28d1f895c6fe 957 {
mbed_official 340:28d1f895c6fe 958 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 959 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 960 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 961
mbed_official 340:28d1f895c6fe 962 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 340:28d1f895c6fe 963 {
mbed_official 630:825f75ca301e 964 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 965 {
mbed_official 630:825f75ca301e 966 /* Error on the CRC reception */
mbed_official 340:28d1f895c6fe 967 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 630:825f75ca301e 968 errorcode = HAL_TIMEOUT;
mbed_official 630:825f75ca301e 969 goto error;
mbed_official 630:825f75ca301e 970 }
mbed_official 340:28d1f895c6fe 971 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 972 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 973 UNUSED(tmpreg);
mbed_official 340:28d1f895c6fe 974 }
mbed_official 340:28d1f895c6fe 975 }
mbed_official 340:28d1f895c6fe 976 }
mbed_official 340:28d1f895c6fe 977
mbed_official 340:28d1f895c6fe 978 /* Check if CRC error occurred */
mbed_official 340:28d1f895c6fe 979 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 340:28d1f895c6fe 980 {
mbed_official 340:28d1f895c6fe 981 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 340:28d1f895c6fe 982 /* Clear CRC Flag */
mbed_official 340:28d1f895c6fe 983 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 630:825f75ca301e 984
mbed_official 441:d2c15dda23c1 985 errorcode = HAL_ERROR;
mbed_official 340:28d1f895c6fe 986 }
mbed_official 441:d2c15dda23c1 987
mbed_official 630:825f75ca301e 988 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 989 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 990 {
mbed_official 630:825f75ca301e 991 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 992 }
mbed_official 630:825f75ca301e 993
mbed_official 630:825f75ca301e 994 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 630:825f75ca301e 995 {
mbed_official 630:825f75ca301e 996 errorcode = HAL_ERROR;
mbed_official 630:825f75ca301e 997 }
mbed_official 630:825f75ca301e 998
mbed_official 630:825f75ca301e 999 error :
mbed_official 441:d2c15dda23c1 1000 hspi->State = HAL_SPI_STATE_READY;
mbed_official 441:d2c15dda23c1 1001 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1002 return errorcode;
mbed_official 340:28d1f895c6fe 1003 }
mbed_official 340:28d1f895c6fe 1004
mbed_official 340:28d1f895c6fe 1005 /**
mbed_official 630:825f75ca301e 1006 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
mbed_official 630:825f75ca301e 1007 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1008 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1009 * @param pData: pointer to data buffer
mbed_official 630:825f75ca301e 1010 * @param Size: amount of data to be sent
mbed_official 340:28d1f895c6fe 1011 * @retval HAL status
mbed_official 340:28d1f895c6fe 1012 */
mbed_official 340:28d1f895c6fe 1013 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 340:28d1f895c6fe 1014 {
mbed_official 441:d2c15dda23c1 1015 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 340:28d1f895c6fe 1016 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 630:825f75ca301e 1017
mbed_official 441:d2c15dda23c1 1018 /* Process Locked */
mbed_official 441:d2c15dda23c1 1019 __HAL_LOCK(hspi);
mbed_official 340:28d1f895c6fe 1020
mbed_official 630:825f75ca301e 1021 if((pData == NULL) || (Size == 0))
mbed_official 441:d2c15dda23c1 1022 {
mbed_official 441:d2c15dda23c1 1023 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1024 goto error;
mbed_official 441:d2c15dda23c1 1025 }
mbed_official 630:825f75ca301e 1026
mbed_official 441:d2c15dda23c1 1027 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 441:d2c15dda23c1 1028 {
mbed_official 441:d2c15dda23c1 1029 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 1030 goto error;
mbed_official 441:d2c15dda23c1 1031 }
mbed_official 630:825f75ca301e 1032
mbed_official 630:825f75ca301e 1033 /* prepare the transfer */
mbed_official 441:d2c15dda23c1 1034 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 441:d2c15dda23c1 1035 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 441:d2c15dda23c1 1036 hspi->pTxBuffPtr = pData;
mbed_official 441:d2c15dda23c1 1037 hspi->TxXferSize = Size;
mbed_official 441:d2c15dda23c1 1038 hspi->TxXferCount = Size;
mbed_official 630:825f75ca301e 1039 hspi->pRxBuffPtr = (uint8_t *)NULL;
mbed_official 441:d2c15dda23c1 1040 hspi->RxXferSize = 0;
mbed_official 441:d2c15dda23c1 1041 hspi->RxXferCount = 0;
mbed_official 630:825f75ca301e 1042 hspi->RxISR = NULL;
mbed_official 441:d2c15dda23c1 1043
mbed_official 630:825f75ca301e 1044 /* Set the function for IT treatment */
mbed_official 441:d2c15dda23c1 1045 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 441:d2c15dda23c1 1046 {
mbed_official 441:d2c15dda23c1 1047 hspi->TxISR = SPI_TxISR_16BIT;
mbed_official 340:28d1f895c6fe 1048 }
mbed_official 340:28d1f895c6fe 1049 else
mbed_official 340:28d1f895c6fe 1050 {
mbed_official 441:d2c15dda23c1 1051 hspi->TxISR = SPI_TxISR_8BIT;
mbed_official 441:d2c15dda23c1 1052 }
mbed_official 630:825f75ca301e 1053
mbed_official 441:d2c15dda23c1 1054 /* Configure communication direction : 1Line */
mbed_official 441:d2c15dda23c1 1055 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 441:d2c15dda23c1 1056 {
mbed_official 630:825f75ca301e 1057 SPI_1LINE_TX(hspi);
mbed_official 441:d2c15dda23c1 1058 }
mbed_official 630:825f75ca301e 1059
mbed_official 441:d2c15dda23c1 1060 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 1061 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1062 {
mbed_official 630:825f75ca301e 1063 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 1064 }
mbed_official 630:825f75ca301e 1065
mbed_official 441:d2c15dda23c1 1066 /* Enable TXE and ERR interrupt */
mbed_official 441:d2c15dda23c1 1067 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
mbed_official 630:825f75ca301e 1068
mbed_official 630:825f75ca301e 1069
mbed_official 630:825f75ca301e 1070 /* Check if the SPI is already enabled */
mbed_official 441:d2c15dda23c1 1071 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 441:d2c15dda23c1 1072 {
mbed_official 630:825f75ca301e 1073 /* Enable SPI peripheral */
mbed_official 441:d2c15dda23c1 1074 __HAL_SPI_ENABLE(hspi);
mbed_official 441:d2c15dda23c1 1075 }
mbed_official 630:825f75ca301e 1076
mbed_official 441:d2c15dda23c1 1077 error :
mbed_official 441:d2c15dda23c1 1078 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1079 return errorcode;
mbed_official 340:28d1f895c6fe 1080 }
mbed_official 340:28d1f895c6fe 1081
mbed_official 340:28d1f895c6fe 1082 /**
mbed_official 630:825f75ca301e 1083 * @brief Receive an amount of data in non-blocking mode with Interrupt.
mbed_official 630:825f75ca301e 1084 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1085 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1086 * @param pData: pointer to data buffer
mbed_official 630:825f75ca301e 1087 * @param Size: amount of data to be sent
mbed_official 340:28d1f895c6fe 1088 * @retval HAL status
mbed_official 340:28d1f895c6fe 1089 */
mbed_official 340:28d1f895c6fe 1090 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 340:28d1f895c6fe 1091 {
mbed_official 441:d2c15dda23c1 1092 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 630:825f75ca301e 1093
mbed_official 441:d2c15dda23c1 1094 /* Process Locked */
mbed_official 441:d2c15dda23c1 1095 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1096
mbed_official 441:d2c15dda23c1 1097 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 340:28d1f895c6fe 1098 {
mbed_official 441:d2c15dda23c1 1099 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 1100 goto error;
mbed_official 441:d2c15dda23c1 1101 }
mbed_official 441:d2c15dda23c1 1102 if((pData == NULL) || (Size == 0))
mbed_official 630:825f75ca301e 1103 {
mbed_official 441:d2c15dda23c1 1104 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1105 goto error;
mbed_official 441:d2c15dda23c1 1106 }
mbed_official 630:825f75ca301e 1107
mbed_official 441:d2c15dda23c1 1108 /* Configure communication */
mbed_official 441:d2c15dda23c1 1109 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 441:d2c15dda23c1 1110 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 441:d2c15dda23c1 1111 hspi->pRxBuffPtr = pData;
mbed_official 441:d2c15dda23c1 1112 hspi->RxXferSize = Size;
mbed_official 441:d2c15dda23c1 1113 hspi->RxXferCount = Size;
mbed_official 630:825f75ca301e 1114 hspi->pTxBuffPtr = (uint8_t *)NULL;
mbed_official 441:d2c15dda23c1 1115 hspi->TxXferSize = 0;
mbed_official 441:d2c15dda23c1 1116 hspi->TxXferCount = 0;
mbed_official 630:825f75ca301e 1117
mbed_official 441:d2c15dda23c1 1118 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 441:d2c15dda23c1 1119 {
mbed_official 340:28d1f895c6fe 1120 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 1121 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1122 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 630:825f75ca301e 1123 /* in this we call the TransmitReceive process */
mbed_official 441:d2c15dda23c1 1124 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
mbed_official 441:d2c15dda23c1 1125 }
mbed_official 630:825f75ca301e 1126
mbed_official 630:825f75ca301e 1127 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1128 {
mbed_official 441:d2c15dda23c1 1129 hspi->CRCSize = 1;
mbed_official 441:d2c15dda23c1 1130 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 340:28d1f895c6fe 1131 {
mbed_official 441:d2c15dda23c1 1132 hspi->CRCSize = 2;
mbed_official 340:28d1f895c6fe 1133 }
mbed_official 340:28d1f895c6fe 1134 }
mbed_official 340:28d1f895c6fe 1135 else
mbed_official 340:28d1f895c6fe 1136 {
mbed_official 441:d2c15dda23c1 1137 hspi->CRCSize = 0;
mbed_official 441:d2c15dda23c1 1138 }
mbed_official 630:825f75ca301e 1139
mbed_official 630:825f75ca301e 1140 hspi->TxISR = NULL;
mbed_official 630:825f75ca301e 1141 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
mbed_official 441:d2c15dda23c1 1142 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 441:d2c15dda23c1 1143 {
mbed_official 630:825f75ca301e 1144 /* set fiforxthresold according the reception data length: 16 bit */
mbed_official 441:d2c15dda23c1 1145 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 441:d2c15dda23c1 1146 hspi->RxISR = SPI_RxISR_16BIT;
mbed_official 441:d2c15dda23c1 1147 }
mbed_official 441:d2c15dda23c1 1148 else
mbed_official 441:d2c15dda23c1 1149 {
mbed_official 630:825f75ca301e 1150 /* set fiforxthresold according the reception data length: 8 bit */
mbed_official 441:d2c15dda23c1 1151 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 441:d2c15dda23c1 1152 hspi->RxISR = SPI_RxISR_8BIT;
mbed_official 340:28d1f895c6fe 1153 }
mbed_official 630:825f75ca301e 1154
mbed_official 441:d2c15dda23c1 1155 /* Configure communication direction : 1Line */
mbed_official 441:d2c15dda23c1 1156 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 441:d2c15dda23c1 1157 {
mbed_official 630:825f75ca301e 1158 SPI_1LINE_RX(hspi);
mbed_official 441:d2c15dda23c1 1159 }
mbed_official 630:825f75ca301e 1160
mbed_official 441:d2c15dda23c1 1161 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 1162 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1163 {
mbed_official 630:825f75ca301e 1164 SPI_RESET_CRC(hspi);
mbed_official 441:d2c15dda23c1 1165 }
mbed_official 630:825f75ca301e 1166
mbed_official 441:d2c15dda23c1 1167 /* Enable TXE and ERR interrupt */
mbed_official 441:d2c15dda23c1 1168 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 1169
mbed_official 630:825f75ca301e 1170 /* Check if the SPI is already enabled */
mbed_official 441:d2c15dda23c1 1171 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 441:d2c15dda23c1 1172 {
mbed_official 630:825f75ca301e 1173 /* Enable SPI peripheral */
mbed_official 441:d2c15dda23c1 1174 __HAL_SPI_ENABLE(hspi);
mbed_official 441:d2c15dda23c1 1175 }
mbed_official 630:825f75ca301e 1176
mbed_official 441:d2c15dda23c1 1177 error :
mbed_official 441:d2c15dda23c1 1178 /* Process Unlocked */
mbed_official 441:d2c15dda23c1 1179 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1180 return errorcode;
mbed_official 340:28d1f895c6fe 1181 }
mbed_official 340:28d1f895c6fe 1182
mbed_official 340:28d1f895c6fe 1183 /**
mbed_official 630:825f75ca301e 1184 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
mbed_official 630:825f75ca301e 1185 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1186 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1187 * @param pTxData: pointer to transmission data buffer
mbed_official 630:825f75ca301e 1188 * @param pRxData: pointer to reception data buffer
mbed_official 630:825f75ca301e 1189 * @param Size: amount of data to be sent and received
mbed_official 340:28d1f895c6fe 1190 * @retval HAL status
mbed_official 340:28d1f895c6fe 1191 */
mbed_official 340:28d1f895c6fe 1192 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 340:28d1f895c6fe 1193 {
mbed_official 441:d2c15dda23c1 1194 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 340:28d1f895c6fe 1195 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 630:825f75ca301e 1196
mbed_official 441:d2c15dda23c1 1197 /* Process locked */
mbed_official 441:d2c15dda23c1 1198 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1199
mbed_official 441:d2c15dda23c1 1200 if(!((hspi->State == HAL_SPI_STATE_READY) || \
mbed_official 441:d2c15dda23c1 1201 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
mbed_official 340:28d1f895c6fe 1202 {
mbed_official 441:d2c15dda23c1 1203 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 1204 goto error;
mbed_official 441:d2c15dda23c1 1205 }
mbed_official 630:825f75ca301e 1206
mbed_official 630:825f75ca301e 1207 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 441:d2c15dda23c1 1208 {
mbed_official 630:825f75ca301e 1209 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1210 goto error;
mbed_official 441:d2c15dda23c1 1211 }
mbed_official 630:825f75ca301e 1212
mbed_official 441:d2c15dda23c1 1213 hspi->CRCSize = 0;
mbed_official 630:825f75ca301e 1214 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1215 {
mbed_official 441:d2c15dda23c1 1216 hspi->CRCSize = 1;
mbed_official 441:d2c15dda23c1 1217 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 340:28d1f895c6fe 1218 {
mbed_official 441:d2c15dda23c1 1219 hspi->CRCSize = 2;
mbed_official 340:28d1f895c6fe 1220 }
mbed_official 441:d2c15dda23c1 1221 }
mbed_official 630:825f75ca301e 1222
mbed_official 441:d2c15dda23c1 1223 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 441:d2c15dda23c1 1224 {
mbed_official 441:d2c15dda23c1 1225 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 441:d2c15dda23c1 1226 }
mbed_official 630:825f75ca301e 1227
mbed_official 441:d2c15dda23c1 1228 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 441:d2c15dda23c1 1229 hspi->pTxBuffPtr = pTxData;
mbed_official 441:d2c15dda23c1 1230 hspi->TxXferSize = Size;
mbed_official 441:d2c15dda23c1 1231 hspi->TxXferCount = Size;
mbed_official 441:d2c15dda23c1 1232 hspi->pRxBuffPtr = pRxData;
mbed_official 441:d2c15dda23c1 1233 hspi->RxXferSize = Size;
mbed_official 441:d2c15dda23c1 1234 hspi->RxXferCount = Size;
mbed_official 630:825f75ca301e 1235
mbed_official 630:825f75ca301e 1236 /* Set the function for IT treatment */
mbed_official 441:d2c15dda23c1 1237 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 441:d2c15dda23c1 1238 {
mbed_official 441:d2c15dda23c1 1239 hspi->RxISR = SPI_2linesRxISR_16BIT;
mbed_official 630:825f75ca301e 1240 hspi->TxISR = SPI_2linesTxISR_16BIT;
mbed_official 340:28d1f895c6fe 1241 }
mbed_official 340:28d1f895c6fe 1242 else
mbed_official 340:28d1f895c6fe 1243 {
mbed_official 441:d2c15dda23c1 1244 hspi->RxISR = SPI_2linesRxISR_8BIT;
mbed_official 441:d2c15dda23c1 1245 hspi->TxISR = SPI_2linesTxISR_8BIT;
mbed_official 441:d2c15dda23c1 1246 }
mbed_official 630:825f75ca301e 1247
mbed_official 441:d2c15dda23c1 1248 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 1249 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1250 {
mbed_official 630:825f75ca301e 1251 SPI_RESET_CRC(hspi);
mbed_official 441:d2c15dda23c1 1252 }
mbed_official 630:825f75ca301e 1253
mbed_official 441:d2c15dda23c1 1254 /* check if packing mode is enabled and if there is more than 2 data to receive */
mbed_official 441:d2c15dda23c1 1255 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
mbed_official 441:d2c15dda23c1 1256 {
mbed_official 630:825f75ca301e 1257 /* set fiforxthresold according the reception data length: 16 bit */
mbed_official 441:d2c15dda23c1 1258 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 1259 }
mbed_official 441:d2c15dda23c1 1260 else
mbed_official 441:d2c15dda23c1 1261 {
mbed_official 630:825f75ca301e 1262 /* set fiforxthresold according the reception data length: 8 bit */
mbed_official 441:d2c15dda23c1 1263 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 441:d2c15dda23c1 1264 }
mbed_official 630:825f75ca301e 1265
mbed_official 441:d2c15dda23c1 1266 /* Enable TXE, RXNE and ERR interrupt */
mbed_official 441:d2c15dda23c1 1267 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 1268
mbed_official 630:825f75ca301e 1269 /* Check if the SPI is already enabled */
mbed_official 441:d2c15dda23c1 1270 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 441:d2c15dda23c1 1271 {
mbed_official 630:825f75ca301e 1272 /* Enable SPI peripheral */
mbed_official 441:d2c15dda23c1 1273 __HAL_SPI_ENABLE(hspi);
mbed_official 441:d2c15dda23c1 1274 }
mbed_official 630:825f75ca301e 1275
mbed_official 441:d2c15dda23c1 1276 error :
mbed_official 441:d2c15dda23c1 1277 /* Process Unlocked */
mbed_official 441:d2c15dda23c1 1278 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1279 return errorcode;
mbed_official 340:28d1f895c6fe 1280 }
mbed_official 340:28d1f895c6fe 1281
mbed_official 340:28d1f895c6fe 1282 /**
mbed_official 630:825f75ca301e 1283 * @brief Transmit an amount of data in non-blocking mode with DMA.
mbed_official 630:825f75ca301e 1284 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1285 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1286 * @param pData: pointer to data buffer
mbed_official 630:825f75ca301e 1287 * @param Size: amount of data to be sent
mbed_official 340:28d1f895c6fe 1288 * @retval HAL status
mbed_official 340:28d1f895c6fe 1289 */
mbed_official 340:28d1f895c6fe 1290 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 630:825f75ca301e 1291 {
mbed_official 441:d2c15dda23c1 1292 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 340:28d1f895c6fe 1293 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 630:825f75ca301e 1294
mbed_official 340:28d1f895c6fe 1295 /* Process Locked */
mbed_official 340:28d1f895c6fe 1296 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1297
mbed_official 630:825f75ca301e 1298 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 441:d2c15dda23c1 1299 {
mbed_official 441:d2c15dda23c1 1300 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 1301 goto error;
mbed_official 441:d2c15dda23c1 1302 }
mbed_official 630:825f75ca301e 1303
mbed_official 441:d2c15dda23c1 1304 if((pData == NULL) || (Size == 0))
mbed_official 441:d2c15dda23c1 1305 {
mbed_official 441:d2c15dda23c1 1306 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1307 goto error;
mbed_official 441:d2c15dda23c1 1308 }
mbed_official 630:825f75ca301e 1309
mbed_official 340:28d1f895c6fe 1310 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 340:28d1f895c6fe 1311 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 1312 hspi->pTxBuffPtr = pData;
mbed_official 340:28d1f895c6fe 1313 hspi->TxXferSize = Size;
mbed_official 340:28d1f895c6fe 1314 hspi->TxXferCount = Size;
mbed_official 630:825f75ca301e 1315 hspi->pRxBuffPtr = (uint8_t *)NULL;
mbed_official 340:28d1f895c6fe 1316 hspi->RxXferSize = 0;
mbed_official 340:28d1f895c6fe 1317 hspi->RxXferCount = 0;
mbed_official 630:825f75ca301e 1318
mbed_official 340:28d1f895c6fe 1319 /* Configure communication direction : 1Line */
mbed_official 340:28d1f895c6fe 1320 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 340:28d1f895c6fe 1321 {
mbed_official 630:825f75ca301e 1322 SPI_1LINE_TX(hspi);
mbed_official 340:28d1f895c6fe 1323 }
mbed_official 630:825f75ca301e 1324
mbed_official 340:28d1f895c6fe 1325 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 1326 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 1327 {
mbed_official 630:825f75ca301e 1328 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 1329 }
mbed_official 630:825f75ca301e 1330
mbed_official 441:d2c15dda23c1 1331 /* Set the SPI TxDMA Half transfer complete callback */
mbed_official 441:d2c15dda23c1 1332 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
mbed_official 630:825f75ca301e 1333
mbed_official 630:825f75ca301e 1334 /* Set the SPI TxDMA transfer complete callback */
mbed_official 441:d2c15dda23c1 1335 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official 630:825f75ca301e 1336
mbed_official 340:28d1f895c6fe 1337 /* Set the DMA error callback */
mbed_official 441:d2c15dda23c1 1338 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 630:825f75ca301e 1339
mbed_official 340:28d1f895c6fe 1340 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 340:28d1f895c6fe 1341 /* packing mode is enabled only if the DMA setting is HALWORD */
mbed_official 340:28d1f895c6fe 1342 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 340:28d1f895c6fe 1343 {
mbed_official 340:28d1f895c6fe 1344 /* Check the even/odd of the data size + crc if enabled */
mbed_official 340:28d1f895c6fe 1345 if((hspi->TxXferCount & 0x1) == 0)
mbed_official 340:28d1f895c6fe 1346 {
mbed_official 340:28d1f895c6fe 1347 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 340:28d1f895c6fe 1348 hspi->TxXferCount = (hspi->TxXferCount >> 1);
mbed_official 340:28d1f895c6fe 1349 }
mbed_official 340:28d1f895c6fe 1350 else
mbed_official 340:28d1f895c6fe 1351 {
mbed_official 340:28d1f895c6fe 1352 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 340:28d1f895c6fe 1353 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 340:28d1f895c6fe 1354 }
mbed_official 340:28d1f895c6fe 1355 }
mbed_official 630:825f75ca301e 1356
mbed_official 340:28d1f895c6fe 1357 /* Enable the Tx DMA channel */
mbed_official 340:28d1f895c6fe 1358 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 630:825f75ca301e 1359
mbed_official 630:825f75ca301e 1360 /* Check if the SPI is already enabled */
mbed_official 340:28d1f895c6fe 1361 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 340:28d1f895c6fe 1362 {
mbed_official 630:825f75ca301e 1363 /* Enable SPI peripheral */
mbed_official 340:28d1f895c6fe 1364 __HAL_SPI_ENABLE(hspi);
mbed_official 340:28d1f895c6fe 1365 }
mbed_official 340:28d1f895c6fe 1366
mbed_official 340:28d1f895c6fe 1367 /* Enable Tx DMA Request */
mbed_official 441:d2c15dda23c1 1368 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 630:825f75ca301e 1369
mbed_official 630:825f75ca301e 1370 error :
mbed_official 340:28d1f895c6fe 1371 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 1372 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1373 return errorcode;
mbed_official 340:28d1f895c6fe 1374 }
mbed_official 340:28d1f895c6fe 1375
mbed_official 340:28d1f895c6fe 1376 /**
mbed_official 630:825f75ca301e 1377 * @brief Receive an amount of data in non-blocking mode with DMA.
mbed_official 630:825f75ca301e 1378 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1379 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1380 * @param pData: pointer to data buffer
mbed_official 630:825f75ca301e 1381 * @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official 630:825f75ca301e 1382 * @param Size: amount of data to be sent
mbed_official 630:825f75ca301e 1383 * @retval HAL status
mbed_official 630:825f75ca301e 1384 */
mbed_official 340:28d1f895c6fe 1385 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 340:28d1f895c6fe 1386 {
mbed_official 441:d2c15dda23c1 1387 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 630:825f75ca301e 1388
mbed_official 340:28d1f895c6fe 1389 /* Process Locked */
mbed_official 340:28d1f895c6fe 1390 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1391
mbed_official 441:d2c15dda23c1 1392 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 441:d2c15dda23c1 1393 {
mbed_official 441:d2c15dda23c1 1394 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 1395 goto error;
mbed_official 441:d2c15dda23c1 1396 }
mbed_official 630:825f75ca301e 1397
mbed_official 441:d2c15dda23c1 1398 if((pData == NULL) || (Size == 0))
mbed_official 441:d2c15dda23c1 1399 {
mbed_official 441:d2c15dda23c1 1400 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1401 goto error;
mbed_official 441:d2c15dda23c1 1402 }
mbed_official 630:825f75ca301e 1403
mbed_official 340:28d1f895c6fe 1404 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 340:28d1f895c6fe 1405 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 340:28d1f895c6fe 1406 hspi->pRxBuffPtr = pData;
mbed_official 340:28d1f895c6fe 1407 hspi->RxXferSize = Size;
mbed_official 340:28d1f895c6fe 1408 hspi->RxXferCount = Size;
mbed_official 630:825f75ca301e 1409 hspi->pTxBuffPtr = (uint8_t *)NULL;
mbed_official 340:28d1f895c6fe 1410 hspi->TxXferSize = 0;
mbed_official 340:28d1f895c6fe 1411 hspi->TxXferCount = 0;
mbed_official 630:825f75ca301e 1412
mbed_official 340:28d1f895c6fe 1413 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 340:28d1f895c6fe 1414 {
mbed_official 340:28d1f895c6fe 1415 /* Process Unlocked */
mbed_official 630:825f75ca301e 1416 __HAL_UNLOCK(hspi);
mbed_official 340:28d1f895c6fe 1417 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 630:825f75ca301e 1418 /* in this case we call the TransmitReceive process */
mbed_official 340:28d1f895c6fe 1419 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
mbed_official 340:28d1f895c6fe 1420 }
mbed_official 630:825f75ca301e 1421
mbed_official 340:28d1f895c6fe 1422 /* Configure communication direction : 1Line */
mbed_official 340:28d1f895c6fe 1423 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 340:28d1f895c6fe 1424 {
mbed_official 630:825f75ca301e 1425 SPI_1LINE_RX(hspi);
mbed_official 340:28d1f895c6fe 1426 }
mbed_official 630:825f75ca301e 1427
mbed_official 340:28d1f895c6fe 1428 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 1429 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 1430 {
mbed_official 630:825f75ca301e 1431 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 1432 }
mbed_official 630:825f75ca301e 1433
mbed_official 340:28d1f895c6fe 1434 /* packing mode management is enabled by the DMA settings */
mbed_official 340:28d1f895c6fe 1435 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 340:28d1f895c6fe 1436 {
mbed_official 340:28d1f895c6fe 1437 /* Restriction the DMA data received is not allowed in this mode */
mbed_official 441:d2c15dda23c1 1438 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1439 goto error;
mbed_official 340:28d1f895c6fe 1440 }
mbed_official 630:825f75ca301e 1441
mbed_official 340:28d1f895c6fe 1442 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 340:28d1f895c6fe 1443 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 340:28d1f895c6fe 1444 {
mbed_official 630:825f75ca301e 1445 /* set fiforxthresold according the reception data length: 16bit */
mbed_official 340:28d1f895c6fe 1446 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 1447 }
mbed_official 340:28d1f895c6fe 1448 else
mbed_official 340:28d1f895c6fe 1449 {
mbed_official 630:825f75ca301e 1450 /* set fiforxthresold according the reception data length: 8bit */
mbed_official 340:28d1f895c6fe 1451 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 340:28d1f895c6fe 1452 }
mbed_official 630:825f75ca301e 1453
mbed_official 441:d2c15dda23c1 1454 /* Set the SPI RxDMA Half transfer complete callback */
mbed_official 441:d2c15dda23c1 1455 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official 630:825f75ca301e 1456
mbed_official 630:825f75ca301e 1457 /* Set the SPI Rx DMA transfer complete callback */
mbed_official 441:d2c15dda23c1 1458 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 630:825f75ca301e 1459
mbed_official 340:28d1f895c6fe 1460 /* Set the DMA error callback */
mbed_official 441:d2c15dda23c1 1461 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 630:825f75ca301e 1462
mbed_official 630:825f75ca301e 1463 /* Enable Rx DMA Request */
mbed_official 441:d2c15dda23c1 1464 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official 630:825f75ca301e 1465
mbed_official 340:28d1f895c6fe 1466 /* Enable the Rx DMA channel */
mbed_official 340:28d1f895c6fe 1467 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 630:825f75ca301e 1468
mbed_official 630:825f75ca301e 1469 /* Check if the SPI is already enabled */
mbed_official 340:28d1f895c6fe 1470 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 340:28d1f895c6fe 1471 {
mbed_official 630:825f75ca301e 1472 /* Enable SPI peripheral */
mbed_official 340:28d1f895c6fe 1473 __HAL_SPI_ENABLE(hspi);
mbed_official 340:28d1f895c6fe 1474 }
mbed_official 630:825f75ca301e 1475
mbed_official 441:d2c15dda23c1 1476 error:
mbed_official 441:d2c15dda23c1 1477 /* Process Unlocked */
mbed_official 630:825f75ca301e 1478 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1479 return errorcode;
mbed_official 340:28d1f895c6fe 1480 }
mbed_official 340:28d1f895c6fe 1481
mbed_official 340:28d1f895c6fe 1482 /**
mbed_official 630:825f75ca301e 1483 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
mbed_official 630:825f75ca301e 1484 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1485 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1486 * @param pTxData: pointer to transmission data buffer
mbed_official 630:825f75ca301e 1487 * @param pRxData: pointer to reception data buffer
mbed_official 630:825f75ca301e 1488 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official 630:825f75ca301e 1489 * @param Size: amount of data to be sent
mbed_official 340:28d1f895c6fe 1490 * @retval HAL status
mbed_official 340:28d1f895c6fe 1491 */
mbed_official 340:28d1f895c6fe 1492 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 340:28d1f895c6fe 1493 {
mbed_official 441:d2c15dda23c1 1494 HAL_StatusTypeDef errorcode = HAL_OK;
mbed_official 340:28d1f895c6fe 1495 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 630:825f75ca301e 1496
mbed_official 441:d2c15dda23c1 1497 /* Process locked */
mbed_official 441:d2c15dda23c1 1498 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1499
mbed_official 441:d2c15dda23c1 1500 if(!((hspi->State == HAL_SPI_STATE_READY) ||
mbed_official 441:d2c15dda23c1 1501 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
mbed_official 441:d2c15dda23c1 1502 {
mbed_official 441:d2c15dda23c1 1503 errorcode = HAL_BUSY;
mbed_official 441:d2c15dda23c1 1504 goto error;
mbed_official 441:d2c15dda23c1 1505 }
mbed_official 630:825f75ca301e 1506
mbed_official 630:825f75ca301e 1507 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 340:28d1f895c6fe 1508 {
mbed_official 441:d2c15dda23c1 1509 errorcode = HAL_ERROR;
mbed_official 441:d2c15dda23c1 1510 goto error;
mbed_official 441:d2c15dda23c1 1511 }
mbed_official 630:825f75ca301e 1512
mbed_official 441:d2c15dda23c1 1513 /* check if the transmit Receive function is not called by a receive master */
mbed_official 441:d2c15dda23c1 1514 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 630:825f75ca301e 1515 {
mbed_official 441:d2c15dda23c1 1516 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 441:d2c15dda23c1 1517 }
mbed_official 630:825f75ca301e 1518
mbed_official 441:d2c15dda23c1 1519 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 441:d2c15dda23c1 1520 hspi->pTxBuffPtr = (uint8_t *)pTxData;
mbed_official 441:d2c15dda23c1 1521 hspi->TxXferSize = Size;
mbed_official 441:d2c15dda23c1 1522 hspi->TxXferCount = Size;
mbed_official 441:d2c15dda23c1 1523 hspi->pRxBuffPtr = (uint8_t *)pRxData;
mbed_official 441:d2c15dda23c1 1524 hspi->RxXferSize = Size;
mbed_official 441:d2c15dda23c1 1525 hspi->RxXferCount = Size;
mbed_official 630:825f75ca301e 1526
mbed_official 441:d2c15dda23c1 1527 /* Reset CRC Calculation + increase the rxsize */
mbed_official 630:825f75ca301e 1528 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1529 {
mbed_official 630:825f75ca301e 1530 SPI_RESET_CRC(hspi);
mbed_official 441:d2c15dda23c1 1531 }
mbed_official 630:825f75ca301e 1532
mbed_official 441:d2c15dda23c1 1533 /* Reset the threshold bit */
mbed_official 441:d2c15dda23c1 1534 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
mbed_official 630:825f75ca301e 1535
mbed_official 441:d2c15dda23c1 1536 /* the packing mode management is enabled by the DMA settings according the spi data size */
mbed_official 441:d2c15dda23c1 1537 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 441:d2c15dda23c1 1538 {
mbed_official 630:825f75ca301e 1539 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 441:d2c15dda23c1 1540 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 441:d2c15dda23c1 1541 }
mbed_official 441:d2c15dda23c1 1542 else
mbed_official 441:d2c15dda23c1 1543 {
mbed_official 630:825f75ca301e 1544 /* set fiforxthresold according the reception data length: 8bit */
mbed_official 441:d2c15dda23c1 1545 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 630:825f75ca301e 1546
mbed_official 441:d2c15dda23c1 1547 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 340:28d1f895c6fe 1548 {
mbed_official 441:d2c15dda23c1 1549 if((hspi->TxXferSize & 0x1) == 0x0)
mbed_official 441:d2c15dda23c1 1550 {
mbed_official 441:d2c15dda23c1 1551 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 441:d2c15dda23c1 1552 hspi->TxXferCount = hspi->TxXferCount >> 1;
mbed_official 441:d2c15dda23c1 1553 }
mbed_official 441:d2c15dda23c1 1554 else
mbed_official 441:d2c15dda23c1 1555 {
mbed_official 441:d2c15dda23c1 1556 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 441:d2c15dda23c1 1557 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 441:d2c15dda23c1 1558 }
mbed_official 340:28d1f895c6fe 1559 }
mbed_official 630:825f75ca301e 1560
mbed_official 441:d2c15dda23c1 1561 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 340:28d1f895c6fe 1562 {
mbed_official 630:825f75ca301e 1563 /* set fiforxthresold according the reception data length: 16bit */
mbed_official 340:28d1f895c6fe 1564 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 630:825f75ca301e 1565
mbed_official 441:d2c15dda23c1 1566 if((hspi->RxXferCount & 0x1) == 0x0 )
mbed_official 340:28d1f895c6fe 1567 {
mbed_official 441:d2c15dda23c1 1568 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 441:d2c15dda23c1 1569 hspi->RxXferCount = hspi->RxXferCount >> 1;
mbed_official 340:28d1f895c6fe 1570 }
mbed_official 441:d2c15dda23c1 1571 else
mbed_official 441:d2c15dda23c1 1572 {
mbed_official 441:d2c15dda23c1 1573 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 441:d2c15dda23c1 1574 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
mbed_official 441:d2c15dda23c1 1575 }
mbed_official 340:28d1f895c6fe 1576 }
mbed_official 441:d2c15dda23c1 1577 }
mbed_official 630:825f75ca301e 1578
mbed_official 441:d2c15dda23c1 1579 /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
mbed_official 441:d2c15dda23c1 1580 reception request (RXNE) */
mbed_official 441:d2c15dda23c1 1581 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 441:d2c15dda23c1 1582 {
mbed_official 441:d2c15dda23c1 1583 /* Set the SPI Rx DMA Half transfer complete callback */
mbed_official 441:d2c15dda23c1 1584 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official 441:d2c15dda23c1 1585 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 340:28d1f895c6fe 1586 }
mbed_official 340:28d1f895c6fe 1587 else
mbed_official 340:28d1f895c6fe 1588 {
mbed_official 441:d2c15dda23c1 1589 /* Set the SPI Rx DMA Half transfer complete callback */
mbed_official 441:d2c15dda23c1 1590 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
mbed_official 441:d2c15dda23c1 1591 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official 441:d2c15dda23c1 1592 }
mbed_official 630:825f75ca301e 1593
mbed_official 441:d2c15dda23c1 1594 /* Set the DMA error callback */
mbed_official 441:d2c15dda23c1 1595 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 630:825f75ca301e 1596
mbed_official 630:825f75ca301e 1597 /* Enable Rx DMA Request */
mbed_official 441:d2c15dda23c1 1598 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official 630:825f75ca301e 1599
mbed_official 441:d2c15dda23c1 1600 /* Enable the Rx DMA channel */
mbed_official 441:d2c15dda23c1 1601 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 630:825f75ca301e 1602
mbed_official 441:d2c15dda23c1 1603 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official 441:d2c15dda23c1 1604 is performed in DMA reception complete callback */
mbed_official 630:825f75ca301e 1605 hspi->hdmatx->XferHalfCpltCallback = NULL;
mbed_official 630:825f75ca301e 1606 hspi->hdmatx->XferCpltCallback = NULL;
mbed_official 630:825f75ca301e 1607
mbed_official 441:d2c15dda23c1 1608 /* Set the DMA error callback */
mbed_official 441:d2c15dda23c1 1609 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 630:825f75ca301e 1610
mbed_official 441:d2c15dda23c1 1611 /* Enable the Tx DMA channel */
mbed_official 441:d2c15dda23c1 1612 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 630:825f75ca301e 1613
mbed_official 441:d2c15dda23c1 1614 /* Check if the SPI is already enabled */
mbed_official 441:d2c15dda23c1 1615 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 441:d2c15dda23c1 1616 {
mbed_official 441:d2c15dda23c1 1617 /* Enable SPI peripheral */
mbed_official 441:d2c15dda23c1 1618 __HAL_SPI_ENABLE(hspi);
mbed_official 340:28d1f895c6fe 1619 }
mbed_official 630:825f75ca301e 1620
mbed_official 441:d2c15dda23c1 1621 /* Enable Tx DMA Request */
mbed_official 441:d2c15dda23c1 1622 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 630:825f75ca301e 1623
mbed_official 630:825f75ca301e 1624 error :
mbed_official 441:d2c15dda23c1 1625 /* Process Unlocked */
mbed_official 441:d2c15dda23c1 1626 __HAL_UNLOCK(hspi);
mbed_official 441:d2c15dda23c1 1627 return errorcode;
mbed_official 441:d2c15dda23c1 1628 }
mbed_official 441:d2c15dda23c1 1629
mbed_official 441:d2c15dda23c1 1630 /**
mbed_official 630:825f75ca301e 1631 * @brief Pause the DMA Transfer.
mbed_official 630:825f75ca301e 1632 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1633 * the configuration information for the specified SPI module.
mbed_official 441:d2c15dda23c1 1634 * @retval HAL status
mbed_official 441:d2c15dda23c1 1635 */
mbed_official 441:d2c15dda23c1 1636 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
mbed_official 441:d2c15dda23c1 1637 {
mbed_official 441:d2c15dda23c1 1638 /* Process Locked */
mbed_official 441:d2c15dda23c1 1639 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1640
mbed_official 441:d2c15dda23c1 1641 /* Disable the SPI DMA Tx & Rx requests */
mbed_official 441:d2c15dda23c1 1642 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 630:825f75ca301e 1643
mbed_official 441:d2c15dda23c1 1644 /* Process Unlocked */
mbed_official 441:d2c15dda23c1 1645 __HAL_UNLOCK(hspi);
mbed_official 630:825f75ca301e 1646
mbed_official 630:825f75ca301e 1647 return HAL_OK;
mbed_official 441:d2c15dda23c1 1648 }
mbed_official 441:d2c15dda23c1 1649
mbed_official 441:d2c15dda23c1 1650 /**
mbed_official 630:825f75ca301e 1651 * @brief Resume the DMA Transfer.
mbed_official 630:825f75ca301e 1652 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1653 * the configuration information for the specified SPI module.
mbed_official 441:d2c15dda23c1 1654 * @retval HAL status
mbed_official 441:d2c15dda23c1 1655 */
mbed_official 441:d2c15dda23c1 1656 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
mbed_official 441:d2c15dda23c1 1657 {
mbed_official 441:d2c15dda23c1 1658 /* Process Locked */
mbed_official 441:d2c15dda23c1 1659 __HAL_LOCK(hspi);
mbed_official 630:825f75ca301e 1660
mbed_official 441:d2c15dda23c1 1661 /* Enable the SPI DMA Tx & Rx requests */
mbed_official 441:d2c15dda23c1 1662 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 630:825f75ca301e 1663
mbed_official 441:d2c15dda23c1 1664 /* Process Unlocked */
mbed_official 441:d2c15dda23c1 1665 __HAL_UNLOCK(hspi);
mbed_official 630:825f75ca301e 1666
mbed_official 441:d2c15dda23c1 1667 return HAL_OK;
mbed_official 441:d2c15dda23c1 1668 }
mbed_official 441:d2c15dda23c1 1669
mbed_official 441:d2c15dda23c1 1670 /**
mbed_official 630:825f75ca301e 1671 * @brief Stop the DMA Transfer.
mbed_official 630:825f75ca301e 1672 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1673 * the configuration information for the specified SPI module.
mbed_official 441:d2c15dda23c1 1674 * @retval HAL status
mbed_official 441:d2c15dda23c1 1675 */
mbed_official 441:d2c15dda23c1 1676 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
mbed_official 441:d2c15dda23c1 1677 {
mbed_official 441:d2c15dda23c1 1678 /* The Lock is not implemented on this API to allow the user application
mbed_official 441:d2c15dda23c1 1679 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
mbed_official 441:d2c15dda23c1 1680 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
mbed_official 441:d2c15dda23c1 1681 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
mbed_official 441:d2c15dda23c1 1682 */
mbed_official 630:825f75ca301e 1683
mbed_official 441:d2c15dda23c1 1684 /* Abort the SPI DMA tx channel */
mbed_official 441:d2c15dda23c1 1685 if(hspi->hdmatx != NULL)
mbed_official 441:d2c15dda23c1 1686 {
mbed_official 441:d2c15dda23c1 1687 HAL_DMA_Abort(hspi->hdmatx);
mbed_official 441:d2c15dda23c1 1688 }
mbed_official 441:d2c15dda23c1 1689 /* Abort the SPI DMA rx channel */
mbed_official 441:d2c15dda23c1 1690 if(hspi->hdmarx != NULL)
mbed_official 441:d2c15dda23c1 1691 {
mbed_official 441:d2c15dda23c1 1692 HAL_DMA_Abort(hspi->hdmarx);
mbed_official 441:d2c15dda23c1 1693 }
mbed_official 630:825f75ca301e 1694
mbed_official 441:d2c15dda23c1 1695 /* Disable the SPI DMA Tx & Rx requests */
mbed_official 441:d2c15dda23c1 1696 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 441:d2c15dda23c1 1697 hspi->State = HAL_SPI_STATE_READY;
mbed_official 441:d2c15dda23c1 1698 return HAL_OK;
mbed_official 340:28d1f895c6fe 1699 }
mbed_official 340:28d1f895c6fe 1700
mbed_official 340:28d1f895c6fe 1701 /**
mbed_official 630:825f75ca301e 1702 * @brief Handle SPI interrupt request.
mbed_official 630:825f75ca301e 1703 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1704 * the configuration information for the specified SPI module.
mbed_official 630:825f75ca301e 1705 * @retval None
mbed_official 340:28d1f895c6fe 1706 */
mbed_official 340:28d1f895c6fe 1707 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 1708 {
mbed_official 441:d2c15dda23c1 1709 uint32_t itsource = hspi->Instance->CR2;
mbed_official 441:d2c15dda23c1 1710 uint32_t itflag = hspi->Instance->SR;
mbed_official 630:825f75ca301e 1711
mbed_official 340:28d1f895c6fe 1712 /* SPI in mode Receiver ----------------------------------------------------*/
mbed_official 441:d2c15dda23c1 1713 if(((itflag & SPI_FLAG_OVR) == RESET) &&
mbed_official 441:d2c15dda23c1 1714 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
mbed_official 340:28d1f895c6fe 1715 {
mbed_official 340:28d1f895c6fe 1716 hspi->RxISR(hspi);
mbed_official 340:28d1f895c6fe 1717 return;
mbed_official 340:28d1f895c6fe 1718 }
mbed_official 630:825f75ca301e 1719
mbed_official 630:825f75ca301e 1720 /* SPI in mode Transmitter ---------------------------------------------------*/
mbed_official 441:d2c15dda23c1 1721 if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
mbed_official 630:825f75ca301e 1722 {
mbed_official 340:28d1f895c6fe 1723 hspi->TxISR(hspi);
mbed_official 340:28d1f895c6fe 1724 return;
mbed_official 340:28d1f895c6fe 1725 }
mbed_official 630:825f75ca301e 1726
mbed_official 630:825f75ca301e 1727 /* SPI in Error Treatment ---------------------------------------------------*/
mbed_official 630:825f75ca301e 1728 if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
mbed_official 340:28d1f895c6fe 1729 {
mbed_official 630:825f75ca301e 1730 /* SPI Overrun error interrupt occurred -------------------------------------*/
mbed_official 441:d2c15dda23c1 1731 if((itflag & SPI_FLAG_OVR) != RESET)
mbed_official 340:28d1f895c6fe 1732 {
mbed_official 340:28d1f895c6fe 1733 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official 340:28d1f895c6fe 1734 {
mbed_official 340:28d1f895c6fe 1735 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
mbed_official 340:28d1f895c6fe 1736 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 340:28d1f895c6fe 1737 }
mbed_official 340:28d1f895c6fe 1738 else
mbed_official 340:28d1f895c6fe 1739 {
mbed_official 340:28d1f895c6fe 1740 return;
mbed_official 340:28d1f895c6fe 1741 }
mbed_official 340:28d1f895c6fe 1742 }
mbed_official 630:825f75ca301e 1743
mbed_official 630:825f75ca301e 1744 /* SPI Mode Fault error interrupt occurred -------------------------------------*/
mbed_official 441:d2c15dda23c1 1745 if((itflag & SPI_FLAG_MODF) != RESET)
mbed_official 630:825f75ca301e 1746 {
mbed_official 340:28d1f895c6fe 1747 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
mbed_official 340:28d1f895c6fe 1748 __HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official 340:28d1f895c6fe 1749 }
mbed_official 630:825f75ca301e 1750
mbed_official 630:825f75ca301e 1751 /* SPI Frame error interrupt occurred ----------------------------------------*/
mbed_official 441:d2c15dda23c1 1752 if((itflag & SPI_FLAG_FRE) != RESET)
mbed_official 630:825f75ca301e 1753 {
mbed_official 340:28d1f895c6fe 1754 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
mbed_official 340:28d1f895c6fe 1755 __HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official 340:28d1f895c6fe 1756 }
mbed_official 630:825f75ca301e 1757
mbed_official 340:28d1f895c6fe 1758 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
mbed_official 340:28d1f895c6fe 1759 hspi->State = HAL_SPI_STATE_READY;
mbed_official 340:28d1f895c6fe 1760 HAL_SPI_ErrorCallback(hspi);
mbed_official 340:28d1f895c6fe 1761 return;
mbed_official 340:28d1f895c6fe 1762 }
mbed_official 340:28d1f895c6fe 1763 }
mbed_official 340:28d1f895c6fe 1764
mbed_official 340:28d1f895c6fe 1765 /**
mbed_official 630:825f75ca301e 1766 * @brief Tx Transfer completed callback.
mbed_official 630:825f75ca301e 1767 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1768 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1769 * @retval None
mbed_official 340:28d1f895c6fe 1770 */
mbed_official 630:825f75ca301e 1771 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 1772 {
mbed_official 630:825f75ca301e 1773 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1774 the HAL_SPI_TxCpltCallback should be implemented in the user file
mbed_official 630:825f75ca301e 1775 */
mbed_official 340:28d1f895c6fe 1776 }
mbed_official 340:28d1f895c6fe 1777
mbed_official 340:28d1f895c6fe 1778 /**
mbed_official 630:825f75ca301e 1779 * @brief Rx Transfer completed callback.
mbed_official 630:825f75ca301e 1780 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1781 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1782 * @retval None
mbed_official 340:28d1f895c6fe 1783 */
mbed_official 630:825f75ca301e 1784 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 1785 {
mbed_official 630:825f75ca301e 1786 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1787 the HAL_SPI_RxCpltCallback should be implemented in the user file
mbed_official 630:825f75ca301e 1788 */
mbed_official 340:28d1f895c6fe 1789 }
mbed_official 340:28d1f895c6fe 1790
mbed_official 340:28d1f895c6fe 1791 /**
mbed_official 630:825f75ca301e 1792 * @brief Tx and Rx Transfer completed callback.
mbed_official 630:825f75ca301e 1793 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1794 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1795 * @retval None
mbed_official 340:28d1f895c6fe 1796 */
mbed_official 340:28d1f895c6fe 1797 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 1798 {
mbed_official 630:825f75ca301e 1799 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1800 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
mbed_official 340:28d1f895c6fe 1801 */
mbed_official 340:28d1f895c6fe 1802 }
mbed_official 441:d2c15dda23c1 1803
mbed_official 441:d2c15dda23c1 1804 /**
mbed_official 630:825f75ca301e 1805 * @brief Tx Half Transfer completed callback.
mbed_official 630:825f75ca301e 1806 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1807 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1808 * @retval None
mbed_official 441:d2c15dda23c1 1809 */
mbed_official 441:d2c15dda23c1 1810 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 441:d2c15dda23c1 1811 {
mbed_official 630:825f75ca301e 1812 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1813 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
mbed_official 630:825f75ca301e 1814 */
mbed_official 630:825f75ca301e 1815 }
mbed_official 630:825f75ca301e 1816
mbed_official 630:825f75ca301e 1817 /**
mbed_official 630:825f75ca301e 1818 * @brief Rx Half Transfer completed callback.
mbed_official 630:825f75ca301e 1819 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1820 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1821 * @retval None
mbed_official 630:825f75ca301e 1822 */
mbed_official 630:825f75ca301e 1823 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 630:825f75ca301e 1824 {
mbed_official 630:825f75ca301e 1825 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1826 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
mbed_official 441:d2c15dda23c1 1827 */
mbed_official 441:d2c15dda23c1 1828 }
mbed_official 441:d2c15dda23c1 1829
mbed_official 441:d2c15dda23c1 1830 /**
mbed_official 630:825f75ca301e 1831 * @brief Tx and Rx Half Transfer callback.
mbed_official 630:825f75ca301e 1832 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1833 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1834 * @retval None
mbed_official 441:d2c15dda23c1 1835 */
mbed_official 630:825f75ca301e 1836 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 441:d2c15dda23c1 1837 {
mbed_official 630:825f75ca301e 1838 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1839 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
mbed_official 441:d2c15dda23c1 1840 */
mbed_official 441:d2c15dda23c1 1841 }
mbed_official 441:d2c15dda23c1 1842
mbed_official 441:d2c15dda23c1 1843 /**
mbed_official 630:825f75ca301e 1844 * @brief SPI error callback.
mbed_official 630:825f75ca301e 1845 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1846 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1847 * @retval None
mbed_official 340:28d1f895c6fe 1848 */
mbed_official 340:28d1f895c6fe 1849 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 1850 {
mbed_official 630:825f75ca301e 1851 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 630:825f75ca301e 1852 the HAL_SPI_ErrorCallback should be implemented in the user file
mbed_official 630:825f75ca301e 1853 */
mbed_official 630:825f75ca301e 1854 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official 630:825f75ca301e 1855 and user can use HAL_SPI_GetError() API to check the latest error occurred
mbed_official 630:825f75ca301e 1856 */
mbed_official 340:28d1f895c6fe 1857 }
mbed_official 340:28d1f895c6fe 1858
mbed_official 340:28d1f895c6fe 1859 /**
mbed_official 340:28d1f895c6fe 1860 * @}
mbed_official 340:28d1f895c6fe 1861 */
mbed_official 340:28d1f895c6fe 1862
mbed_official 630:825f75ca301e 1863 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
mbed_official 630:825f75ca301e 1864 * @brief SPI control functions
mbed_official 340:28d1f895c6fe 1865 *
mbed_official 630:825f75ca301e 1866 @verbatim
mbed_official 340:28d1f895c6fe 1867 ===============================================================================
mbed_official 630:825f75ca301e 1868 ##### Peripheral State and Errors functions #####
mbed_official 630:825f75ca301e 1869 ===============================================================================
mbed_official 340:28d1f895c6fe 1870 [..]
mbed_official 340:28d1f895c6fe 1871 This subsection provides a set of functions allowing to control the SPI.
mbed_official 630:825f75ca301e 1872 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official 441:d2c15dda23c1 1873 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official 340:28d1f895c6fe 1874 @endverbatim
mbed_official 340:28d1f895c6fe 1875 * @{
mbed_official 340:28d1f895c6fe 1876 */
mbed_official 340:28d1f895c6fe 1877
mbed_official 340:28d1f895c6fe 1878 /**
mbed_official 630:825f75ca301e 1879 * @brief Return the SPI handle state.
mbed_official 630:825f75ca301e 1880 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1881 * the configuration information for SPI module.
mbed_official 441:d2c15dda23c1 1882 * @retval SPI state
mbed_official 340:28d1f895c6fe 1883 */
mbed_official 340:28d1f895c6fe 1884 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 1885 {
mbed_official 630:825f75ca301e 1886 /* Return SPI handle state */
mbed_official 340:28d1f895c6fe 1887 return hspi->State;
mbed_official 340:28d1f895c6fe 1888 }
mbed_official 441:d2c15dda23c1 1889
mbed_official 441:d2c15dda23c1 1890 /**
mbed_official 630:825f75ca301e 1891 * @brief Return the SPI error code.
mbed_official 630:825f75ca301e 1892 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1893 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 1894 * @retval SPI error code in bitmap format
mbed_official 441:d2c15dda23c1 1895 */
mbed_official 441:d2c15dda23c1 1896 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official 441:d2c15dda23c1 1897 {
mbed_official 441:d2c15dda23c1 1898 return hspi->ErrorCode;
mbed_official 441:d2c15dda23c1 1899 }
mbed_official 441:d2c15dda23c1 1900
mbed_official 340:28d1f895c6fe 1901 /**
mbed_official 340:28d1f895c6fe 1902 * @}
mbed_official 340:28d1f895c6fe 1903 */
mbed_official 340:28d1f895c6fe 1904
mbed_official 441:d2c15dda23c1 1905
mbed_official 340:28d1f895c6fe 1906 /**
mbed_official 340:28d1f895c6fe 1907 * @}
mbed_official 340:28d1f895c6fe 1908 */
mbed_official 340:28d1f895c6fe 1909
mbed_official 630:825f75ca301e 1910 /** @addtogroup SPI_Private_Functions
mbed_official 630:825f75ca301e 1911 * @brief Private functions
mbed_official 340:28d1f895c6fe 1912 * @{
mbed_official 340:28d1f895c6fe 1913 */
mbed_official 340:28d1f895c6fe 1914
mbed_official 340:28d1f895c6fe 1915 /**
mbed_official 630:825f75ca301e 1916 * @brief DMA SPI transmit process complete callback.
mbed_official 630:825f75ca301e 1917 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1918 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 1919 * @retval None
mbed_official 441:d2c15dda23c1 1920 */
mbed_official 630:825f75ca301e 1921 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 1922 {
mbed_official 441:d2c15dda23c1 1923 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 1924
mbed_official 441:d2c15dda23c1 1925 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
mbed_official 441:d2c15dda23c1 1926 {
mbed_official 441:d2c15dda23c1 1927 /* Disable Tx DMA Request */
mbed_official 441:d2c15dda23c1 1928 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 630:825f75ca301e 1929
mbed_official 630:825f75ca301e 1930 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 1931 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 630:825f75ca301e 1932 {
mbed_official 630:825f75ca301e 1933 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 1934 }
mbed_official 630:825f75ca301e 1935
mbed_official 630:825f75ca301e 1936 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
mbed_official 441:d2c15dda23c1 1937 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 441:d2c15dda23c1 1938 {
mbed_official 441:d2c15dda23c1 1939 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 441:d2c15dda23c1 1940 }
mbed_official 630:825f75ca301e 1941
mbed_official 441:d2c15dda23c1 1942 hspi->TxXferCount = 0;
mbed_official 441:d2c15dda23c1 1943 hspi->State = HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 1944
mbed_official 441:d2c15dda23c1 1945 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 441:d2c15dda23c1 1946 {
mbed_official 441:d2c15dda23c1 1947 HAL_SPI_ErrorCallback(hspi);
mbed_official 441:d2c15dda23c1 1948 return;
mbed_official 441:d2c15dda23c1 1949 }
mbed_official 441:d2c15dda23c1 1950 }
mbed_official 441:d2c15dda23c1 1951 HAL_SPI_TxCpltCallback(hspi);
mbed_official 441:d2c15dda23c1 1952 }
mbed_official 441:d2c15dda23c1 1953
mbed_official 441:d2c15dda23c1 1954 /**
mbed_official 630:825f75ca301e 1955 * @brief DMA SPI receive process complete callback.
mbed_official 630:825f75ca301e 1956 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 1957 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 1958 * @retval None
mbed_official 441:d2c15dda23c1 1959 */
mbed_official 630:825f75ca301e 1960 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 1961 {
mbed_official 441:d2c15dda23c1 1962 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 1963
mbed_official 441:d2c15dda23c1 1964 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
mbed_official 441:d2c15dda23c1 1965 {
mbed_official 441:d2c15dda23c1 1966 __IO uint16_t tmpreg;
mbed_official 630:825f75ca301e 1967
mbed_official 441:d2c15dda23c1 1968 /* CRC handling */
mbed_official 630:825f75ca301e 1969 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 1970 {
mbed_official 441:d2c15dda23c1 1971 /* Wait until TXE flag */
mbed_official 441:d2c15dda23c1 1972 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 441:d2c15dda23c1 1973 {
mbed_official 630:825f75ca301e 1974 /* Error on the CRC reception */
mbed_official 630:825f75ca301e 1975 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 441:d2c15dda23c1 1976 }
mbed_official 441:d2c15dda23c1 1977 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 630:825f75ca301e 1978 {
mbed_official 441:d2c15dda23c1 1979 tmpreg = hspi->Instance->DR;
mbed_official 630:825f75ca301e 1980 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 1981 UNUSED(tmpreg);
mbed_official 441:d2c15dda23c1 1982 }
mbed_official 441:d2c15dda23c1 1983 else
mbed_official 441:d2c15dda23c1 1984 {
mbed_official 441:d2c15dda23c1 1985 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 1986 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 1987 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 1988
mbed_official 441:d2c15dda23c1 1989 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 441:d2c15dda23c1 1990 {
mbed_official 441:d2c15dda23c1 1991 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 441:d2c15dda23c1 1992 {
mbed_official 630:825f75ca301e 1993 /* Error on the CRC reception */
mbed_official 630:825f75ca301e 1994 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 441:d2c15dda23c1 1995 }
mbed_official 441:d2c15dda23c1 1996 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 1997 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 1998 UNUSED(tmpreg);
mbed_official 441:d2c15dda23c1 1999 }
mbed_official 441:d2c15dda23c1 2000 }
mbed_official 441:d2c15dda23c1 2001 }
mbed_official 630:825f75ca301e 2002
mbed_official 441:d2c15dda23c1 2003 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
mbed_official 441:d2c15dda23c1 2004 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 441:d2c15dda23c1 2005
mbed_official 441:d2c15dda23c1 2006 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 2007 if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
mbed_official 630:825f75ca301e 2008 {
mbed_official 630:825f75ca301e 2009 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2010 }
mbed_official 630:825f75ca301e 2011
mbed_official 441:d2c15dda23c1 2012 hspi->RxXferCount = 0;
mbed_official 441:d2c15dda23c1 2013 hspi->State = HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 2014
mbed_official 441:d2c15dda23c1 2015 /* Check if CRC error occurred */
mbed_official 441:d2c15dda23c1 2016 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 441:d2c15dda23c1 2017 {
mbed_official 441:d2c15dda23c1 2018 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 441:d2c15dda23c1 2019 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 441:d2c15dda23c1 2020 }
mbed_official 630:825f75ca301e 2021
mbed_official 441:d2c15dda23c1 2022 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 441:d2c15dda23c1 2023 {
mbed_official 441:d2c15dda23c1 2024 HAL_SPI_ErrorCallback(hspi);
mbed_official 441:d2c15dda23c1 2025 return;
mbed_official 441:d2c15dda23c1 2026 }
mbed_official 441:d2c15dda23c1 2027 }
mbed_official 441:d2c15dda23c1 2028 HAL_SPI_RxCpltCallback(hspi);
mbed_official 441:d2c15dda23c1 2029 }
mbed_official 441:d2c15dda23c1 2030
mbed_official 441:d2c15dda23c1 2031 /**
mbed_official 630:825f75ca301e 2032 * @brief DMA SPI transmit receive process complete callback.
mbed_official 441:d2c15dda23c1 2033 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2034 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 2035 * @retval None
mbed_official 441:d2c15dda23c1 2036 */
mbed_official 630:825f75ca301e 2037 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 2038 {
mbed_official 441:d2c15dda23c1 2039 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 2040
mbed_official 441:d2c15dda23c1 2041 if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
mbed_official 441:d2c15dda23c1 2042 {
mbed_official 441:d2c15dda23c1 2043 __IO int16_t tmpreg;
mbed_official 441:d2c15dda23c1 2044 /* CRC handling */
mbed_official 630:825f75ca301e 2045 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 441:d2c15dda23c1 2046 {
mbed_official 441:d2c15dda23c1 2047 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
mbed_official 630:825f75ca301e 2048 {
mbed_official 441:d2c15dda23c1 2049 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 441:d2c15dda23c1 2050 {
mbed_official 630:825f75ca301e 2051 /* Error on the CRC reception */
mbed_official 630:825f75ca301e 2052 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 441:d2c15dda23c1 2053 }
mbed_official 441:d2c15dda23c1 2054 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 630:825f75ca301e 2055 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2056 UNUSED(tmpreg);
mbed_official 441:d2c15dda23c1 2057 }
mbed_official 441:d2c15dda23c1 2058 else
mbed_official 441:d2c15dda23c1 2059 {
mbed_official 441:d2c15dda23c1 2060 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 441:d2c15dda23c1 2061 {
mbed_official 630:825f75ca301e 2062 /* Error on the CRC reception */
mbed_official 630:825f75ca301e 2063 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 441:d2c15dda23c1 2064 }
mbed_official 441:d2c15dda23c1 2065 tmpreg = hspi->Instance->DR;
mbed_official 630:825f75ca301e 2066 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2067 UNUSED(tmpreg);
mbed_official 441:d2c15dda23c1 2068 }
mbed_official 630:825f75ca301e 2069 }
mbed_official 630:825f75ca301e 2070
mbed_official 630:825f75ca301e 2071 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 2072 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 630:825f75ca301e 2073 {
mbed_official 630:825f75ca301e 2074 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2075 }
mbed_official 630:825f75ca301e 2076
mbed_official 441:d2c15dda23c1 2077 /* Disable Rx/Tx DMA Request */
mbed_official 441:d2c15dda23c1 2078 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 441:d2c15dda23c1 2079
mbed_official 441:d2c15dda23c1 2080 hspi->TxXferCount = 0;
mbed_official 441:d2c15dda23c1 2081 hspi->RxXferCount = 0;
mbed_official 441:d2c15dda23c1 2082 hspi->State = HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 2083
mbed_official 441:d2c15dda23c1 2084 /* Check if CRC error occurred */
mbed_official 441:d2c15dda23c1 2085 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 441:d2c15dda23c1 2086 {
mbed_official 630:825f75ca301e 2087 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 441:d2c15dda23c1 2088 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 441:d2c15dda23c1 2089 }
mbed_official 630:825f75ca301e 2090
mbed_official 441:d2c15dda23c1 2091 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 441:d2c15dda23c1 2092 {
mbed_official 441:d2c15dda23c1 2093 HAL_SPI_ErrorCallback(hspi);
mbed_official 441:d2c15dda23c1 2094 return;
mbed_official 441:d2c15dda23c1 2095 }
mbed_official 441:d2c15dda23c1 2096 }
mbed_official 441:d2c15dda23c1 2097 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 441:d2c15dda23c1 2098 }
mbed_official 441:d2c15dda23c1 2099
mbed_official 441:d2c15dda23c1 2100 /**
mbed_official 630:825f75ca301e 2101 * @brief DMA SPI half transmit process complete callback.
mbed_official 441:d2c15dda23c1 2102 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2103 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 2104 * @retval None
mbed_official 441:d2c15dda23c1 2105 */
mbed_official 441:d2c15dda23c1 2106 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 2107 {
mbed_official 441:d2c15dda23c1 2108 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 441:d2c15dda23c1 2109
mbed_official 441:d2c15dda23c1 2110 HAL_SPI_TxHalfCpltCallback(hspi);
mbed_official 441:d2c15dda23c1 2111 }
mbed_official 441:d2c15dda23c1 2112
mbed_official 441:d2c15dda23c1 2113 /**
mbed_official 630:825f75ca301e 2114 * @brief DMA SPI half receive process complete callback
mbed_official 441:d2c15dda23c1 2115 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2116 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 2117 * @retval None
mbed_official 441:d2c15dda23c1 2118 */
mbed_official 441:d2c15dda23c1 2119 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 2120 {
mbed_official 441:d2c15dda23c1 2121 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 441:d2c15dda23c1 2122
mbed_official 441:d2c15dda23c1 2123 HAL_SPI_RxHalfCpltCallback(hspi);
mbed_official 441:d2c15dda23c1 2124 }
mbed_official 441:d2c15dda23c1 2125
mbed_official 441:d2c15dda23c1 2126 /**
mbed_official 630:825f75ca301e 2127 * @brief DMA SPI half transmit receive process complete callback.
mbed_official 441:d2c15dda23c1 2128 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2129 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 2130 * @retval None
mbed_official 441:d2c15dda23c1 2131 */
mbed_official 630:825f75ca301e 2132 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 2133 {
mbed_official 441:d2c15dda23c1 2134 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 441:d2c15dda23c1 2135
mbed_official 441:d2c15dda23c1 2136 HAL_SPI_TxRxHalfCpltCallback(hspi);
mbed_official 441:d2c15dda23c1 2137 }
mbed_official 441:d2c15dda23c1 2138
mbed_official 441:d2c15dda23c1 2139 /**
mbed_official 630:825f75ca301e 2140 * @brief DMA SPI communication error callback.
mbed_official 441:d2c15dda23c1 2141 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2142 * the configuration information for the specified DMA module.
mbed_official 630:825f75ca301e 2143 * @retval None
mbed_official 441:d2c15dda23c1 2144 */
mbed_official 630:825f75ca301e 2145 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 441:d2c15dda23c1 2146 {
mbed_official 441:d2c15dda23c1 2147 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 2148
mbed_official 441:d2c15dda23c1 2149 /* Stop the disable DMA transfer on SPI side */
mbed_official 441:d2c15dda23c1 2150 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 630:825f75ca301e 2151
mbed_official 441:d2c15dda23c1 2152 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
mbed_official 441:d2c15dda23c1 2153 hspi->State = HAL_SPI_STATE_READY;
mbed_official 441:d2c15dda23c1 2154 HAL_SPI_ErrorCallback(hspi);
mbed_official 441:d2c15dda23c1 2155 }
mbed_official 441:d2c15dda23c1 2156
mbed_official 441:d2c15dda23c1 2157 /**
mbed_official 630:825f75ca301e 2158 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
mbed_official 630:825f75ca301e 2159 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2160 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2161 * @retval None
mbed_official 340:28d1f895c6fe 2162 */
mbed_official 340:28d1f895c6fe 2163 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2164 {
mbed_official 340:28d1f895c6fe 2165 /* Receive data in packing mode */
mbed_official 340:28d1f895c6fe 2166 if(hspi->RxXferCount > 1)
mbed_official 340:28d1f895c6fe 2167 {
mbed_official 340:28d1f895c6fe 2168 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 2169 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 2170 hspi->RxXferCount -= 2;
mbed_official 630:825f75ca301e 2171 if(hspi->RxXferCount == 1)
mbed_official 340:28d1f895c6fe 2172 {
mbed_official 630:825f75ca301e 2173 /* set fiforxthresold according the reception data length: 8bit */
mbed_official 630:825f75ca301e 2174 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 630:825f75ca301e 2175 }
mbed_official 340:28d1f895c6fe 2176 }
mbed_official 340:28d1f895c6fe 2177 /* Receive data in 8 Bit mode */
mbed_official 340:28d1f895c6fe 2178 else
mbed_official 340:28d1f895c6fe 2179 {
mbed_official 340:28d1f895c6fe 2180 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 340:28d1f895c6fe 2181 hspi->RxXferCount--;
mbed_official 340:28d1f895c6fe 2182 }
mbed_official 630:825f75ca301e 2183
mbed_official 340:28d1f895c6fe 2184 /* check end of the reception */
mbed_official 340:28d1f895c6fe 2185 if(hspi->RxXferCount == 0)
mbed_official 340:28d1f895c6fe 2186 {
mbed_official 630:825f75ca301e 2187 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2188 {
mbed_official 630:825f75ca301e 2189 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 630:825f75ca301e 2190 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
mbed_official 340:28d1f895c6fe 2191 return;
mbed_official 340:28d1f895c6fe 2192 }
mbed_official 630:825f75ca301e 2193
mbed_official 340:28d1f895c6fe 2194 /* Disable RXNE interrupt */
mbed_official 630:825f75ca301e 2195 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 630:825f75ca301e 2196
mbed_official 340:28d1f895c6fe 2197 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2198 {
mbed_official 340:28d1f895c6fe 2199 SPI_CloseRxTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2200 }
mbed_official 340:28d1f895c6fe 2201 }
mbed_official 340:28d1f895c6fe 2202 }
mbed_official 340:28d1f895c6fe 2203
mbed_official 340:28d1f895c6fe 2204 /**
mbed_official 630:825f75ca301e 2205 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
mbed_official 630:825f75ca301e 2206 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2207 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2208 * @retval None
mbed_official 340:28d1f895c6fe 2209 */
mbed_official 340:28d1f895c6fe 2210 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2211 {
mbed_official 441:d2c15dda23c1 2212 __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 630:825f75ca301e 2213 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2214 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 2215
mbed_official 340:28d1f895c6fe 2216 hspi->CRCSize--;
mbed_official 630:825f75ca301e 2217
mbed_official 340:28d1f895c6fe 2218 /* check end of the reception */
mbed_official 340:28d1f895c6fe 2219 if(hspi->CRCSize == 0)
mbed_official 340:28d1f895c6fe 2220 {
mbed_official 340:28d1f895c6fe 2221 /* Disable RXNE interrupt */
mbed_official 630:825f75ca301e 2222 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 630:825f75ca301e 2223
mbed_official 340:28d1f895c6fe 2224 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2225 {
mbed_official 340:28d1f895c6fe 2226 SPI_CloseRxTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2227 }
mbed_official 340:28d1f895c6fe 2228 }
mbed_official 340:28d1f895c6fe 2229 }
mbed_official 340:28d1f895c6fe 2230
mbed_official 340:28d1f895c6fe 2231 /**
mbed_official 630:825f75ca301e 2232 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
mbed_official 630:825f75ca301e 2233 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2234 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2235 * @retval None
mbed_official 340:28d1f895c6fe 2236 */
mbed_official 340:28d1f895c6fe 2237 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2238 {
mbed_official 340:28d1f895c6fe 2239 /* Transmit data in packing Bit mode */
mbed_official 340:28d1f895c6fe 2240 if(hspi->TxXferCount >= 2)
mbed_official 340:28d1f895c6fe 2241 {
mbed_official 340:28d1f895c6fe 2242 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 340:28d1f895c6fe 2243 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 2244 hspi->TxXferCount -= 2;
mbed_official 340:28d1f895c6fe 2245 }
mbed_official 340:28d1f895c6fe 2246 /* Transmit data in 8 Bit mode */
mbed_official 340:28d1f895c6fe 2247 else
mbed_official 630:825f75ca301e 2248 {
mbed_official 340:28d1f895c6fe 2249 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 340:28d1f895c6fe 2250 hspi->TxXferCount--;
mbed_official 340:28d1f895c6fe 2251 }
mbed_official 630:825f75ca301e 2252
mbed_official 340:28d1f895c6fe 2253 /* check the end of the transmission */
mbed_official 340:28d1f895c6fe 2254 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2255 {
mbed_official 630:825f75ca301e 2256 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2257 {
mbed_official 340:28d1f895c6fe 2258 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 2259 }
mbed_official 340:28d1f895c6fe 2260 /* Disable TXE interrupt */
mbed_official 340:28d1f895c6fe 2261 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 630:825f75ca301e 2262
mbed_official 340:28d1f895c6fe 2263 if(hspi->RxXferCount == 0)
mbed_official 630:825f75ca301e 2264 {
mbed_official 340:28d1f895c6fe 2265 SPI_CloseRxTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2266 }
mbed_official 340:28d1f895c6fe 2267 }
mbed_official 340:28d1f895c6fe 2268 }
mbed_official 340:28d1f895c6fe 2269
mbed_official 340:28d1f895c6fe 2270 /**
mbed_official 630:825f75ca301e 2271 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
mbed_official 630:825f75ca301e 2272 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2273 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2274 * @retval None
mbed_official 340:28d1f895c6fe 2275 */
mbed_official 340:28d1f895c6fe 2276 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2277 {
mbed_official 340:28d1f895c6fe 2278 /* Receive data in 16 Bit mode */
mbed_official 340:28d1f895c6fe 2279 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 2280 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 630:825f75ca301e 2281 hspi->RxXferCount--;
mbed_official 630:825f75ca301e 2282
mbed_official 340:28d1f895c6fe 2283 if(hspi->RxXferCount == 0)
mbed_official 340:28d1f895c6fe 2284 {
mbed_official 630:825f75ca301e 2285 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2286 {
mbed_official 630:825f75ca301e 2287 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
mbed_official 340:28d1f895c6fe 2288 return;
mbed_official 340:28d1f895c6fe 2289 }
mbed_official 630:825f75ca301e 2290
mbed_official 340:28d1f895c6fe 2291 /* Disable RXNE interrupt */
mbed_official 630:825f75ca301e 2292 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 630:825f75ca301e 2293
mbed_official 340:28d1f895c6fe 2294 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2295 {
mbed_official 340:28d1f895c6fe 2296 SPI_CloseRxTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2297 }
mbed_official 340:28d1f895c6fe 2298 }
mbed_official 340:28d1f895c6fe 2299 }
mbed_official 340:28d1f895c6fe 2300
mbed_official 340:28d1f895c6fe 2301 /**
mbed_official 630:825f75ca301e 2302 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
mbed_official 630:825f75ca301e 2303 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2304 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2305 * @retval None
mbed_official 340:28d1f895c6fe 2306 */
mbed_official 340:28d1f895c6fe 2307 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2308 {
mbed_official 340:28d1f895c6fe 2309 /* Receive data in 16 Bit mode */
mbed_official 441:d2c15dda23c1 2310 __IO uint16_t tmpreg = hspi->Instance->DR;
mbed_official 630:825f75ca301e 2311 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2312 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 2313
mbed_official 340:28d1f895c6fe 2314 /* Disable RXNE interrupt */
mbed_official 630:825f75ca301e 2315 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 630:825f75ca301e 2316
mbed_official 340:28d1f895c6fe 2317 SPI_CloseRxTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2318 }
mbed_official 340:28d1f895c6fe 2319
mbed_official 340:28d1f895c6fe 2320 /**
mbed_official 630:825f75ca301e 2321 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
mbed_official 630:825f75ca301e 2322 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2323 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2324 * @retval None
mbed_official 340:28d1f895c6fe 2325 */
mbed_official 340:28d1f895c6fe 2326 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2327 {
mbed_official 340:28d1f895c6fe 2328 /* Transmit data in 16 Bit mode */
mbed_official 340:28d1f895c6fe 2329 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 340:28d1f895c6fe 2330 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 2331 hspi->TxXferCount--;
mbed_official 630:825f75ca301e 2332
mbed_official 340:28d1f895c6fe 2333 /* Enable CRC Transmission */
mbed_official 340:28d1f895c6fe 2334 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2335 {
mbed_official 630:825f75ca301e 2336 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2337 {
mbed_official 340:28d1f895c6fe 2338 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 2339 }
mbed_official 340:28d1f895c6fe 2340 /* Disable TXE interrupt */
mbed_official 340:28d1f895c6fe 2341 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 630:825f75ca301e 2342
mbed_official 340:28d1f895c6fe 2343 if(hspi->RxXferCount == 0)
mbed_official 630:825f75ca301e 2344 {
mbed_official 340:28d1f895c6fe 2345 SPI_CloseRxTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2346 }
mbed_official 340:28d1f895c6fe 2347 }
mbed_official 340:28d1f895c6fe 2348 }
mbed_official 340:28d1f895c6fe 2349
mbed_official 340:28d1f895c6fe 2350 /**
mbed_official 630:825f75ca301e 2351 * @brief Manage the CRC 8-bit receive in Interrupt context.
mbed_official 630:825f75ca301e 2352 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2353 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2354 * @retval None
mbed_official 340:28d1f895c6fe 2355 */
mbed_official 340:28d1f895c6fe 2356 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2357 {
mbed_official 630:825f75ca301e 2358 __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 630:825f75ca301e 2359 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2360 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 2361
mbed_official 340:28d1f895c6fe 2362 hspi->CRCSize--;
mbed_official 630:825f75ca301e 2363
mbed_official 340:28d1f895c6fe 2364 if(hspi->CRCSize == 0)
mbed_official 630:825f75ca301e 2365 {
mbed_official 340:28d1f895c6fe 2366 SPI_CloseRx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2367 }
mbed_official 340:28d1f895c6fe 2368 }
mbed_official 340:28d1f895c6fe 2369
mbed_official 340:28d1f895c6fe 2370 /**
mbed_official 630:825f75ca301e 2371 * @brief Manage the receive 8-bit in Interrupt context.
mbed_official 630:825f75ca301e 2372 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2373 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2374 * @retval None
mbed_official 340:28d1f895c6fe 2375 */
mbed_official 340:28d1f895c6fe 2376 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2377 {
mbed_official 340:28d1f895c6fe 2378 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
mbed_official 340:28d1f895c6fe 2379 hspi->RxXferCount--;
mbed_official 630:825f75ca301e 2380
mbed_official 340:28d1f895c6fe 2381 /* Enable CRC Transmission */
mbed_official 630:825f75ca301e 2382 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 340:28d1f895c6fe 2383 {
mbed_official 340:28d1f895c6fe 2384 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 2385 }
mbed_official 630:825f75ca301e 2386
mbed_official 340:28d1f895c6fe 2387 if(hspi->RxXferCount == 0)
mbed_official 340:28d1f895c6fe 2388 {
mbed_official 630:825f75ca301e 2389 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2390 {
mbed_official 630:825f75ca301e 2391 hspi->RxISR = SPI_RxISR_8BITCRC;
mbed_official 340:28d1f895c6fe 2392 return;
mbed_official 340:28d1f895c6fe 2393 }
mbed_official 340:28d1f895c6fe 2394 SPI_CloseRx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2395 }
mbed_official 340:28d1f895c6fe 2396 }
mbed_official 340:28d1f895c6fe 2397
mbed_official 340:28d1f895c6fe 2398 /**
mbed_official 630:825f75ca301e 2399 * @brief Manage the CRC 16-bit receive in Interrupt context.
mbed_official 630:825f75ca301e 2400 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2401 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2402 * @retval None
mbed_official 340:28d1f895c6fe 2403 */
mbed_official 340:28d1f895c6fe 2404 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2405 {
mbed_official 340:28d1f895c6fe 2406 __IO uint16_t tmpreg;
mbed_official 630:825f75ca301e 2407
mbed_official 340:28d1f895c6fe 2408 tmpreg = hspi->Instance->DR;
mbed_official 630:825f75ca301e 2409 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2410 UNUSED(tmpreg);
mbed_official 630:825f75ca301e 2411
mbed_official 340:28d1f895c6fe 2412 /* Disable RXNE and ERR interrupt */
mbed_official 340:28d1f895c6fe 2413 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 2414
mbed_official 340:28d1f895c6fe 2415 SPI_CloseRx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2416 }
mbed_official 340:28d1f895c6fe 2417
mbed_official 340:28d1f895c6fe 2418 /**
mbed_official 630:825f75ca301e 2419 * @brief Manage the 16-bit receive in Interrupt context.
mbed_official 630:825f75ca301e 2420 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2421 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2422 * @retval None
mbed_official 340:28d1f895c6fe 2423 */
mbed_official 340:28d1f895c6fe 2424 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2425 {
mbed_official 340:28d1f895c6fe 2426 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 340:28d1f895c6fe 2427 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 2428 hspi->RxXferCount--;
mbed_official 630:825f75ca301e 2429
mbed_official 340:28d1f895c6fe 2430 /* Enable CRC Transmission */
mbed_official 630:825f75ca301e 2431 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 340:28d1f895c6fe 2432 {
mbed_official 340:28d1f895c6fe 2433 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 2434 }
mbed_official 630:825f75ca301e 2435
mbed_official 340:28d1f895c6fe 2436 if(hspi->RxXferCount == 0)
mbed_official 630:825f75ca301e 2437 {
mbed_official 630:825f75ca301e 2438 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2439 {
mbed_official 340:28d1f895c6fe 2440 hspi->RxISR = SPI_RxISR_16BITCRC;
mbed_official 340:28d1f895c6fe 2441 return;
mbed_official 340:28d1f895c6fe 2442 }
mbed_official 340:28d1f895c6fe 2443 SPI_CloseRx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2444 }
mbed_official 340:28d1f895c6fe 2445 }
mbed_official 340:28d1f895c6fe 2446
mbed_official 340:28d1f895c6fe 2447 /**
mbed_official 630:825f75ca301e 2448 * @brief Handle the data 8-bit transmit in Interrupt mode.
mbed_official 630:825f75ca301e 2449 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2450 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2451 * @retval None
mbed_official 340:28d1f895c6fe 2452 */
mbed_official 340:28d1f895c6fe 2453 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2454 {
mbed_official 340:28d1f895c6fe 2455 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 340:28d1f895c6fe 2456 hspi->TxXferCount--;
mbed_official 630:825f75ca301e 2457
mbed_official 340:28d1f895c6fe 2458 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2459 {
mbed_official 630:825f75ca301e 2460 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2461 {
mbed_official 340:28d1f895c6fe 2462 /* Enable CRC Transmission */
mbed_official 340:28d1f895c6fe 2463 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 2464 }
mbed_official 340:28d1f895c6fe 2465 SPI_CloseTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2466 }
mbed_official 340:28d1f895c6fe 2467 }
mbed_official 340:28d1f895c6fe 2468
mbed_official 340:28d1f895c6fe 2469 /**
mbed_official 630:825f75ca301e 2470 * @brief Handle the data 16-bit transmit in Interrupt mode.
mbed_official 630:825f75ca301e 2471 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2472 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2473 * @retval None
mbed_official 340:28d1f895c6fe 2474 */
mbed_official 340:28d1f895c6fe 2475 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 630:825f75ca301e 2476 {
mbed_official 340:28d1f895c6fe 2477 /* Transmit data in 16 Bit mode */
mbed_official 340:28d1f895c6fe 2478 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 340:28d1f895c6fe 2479 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 340:28d1f895c6fe 2480 hspi->TxXferCount--;
mbed_official 630:825f75ca301e 2481
mbed_official 340:28d1f895c6fe 2482 if(hspi->TxXferCount == 0)
mbed_official 340:28d1f895c6fe 2483 {
mbed_official 630:825f75ca301e 2484 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2485 {
mbed_official 340:28d1f895c6fe 2486 /* Enable CRC Transmission */
mbed_official 340:28d1f895c6fe 2487 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 340:28d1f895c6fe 2488 }
mbed_official 340:28d1f895c6fe 2489 SPI_CloseTx_ISR(hspi);
mbed_official 340:28d1f895c6fe 2490 }
mbed_official 340:28d1f895c6fe 2491 }
mbed_official 340:28d1f895c6fe 2492
mbed_official 340:28d1f895c6fe 2493 /**
mbed_official 630:825f75ca301e 2494 * @brief Handle SPI Communication Timeout.
mbed_official 630:825f75ca301e 2495 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2496 * the configuration information for SPI module.
mbed_official 340:28d1f895c6fe 2497 * @param Flag : SPI flag to check
mbed_official 340:28d1f895c6fe 2498 * @param State : flag state to check
mbed_official 340:28d1f895c6fe 2499 * @param Timeout : Timeout duration
mbed_official 340:28d1f895c6fe 2500 * @retval HAL status
mbed_official 340:28d1f895c6fe 2501 */
mbed_official 340:28d1f895c6fe 2502 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 2503 {
mbed_official 340:28d1f895c6fe 2504 uint32_t tickstart = HAL_GetTick();
mbed_official 630:825f75ca301e 2505
mbed_official 340:28d1f895c6fe 2506 while((hspi->Instance->SR & Flag) != State)
mbed_official 340:28d1f895c6fe 2507 {
mbed_official 340:28d1f895c6fe 2508 if(Timeout != HAL_MAX_DELAY)
mbed_official 340:28d1f895c6fe 2509 {
mbed_official 441:d2c15dda23c1 2510 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
mbed_official 340:28d1f895c6fe 2511 {
mbed_official 340:28d1f895c6fe 2512 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 340:28d1f895c6fe 2513 on both master and slave sides in order to resynchronize the master
mbed_official 340:28d1f895c6fe 2514 and slave for their respective CRC calculation */
mbed_official 630:825f75ca301e 2515
mbed_official 340:28d1f895c6fe 2516 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 340:28d1f895c6fe 2517 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 2518
mbed_official 340:28d1f895c6fe 2519 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 340:28d1f895c6fe 2520 {
mbed_official 340:28d1f895c6fe 2521 /* Disable SPI peripheral */
mbed_official 340:28d1f895c6fe 2522 __HAL_SPI_DISABLE(hspi);
mbed_official 340:28d1f895c6fe 2523 }
mbed_official 630:825f75ca301e 2524
mbed_official 340:28d1f895c6fe 2525 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 2526 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2527 {
mbed_official 630:825f75ca301e 2528 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 2529 }
mbed_official 630:825f75ca301e 2530
mbed_official 340:28d1f895c6fe 2531 hspi->State= HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 2532
mbed_official 340:28d1f895c6fe 2533 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 2534 __HAL_UNLOCK(hspi);
mbed_official 630:825f75ca301e 2535
mbed_official 340:28d1f895c6fe 2536 return HAL_TIMEOUT;
mbed_official 340:28d1f895c6fe 2537 }
mbed_official 340:28d1f895c6fe 2538 }
mbed_official 340:28d1f895c6fe 2539 }
mbed_official 630:825f75ca301e 2540
mbed_official 630:825f75ca301e 2541 return HAL_OK;
mbed_official 340:28d1f895c6fe 2542 }
mbed_official 340:28d1f895c6fe 2543
mbed_official 340:28d1f895c6fe 2544 /**
mbed_official 630:825f75ca301e 2545 * @brief Handle SPI FIFO Communication Timeout.
mbed_official 630:825f75ca301e 2546 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2547 * the configuration information for SPI module.
mbed_official 441:d2c15dda23c1 2548 * @param Fifo : Fifo to check
mbed_official 441:d2c15dda23c1 2549 * @param State : Fifo state to check
mbed_official 340:28d1f895c6fe 2550 * @param Timeout : Timeout duration
mbed_official 340:28d1f895c6fe 2551 * @retval HAL status
mbed_official 340:28d1f895c6fe 2552 */
mbed_official 340:28d1f895c6fe 2553 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 2554 {
mbed_official 340:28d1f895c6fe 2555 __IO uint8_t tmpreg;
mbed_official 340:28d1f895c6fe 2556 uint32_t tickstart = HAL_GetTick();
mbed_official 340:28d1f895c6fe 2557
mbed_official 340:28d1f895c6fe 2558 while((hspi->Instance->SR & Fifo) != State)
mbed_official 340:28d1f895c6fe 2559 {
mbed_official 340:28d1f895c6fe 2560 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
mbed_official 340:28d1f895c6fe 2561 {
mbed_official 340:28d1f895c6fe 2562 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 630:825f75ca301e 2563 /* To avoid GCC warning */
mbed_official 441:d2c15dda23c1 2564 UNUSED(tmpreg);
mbed_official 340:28d1f895c6fe 2565 }
mbed_official 630:825f75ca301e 2566
mbed_official 340:28d1f895c6fe 2567 if(Timeout != HAL_MAX_DELAY)
mbed_official 340:28d1f895c6fe 2568 {
mbed_official 441:d2c15dda23c1 2569 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
mbed_official 340:28d1f895c6fe 2570 {
mbed_official 340:28d1f895c6fe 2571 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 441:d2c15dda23c1 2572 on both master and slave sides in order to resynchronize the master
mbed_official 441:d2c15dda23c1 2573 and slave for their respective CRC calculation */
mbed_official 630:825f75ca301e 2574
mbed_official 340:28d1f895c6fe 2575 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 340:28d1f895c6fe 2576 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 2577
mbed_official 340:28d1f895c6fe 2578 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 340:28d1f895c6fe 2579 {
mbed_official 340:28d1f895c6fe 2580 /* Disable SPI peripheral */
mbed_official 340:28d1f895c6fe 2581 __HAL_SPI_DISABLE(hspi);
mbed_official 340:28d1f895c6fe 2582 }
mbed_official 630:825f75ca301e 2583
mbed_official 340:28d1f895c6fe 2584 /* Reset CRC Calculation */
mbed_official 630:825f75ca301e 2585 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 340:28d1f895c6fe 2586 {
mbed_official 630:825f75ca301e 2587 SPI_RESET_CRC(hspi);
mbed_official 340:28d1f895c6fe 2588 }
mbed_official 630:825f75ca301e 2589
mbed_official 340:28d1f895c6fe 2590 hspi->State = HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 2591
mbed_official 340:28d1f895c6fe 2592 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 2593 __HAL_UNLOCK(hspi);
mbed_official 630:825f75ca301e 2594
mbed_official 340:28d1f895c6fe 2595 return HAL_TIMEOUT;
mbed_official 340:28d1f895c6fe 2596 }
mbed_official 340:28d1f895c6fe 2597 }
mbed_official 340:28d1f895c6fe 2598 }
mbed_official 630:825f75ca301e 2599
mbed_official 630:825f75ca301e 2600 return HAL_OK;
mbed_official 340:28d1f895c6fe 2601 }
mbed_official 340:28d1f895c6fe 2602
mbed_official 340:28d1f895c6fe 2603 /**
mbed_official 630:825f75ca301e 2604 * @brief Handle the check of the RX transaction complete.
mbed_official 630:825f75ca301e 2605 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2606 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2607 * @param Timeout : Timeout duration
mbed_official 441:d2c15dda23c1 2608 * @retval None.
mbed_official 340:28d1f895c6fe 2609 */
mbed_official 340:28d1f895c6fe 2610 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 2611 {
mbed_official 340:28d1f895c6fe 2612 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 340:28d1f895c6fe 2613 {
mbed_official 340:28d1f895c6fe 2614 /* Disable SPI peripheral */
mbed_official 340:28d1f895c6fe 2615 __HAL_SPI_DISABLE(hspi);
mbed_official 630:825f75ca301e 2616 }
mbed_official 630:825f75ca301e 2617
mbed_official 630:825f75ca301e 2618 /* Control the BSY flag */
mbed_official 630:825f75ca301e 2619 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 2620 {
mbed_official 630:825f75ca301e 2621 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2622 return HAL_TIMEOUT;
mbed_official 630:825f75ca301e 2623 }
mbed_official 630:825f75ca301e 2624
mbed_official 630:825f75ca301e 2625 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 630:825f75ca301e 2626 {
mbed_official 630:825f75ca301e 2627 /* Empty the FRLVL fifo */
mbed_official 630:825f75ca301e 2628 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 441:d2c15dda23c1 2629 {
mbed_official 441:d2c15dda23c1 2630 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 441:d2c15dda23c1 2631 return HAL_TIMEOUT;
mbed_official 441:d2c15dda23c1 2632 }
mbed_official 630:825f75ca301e 2633 }
mbed_official 340:28d1f895c6fe 2634 return HAL_OK;
mbed_official 340:28d1f895c6fe 2635 }
mbed_official 630:825f75ca301e 2636
mbed_official 340:28d1f895c6fe 2637 /**
mbed_official 630:825f75ca301e 2638 * @brief Handle the check of the RXTX or TX transaction complete.
mbed_official 630:825f75ca301e 2639 * @param hspi: SPI handle
mbed_official 630:825f75ca301e 2640 * @param Timeout : Timeout duration
mbed_official 630:825f75ca301e 2641 */
mbed_official 630:825f75ca301e 2642 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 630:825f75ca301e 2643 {
mbed_official 630:825f75ca301e 2644 /* Control if the TX fifo is empty */
mbed_official 630:825f75ca301e 2645 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 2646 {
mbed_official 630:825f75ca301e 2647 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2648 return HAL_TIMEOUT;
mbed_official 630:825f75ca301e 2649 }
mbed_official 630:825f75ca301e 2650 /* Control the BSY flag */
mbed_official 630:825f75ca301e 2651 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 630:825f75ca301e 2652 {
mbed_official 630:825f75ca301e 2653 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2654 return HAL_TIMEOUT;
mbed_official 630:825f75ca301e 2655 }
mbed_official 630:825f75ca301e 2656 return HAL_OK;
mbed_official 630:825f75ca301e 2657 }
mbed_official 630:825f75ca301e 2658
mbed_official 630:825f75ca301e 2659 /**
mbed_official 630:825f75ca301e 2660 * @brief Handle the end of the RXTX transaction.
mbed_official 630:825f75ca301e 2661 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2662 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2663 * @retval None
mbed_official 340:28d1f895c6fe 2664 */
mbed_official 340:28d1f895c6fe 2665 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2666 {
mbed_official 340:28d1f895c6fe 2667 /* Disable ERR interrupt */
mbed_official 340:28d1f895c6fe 2668 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
mbed_official 630:825f75ca301e 2669
mbed_official 630:825f75ca301e 2670 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 2671 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
mbed_official 630:825f75ca301e 2672 {
mbed_official 630:825f75ca301e 2673 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2674 }
mbed_official 630:825f75ca301e 2675
mbed_official 340:28d1f895c6fe 2676 /* Check if CRC error occurred */
mbed_official 340:28d1f895c6fe 2677 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 340:28d1f895c6fe 2678 {
mbed_official 340:28d1f895c6fe 2679 hspi->State = HAL_SPI_STATE_READY;
mbed_official 340:28d1f895c6fe 2680 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 340:28d1f895c6fe 2681 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 340:28d1f895c6fe 2682 HAL_SPI_ErrorCallback(hspi);
mbed_official 340:28d1f895c6fe 2683 }
mbed_official 340:28d1f895c6fe 2684 else
mbed_official 340:28d1f895c6fe 2685 {
mbed_official 340:28d1f895c6fe 2686 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 340:28d1f895c6fe 2687 {
mbed_official 340:28d1f895c6fe 2688 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 340:28d1f895c6fe 2689 {
mbed_official 340:28d1f895c6fe 2690 hspi->State = HAL_SPI_STATE_READY;
mbed_official 340:28d1f895c6fe 2691 HAL_SPI_RxCpltCallback(hspi);
mbed_official 340:28d1f895c6fe 2692 }
mbed_official 340:28d1f895c6fe 2693 else
mbed_official 340:28d1f895c6fe 2694 {
mbed_official 340:28d1f895c6fe 2695 hspi->State = HAL_SPI_STATE_READY;
mbed_official 340:28d1f895c6fe 2696 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 630:825f75ca301e 2697 }
mbed_official 340:28d1f895c6fe 2698 }
mbed_official 340:28d1f895c6fe 2699 else
mbed_official 340:28d1f895c6fe 2700 {
mbed_official 340:28d1f895c6fe 2701 hspi->State = HAL_SPI_STATE_READY;
mbed_official 340:28d1f895c6fe 2702 HAL_SPI_ErrorCallback(hspi);
mbed_official 340:28d1f895c6fe 2703 }
mbed_official 340:28d1f895c6fe 2704 }
mbed_official 340:28d1f895c6fe 2705 }
mbed_official 340:28d1f895c6fe 2706
mbed_official 340:28d1f895c6fe 2707 /**
mbed_official 630:825f75ca301e 2708 * @brief Handle the end of the RX transaction.
mbed_official 630:825f75ca301e 2709 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2710 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2711 * @retval None
mbed_official 340:28d1f895c6fe 2712 */
mbed_official 340:28d1f895c6fe 2713 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2714 {
mbed_official 340:28d1f895c6fe 2715 /* Disable RXNE and ERR interrupt */
mbed_official 340:28d1f895c6fe 2716 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 2717
mbed_official 340:28d1f895c6fe 2718 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 2719 if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
mbed_official 630:825f75ca301e 2720 {
mbed_official 630:825f75ca301e 2721 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2722 }
mbed_official 630:825f75ca301e 2723 hspi->State = HAL_SPI_STATE_READY;
mbed_official 630:825f75ca301e 2724
mbed_official 340:28d1f895c6fe 2725 /* Check if CRC error occurred */
mbed_official 340:28d1f895c6fe 2726 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 340:28d1f895c6fe 2727 {
mbed_official 340:28d1f895c6fe 2728 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 340:28d1f895c6fe 2729 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 630:825f75ca301e 2730 HAL_SPI_ErrorCallback(hspi);
mbed_official 340:28d1f895c6fe 2731 }
mbed_official 340:28d1f895c6fe 2732 else
mbed_official 340:28d1f895c6fe 2733 {
mbed_official 340:28d1f895c6fe 2734 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 340:28d1f895c6fe 2735 {
mbed_official 630:825f75ca301e 2736 HAL_SPI_RxCpltCallback(hspi);
mbed_official 340:28d1f895c6fe 2737 }
mbed_official 340:28d1f895c6fe 2738 else
mbed_official 340:28d1f895c6fe 2739 {
mbed_official 340:28d1f895c6fe 2740 HAL_SPI_ErrorCallback(hspi);
mbed_official 340:28d1f895c6fe 2741 }
mbed_official 340:28d1f895c6fe 2742 }
mbed_official 340:28d1f895c6fe 2743 }
mbed_official 340:28d1f895c6fe 2744
mbed_official 340:28d1f895c6fe 2745 /**
mbed_official 630:825f75ca301e 2746 * @brief Handle the end of the TX transaction.
mbed_official 630:825f75ca301e 2747 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 630:825f75ca301e 2748 * the configuration information for SPI module.
mbed_official 630:825f75ca301e 2749 * @retval None
mbed_official 340:28d1f895c6fe 2750 */
mbed_official 340:28d1f895c6fe 2751 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 340:28d1f895c6fe 2752 {
mbed_official 340:28d1f895c6fe 2753 /* Disable TXE and ERR interrupt */
mbed_official 340:28d1f895c6fe 2754 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
mbed_official 630:825f75ca301e 2755
mbed_official 630:825f75ca301e 2756 /* Check the end of the transaction */
mbed_official 630:825f75ca301e 2757 if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
mbed_official 630:825f75ca301e 2758 {
mbed_official 630:825f75ca301e 2759 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
mbed_official 630:825f75ca301e 2760 }
mbed_official 630:825f75ca301e 2761
mbed_official 630:825f75ca301e 2762 /* Clear overrun flag in 2 Lines communication mode because received is not read */
mbed_official 340:28d1f895c6fe 2763 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 340:28d1f895c6fe 2764 {
mbed_official 340:28d1f895c6fe 2765 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 340:28d1f895c6fe 2766 }
mbed_official 630:825f75ca301e 2767
mbed_official 340:28d1f895c6fe 2768 hspi->State = HAL_SPI_STATE_READY;
mbed_official 340:28d1f895c6fe 2769 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 340:28d1f895c6fe 2770 {
mbed_official 340:28d1f895c6fe 2771 HAL_SPI_ErrorCallback(hspi);
mbed_official 340:28d1f895c6fe 2772 }
mbed_official 340:28d1f895c6fe 2773 else
mbed_official 340:28d1f895c6fe 2774 {
mbed_official 340:28d1f895c6fe 2775 HAL_SPI_TxCpltCallback(hspi);
mbed_official 340:28d1f895c6fe 2776 }
mbed_official 340:28d1f895c6fe 2777 }
mbed_official 340:28d1f895c6fe 2778
mbed_official 340:28d1f895c6fe 2779 /**
mbed_official 340:28d1f895c6fe 2780 * @}
mbed_official 340:28d1f895c6fe 2781 */
mbed_official 340:28d1f895c6fe 2782
mbed_official 340:28d1f895c6fe 2783 #endif /* HAL_SPI_MODULE_ENABLED */
mbed_official 630:825f75ca301e 2784
mbed_official 340:28d1f895c6fe 2785 /**
mbed_official 340:28d1f895c6fe 2786 * @}
mbed_official 340:28d1f895c6fe 2787 */
mbed_official 340:28d1f895c6fe 2788
mbed_official 340:28d1f895c6fe 2789 /**
mbed_official 340:28d1f895c6fe 2790 * @}
mbed_official 340:28d1f895c6fe 2791 */
mbed_official 340:28d1f895c6fe 2792
mbed_official 340:28d1f895c6fe 2793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/