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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Parent:
441:d2c15dda23c1 
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 392:2b59412bb664 1 /**
mbed_official 392:2b59412bb664 2 ******************************************************************************
mbed_official 392:2b59412bb664 3 * @file stm32f072xb.h
mbed_official 392:2b59412bb664 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V2.2.2
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 392:2b59412bb664 7 * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
mbed_official 392:2b59412bb664 8 *
mbed_official 392:2b59412bb664 9 * This file contains:
mbed_official 392:2b59412bb664 10 * - Data structures and the address mapping for all peripherals
mbed_official 392:2b59412bb664 11 * - Peripheral's registers declarations and bits definition
mbed_official 392:2b59412bb664 12 * - Macros to access peripheral’s registers hardware
mbed_official 392:2b59412bb664 13 *
mbed_official 392:2b59412bb664 14 ******************************************************************************
mbed_official 392:2b59412bb664 15 * @attention
mbed_official 392:2b59412bb664 16 *
mbed_official 630:825f75ca301e 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 392:2b59412bb664 18 *
mbed_official 392:2b59412bb664 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 392:2b59412bb664 20 * are permitted provided that the following conditions are met:
mbed_official 392:2b59412bb664 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 392:2b59412bb664 22 * this list of conditions and the following disclaimer.
mbed_official 392:2b59412bb664 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 392:2b59412bb664 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 392:2b59412bb664 25 * and/or other materials provided with the distribution.
mbed_official 392:2b59412bb664 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 392:2b59412bb664 27 * may be used to endorse or promote products derived from this software
mbed_official 392:2b59412bb664 28 * without specific prior written permission.
mbed_official 392:2b59412bb664 29 *
mbed_official 392:2b59412bb664 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 392:2b59412bb664 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 392:2b59412bb664 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 392:2b59412bb664 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 392:2b59412bb664 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 392:2b59412bb664 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 392:2b59412bb664 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 392:2b59412bb664 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 392:2b59412bb664 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 392:2b59412bb664 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 392:2b59412bb664 40 *
mbed_official 392:2b59412bb664 41 ******************************************************************************
mbed_official 392:2b59412bb664 42 */
mbed_official 392:2b59412bb664 43
mbed_official 392:2b59412bb664 44 /** @addtogroup CMSIS_Device
mbed_official 392:2b59412bb664 45 * @{
mbed_official 392:2b59412bb664 46 */
mbed_official 392:2b59412bb664 47
mbed_official 392:2b59412bb664 48 /** @addtogroup stm32f072xb
mbed_official 392:2b59412bb664 49 * @{
mbed_official 392:2b59412bb664 50 */
mbed_official 392:2b59412bb664 51
mbed_official 392:2b59412bb664 52 #ifndef __STM32F072xB_H
mbed_official 392:2b59412bb664 53 #define __STM32F072xB_H
mbed_official 392:2b59412bb664 54
mbed_official 392:2b59412bb664 55 #ifdef __cplusplus
mbed_official 392:2b59412bb664 56 extern "C" {
mbed_official 392:2b59412bb664 57 #endif /* __cplusplus */
mbed_official 392:2b59412bb664 58
mbed_official 392:2b59412bb664 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 392:2b59412bb664 60 * @{
mbed_official 392:2b59412bb664 61 */
mbed_official 392:2b59412bb664 62 /**
mbed_official 392:2b59412bb664 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official 392:2b59412bb664 64 */
mbed_official 392:2b59412bb664 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
mbed_official 392:2b59412bb664 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
mbed_official 392:2b59412bb664 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
mbed_official 392:2b59412bb664 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 392:2b59412bb664 69
mbed_official 392:2b59412bb664 70 /**
mbed_official 392:2b59412bb664 71 * @}
mbed_official 392:2b59412bb664 72 */
mbed_official 392:2b59412bb664 73
mbed_official 392:2b59412bb664 74 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 392:2b59412bb664 75 * @{
mbed_official 392:2b59412bb664 76 */
mbed_official 392:2b59412bb664 77
mbed_official 392:2b59412bb664 78 /**
mbed_official 392:2b59412bb664 79 * @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
mbed_official 392:2b59412bb664 80 */
mbed_official 392:2b59412bb664 81 typedef enum
mbed_official 392:2b59412bb664 82 {
mbed_official 392:2b59412bb664 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
mbed_official 392:2b59412bb664 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 392:2b59412bb664 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 392:2b59412bb664 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 392:2b59412bb664 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 392:2b59412bb664 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 392:2b59412bb664 89
mbed_official 392:2b59412bb664 90 /****** STM32F072x8/STM32F072xB specific Interrupt Numbers **************************************************/
mbed_official 392:2b59412bb664 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 392:2b59412bb664 92 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
mbed_official 392:2b59412bb664 93 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
mbed_official 392:2b59412bb664 94 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
mbed_official 392:2b59412bb664 95 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
mbed_official 392:2b59412bb664 96 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 392:2b59412bb664 97 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 392:2b59412bb664 98 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 392:2b59412bb664 99 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
mbed_official 392:2b59412bb664 100 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 392:2b59412bb664 101 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 392:2b59412bb664 102 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupts */
mbed_official 392:2b59412bb664 103 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
mbed_official 392:2b59412bb664 104 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 392:2b59412bb664 105 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 392:2b59412bb664 106 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
mbed_official 392:2b59412bb664 107 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
mbed_official 392:2b59412bb664 108 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
mbed_official 392:2b59412bb664 109 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
mbed_official 392:2b59412bb664 110 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
mbed_official 392:2b59412bb664 111 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
mbed_official 392:2b59412bb664 112 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
mbed_official 392:2b59412bb664 113 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
mbed_official 392:2b59412bb664 114 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 392:2b59412bb664 115 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
mbed_official 392:2b59412bb664 116 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
mbed_official 392:2b59412bb664 117 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
mbed_official 392:2b59412bb664 118 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 392:2b59412bb664 119 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
mbed_official 392:2b59412bb664 120 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
mbed_official 392:2b59412bb664 121 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
mbed_official 392:2b59412bb664 122 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
mbed_official 392:2b59412bb664 123 } IRQn_Type;
mbed_official 392:2b59412bb664 124
mbed_official 392:2b59412bb664 125 /**
mbed_official 392:2b59412bb664 126 * @}
mbed_official 392:2b59412bb664 127 */
mbed_official 392:2b59412bb664 128
mbed_official 392:2b59412bb664 129 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official 392:2b59412bb664 130 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official 392:2b59412bb664 131 #include <stdint.h>
mbed_official 392:2b59412bb664 132
mbed_official 392:2b59412bb664 133 /** @addtogroup Peripheral_registers_structures
mbed_official 392:2b59412bb664 134 * @{
mbed_official 392:2b59412bb664 135 */
mbed_official 392:2b59412bb664 136
mbed_official 392:2b59412bb664 137 /**
mbed_official 392:2b59412bb664 138 * @brief Analog to Digital Converter
mbed_official 392:2b59412bb664 139 */
mbed_official 392:2b59412bb664 140
mbed_official 392:2b59412bb664 141 typedef struct
mbed_official 392:2b59412bb664 142 {
mbed_official 392:2b59412bb664 143 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
mbed_official 392:2b59412bb664 144 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
mbed_official 392:2b59412bb664 145 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
mbed_official 392:2b59412bb664 146 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
mbed_official 392:2b59412bb664 147 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
mbed_official 392:2b59412bb664 148 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
mbed_official 392:2b59412bb664 149 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 392:2b59412bb664 150 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 392:2b59412bb664 151 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
mbed_official 392:2b59412bb664 152 uint32_t RESERVED3; /*!< Reserved, 0x24 */
mbed_official 392:2b59412bb664 153 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
mbed_official 392:2b59412bb664 154 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
mbed_official 392:2b59412bb664 155 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
mbed_official 392:2b59412bb664 156 }ADC_TypeDef;
mbed_official 392:2b59412bb664 157
mbed_official 392:2b59412bb664 158 typedef struct
mbed_official 392:2b59412bb664 159 {
mbed_official 392:2b59412bb664 160 __IO uint32_t CCR;
mbed_official 392:2b59412bb664 161 }ADC_Common_TypeDef;
mbed_official 392:2b59412bb664 162
mbed_official 392:2b59412bb664 163 /**
mbed_official 392:2b59412bb664 164 * @brief Controller Area Network TxMailBox
mbed_official 392:2b59412bb664 165 */
mbed_official 392:2b59412bb664 166 typedef struct
mbed_official 392:2b59412bb664 167 {
mbed_official 392:2b59412bb664 168 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 392:2b59412bb664 169 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 392:2b59412bb664 170 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 392:2b59412bb664 171 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 392:2b59412bb664 172 }CAN_TxMailBox_TypeDef;
mbed_official 392:2b59412bb664 173
mbed_official 392:2b59412bb664 174 /**
mbed_official 392:2b59412bb664 175 * @brief Controller Area Network FIFOMailBox
mbed_official 392:2b59412bb664 176 */
mbed_official 392:2b59412bb664 177 typedef struct
mbed_official 392:2b59412bb664 178 {
mbed_official 392:2b59412bb664 179 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 392:2b59412bb664 180 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 392:2b59412bb664 181 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 392:2b59412bb664 182 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 392:2b59412bb664 183 }CAN_FIFOMailBox_TypeDef;
mbed_official 392:2b59412bb664 184
mbed_official 392:2b59412bb664 185 /**
mbed_official 392:2b59412bb664 186 * @brief Controller Area Network FilterRegister
mbed_official 392:2b59412bb664 187 */
mbed_official 392:2b59412bb664 188 typedef struct
mbed_official 392:2b59412bb664 189 {
mbed_official 392:2b59412bb664 190 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 392:2b59412bb664 191 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 392:2b59412bb664 192 }CAN_FilterRegister_TypeDef;
mbed_official 392:2b59412bb664 193
mbed_official 392:2b59412bb664 194 /**
mbed_official 392:2b59412bb664 195 * @brief Controller Area Network
mbed_official 392:2b59412bb664 196 */
mbed_official 392:2b59412bb664 197 typedef struct
mbed_official 392:2b59412bb664 198 {
mbed_official 392:2b59412bb664 199 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 200 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 201 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 202 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 203 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 204 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 205 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 206 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 207 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 392:2b59412bb664 208 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 392:2b59412bb664 209 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 392:2b59412bb664 210 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 392:2b59412bb664 211 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 392:2b59412bb664 212 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 392:2b59412bb664 213 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 392:2b59412bb664 214 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 392:2b59412bb664 215 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 392:2b59412bb664 216 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 392:2b59412bb664 217 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 392:2b59412bb664 218 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 392:2b59412bb664 219 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 392:2b59412bb664 220 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 392:2b59412bb664 221 }CAN_TypeDef;
mbed_official 392:2b59412bb664 222
mbed_official 392:2b59412bb664 223 /**
mbed_official 392:2b59412bb664 224 * @brief HDMI-CEC
mbed_official 392:2b59412bb664 225 */
mbed_official 392:2b59412bb664 226
mbed_official 392:2b59412bb664 227 typedef struct
mbed_official 392:2b59412bb664 228 {
mbed_official 392:2b59412bb664 229 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 392:2b59412bb664 230 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 392:2b59412bb664 231 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 392:2b59412bb664 232 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 392:2b59412bb664 233 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 392:2b59412bb664 234 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 392:2b59412bb664 235 }CEC_TypeDef;
mbed_official 392:2b59412bb664 236
mbed_official 392:2b59412bb664 237 /**
mbed_official 392:2b59412bb664 238 * @brief Comparator
mbed_official 392:2b59412bb664 239 */
mbed_official 392:2b59412bb664 240
mbed_official 392:2b59412bb664 241 typedef struct
mbed_official 392:2b59412bb664 242 {
mbed_official 392:2b59412bb664 243 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 244 }COMP1_2_TypeDef;
mbed_official 392:2b59412bb664 245
mbed_official 392:2b59412bb664 246 typedef struct
mbed_official 392:2b59412bb664 247 {
mbed_official 392:2b59412bb664 248 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 249 }COMP_TypeDef;
mbed_official 392:2b59412bb664 250
mbed_official 392:2b59412bb664 251 /**
mbed_official 392:2b59412bb664 252 * @brief CRC calculation unit
mbed_official 392:2b59412bb664 253 */
mbed_official 392:2b59412bb664 254
mbed_official 392:2b59412bb664 255 typedef struct
mbed_official 392:2b59412bb664 256 {
mbed_official 392:2b59412bb664 257 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 258 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 259 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 392:2b59412bb664 260 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 392:2b59412bb664 261 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 262 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 392:2b59412bb664 263 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 264 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 265 }CRC_TypeDef;
mbed_official 392:2b59412bb664 266
mbed_official 392:2b59412bb664 267 /**
mbed_official 392:2b59412bb664 268 * @brief Clock Recovery System
mbed_official 392:2b59412bb664 269 */
mbed_official 392:2b59412bb664 270 typedef struct
mbed_official 392:2b59412bb664 271 {
mbed_official 392:2b59412bb664 272 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 273 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 274 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 275 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 276 }CRS_TypeDef;
mbed_official 392:2b59412bb664 277
mbed_official 392:2b59412bb664 278 /**
mbed_official 392:2b59412bb664 279 * @brief Digital to Analog Converter
mbed_official 392:2b59412bb664 280 */
mbed_official 392:2b59412bb664 281
mbed_official 392:2b59412bb664 282 typedef struct
mbed_official 392:2b59412bb664 283 {
mbed_official 392:2b59412bb664 284 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 285 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 286 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 287 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 288 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 289 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 290 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 291 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 292 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 293 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 392:2b59412bb664 294 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 295 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 392:2b59412bb664 296 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 392:2b59412bb664 297 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 392:2b59412bb664 298 }DAC_TypeDef;
mbed_official 392:2b59412bb664 299
mbed_official 392:2b59412bb664 300 /**
mbed_official 392:2b59412bb664 301 * @brief Debug MCU
mbed_official 392:2b59412bb664 302 */
mbed_official 392:2b59412bb664 303
mbed_official 392:2b59412bb664 304 typedef struct
mbed_official 392:2b59412bb664 305 {
mbed_official 392:2b59412bb664 306 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 392:2b59412bb664 307 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 308 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 309 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 310 }DBGMCU_TypeDef;
mbed_official 392:2b59412bb664 311
mbed_official 392:2b59412bb664 312 /**
mbed_official 392:2b59412bb664 313 * @brief DMA Controller
mbed_official 392:2b59412bb664 314 */
mbed_official 392:2b59412bb664 315
mbed_official 392:2b59412bb664 316 typedef struct
mbed_official 392:2b59412bb664 317 {
mbed_official 392:2b59412bb664 318 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 392:2b59412bb664 319 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 392:2b59412bb664 320 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 392:2b59412bb664 321 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 392:2b59412bb664 322 }DMA_Channel_TypeDef;
mbed_official 392:2b59412bb664 323
mbed_official 392:2b59412bb664 324 typedef struct
mbed_official 392:2b59412bb664 325 {
mbed_official 392:2b59412bb664 326 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 327 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 328 }DMA_TypeDef;
mbed_official 392:2b59412bb664 329
mbed_official 392:2b59412bb664 330 /**
mbed_official 392:2b59412bb664 331 * @brief External Interrupt/Event Controller
mbed_official 392:2b59412bb664 332 */
mbed_official 392:2b59412bb664 333
mbed_official 392:2b59412bb664 334 typedef struct
mbed_official 392:2b59412bb664 335 {
mbed_official 392:2b59412bb664 336 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 337 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 338 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 392:2b59412bb664 339 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 340 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 341 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 342 }EXTI_TypeDef;
mbed_official 392:2b59412bb664 343
mbed_official 392:2b59412bb664 344 /**
mbed_official 392:2b59412bb664 345 * @brief FLASH Registers
mbed_official 392:2b59412bb664 346 */
mbed_official 392:2b59412bb664 347 typedef struct
mbed_official 392:2b59412bb664 348 {
mbed_official 392:2b59412bb664 349 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 350 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 351 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 352 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 353 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 354 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 355 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 392:2b59412bb664 356 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 357 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 358 }FLASH_TypeDef;
mbed_official 392:2b59412bb664 359
mbed_official 392:2b59412bb664 360
mbed_official 392:2b59412bb664 361 /**
mbed_official 392:2b59412bb664 362 * @brief Option Bytes Registers
mbed_official 392:2b59412bb664 363 */
mbed_official 392:2b59412bb664 364 typedef struct
mbed_official 392:2b59412bb664 365 {
mbed_official 392:2b59412bb664 366 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 392:2b59412bb664 367 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
mbed_official 392:2b59412bb664 368 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
mbed_official 392:2b59412bb664 369 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
mbed_official 392:2b59412bb664 370 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 392:2b59412bb664 371 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
mbed_official 392:2b59412bb664 372 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
mbed_official 392:2b59412bb664 373 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
mbed_official 392:2b59412bb664 374 }OB_TypeDef;
mbed_official 392:2b59412bb664 375
mbed_official 392:2b59412bb664 376 /**
mbed_official 392:2b59412bb664 377 * @brief General Purpose I/O
mbed_official 392:2b59412bb664 378 */
mbed_official 392:2b59412bb664 379
mbed_official 392:2b59412bb664 380 typedef struct
mbed_official 392:2b59412bb664 381 {
mbed_official 392:2b59412bb664 382 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 383 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 384 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 385 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 386 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 387 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 388 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
mbed_official 392:2b59412bb664 389 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 390 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
mbed_official 392:2b59412bb664 391 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 392 }GPIO_TypeDef;
mbed_official 392:2b59412bb664 393
mbed_official 392:2b59412bb664 394 /**
mbed_official 392:2b59412bb664 395 * @brief SysTem Configuration
mbed_official 392:2b59412bb664 396 */
mbed_official 392:2b59412bb664 397
mbed_official 392:2b59412bb664 398 typedef struct
mbed_official 392:2b59412bb664 399 {
mbed_official 392:2b59412bb664 400 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 392:2b59412bb664 401 uint32_t RESERVED; /*!< Reserved, 0x04 */
mbed_official 392:2b59412bb664 402 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
mbed_official 392:2b59412bb664 403 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 392:2b59412bb664 404 }SYSCFG_TypeDef;
mbed_official 392:2b59412bb664 405
mbed_official 392:2b59412bb664 406 /**
mbed_official 392:2b59412bb664 407 * @brief Inter-integrated Circuit Interface
mbed_official 392:2b59412bb664 408 */
mbed_official 392:2b59412bb664 409
mbed_official 392:2b59412bb664 410 typedef struct
mbed_official 392:2b59412bb664 411 {
mbed_official 392:2b59412bb664 412 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 392:2b59412bb664 413 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 392:2b59412bb664 414 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 415 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 416 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 417 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 418 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 419 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 420 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 421 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 392:2b59412bb664 422 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 423 }I2C_TypeDef;
mbed_official 392:2b59412bb664 424
mbed_official 392:2b59412bb664 425 /**
mbed_official 392:2b59412bb664 426 * @brief Independent WATCHDOG
mbed_official 392:2b59412bb664 427 */
mbed_official 392:2b59412bb664 428
mbed_official 392:2b59412bb664 429 typedef struct
mbed_official 392:2b59412bb664 430 {
mbed_official 392:2b59412bb664 431 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 432 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 433 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 434 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 435 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 436 }IWDG_TypeDef;
mbed_official 392:2b59412bb664 437
mbed_official 392:2b59412bb664 438 /**
mbed_official 392:2b59412bb664 439 * @brief Power Control
mbed_official 392:2b59412bb664 440 */
mbed_official 392:2b59412bb664 441
mbed_official 392:2b59412bb664 442 typedef struct
mbed_official 392:2b59412bb664 443 {
mbed_official 392:2b59412bb664 444 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 445 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 446 }PWR_TypeDef;
mbed_official 392:2b59412bb664 447
mbed_official 392:2b59412bb664 448 /**
mbed_official 392:2b59412bb664 449 * @brief Reset and Clock Control
mbed_official 392:2b59412bb664 450 */
mbed_official 630:825f75ca301e 451
mbed_official 392:2b59412bb664 452 typedef struct
mbed_official 392:2b59412bb664 453 {
mbed_official 392:2b59412bb664 454 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 455 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 456 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 457 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 458 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 459 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 460 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 461 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 462 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 463 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 392:2b59412bb664 464 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 465 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 392:2b59412bb664 466 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 392:2b59412bb664 467 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
mbed_official 392:2b59412bb664 468 }RCC_TypeDef;
mbed_official 392:2b59412bb664 469
mbed_official 392:2b59412bb664 470 /**
mbed_official 392:2b59412bb664 471 * @brief Real-Time Clock
mbed_official 392:2b59412bb664 472 */
mbed_official 392:2b59412bb664 473 typedef struct
mbed_official 392:2b59412bb664 474 {
mbed_official 392:2b59412bb664 475 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 476 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 477 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 478 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 479 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 480 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 481 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
mbed_official 392:2b59412bb664 482 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 483 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
mbed_official 392:2b59412bb664 484 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 392:2b59412bb664 485 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 486 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 392:2b59412bb664 487 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 392:2b59412bb664 488 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 392:2b59412bb664 489 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 392:2b59412bb664 490 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 392:2b59412bb664 491 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 392:2b59412bb664 492 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 392:2b59412bb664 493 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
mbed_official 392:2b59412bb664 494 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
mbed_official 392:2b59412bb664 495 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 392:2b59412bb664 496 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 392:2b59412bb664 497 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 392:2b59412bb664 498 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 392:2b59412bb664 499 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 392:2b59412bb664 500 }RTC_TypeDef;
mbed_official 392:2b59412bb664 501
mbed_official 392:2b59412bb664 502 /**
mbed_official 392:2b59412bb664 503 * @brief Serial Peripheral Interface
mbed_official 392:2b59412bb664 504 */
mbed_official 392:2b59412bb664 505
mbed_official 392:2b59412bb664 506 typedef struct
mbed_official 392:2b59412bb664 507 {
mbed_official 441:d2c15dda23c1 508 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 509 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 510 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 511 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 512 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 513 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 514 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 515 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 516 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 517 }SPI_TypeDef;
mbed_official 392:2b59412bb664 518
mbed_official 392:2b59412bb664 519 /**
mbed_official 392:2b59412bb664 520 * @brief TIM
mbed_official 392:2b59412bb664 521 */
mbed_official 392:2b59412bb664 522 typedef struct
mbed_official 392:2b59412bb664 523 {
mbed_official 392:2b59412bb664 524 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 392:2b59412bb664 525 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 392:2b59412bb664 526 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 527 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 528 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 529 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 530 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 392:2b59412bb664 531 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 392:2b59412bb664 532 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 533 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 392:2b59412bb664 534 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 535 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 392:2b59412bb664 536 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 392:2b59412bb664 537 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 392:2b59412bb664 538 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 392:2b59412bb664 539 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 392:2b59412bb664 540 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 392:2b59412bb664 541 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 392:2b59412bb664 542 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 392:2b59412bb664 543 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 392:2b59412bb664 544 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 392:2b59412bb664 545 }TIM_TypeDef;
mbed_official 392:2b59412bb664 546
mbed_official 392:2b59412bb664 547 /**
mbed_official 392:2b59412bb664 548 * @brief Touch Sensing Controller (TSC)
mbed_official 392:2b59412bb664 549 */
mbed_official 392:2b59412bb664 550 typedef struct
mbed_official 392:2b59412bb664 551 {
mbed_official 392:2b59412bb664 552 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 553 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 554 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 555 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 556 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 557 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 392:2b59412bb664 558 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 559 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 392:2b59412bb664 560 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 561 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 392:2b59412bb664 562 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 563 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 392:2b59412bb664 564 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 392:2b59412bb664 565 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 392:2b59412bb664 566 }TSC_TypeDef;
mbed_official 392:2b59412bb664 567
mbed_official 392:2b59412bb664 568 /**
mbed_official 392:2b59412bb664 569 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 392:2b59412bb664 570 */
mbed_official 392:2b59412bb664 571
mbed_official 392:2b59412bb664 572 typedef struct
mbed_official 392:2b59412bb664 573 {
mbed_official 392:2b59412bb664 574 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 392:2b59412bb664 575 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 392:2b59412bb664 576 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 392:2b59412bb664 577 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 578 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 579 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 580 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 581 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 582 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 392:2b59412bb664 583 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 392:2b59412bb664 584 uint16_t RESERVED1; /*!< Reserved, 0x26 */
mbed_official 392:2b59412bb664 585 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 392:2b59412bb664 586 uint16_t RESERVED2; /*!< Reserved, 0x2A */
mbed_official 392:2b59412bb664 587 }USART_TypeDef;
mbed_official 392:2b59412bb664 588
mbed_official 392:2b59412bb664 589 /**
mbed_official 392:2b59412bb664 590 * @brief Universal Serial Bus Full Speed Device
mbed_official 392:2b59412bb664 591 */
mbed_official 392:2b59412bb664 592
mbed_official 392:2b59412bb664 593 typedef struct
mbed_official 392:2b59412bb664 594 {
mbed_official 392:2b59412bb664 595 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 596 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 392:2b59412bb664 597 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 598 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 392:2b59412bb664 599 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 600 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 392:2b59412bb664 601 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 392:2b59412bb664 602 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 392:2b59412bb664 603 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 392:2b59412bb664 604 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 392:2b59412bb664 605 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 392:2b59412bb664 606 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 392:2b59412bb664 607 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 392:2b59412bb664 608 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 392:2b59412bb664 609 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 392:2b59412bb664 610 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 392:2b59412bb664 611 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 392:2b59412bb664 612 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 392:2b59412bb664 613 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 392:2b59412bb664 614 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 392:2b59412bb664 615 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 392:2b59412bb664 616 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 392:2b59412bb664 617 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 392:2b59412bb664 618 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 392:2b59412bb664 619 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 392:2b59412bb664 620 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 392:2b59412bb664 621 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
mbed_official 392:2b59412bb664 622 __IO uint16_t RESERVEDD; /*!< Reserved */
mbed_official 392:2b59412bb664 623 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
mbed_official 392:2b59412bb664 624 __IO uint16_t RESERVEDE; /*!< Reserved */
mbed_official 392:2b59412bb664 625 }USB_TypeDef;
mbed_official 392:2b59412bb664 626
mbed_official 392:2b59412bb664 627 /**
mbed_official 392:2b59412bb664 628 * @brief Window WATCHDOG
mbed_official 392:2b59412bb664 629 */
mbed_official 392:2b59412bb664 630 typedef struct
mbed_official 392:2b59412bb664 631 {
mbed_official 392:2b59412bb664 632 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 392:2b59412bb664 633 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 392:2b59412bb664 634 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 392:2b59412bb664 635 }WWDG_TypeDef;
mbed_official 392:2b59412bb664 636
mbed_official 392:2b59412bb664 637 /**
mbed_official 392:2b59412bb664 638 * @}
mbed_official 392:2b59412bb664 639 */
mbed_official 392:2b59412bb664 640
mbed_official 392:2b59412bb664 641 /** @addtogroup Peripheral_memory_map
mbed_official 392:2b59412bb664 642 * @{
mbed_official 392:2b59412bb664 643 */
mbed_official 392:2b59412bb664 644
mbed_official 392:2b59412bb664 645 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 630:825f75ca301e 646 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
mbed_official 392:2b59412bb664 647 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 392:2b59412bb664 648 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 392:2b59412bb664 649
mbed_official 392:2b59412bb664 650 /*!< Peripheral memory map */
mbed_official 392:2b59412bb664 651 #define APBPERIPH_BASE PERIPH_BASE
mbed_official 392:2b59412bb664 652 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 392:2b59412bb664 653 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 392:2b59412bb664 654
mbed_official 392:2b59412bb664 655 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official 392:2b59412bb664 656 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official 392:2b59412bb664 657 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
mbed_official 392:2b59412bb664 658 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
mbed_official 392:2b59412bb664 659 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official 392:2b59412bb664 660 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official 392:2b59412bb664 661 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official 392:2b59412bb664 662 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official 392:2b59412bb664 663 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official 392:2b59412bb664 664 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official 392:2b59412bb664 665 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
mbed_official 392:2b59412bb664 666 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
mbed_official 392:2b59412bb664 667 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official 392:2b59412bb664 668 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
mbed_official 392:2b59412bb664 669 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
mbed_official 392:2b59412bb664 670 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
mbed_official 392:2b59412bb664 671 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
mbed_official 392:2b59412bb664 672 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
mbed_official 392:2b59412bb664 673 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official 392:2b59412bb664 674 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
mbed_official 630:825f75ca301e 675
mbed_official 392:2b59412bb664 676 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
mbed_official 392:2b59412bb664 677
mbed_official 392:2b59412bb664 678 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official 392:2b59412bb664 679 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official 392:2b59412bb664 680 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official 392:2b59412bb664 681 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official 392:2b59412bb664 682 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official 392:2b59412bb664 683 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official 392:2b59412bb664 684 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official 392:2b59412bb664 685 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official 392:2b59412bb664 686 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
mbed_official 392:2b59412bb664 687 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official 392:2b59412bb664 688 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official 392:2b59412bb664 689 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official 392:2b59412bb664 690
mbed_official 392:2b59412bb664 691 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 392:2b59412bb664 692 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 392:2b59412bb664 693 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 392:2b59412bb664 694 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 392:2b59412bb664 695 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 392:2b59412bb664 696 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 392:2b59412bb664 697 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official 392:2b59412bb664 698 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official 392:2b59412bb664 699
mbed_official 392:2b59412bb664 700 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 392:2b59412bb664 701 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
mbed_official 392:2b59412bb664 702 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
mbed_official 392:2b59412bb664 703 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 392:2b59412bb664 704 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
mbed_official 392:2b59412bb664 705
mbed_official 392:2b59412bb664 706 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 392:2b59412bb664 707 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 392:2b59412bb664 708 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 392:2b59412bb664 709 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 392:2b59412bb664 710 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
mbed_official 392:2b59412bb664 711 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 392:2b59412bb664 712
mbed_official 392:2b59412bb664 713 /**
mbed_official 392:2b59412bb664 714 * @}
mbed_official 392:2b59412bb664 715 */
mbed_official 392:2b59412bb664 716
mbed_official 392:2b59412bb664 717 /** @addtogroup Peripheral_declaration
mbed_official 392:2b59412bb664 718 * @{
mbed_official 392:2b59412bb664 719 */
mbed_official 392:2b59412bb664 720
mbed_official 392:2b59412bb664 721 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 392:2b59412bb664 722 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 392:2b59412bb664 723 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 392:2b59412bb664 724 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 392:2b59412bb664 725 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 392:2b59412bb664 726 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 392:2b59412bb664 727 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 392:2b59412bb664 728 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 392:2b59412bb664 729 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 392:2b59412bb664 730 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 392:2b59412bb664 731 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 392:2b59412bb664 732 #define USART4 ((USART_TypeDef *) USART4_BASE)
mbed_official 392:2b59412bb664 733 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 392:2b59412bb664 734 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 392:2b59412bb664 735 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 392:2b59412bb664 736 #define CRS ((CRS_TypeDef *) CRS_BASE)
mbed_official 392:2b59412bb664 737 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 392:2b59412bb664 738 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 392:2b59412bb664 739 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 392:2b59412bb664 740 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 392:2b59412bb664 741 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
mbed_official 392:2b59412bb664 742 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
mbed_official 392:2b59412bb664 743 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
mbed_official 392:2b59412bb664 744 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 392:2b59412bb664 745 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 392:2b59412bb664 746 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 392:2b59412bb664 747 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 392:2b59412bb664 748 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 392:2b59412bb664 749 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 392:2b59412bb664 750 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 392:2b59412bb664 751 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 392:2b59412bb664 752 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 392:2b59412bb664 753 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 392:2b59412bb664 754 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 392:2b59412bb664 755 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 392:2b59412bb664 756 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 392:2b59412bb664 757 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 392:2b59412bb664 758 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 392:2b59412bb664 759 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 392:2b59412bb664 760 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 392:2b59412bb664 761 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 392:2b59412bb664 762 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 392:2b59412bb664 763 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 392:2b59412bb664 764 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 392:2b59412bb664 765 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 392:2b59412bb664 766 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 392:2b59412bb664 767 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 392:2b59412bb664 768 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 392:2b59412bb664 769 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 392:2b59412bb664 770 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 392:2b59412bb664 771 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 392:2b59412bb664 772 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 392:2b59412bb664 773 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 392:2b59412bb664 774 /**
mbed_official 392:2b59412bb664 775 * @}
mbed_official 392:2b59412bb664 776 */
mbed_official 392:2b59412bb664 777
mbed_official 392:2b59412bb664 778 /** @addtogroup Exported_constants
mbed_official 392:2b59412bb664 779 * @{
mbed_official 392:2b59412bb664 780 */
mbed_official 392:2b59412bb664 781
mbed_official 392:2b59412bb664 782 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 392:2b59412bb664 783 * @{
mbed_official 392:2b59412bb664 784 */
mbed_official 392:2b59412bb664 785
mbed_official 392:2b59412bb664 786 /******************************************************************************/
mbed_official 392:2b59412bb664 787 /* Peripheral Registers Bits Definition */
mbed_official 392:2b59412bb664 788 /******************************************************************************/
mbed_official 392:2b59412bb664 789 /******************************************************************************/
mbed_official 392:2b59412bb664 790 /* */
mbed_official 392:2b59412bb664 791 /* Analog to Digital Converter (ADC) */
mbed_official 392:2b59412bb664 792 /* */
mbed_official 392:2b59412bb664 793 /******************************************************************************/
mbed_official 392:2b59412bb664 794 /******************** Bits definition for ADC_ISR register ******************/
mbed_official 392:2b59412bb664 795 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
mbed_official 392:2b59412bb664 796 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
mbed_official 392:2b59412bb664 797 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
mbed_official 392:2b59412bb664 798 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
mbed_official 392:2b59412bb664 799 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
mbed_official 392:2b59412bb664 800 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
mbed_official 392:2b59412bb664 801
mbed_official 392:2b59412bb664 802 /* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 803 #define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official 392:2b59412bb664 804
mbed_official 392:2b59412bb664 805 /******************** Bits definition for ADC_IER register ******************/
mbed_official 392:2b59412bb664 806 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
mbed_official 392:2b59412bb664 807 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
mbed_official 392:2b59412bb664 808 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
mbed_official 392:2b59412bb664 809 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
mbed_official 392:2b59412bb664 810 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
mbed_official 392:2b59412bb664 811 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
mbed_official 392:2b59412bb664 812
mbed_official 392:2b59412bb664 813 /* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 814 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official 392:2b59412bb664 815
mbed_official 392:2b59412bb664 816 /******************** Bits definition for ADC_CR register *******************/
mbed_official 392:2b59412bb664 817 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
mbed_official 392:2b59412bb664 818 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
mbed_official 392:2b59412bb664 819 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
mbed_official 392:2b59412bb664 820 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
mbed_official 392:2b59412bb664 821 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
mbed_official 392:2b59412bb664 822
mbed_official 392:2b59412bb664 823 /******************* Bits definition for ADC_CFGR1 register *****************/
mbed_official 392:2b59412bb664 824 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 392:2b59412bb664 825 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 826 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 827 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 828 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 829 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 392:2b59412bb664 830 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 392:2b59412bb664 831 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
mbed_official 392:2b59412bb664 832 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
mbed_official 392:2b59412bb664 833 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
mbed_official 392:2b59412bb664 834 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
mbed_official 392:2b59412bb664 835 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
mbed_official 392:2b59412bb664 836 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
mbed_official 392:2b59412bb664 837 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 392:2b59412bb664 838 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 392:2b59412bb664 839 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 392:2b59412bb664 840 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 392:2b59412bb664 841 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 392:2b59412bb664 842 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 392:2b59412bb664 843 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 392:2b59412bb664 844 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
mbed_official 392:2b59412bb664 845 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
mbed_official 392:2b59412bb664 846 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 392:2b59412bb664 847 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 392:2b59412bb664 848 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
mbed_official 392:2b59412bb664 849 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
mbed_official 392:2b59412bb664 850 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
mbed_official 392:2b59412bb664 851
mbed_official 392:2b59412bb664 852 /* Old WAIT bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 853 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official 392:2b59412bb664 854
mbed_official 392:2b59412bb664 855 /******************* Bits definition for ADC_CFGR2 register *****************/
mbed_official 392:2b59412bb664 856 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
mbed_official 392:2b59412bb664 857 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
mbed_official 392:2b59412bb664 858 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
mbed_official 392:2b59412bb664 859
mbed_official 392:2b59412bb664 860 /* Old bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 861 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
mbed_official 392:2b59412bb664 862 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
mbed_official 392:2b59412bb664 863
mbed_official 392:2b59412bb664 864 /****************** Bit definition for ADC_SMPR register ********************/
mbed_official 392:2b59412bb664 865 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 392:2b59412bb664 866 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 392:2b59412bb664 867 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 392:2b59412bb664 868 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 392:2b59412bb664 869
mbed_official 392:2b59412bb664 870 /* Old bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 871 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 392:2b59412bb664 872 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
mbed_official 392:2b59412bb664 873 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
mbed_official 392:2b59412bb664 874 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
mbed_official 392:2b59412bb664 875
mbed_official 392:2b59412bb664 876 /******************* Bit definition for ADC_TR register ********************/
mbed_official 392:2b59412bb664 877 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
mbed_official 392:2b59412bb664 878 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 392:2b59412bb664 879
mbed_official 392:2b59412bb664 880 /* Old bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 881 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
mbed_official 392:2b59412bb664 882 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
mbed_official 392:2b59412bb664 883
mbed_official 392:2b59412bb664 884 /****************** Bit definition for ADC_CHSELR register ******************/
mbed_official 392:2b59412bb664 885 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
mbed_official 392:2b59412bb664 886 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
mbed_official 392:2b59412bb664 887 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
mbed_official 392:2b59412bb664 888 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
mbed_official 392:2b59412bb664 889 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
mbed_official 392:2b59412bb664 890 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
mbed_official 392:2b59412bb664 891 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
mbed_official 392:2b59412bb664 892 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
mbed_official 392:2b59412bb664 893 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
mbed_official 392:2b59412bb664 894 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
mbed_official 392:2b59412bb664 895 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
mbed_official 392:2b59412bb664 896 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
mbed_official 392:2b59412bb664 897 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
mbed_official 392:2b59412bb664 898 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
mbed_official 392:2b59412bb664 899 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
mbed_official 392:2b59412bb664 900 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
mbed_official 392:2b59412bb664 901 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
mbed_official 392:2b59412bb664 902 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
mbed_official 392:2b59412bb664 903 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
mbed_official 392:2b59412bb664 904
mbed_official 392:2b59412bb664 905 /******************** Bit definition for ADC_DR register ********************/
mbed_official 392:2b59412bb664 906 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 392:2b59412bb664 907
mbed_official 392:2b59412bb664 908 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 392:2b59412bb664 909 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
mbed_official 392:2b59412bb664 910 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
mbed_official 392:2b59412bb664 911 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
mbed_official 392:2b59412bb664 912
mbed_official 392:2b59412bb664 913 /******************************************************************************/
mbed_official 392:2b59412bb664 914 /* */
mbed_official 392:2b59412bb664 915 /* Controller Area Network (CAN ) */
mbed_official 392:2b59412bb664 916 /* */
mbed_official 392:2b59412bb664 917 /******************************************************************************/
mbed_official 392:2b59412bb664 918 /*!<CAN control and status registers */
mbed_official 392:2b59412bb664 919 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 392:2b59412bb664 920 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 392:2b59412bb664 921 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 392:2b59412bb664 922 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 392:2b59412bb664 923 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 392:2b59412bb664 924 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 392:2b59412bb664 925 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 392:2b59412bb664 926 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 392:2b59412bb664 927 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 392:2b59412bb664 928 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 392:2b59412bb664 929
mbed_official 392:2b59412bb664 930 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 392:2b59412bb664 931 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
mbed_official 392:2b59412bb664 932 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
mbed_official 392:2b59412bb664 933 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
mbed_official 392:2b59412bb664 934 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
mbed_official 392:2b59412bb664 935 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
mbed_official 392:2b59412bb664 936 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
mbed_official 392:2b59412bb664 937 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
mbed_official 392:2b59412bb664 938 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
mbed_official 392:2b59412bb664 939 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
mbed_official 392:2b59412bb664 940
mbed_official 392:2b59412bb664 941 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 392:2b59412bb664 942 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 392:2b59412bb664 943 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 392:2b59412bb664 944 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 392:2b59412bb664 945 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 392:2b59412bb664 946 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 392:2b59412bb664 947 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 392:2b59412bb664 948 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 392:2b59412bb664 949 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 392:2b59412bb664 950 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 392:2b59412bb664 951 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 392:2b59412bb664 952 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 392:2b59412bb664 953 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 392:2b59412bb664 954 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 392:2b59412bb664 955 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 392:2b59412bb664 956 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 392:2b59412bb664 957 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 392:2b59412bb664 958
mbed_official 392:2b59412bb664 959 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 392:2b59412bb664 960 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 392:2b59412bb664 961 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 392:2b59412bb664 962 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 392:2b59412bb664 963
mbed_official 392:2b59412bb664 964 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 392:2b59412bb664 965 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 392:2b59412bb664 966 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 392:2b59412bb664 967 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 392:2b59412bb664 968
mbed_official 392:2b59412bb664 969 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 392:2b59412bb664 970 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
mbed_official 392:2b59412bb664 971 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
mbed_official 392:2b59412bb664 972 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
mbed_official 392:2b59412bb664 973 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
mbed_official 392:2b59412bb664 974
mbed_official 392:2b59412bb664 975 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 392:2b59412bb664 976 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
mbed_official 392:2b59412bb664 977 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
mbed_official 392:2b59412bb664 978 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
mbed_official 392:2b59412bb664 979 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
mbed_official 392:2b59412bb664 980
mbed_official 392:2b59412bb664 981 /******************** Bit definition for CAN_IER register *******************/
mbed_official 392:2b59412bb664 982 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 392:2b59412bb664 983 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 392:2b59412bb664 984 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 392:2b59412bb664 985 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 392:2b59412bb664 986 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 392:2b59412bb664 987 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 392:2b59412bb664 988 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 392:2b59412bb664 989 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 392:2b59412bb664 990 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 392:2b59412bb664 991 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 392:2b59412bb664 992 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 392:2b59412bb664 993 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 392:2b59412bb664 994 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 392:2b59412bb664 995 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 392:2b59412bb664 996
mbed_official 392:2b59412bb664 997 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 392:2b59412bb664 998 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 392:2b59412bb664 999 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 392:2b59412bb664 1000 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 392:2b59412bb664 1001
mbed_official 392:2b59412bb664 1002 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 392:2b59412bb664 1003 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 1004 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 1005 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 1006
mbed_official 392:2b59412bb664 1007 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 392:2b59412bb664 1008 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 392:2b59412bb664 1009
mbed_official 392:2b59412bb664 1010 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 392:2b59412bb664 1011 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 392:2b59412bb664 1012 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 392:2b59412bb664 1013 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
mbed_official 392:2b59412bb664 1014 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
mbed_official 392:2b59412bb664 1015 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
mbed_official 392:2b59412bb664 1016 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
mbed_official 392:2b59412bb664 1017 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 392:2b59412bb664 1018 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
mbed_official 392:2b59412bb664 1019 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
mbed_official 392:2b59412bb664 1020 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
mbed_official 392:2b59412bb664 1021 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 392:2b59412bb664 1022 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
mbed_official 392:2b59412bb664 1023 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
mbed_official 392:2b59412bb664 1024 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 392:2b59412bb664 1025 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 392:2b59412bb664 1026
mbed_official 392:2b59412bb664 1027 /*!<Mailbox registers */
mbed_official 392:2b59412bb664 1028 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 392:2b59412bb664 1029 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 392:2b59412bb664 1030 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 392:2b59412bb664 1031 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 392:2b59412bb664 1032 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 392:2b59412bb664 1033 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 392:2b59412bb664 1034
mbed_official 392:2b59412bb664 1035 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 392:2b59412bb664 1036 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 392:2b59412bb664 1037 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 392:2b59412bb664 1038 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 392:2b59412bb664 1039
mbed_official 392:2b59412bb664 1040 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 392:2b59412bb664 1041 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 392:2b59412bb664 1042 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 392:2b59412bb664 1043 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 392:2b59412bb664 1044 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 392:2b59412bb664 1045
mbed_official 392:2b59412bb664 1046 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 392:2b59412bb664 1047 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 392:2b59412bb664 1048 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 392:2b59412bb664 1049 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 392:2b59412bb664 1050 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 392:2b59412bb664 1051
mbed_official 392:2b59412bb664 1052 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 392:2b59412bb664 1053 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 392:2b59412bb664 1054 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 392:2b59412bb664 1055 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 392:2b59412bb664 1056 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 392:2b59412bb664 1057 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 392:2b59412bb664 1058
mbed_official 392:2b59412bb664 1059 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 392:2b59412bb664 1060 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 392:2b59412bb664 1061 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 392:2b59412bb664 1062 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 392:2b59412bb664 1063
mbed_official 392:2b59412bb664 1064 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 392:2b59412bb664 1065 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 392:2b59412bb664 1066 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 392:2b59412bb664 1067 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 392:2b59412bb664 1068 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 392:2b59412bb664 1069
mbed_official 392:2b59412bb664 1070 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 392:2b59412bb664 1071 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 392:2b59412bb664 1072 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 392:2b59412bb664 1073 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 392:2b59412bb664 1074 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 392:2b59412bb664 1075
mbed_official 392:2b59412bb664 1076 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 392:2b59412bb664 1077 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 392:2b59412bb664 1078 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 392:2b59412bb664 1079 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 392:2b59412bb664 1080 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 392:2b59412bb664 1081 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 392:2b59412bb664 1082
mbed_official 392:2b59412bb664 1083 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 392:2b59412bb664 1084 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 392:2b59412bb664 1085 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 392:2b59412bb664 1086 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 392:2b59412bb664 1087
mbed_official 392:2b59412bb664 1088 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 392:2b59412bb664 1089 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 392:2b59412bb664 1090 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 392:2b59412bb664 1091 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 392:2b59412bb664 1092 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 392:2b59412bb664 1093
mbed_official 392:2b59412bb664 1094 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 392:2b59412bb664 1095 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 392:2b59412bb664 1096 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 392:2b59412bb664 1097 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 392:2b59412bb664 1098 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 392:2b59412bb664 1099
mbed_official 392:2b59412bb664 1100 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 392:2b59412bb664 1101 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 392:2b59412bb664 1102 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 392:2b59412bb664 1103 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 392:2b59412bb664 1104 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 392:2b59412bb664 1105
mbed_official 392:2b59412bb664 1106 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 392:2b59412bb664 1107 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 392:2b59412bb664 1108 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 392:2b59412bb664 1109 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 392:2b59412bb664 1110
mbed_official 392:2b59412bb664 1111 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 392:2b59412bb664 1112 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 392:2b59412bb664 1113 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 392:2b59412bb664 1114 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 392:2b59412bb664 1115 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 392:2b59412bb664 1116
mbed_official 392:2b59412bb664 1117 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 392:2b59412bb664 1118 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 392:2b59412bb664 1119 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 392:2b59412bb664 1120 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 392:2b59412bb664 1121 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 392:2b59412bb664 1122
mbed_official 392:2b59412bb664 1123 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 392:2b59412bb664 1124 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 392:2b59412bb664 1125 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 392:2b59412bb664 1126 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 392:2b59412bb664 1127 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 392:2b59412bb664 1128
mbed_official 392:2b59412bb664 1129 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 392:2b59412bb664 1130 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 392:2b59412bb664 1131 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 392:2b59412bb664 1132 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 392:2b59412bb664 1133
mbed_official 392:2b59412bb664 1134 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 392:2b59412bb664 1135 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 392:2b59412bb664 1136 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 392:2b59412bb664 1137 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 392:2b59412bb664 1138 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 392:2b59412bb664 1139
mbed_official 392:2b59412bb664 1140 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 392:2b59412bb664 1141 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 392:2b59412bb664 1142 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 392:2b59412bb664 1143 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 392:2b59412bb664 1144 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 392:2b59412bb664 1145
mbed_official 392:2b59412bb664 1146 /*!<CAN filter registers */
mbed_official 392:2b59412bb664 1147 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 392:2b59412bb664 1148 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
mbed_official 630:825f75ca301e 1149 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
mbed_official 392:2b59412bb664 1150
mbed_official 392:2b59412bb664 1151 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 630:825f75ca301e 1152 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
mbed_official 392:2b59412bb664 1153 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 392:2b59412bb664 1154 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 392:2b59412bb664 1155 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 392:2b59412bb664 1156 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 392:2b59412bb664 1157 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 392:2b59412bb664 1158 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 392:2b59412bb664 1159 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 392:2b59412bb664 1160 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 392:2b59412bb664 1161 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 392:2b59412bb664 1162 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 392:2b59412bb664 1163 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 392:2b59412bb664 1164 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 392:2b59412bb664 1165 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 392:2b59412bb664 1166 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 630:825f75ca301e 1167 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
mbed_official 630:825f75ca301e 1168 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
mbed_official 630:825f75ca301e 1169 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
mbed_official 630:825f75ca301e 1170 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
mbed_official 630:825f75ca301e 1171 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
mbed_official 630:825f75ca301e 1172 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
mbed_official 630:825f75ca301e 1173 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
mbed_official 630:825f75ca301e 1174 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
mbed_official 630:825f75ca301e 1175 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
mbed_official 630:825f75ca301e 1176 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
mbed_official 630:825f75ca301e 1177 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
mbed_official 630:825f75ca301e 1178 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
mbed_official 630:825f75ca301e 1179 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
mbed_official 630:825f75ca301e 1180 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
mbed_official 392:2b59412bb664 1181
mbed_official 392:2b59412bb664 1182 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 630:825f75ca301e 1183 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
mbed_official 392:2b59412bb664 1184 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 392:2b59412bb664 1185 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 392:2b59412bb664 1186 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 392:2b59412bb664 1187 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 392:2b59412bb664 1188 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 392:2b59412bb664 1189 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 392:2b59412bb664 1190 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 392:2b59412bb664 1191 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 392:2b59412bb664 1192 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 392:2b59412bb664 1193 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 392:2b59412bb664 1194 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 392:2b59412bb664 1195 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 392:2b59412bb664 1196 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 392:2b59412bb664 1197 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 630:825f75ca301e 1198 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
mbed_official 630:825f75ca301e 1199 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
mbed_official 630:825f75ca301e 1200 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
mbed_official 630:825f75ca301e 1201 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
mbed_official 630:825f75ca301e 1202 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
mbed_official 630:825f75ca301e 1203 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
mbed_official 630:825f75ca301e 1204 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
mbed_official 630:825f75ca301e 1205 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
mbed_official 630:825f75ca301e 1206 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
mbed_official 630:825f75ca301e 1207 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
mbed_official 630:825f75ca301e 1208 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
mbed_official 630:825f75ca301e 1209 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
mbed_official 630:825f75ca301e 1210 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
mbed_official 630:825f75ca301e 1211 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
mbed_official 392:2b59412bb664 1212
mbed_official 392:2b59412bb664 1213 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 630:825f75ca301e 1214 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
mbed_official 630:825f75ca301e 1215 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
mbed_official 630:825f75ca301e 1216 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
mbed_official 630:825f75ca301e 1217 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
mbed_official 630:825f75ca301e 1218 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
mbed_official 630:825f75ca301e 1219 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
mbed_official 630:825f75ca301e 1220 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
mbed_official 630:825f75ca301e 1221 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
mbed_official 630:825f75ca301e 1222 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
mbed_official 630:825f75ca301e 1223 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
mbed_official 630:825f75ca301e 1224 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
mbed_official 630:825f75ca301e 1225 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
mbed_official 630:825f75ca301e 1226 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
mbed_official 630:825f75ca301e 1227 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
mbed_official 630:825f75ca301e 1228 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
mbed_official 630:825f75ca301e 1229 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
mbed_official 630:825f75ca301e 1230 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
mbed_official 630:825f75ca301e 1231 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
mbed_official 630:825f75ca301e 1232 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
mbed_official 630:825f75ca301e 1233 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
mbed_official 630:825f75ca301e 1234 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
mbed_official 630:825f75ca301e 1235 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
mbed_official 630:825f75ca301e 1236 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
mbed_official 630:825f75ca301e 1237 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
mbed_official 630:825f75ca301e 1238 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
mbed_official 630:825f75ca301e 1239 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
mbed_official 630:825f75ca301e 1240 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
mbed_official 630:825f75ca301e 1241 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
mbed_official 630:825f75ca301e 1242 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
mbed_official 392:2b59412bb664 1243
mbed_official 392:2b59412bb664 1244 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 630:825f75ca301e 1245 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
mbed_official 630:825f75ca301e 1246 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
mbed_official 630:825f75ca301e 1247 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
mbed_official 630:825f75ca301e 1248 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
mbed_official 630:825f75ca301e 1249 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
mbed_official 630:825f75ca301e 1250 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
mbed_official 630:825f75ca301e 1251 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
mbed_official 630:825f75ca301e 1252 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
mbed_official 630:825f75ca301e 1253 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
mbed_official 630:825f75ca301e 1254 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
mbed_official 630:825f75ca301e 1255 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
mbed_official 630:825f75ca301e 1256 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
mbed_official 630:825f75ca301e 1257 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
mbed_official 630:825f75ca301e 1258 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
mbed_official 630:825f75ca301e 1259 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
mbed_official 630:825f75ca301e 1260 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
mbed_official 630:825f75ca301e 1261 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
mbed_official 630:825f75ca301e 1262 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
mbed_official 630:825f75ca301e 1263 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
mbed_official 630:825f75ca301e 1264 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
mbed_official 630:825f75ca301e 1265 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
mbed_official 630:825f75ca301e 1266 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
mbed_official 630:825f75ca301e 1267 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
mbed_official 630:825f75ca301e 1268 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
mbed_official 630:825f75ca301e 1269 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
mbed_official 630:825f75ca301e 1270 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
mbed_official 630:825f75ca301e 1271 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
mbed_official 630:825f75ca301e 1272 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
mbed_official 630:825f75ca301e 1273 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
mbed_official 392:2b59412bb664 1274
mbed_official 392:2b59412bb664 1275 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 392:2b59412bb664 1276 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1277 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1278 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1279 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1280 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1281 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1282 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1283 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1284 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1285 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1286 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1287 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1288 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1289 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1290 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1291 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1292 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1293 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1294 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1295 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1296 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1297 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1298 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1299 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1300 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1301 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1302 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1303 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1304 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1305 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1306 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1307 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1308
mbed_official 392:2b59412bb664 1309 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 392:2b59412bb664 1310 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1311 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1312 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1313 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1314 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1315 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1316 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1317 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1318 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1319 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1320 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1321 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1322 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1323 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1324 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1325 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1326 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1327 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1328 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1329 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1330 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1331 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1332 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1333 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1334 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1335 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1336 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1337 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1338 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1339 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1340 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1341 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1342
mbed_official 392:2b59412bb664 1343 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 392:2b59412bb664 1344 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1345 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1346 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1347 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1348 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1349 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1350 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1351 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1352 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1353 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1354 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1355 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1356 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1357 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1358 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1359 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1360 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1361 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1362 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1363 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1364 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1365 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1366 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1367 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1368 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1369 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1370 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1371 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1372 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1373 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1374 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1375 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1376
mbed_official 392:2b59412bb664 1377 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 392:2b59412bb664 1378 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1379 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1380 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1381 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1382 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1383 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1384 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1385 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1386 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1387 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1388 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1389 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1390 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1391 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1392 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1393 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1394 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1395 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1396 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1397 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1398 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1399 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1400 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1401 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1402 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1403 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1404 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1405 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1406 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1407 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1408 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1409 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1410
mbed_official 392:2b59412bb664 1411 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 392:2b59412bb664 1412 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1413 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1414 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1415 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1416 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1417 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1418 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1419 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1420 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1421 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1422 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1423 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1424 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1425 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1426 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1427 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1428 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1429 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1430 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1431 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1432 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1433 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1434 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1435 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1436 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1437 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1438 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1439 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1440 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1441 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1442 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1443 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1444
mbed_official 392:2b59412bb664 1445 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 392:2b59412bb664 1446 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1447 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1448 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1449 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1450 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1451 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1452 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1453 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1454 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1455 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1456 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1457 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1458 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1459 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1460 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1461 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1462 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1463 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1464 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1465 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1466 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1467 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1468 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1469 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1470 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1471 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1472 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1473 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1474 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1475 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1476 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1477 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1478
mbed_official 392:2b59412bb664 1479 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 392:2b59412bb664 1480 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1481 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1482 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1483 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1484 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1485 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1486 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1487 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1488 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1489 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1490 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1491 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1492 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1493 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1494 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1495 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1496 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1497 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1498 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1499 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1500 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1501 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1502 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1503 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1504 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1505 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1506 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1507 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1508 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1509 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1510 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1511 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1512
mbed_official 392:2b59412bb664 1513 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 392:2b59412bb664 1514 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1515 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1516 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1517 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1518 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1519 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1520 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1521 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1522 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1523 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1524 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1525 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1526 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1527 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1528 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1529 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1530 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1531 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1532 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1533 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1534 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1535 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1536 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1537 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1538 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1539 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1540 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1541 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1542 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1543 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1544 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1545 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1546
mbed_official 392:2b59412bb664 1547 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 392:2b59412bb664 1548 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1549 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1550 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1551 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1552 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1553 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1554 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1555 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1556 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1557 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1558 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1559 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1560 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1561 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1562 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1563 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1564 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1565 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1566 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1567 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1568 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1569 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1570 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1571 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1572 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1573 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1574 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1575 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1576 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1577 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1578 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1579 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1580
mbed_official 392:2b59412bb664 1581 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 392:2b59412bb664 1582 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1583 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1584 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1585 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1586 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1587 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1588 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1589 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1590 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1591 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1592 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1593 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1594 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1595 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1596 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1597 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1598 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1599 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1600 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1601 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1602 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1603 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1604 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1605 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1606 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1607 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1608 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1609 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1610 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1611 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1612 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1613 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1614
mbed_official 392:2b59412bb664 1615 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 392:2b59412bb664 1616 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1617 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1618 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1619 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1620 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1621 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1622 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1623 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1624 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1625 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1626 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1627 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1628 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1629 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1630 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1631 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1632 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1633 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1634 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1635 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1636 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1637 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1638 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1639 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1640 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1641 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1642 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1643 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1644 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1645 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1646 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1647 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1648
mbed_official 392:2b59412bb664 1649 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 392:2b59412bb664 1650 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1651 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1652 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1653 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1654 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1655 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1656 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1657 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1658 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1659 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1660 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1661 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1662 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1663 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1664 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1665 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1666 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1667 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1668 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1669 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1670 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1671 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1672 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1673 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1674 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1675 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1676 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1677 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1678 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1679 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1680 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1681 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1682
mbed_official 392:2b59412bb664 1683 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 392:2b59412bb664 1684 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1685 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1686 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1687 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1688 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1689 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1690 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1691 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1692 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1693 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1694 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1695 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1696 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1697 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1698 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1699 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1700 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1701 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1702 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1703 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1704 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1705 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1706 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1707 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1708 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1709 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1710 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1711 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1712 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1713 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1714 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1715 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1716
mbed_official 392:2b59412bb664 1717 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 392:2b59412bb664 1718 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1719 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1720 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1721 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1722 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1723 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1724 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1725 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1726 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1727 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1728 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1729 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1730 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1731 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1732 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1733 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1734 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1735 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1736 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1737 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1738 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1739 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1740 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1741 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1742 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1743 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1744 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1745 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1746 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1747 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1748 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1749 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1750
mbed_official 392:2b59412bb664 1751 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 392:2b59412bb664 1752 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1753 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1754 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1755 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1756 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1757 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1758 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1759 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1760 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1761 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1762 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1763 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1764 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1765 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1766 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1767 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1768 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1769 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1770 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1771 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1772 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1773 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1774 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1775 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1776 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1777 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1778 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1779 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1780 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1781 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1782 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1783 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1784
mbed_official 392:2b59412bb664 1785 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 392:2b59412bb664 1786 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1787 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1788 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1789 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1790 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1791 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1792 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1793 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1794 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1795 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1796 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1797 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1798 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1799 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1800 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1801 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1802 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1803 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1804 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1805 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1806 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1807 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1808 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1809 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1810 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1811 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1812 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1813 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1814 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1815 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1816 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1817 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1818
mbed_official 392:2b59412bb664 1819 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 392:2b59412bb664 1820 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1821 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1822 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1823 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1824 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1825 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1826 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1827 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1828 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1829 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1830 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1831 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1832 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1833 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1834 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1835 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1836 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1837 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1838 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1839 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1840 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1841 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1842 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1843 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1844 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1845 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1846 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1847 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1848 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1849 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1850 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1851 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1852
mbed_official 392:2b59412bb664 1853 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 392:2b59412bb664 1854 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1855 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1856 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1857 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1858 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1859 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1860 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1861 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1862 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1863 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1864 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1865 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1866 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1867 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1868 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1869 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1870 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1871 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1872 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1873 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1874 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1875 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1876 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1877 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1878 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1879 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1880 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1881 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1882 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1883 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1884 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1885 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1886
mbed_official 392:2b59412bb664 1887 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 392:2b59412bb664 1888 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1889 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1890 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1891 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1892 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1893 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1894 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1895 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1896 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1897 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1898 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1899 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1900 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1901 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1902 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1903 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1904 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1905 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1906 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1907 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1908 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1909 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1910 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1911 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1912 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1913 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1914 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1915 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1916 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1917 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1918 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1919 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1920
mbed_official 392:2b59412bb664 1921 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 392:2b59412bb664 1922 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1923 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1924 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1925 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1926 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1927 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1928 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1929 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1930 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1931 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1932 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1933 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1934 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1935 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1936 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1937 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1938 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1939 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1940 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1941 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1942 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1943 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1944 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1945 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1946 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1947 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1948 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1949 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1950 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1951 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1952 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1953 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1954
mbed_official 392:2b59412bb664 1955 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 392:2b59412bb664 1956 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1957 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1958 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1959 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1960 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1961 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1962 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1963 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1964 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1965 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 1966 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 1967 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 1968 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 1969 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 1970 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 1971 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 1972 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 1973 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 1974 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 1975 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 1976 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 1977 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 1978 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 1979 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 1980 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 1981 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 1982 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 1983 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 1984 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 1985 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 1986 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 1987 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 1988
mbed_official 392:2b59412bb664 1989 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 392:2b59412bb664 1990 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 1991 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 1992 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 1993 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 1994 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 1995 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 1996 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 1997 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 1998 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 1999 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2000 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2001 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2002 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2003 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2004 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2005 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2006 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2007 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2008 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2009 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2010 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2011 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2012 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2013 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2014 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2015 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2016 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2017 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2018 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2019 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2020 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2021 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2022
mbed_official 392:2b59412bb664 2023 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 392:2b59412bb664 2024 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 2025 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 2026 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 2027 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 2028 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 2029 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 2030 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 2031 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 2032 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 2033 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2034 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2035 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2036 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2037 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2038 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2039 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2040 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2041 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2042 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2043 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2044 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2045 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2046 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2047 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2048 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2049 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2050 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2051 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2052 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2053 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2054 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2055 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2056
mbed_official 392:2b59412bb664 2057 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 392:2b59412bb664 2058 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 2059 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 2060 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 2061 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 2062 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 2063 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 2064 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 2065 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 2066 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 2067 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2068 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2069 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2070 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2071 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2072 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2073 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2074 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2075 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2076 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2077 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2078 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2079 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2080 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2081 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2082 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2083 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2084 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2085 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2086 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2087 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2088 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2089 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2090
mbed_official 392:2b59412bb664 2091 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 392:2b59412bb664 2092 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 2093 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 2094 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 2095 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 2096 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 2097 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 2098 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 2099 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 2100 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 2101 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2102 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2103 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2104 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2105 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2106 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2107 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2108 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2109 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2110 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2111 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2112 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2113 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2114 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2115 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2116 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2117 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2118 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2119 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2120 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2121 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2122 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2123 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2124
mbed_official 392:2b59412bb664 2125 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 392:2b59412bb664 2126 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 2127 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 2128 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 2129 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 2130 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 2131 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 2132 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 2133 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 2134 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 2135 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2136 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2137 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2138 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2139 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2140 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2141 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2142 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2143 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2144 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2145 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2146 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2147 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2148 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2149 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2150 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2151 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2152 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2153 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2154 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2155 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2156 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2157 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2158
mbed_official 392:2b59412bb664 2159 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 392:2b59412bb664 2160 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 2161 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 2162 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 2163 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 2164 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 2165 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 2166 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 2167 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 2168 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 2169 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2170 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2171 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2172 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2173 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2174 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2175 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2176 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2177 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2178 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2179 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2180 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2181 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2182 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2183 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2184 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2185 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2186 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2187 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2188 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2189 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2190 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2191 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2192
mbed_official 392:2b59412bb664 2193 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 392:2b59412bb664 2194 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 392:2b59412bb664 2195 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 392:2b59412bb664 2196 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 392:2b59412bb664 2197 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 392:2b59412bb664 2198 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 392:2b59412bb664 2199 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 392:2b59412bb664 2200 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 392:2b59412bb664 2201 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 392:2b59412bb664 2202 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 392:2b59412bb664 2203 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 392:2b59412bb664 2204 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 392:2b59412bb664 2205 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 392:2b59412bb664 2206 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 392:2b59412bb664 2207 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 392:2b59412bb664 2208 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 392:2b59412bb664 2209 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 392:2b59412bb664 2210 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 392:2b59412bb664 2211 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 392:2b59412bb664 2212 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 392:2b59412bb664 2213 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 392:2b59412bb664 2214 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 392:2b59412bb664 2215 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 392:2b59412bb664 2216 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 392:2b59412bb664 2217 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 392:2b59412bb664 2218 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 392:2b59412bb664 2219 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 392:2b59412bb664 2220 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 392:2b59412bb664 2221 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 392:2b59412bb664 2222 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 392:2b59412bb664 2223 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 392:2b59412bb664 2224 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 392:2b59412bb664 2225 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 392:2b59412bb664 2226
mbed_official 392:2b59412bb664 2227 /******************************************************************************/
mbed_official 392:2b59412bb664 2228 /* */
mbed_official 392:2b59412bb664 2229 /* HDMI-CEC (CEC) */
mbed_official 392:2b59412bb664 2230 /* */
mbed_official 392:2b59412bb664 2231 /******************************************************************************/
mbed_official 392:2b59412bb664 2232
mbed_official 392:2b59412bb664 2233 /******************* Bit definition for CEC_CR register *********************/
mbed_official 392:2b59412bb664 2234 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
mbed_official 392:2b59412bb664 2235 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
mbed_official 392:2b59412bb664 2236 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
mbed_official 392:2b59412bb664 2237
mbed_official 392:2b59412bb664 2238 /******************* Bit definition for CEC_CFGR register *******************/
mbed_official 392:2b59412bb664 2239 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
mbed_official 392:2b59412bb664 2240 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
mbed_official 392:2b59412bb664 2241 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
mbed_official 392:2b59412bb664 2242 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
mbed_official 392:2b59412bb664 2243 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
mbed_official 392:2b59412bb664 2244 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
mbed_official 392:2b59412bb664 2245 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
mbed_official 392:2b59412bb664 2246 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
mbed_official 392:2b59412bb664 2247 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
mbed_official 392:2b59412bb664 2248
mbed_official 392:2b59412bb664 2249 /******************* Bit definition for CEC_TXDR register *******************/
mbed_official 392:2b59412bb664 2250 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
mbed_official 392:2b59412bb664 2251
mbed_official 392:2b59412bb664 2252 /******************* Bit definition for CEC_RXDR register *******************/
mbed_official 392:2b59412bb664 2253 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
mbed_official 392:2b59412bb664 2254
mbed_official 392:2b59412bb664 2255 /******************* Bit definition for CEC_ISR register ********************/
mbed_official 392:2b59412bb664 2256 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
mbed_official 392:2b59412bb664 2257 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
mbed_official 392:2b59412bb664 2258 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
mbed_official 392:2b59412bb664 2259 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
mbed_official 392:2b59412bb664 2260 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
mbed_official 392:2b59412bb664 2261 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
mbed_official 392:2b59412bb664 2262 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
mbed_official 392:2b59412bb664 2263 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
mbed_official 392:2b59412bb664 2264 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
mbed_official 392:2b59412bb664 2265 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
mbed_official 392:2b59412bb664 2266 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
mbed_official 392:2b59412bb664 2267 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
mbed_official 392:2b59412bb664 2268 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
mbed_official 392:2b59412bb664 2269
mbed_official 392:2b59412bb664 2270 /******************* Bit definition for CEC_IER register ********************/
mbed_official 392:2b59412bb664 2271 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
mbed_official 392:2b59412bb664 2272 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
mbed_official 392:2b59412bb664 2273 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
mbed_official 392:2b59412bb664 2274 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
mbed_official 392:2b59412bb664 2275 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
mbed_official 392:2b59412bb664 2276 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
mbed_official 392:2b59412bb664 2277 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
mbed_official 392:2b59412bb664 2278 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
mbed_official 392:2b59412bb664 2279 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
mbed_official 392:2b59412bb664 2280 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
mbed_official 392:2b59412bb664 2281 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
mbed_official 392:2b59412bb664 2282 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
mbed_official 392:2b59412bb664 2283 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 392:2b59412bb664 2284
mbed_official 392:2b59412bb664 2285 /******************************************************************************/
mbed_official 392:2b59412bb664 2286 /* */
mbed_official 392:2b59412bb664 2287 /* Analog Comparators (COMP) */
mbed_official 392:2b59412bb664 2288 /* */
mbed_official 392:2b59412bb664 2289 /******************************************************************************/
mbed_official 392:2b59412bb664 2290 /*********************** Bit definition for COMP_CSR register ***************/
mbed_official 392:2b59412bb664 2291 /* COMP1 bits definition */
mbed_official 392:2b59412bb664 2292 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 392:2b59412bb664 2293 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
mbed_official 392:2b59412bb664 2294 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
mbed_official 392:2b59412bb664 2295 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
mbed_official 392:2b59412bb664 2296 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
mbed_official 392:2b59412bb664 2297 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 392:2b59412bb664 2298 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 392:2b59412bb664 2299 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 392:2b59412bb664 2300 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 392:2b59412bb664 2301 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
mbed_official 392:2b59412bb664 2302 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
mbed_official 392:2b59412bb664 2303 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
mbed_official 392:2b59412bb664 2304 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
mbed_official 392:2b59412bb664 2305 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
mbed_official 392:2b59412bb664 2306 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
mbed_official 392:2b59412bb664 2307 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
mbed_official 392:2b59412bb664 2308 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
mbed_official 392:2b59412bb664 2309 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
mbed_official 392:2b59412bb664 2310 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
mbed_official 392:2b59412bb664 2311 /* COMP2 bits definition */
mbed_official 392:2b59412bb664 2312 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
mbed_official 392:2b59412bb664 2313 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
mbed_official 392:2b59412bb664 2314 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
mbed_official 392:2b59412bb664 2315 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
mbed_official 392:2b59412bb664 2316 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
mbed_official 392:2b59412bb664 2317 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
mbed_official 392:2b59412bb664 2318 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
mbed_official 392:2b59412bb664 2319 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
mbed_official 392:2b59412bb664 2320 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
mbed_official 392:2b59412bb664 2321 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
mbed_official 392:2b59412bb664 2322 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
mbed_official 392:2b59412bb664 2323 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
mbed_official 392:2b59412bb664 2324 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
mbed_official 392:2b59412bb664 2325 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
mbed_official 392:2b59412bb664 2326 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
mbed_official 392:2b59412bb664 2327 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
mbed_official 392:2b59412bb664 2328 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
mbed_official 392:2b59412bb664 2329 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 392:2b59412bb664 2330 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 392:2b59412bb664 2331 /* COMPx bits definition */
mbed_official 630:825f75ca301e 2332 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
mbed_official 630:825f75ca301e 2333 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
mbed_official 630:825f75ca301e 2334 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
mbed_official 630:825f75ca301e 2335 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
mbed_official 630:825f75ca301e 2336 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
mbed_official 630:825f75ca301e 2337 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
mbed_official 630:825f75ca301e 2338 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
mbed_official 630:825f75ca301e 2339 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
mbed_official 630:825f75ca301e 2340 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
mbed_official 630:825f75ca301e 2341 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
mbed_official 630:825f75ca301e 2342 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
mbed_official 630:825f75ca301e 2343 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
mbed_official 630:825f75ca301e 2344 #define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
mbed_official 630:825f75ca301e 2345 #define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
mbed_official 630:825f75ca301e 2346 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
mbed_official 630:825f75ca301e 2347 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
mbed_official 630:825f75ca301e 2348 #define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
mbed_official 630:825f75ca301e 2349 #define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
mbed_official 392:2b59412bb664 2350
mbed_official 392:2b59412bb664 2351 /******************************************************************************/
mbed_official 392:2b59412bb664 2352 /* */
mbed_official 392:2b59412bb664 2353 /* CRC calculation unit (CRC) */
mbed_official 392:2b59412bb664 2354 /* */
mbed_official 392:2b59412bb664 2355 /******************************************************************************/
mbed_official 392:2b59412bb664 2356 /******************* Bit definition for CRC_DR register *********************/
mbed_official 392:2b59412bb664 2357 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 392:2b59412bb664 2358
mbed_official 392:2b59412bb664 2359 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 392:2b59412bb664 2360 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 392:2b59412bb664 2361
mbed_official 392:2b59412bb664 2362 /******************** Bit definition for CRC_CR register ********************/
mbed_official 392:2b59412bb664 2363 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 392:2b59412bb664 2364 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 392:2b59412bb664 2365 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 392:2b59412bb664 2366 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 392:2b59412bb664 2367 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 392:2b59412bb664 2368 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
mbed_official 392:2b59412bb664 2369 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
mbed_official 392:2b59412bb664 2370 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 392:2b59412bb664 2371
mbed_official 392:2b59412bb664 2372 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 392:2b59412bb664 2373 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 392:2b59412bb664 2374
mbed_official 392:2b59412bb664 2375 /******************* Bit definition for CRC_POL register ********************/
mbed_official 392:2b59412bb664 2376 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 392:2b59412bb664 2377
mbed_official 392:2b59412bb664 2378 /******************************************************************************/
mbed_official 392:2b59412bb664 2379 /* */
mbed_official 392:2b59412bb664 2380 /* CRS Clock Recovery System */
mbed_official 392:2b59412bb664 2381 /******************************************************************************/
mbed_official 392:2b59412bb664 2382
mbed_official 392:2b59412bb664 2383 /******************* Bit definition for CRS_CR register *********************/
mbed_official 392:2b59412bb664 2384 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
mbed_official 392:2b59412bb664 2385 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
mbed_official 392:2b59412bb664 2386 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
mbed_official 392:2b59412bb664 2387 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
mbed_official 392:2b59412bb664 2388 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
mbed_official 392:2b59412bb664 2389 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
mbed_official 392:2b59412bb664 2390 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
mbed_official 392:2b59412bb664 2391 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
mbed_official 392:2b59412bb664 2392
mbed_official 392:2b59412bb664 2393 /******************* Bit definition for CRS_CFGR register *********************/
mbed_official 392:2b59412bb664 2394 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
mbed_official 392:2b59412bb664 2395 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
mbed_official 392:2b59412bb664 2396
mbed_official 392:2b59412bb664 2397 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
mbed_official 392:2b59412bb664 2398 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
mbed_official 392:2b59412bb664 2399 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
mbed_official 392:2b59412bb664 2400 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
mbed_official 392:2b59412bb664 2401
mbed_official 392:2b59412bb664 2402 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
mbed_official 392:2b59412bb664 2403 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
mbed_official 392:2b59412bb664 2404 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
mbed_official 392:2b59412bb664 2405
mbed_official 392:2b59412bb664 2406 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
mbed_official 392:2b59412bb664 2407
mbed_official 392:2b59412bb664 2408 /******************* Bit definition for CRS_ISR register *********************/
mbed_official 392:2b59412bb664 2409 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
mbed_official 392:2b59412bb664 2410 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
mbed_official 392:2b59412bb664 2411 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
mbed_official 392:2b59412bb664 2412 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
mbed_official 392:2b59412bb664 2413 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
mbed_official 392:2b59412bb664 2414 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
mbed_official 392:2b59412bb664 2415 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
mbed_official 392:2b59412bb664 2416 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
mbed_official 392:2b59412bb664 2417 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
mbed_official 392:2b59412bb664 2418
mbed_official 392:2b59412bb664 2419 /******************* Bit definition for CRS_ICR register *********************/
mbed_official 392:2b59412bb664 2420 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
mbed_official 392:2b59412bb664 2421 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
mbed_official 392:2b59412bb664 2422 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
mbed_official 392:2b59412bb664 2423 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
mbed_official 392:2b59412bb664 2424
mbed_official 392:2b59412bb664 2425 /******************************************************************************/
mbed_official 392:2b59412bb664 2426 /* */
mbed_official 392:2b59412bb664 2427 /* Digital to Analog Converter (DAC) */
mbed_official 392:2b59412bb664 2428 /* */
mbed_official 392:2b59412bb664 2429 /******************************************************************************/
mbed_official 392:2b59412bb664 2430 /******************** Bit definition for DAC_CR register ********************/
mbed_official 392:2b59412bb664 2431 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 392:2b59412bb664 2432 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 392:2b59412bb664 2433 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 392:2b59412bb664 2434
mbed_official 392:2b59412bb664 2435 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 392:2b59412bb664 2436 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2437 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2438 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 392:2b59412bb664 2439
mbed_official 392:2b59412bb664 2440 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 392:2b59412bb664 2441 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2442 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2443
mbed_official 392:2b59412bb664 2444 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 392:2b59412bb664 2445 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2446 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2447 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 392:2b59412bb664 2448 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 392:2b59412bb664 2449
mbed_official 392:2b59412bb664 2450 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 392:2b59412bb664 2451 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
mbed_official 392:2b59412bb664 2452
mbed_official 392:2b59412bb664 2453 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 392:2b59412bb664 2454 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 392:2b59412bb664 2455 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 392:2b59412bb664 2456
mbed_official 392:2b59412bb664 2457 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 392:2b59412bb664 2458 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2459 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2460 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 2461
mbed_official 392:2b59412bb664 2462 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 392:2b59412bb664 2463 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2464 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2465
mbed_official 392:2b59412bb664 2466 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 392:2b59412bb664 2467 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2468 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2469 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 2470 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 2471
mbed_official 392:2b59412bb664 2472 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 392:2b59412bb664 2473 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
mbed_official 392:2b59412bb664 2474
mbed_official 392:2b59412bb664 2475 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 392:2b59412bb664 2476 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
mbed_official 392:2b59412bb664 2477 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
mbed_official 392:2b59412bb664 2478
mbed_official 392:2b59412bb664 2479 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 392:2b59412bb664 2480 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 392:2b59412bb664 2481
mbed_official 392:2b59412bb664 2482 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 392:2b59412bb664 2483 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 392:2b59412bb664 2484
mbed_official 392:2b59412bb664 2485 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 392:2b59412bb664 2486 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 392:2b59412bb664 2487
mbed_official 392:2b59412bb664 2488 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 392:2b59412bb664 2489 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 392:2b59412bb664 2490
mbed_official 392:2b59412bb664 2491 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 392:2b59412bb664 2492 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 392:2b59412bb664 2493
mbed_official 392:2b59412bb664 2494 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 392:2b59412bb664 2495 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 392:2b59412bb664 2496
mbed_official 392:2b59412bb664 2497 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 392:2b59412bb664 2498 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 392:2b59412bb664 2499 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 392:2b59412bb664 2500
mbed_official 392:2b59412bb664 2501 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 392:2b59412bb664 2502 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 392:2b59412bb664 2503 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 392:2b59412bb664 2504
mbed_official 392:2b59412bb664 2505 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 392:2b59412bb664 2506 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 392:2b59412bb664 2507 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 392:2b59412bb664 2508
mbed_official 392:2b59412bb664 2509 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 392:2b59412bb664 2510 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
mbed_official 392:2b59412bb664 2511
mbed_official 392:2b59412bb664 2512 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 392:2b59412bb664 2513 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
mbed_official 392:2b59412bb664 2514
mbed_official 392:2b59412bb664 2515 /******************** Bit definition for DAC_SR register ********************/
mbed_official 392:2b59412bb664 2516 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 392:2b59412bb664 2517 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 392:2b59412bb664 2518
mbed_official 392:2b59412bb664 2519 /******************************************************************************/
mbed_official 392:2b59412bb664 2520 /* */
mbed_official 392:2b59412bb664 2521 /* Debug MCU (DBGMCU) */
mbed_official 392:2b59412bb664 2522 /* */
mbed_official 392:2b59412bb664 2523 /******************************************************************************/
mbed_official 392:2b59412bb664 2524
mbed_official 392:2b59412bb664 2525 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 392:2b59412bb664 2526 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 392:2b59412bb664 2527
mbed_official 392:2b59412bb664 2528 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 392:2b59412bb664 2529 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2530 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2531 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 2532 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 2533 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 392:2b59412bb664 2534 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 392:2b59412bb664 2535 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 392:2b59412bb664 2536 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 392:2b59412bb664 2537 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 392:2b59412bb664 2538 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 392:2b59412bb664 2539 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 392:2b59412bb664 2540 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 392:2b59412bb664 2541 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 392:2b59412bb664 2542 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 392:2b59412bb664 2543 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 392:2b59412bb664 2544 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 392:2b59412bb664 2545
mbed_official 392:2b59412bb664 2546 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 392:2b59412bb664 2547 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 392:2b59412bb664 2548 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 392:2b59412bb664 2549
mbed_official 392:2b59412bb664 2550 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 392:2b59412bb664 2551 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2552 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2553 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2554 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2555 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2556 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
mbed_official 392:2b59412bb664 2557 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 392:2b59412bb664 2558 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 392:2b59412bb664 2559 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
mbed_official 392:2b59412bb664 2560 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
mbed_official 392:2b59412bb664 2561
mbed_official 392:2b59412bb664 2562 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 392:2b59412bb664 2563 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2564 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2565 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2566 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
mbed_official 392:2b59412bb664 2567
mbed_official 392:2b59412bb664 2568 /******************************************************************************/
mbed_official 392:2b59412bb664 2569 /* */
mbed_official 392:2b59412bb664 2570 /* DMA Controller (DMA) */
mbed_official 392:2b59412bb664 2571 /* */
mbed_official 392:2b59412bb664 2572 /******************************************************************************/
mbed_official 392:2b59412bb664 2573 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 392:2b59412bb664 2574 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 392:2b59412bb664 2575 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 392:2b59412bb664 2576 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 392:2b59412bb664 2577 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 392:2b59412bb664 2578 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 392:2b59412bb664 2579 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 392:2b59412bb664 2580 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 392:2b59412bb664 2581 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 392:2b59412bb664 2582 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 392:2b59412bb664 2583 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 392:2b59412bb664 2584 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 392:2b59412bb664 2585 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 392:2b59412bb664 2586 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 392:2b59412bb664 2587 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 392:2b59412bb664 2588 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 392:2b59412bb664 2589 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 392:2b59412bb664 2590 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 392:2b59412bb664 2591 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 392:2b59412bb664 2592 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 392:2b59412bb664 2593 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 392:2b59412bb664 2594 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 392:2b59412bb664 2595 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 392:2b59412bb664 2596 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 392:2b59412bb664 2597 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 392:2b59412bb664 2598 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 392:2b59412bb664 2599 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 392:2b59412bb664 2600 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 392:2b59412bb664 2601 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 392:2b59412bb664 2602
mbed_official 392:2b59412bb664 2603 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 392:2b59412bb664 2604 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 392:2b59412bb664 2605 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 392:2b59412bb664 2606 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 392:2b59412bb664 2607 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 392:2b59412bb664 2608 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 392:2b59412bb664 2609 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 392:2b59412bb664 2610 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 392:2b59412bb664 2611 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 392:2b59412bb664 2612 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 392:2b59412bb664 2613 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 392:2b59412bb664 2614 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 392:2b59412bb664 2615 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 392:2b59412bb664 2616 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 392:2b59412bb664 2617 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 392:2b59412bb664 2618 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 392:2b59412bb664 2619 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 392:2b59412bb664 2620 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 392:2b59412bb664 2621 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 392:2b59412bb664 2622 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 392:2b59412bb664 2623 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 392:2b59412bb664 2624 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 392:2b59412bb664 2625 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 392:2b59412bb664 2626 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 392:2b59412bb664 2627 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 392:2b59412bb664 2628 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 392:2b59412bb664 2629 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 392:2b59412bb664 2630 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 392:2b59412bb664 2631 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 392:2b59412bb664 2632
mbed_official 392:2b59412bb664 2633 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 392:2b59412bb664 2634 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 392:2b59412bb664 2635 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 392:2b59412bb664 2636 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 392:2b59412bb664 2637 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 392:2b59412bb664 2638 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 392:2b59412bb664 2639 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 392:2b59412bb664 2640 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 392:2b59412bb664 2641 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 392:2b59412bb664 2642
mbed_official 392:2b59412bb664 2643 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 392:2b59412bb664 2644 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2645 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2646
mbed_official 392:2b59412bb664 2647 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 392:2b59412bb664 2648 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2649 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2650
mbed_official 392:2b59412bb664 2651 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 392:2b59412bb664 2652 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 2653 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 2654
mbed_official 392:2b59412bb664 2655 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 392:2b59412bb664 2656
mbed_official 392:2b59412bb664 2657 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 392:2b59412bb664 2658 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 392:2b59412bb664 2659
mbed_official 392:2b59412bb664 2660 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 392:2b59412bb664 2661 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 392:2b59412bb664 2662
mbed_official 392:2b59412bb664 2663 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 392:2b59412bb664 2664 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 392:2b59412bb664 2665
mbed_official 392:2b59412bb664 2666 /******************************************************************************/
mbed_official 392:2b59412bb664 2667 /* */
mbed_official 392:2b59412bb664 2668 /* External Interrupt/Event Controller (EXTI) */
mbed_official 392:2b59412bb664 2669 /* */
mbed_official 392:2b59412bb664 2670 /******************************************************************************/
mbed_official 392:2b59412bb664 2671 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 392:2b59412bb664 2672 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 392:2b59412bb664 2673 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 392:2b59412bb664 2674 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 392:2b59412bb664 2675 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 392:2b59412bb664 2676 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 392:2b59412bb664 2677 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 392:2b59412bb664 2678 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 392:2b59412bb664 2679 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 392:2b59412bb664 2680 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 392:2b59412bb664 2681 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 392:2b59412bb664 2682 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 392:2b59412bb664 2683 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 392:2b59412bb664 2684 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 392:2b59412bb664 2685 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 392:2b59412bb664 2686 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 392:2b59412bb664 2687 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 392:2b59412bb664 2688 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 392:2b59412bb664 2689 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 630:825f75ca301e 2690 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 392:2b59412bb664 2691 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 630:825f75ca301e 2692 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 392:2b59412bb664 2693 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 392:2b59412bb664 2694 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 392:2b59412bb664 2695 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 630:825f75ca301e 2696 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */
mbed_official 392:2b59412bb664 2697 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 630:825f75ca301e 2698 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 392:2b59412bb664 2699 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 630:825f75ca301e 2700 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */
mbed_official 630:825f75ca301e 2701 #define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */
mbed_official 630:825f75ca301e 2702 #define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */
mbed_official 630:825f75ca301e 2703 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
mbed_official 392:2b59412bb664 2704
mbed_official 392:2b59412bb664 2705 /****************** Bit definition for EXTI_EMR register ********************/
mbed_official 392:2b59412bb664 2706 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 392:2b59412bb664 2707 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 392:2b59412bb664 2708 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 392:2b59412bb664 2709 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 392:2b59412bb664 2710 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 392:2b59412bb664 2711 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 392:2b59412bb664 2712 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 392:2b59412bb664 2713 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 392:2b59412bb664 2714 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 392:2b59412bb664 2715 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 392:2b59412bb664 2716 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 392:2b59412bb664 2717 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 392:2b59412bb664 2718 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 392:2b59412bb664 2719 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 392:2b59412bb664 2720 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 392:2b59412bb664 2721 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 392:2b59412bb664 2722 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 392:2b59412bb664 2723 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 630:825f75ca301e 2724 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 392:2b59412bb664 2725 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 630:825f75ca301e 2726 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 392:2b59412bb664 2727 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 392:2b59412bb664 2728 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 392:2b59412bb664 2729 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 630:825f75ca301e 2730 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */
mbed_official 392:2b59412bb664 2731 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 630:825f75ca301e 2732 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 392:2b59412bb664 2733 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 630:825f75ca301e 2734 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */
mbed_official 630:825f75ca301e 2735 #define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */
mbed_official 630:825f75ca301e 2736 #define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */
mbed_official 630:825f75ca301e 2737 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
mbed_official 392:2b59412bb664 2738
mbed_official 392:2b59412bb664 2739 /******************* Bit definition for EXTI_RTSR register ******************/
mbed_official 392:2b59412bb664 2740 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 392:2b59412bb664 2741 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 392:2b59412bb664 2742 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 392:2b59412bb664 2743 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 392:2b59412bb664 2744 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 392:2b59412bb664 2745 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 392:2b59412bb664 2746 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 392:2b59412bb664 2747 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 392:2b59412bb664 2748 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 392:2b59412bb664 2749 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 392:2b59412bb664 2750 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 392:2b59412bb664 2751 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 392:2b59412bb664 2752 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 392:2b59412bb664 2753 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 392:2b59412bb664 2754 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 392:2b59412bb664 2755 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 392:2b59412bb664 2756 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 392:2b59412bb664 2757 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 392:2b59412bb664 2758 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 630:825f75ca301e 2759 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 630:825f75ca301e 2760 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 630:825f75ca301e 2761 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 392:2b59412bb664 2762
mbed_official 392:2b59412bb664 2763 /******************* Bit definition for EXTI_FTSR register *******************/
mbed_official 392:2b59412bb664 2764 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 392:2b59412bb664 2765 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 392:2b59412bb664 2766 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 392:2b59412bb664 2767 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 392:2b59412bb664 2768 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 392:2b59412bb664 2769 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 392:2b59412bb664 2770 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 392:2b59412bb664 2771 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 392:2b59412bb664 2772 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 392:2b59412bb664 2773 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 392:2b59412bb664 2774 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 392:2b59412bb664 2775 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 392:2b59412bb664 2776 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 392:2b59412bb664 2777 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 392:2b59412bb664 2778 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 392:2b59412bb664 2779 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 392:2b59412bb664 2780 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 392:2b59412bb664 2781 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 392:2b59412bb664 2782 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 630:825f75ca301e 2783 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 630:825f75ca301e 2784 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 630:825f75ca301e 2785 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 392:2b59412bb664 2786
mbed_official 392:2b59412bb664 2787 /******************* Bit definition for EXTI_SWIER register *******************/
mbed_official 392:2b59412bb664 2788 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 392:2b59412bb664 2789 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 392:2b59412bb664 2790 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 392:2b59412bb664 2791 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 392:2b59412bb664 2792 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 392:2b59412bb664 2793 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 392:2b59412bb664 2794 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 392:2b59412bb664 2795 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 392:2b59412bb664 2796 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 392:2b59412bb664 2797 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 392:2b59412bb664 2798 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 392:2b59412bb664 2799 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 392:2b59412bb664 2800 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 392:2b59412bb664 2801 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 392:2b59412bb664 2802 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 392:2b59412bb664 2803 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 392:2b59412bb664 2804 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 392:2b59412bb664 2805 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 392:2b59412bb664 2806 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 630:825f75ca301e 2807 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 630:825f75ca301e 2808 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 630:825f75ca301e 2809 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 392:2b59412bb664 2810
mbed_official 392:2b59412bb664 2811 /****************** Bit definition for EXTI_PR register *********************/
mbed_official 392:2b59412bb664 2812 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 392:2b59412bb664 2813 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 392:2b59412bb664 2814 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 392:2b59412bb664 2815 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 392:2b59412bb664 2816 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 392:2b59412bb664 2817 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 392:2b59412bb664 2818 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 392:2b59412bb664 2819 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 392:2b59412bb664 2820 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 392:2b59412bb664 2821 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 392:2b59412bb664 2822 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 392:2b59412bb664 2823 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 392:2b59412bb664 2824 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 392:2b59412bb664 2825 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 392:2b59412bb664 2826 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 392:2b59412bb664 2827 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 392:2b59412bb664 2828 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 392:2b59412bb664 2829 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 392:2b59412bb664 2830 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 630:825f75ca301e 2831 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
mbed_official 630:825f75ca301e 2832 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
mbed_official 630:825f75ca301e 2833 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
mbed_official 392:2b59412bb664 2834
mbed_official 392:2b59412bb664 2835 /******************************************************************************/
mbed_official 392:2b59412bb664 2836 /* */
mbed_official 392:2b59412bb664 2837 /* FLASH and Option Bytes Registers */
mbed_official 392:2b59412bb664 2838 /* */
mbed_official 392:2b59412bb664 2839 /******************************************************************************/
mbed_official 392:2b59412bb664 2840
mbed_official 392:2b59412bb664 2841 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 392:2b59412bb664 2842 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
mbed_official 392:2b59412bb664 2843
mbed_official 392:2b59412bb664 2844 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 392:2b59412bb664 2845 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 392:2b59412bb664 2846
mbed_official 392:2b59412bb664 2847 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 392:2b59412bb664 2848 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 392:2b59412bb664 2849
mbed_official 392:2b59412bb664 2850 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 392:2b59412bb664 2851 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 392:2b59412bb664 2852
mbed_official 392:2b59412bb664 2853 /****************** FLASH Keys **********************************************/
mbed_official 630:825f75ca301e 2854 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
mbed_official 630:825f75ca301e 2855 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official 392:2b59412bb664 2856 to unlock the write access to the FPEC. */
mbed_official 392:2b59412bb664 2857
mbed_official 392:2b59412bb664 2858 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
mbed_official 392:2b59412bb664 2859 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official 392:2b59412bb664 2860 unlock the write access to the option byte block */
mbed_official 392:2b59412bb664 2861
mbed_official 392:2b59412bb664 2862 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 392:2b59412bb664 2863 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 392:2b59412bb664 2864 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 392:2b59412bb664 2865 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 392:2b59412bb664 2866 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 392:2b59412bb664 2867 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
mbed_official 392:2b59412bb664 2868
mbed_official 392:2b59412bb664 2869 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 392:2b59412bb664 2870 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 392:2b59412bb664 2871 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 392:2b59412bb664 2872 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 392:2b59412bb664 2873 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 392:2b59412bb664 2874 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 392:2b59412bb664 2875 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 392:2b59412bb664 2876 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 392:2b59412bb664 2877 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 392:2b59412bb664 2878 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 392:2b59412bb664 2879 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 392:2b59412bb664 2880 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
mbed_official 392:2b59412bb664 2881
mbed_official 392:2b59412bb664 2882 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 392:2b59412bb664 2883 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 392:2b59412bb664 2884
mbed_official 392:2b59412bb664 2885 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 392:2b59412bb664 2886 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 392:2b59412bb664 2887 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 392:2b59412bb664 2888 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
mbed_official 392:2b59412bb664 2889
mbed_official 630:825f75ca301e 2890 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
mbed_official 392:2b59412bb664 2891 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 392:2b59412bb664 2892 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 392:2b59412bb664 2893 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 392:2b59412bb664 2894 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 392:2b59412bb664 2895 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
mbed_official 630:825f75ca301e 2896 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
mbed_official 392:2b59412bb664 2897
mbed_official 392:2b59412bb664 2898 /* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 2899 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official 392:2b59412bb664 2900
mbed_official 392:2b59412bb664 2901 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official 392:2b59412bb664 2902 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official 392:2b59412bb664 2903
mbed_official 392:2b59412bb664 2904 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 392:2b59412bb664 2905 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
mbed_official 392:2b59412bb664 2906
mbed_official 392:2b59412bb664 2907 /*----------------------------------------------------------------------------*/
mbed_official 392:2b59412bb664 2908
mbed_official 392:2b59412bb664 2909 /****************** Bit definition for OB_RDP register **********************/
mbed_official 392:2b59412bb664 2910 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 392:2b59412bb664 2911 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 392:2b59412bb664 2912
mbed_official 392:2b59412bb664 2913 /****************** Bit definition for OB_USER register *********************/
mbed_official 392:2b59412bb664 2914 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 392:2b59412bb664 2915 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 392:2b59412bb664 2916
mbed_official 392:2b59412bb664 2917 /****************** Bit definition for OB_WRP0 register *********************/
mbed_official 392:2b59412bb664 2918 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 392:2b59412bb664 2919 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 392:2b59412bb664 2920
mbed_official 392:2b59412bb664 2921 /****************** Bit definition for OB_WRP1 register *********************/
mbed_official 392:2b59412bb664 2922 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 392:2b59412bb664 2923 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 392:2b59412bb664 2924
mbed_official 392:2b59412bb664 2925 /****************** Bit definition for OB_WRP2 register *********************/
mbed_official 392:2b59412bb664 2926 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 392:2b59412bb664 2927 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 392:2b59412bb664 2928
mbed_official 392:2b59412bb664 2929 /****************** Bit definition for OB_WRP3 register *********************/
mbed_official 392:2b59412bb664 2930 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 392:2b59412bb664 2931 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 392:2b59412bb664 2932
mbed_official 392:2b59412bb664 2933 /******************************************************************************/
mbed_official 392:2b59412bb664 2934 /* */
mbed_official 392:2b59412bb664 2935 /* General Purpose IOs (GPIO) */
mbed_official 392:2b59412bb664 2936 /* */
mbed_official 392:2b59412bb664 2937 /******************************************************************************/
mbed_official 392:2b59412bb664 2938 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 392:2b59412bb664 2939 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 392:2b59412bb664 2940 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 2941 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 2942 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 392:2b59412bb664 2943 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 2944 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 2945 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 392:2b59412bb664 2946 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 2947 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 2948 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 392:2b59412bb664 2949 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 2950 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 2951 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 392:2b59412bb664 2952 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 2953 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 2954 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 392:2b59412bb664 2955 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 2956 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 2957 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 392:2b59412bb664 2958 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 2959 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 2960 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 392:2b59412bb664 2961 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 2962 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 2963 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 392:2b59412bb664 2964 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 2965 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 2966 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 392:2b59412bb664 2967 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 2968 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 2969 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 392:2b59412bb664 2970 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 2971 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 2972 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 392:2b59412bb664 2973 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 2974 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 2975 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 392:2b59412bb664 2976 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 392:2b59412bb664 2977 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 392:2b59412bb664 2978 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 392:2b59412bb664 2979 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 392:2b59412bb664 2980 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 392:2b59412bb664 2981 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 392:2b59412bb664 2982 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 392:2b59412bb664 2983 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 392:2b59412bb664 2984 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 392:2b59412bb664 2985 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 392:2b59412bb664 2986 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 392:2b59412bb664 2987
mbed_official 392:2b59412bb664 2988 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 392:2b59412bb664 2989 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 2990 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 2991 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 2992 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 2993 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 2994 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 2995 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 2996 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 2997 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 2998 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 2999 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3000 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3001 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3002 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3003 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3004 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3005
mbed_official 392:2b59412bb664 3006 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 392:2b59412bb664 3007 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 392:2b59412bb664 3008 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3009 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3010 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 392:2b59412bb664 3011 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3012 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3013 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 392:2b59412bb664 3014 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3015 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3016 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 392:2b59412bb664 3017 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3018 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3019 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 392:2b59412bb664 3020 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3021 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3022 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 392:2b59412bb664 3023 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3024 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3025 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 392:2b59412bb664 3026 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3027 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3028 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 392:2b59412bb664 3029 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3030 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3031 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 392:2b59412bb664 3032 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3033 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3034 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 392:2b59412bb664 3035 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3036 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3037 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 392:2b59412bb664 3038 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3039 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3040 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 392:2b59412bb664 3041 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3042 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 3043 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 392:2b59412bb664 3044 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 392:2b59412bb664 3045 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 392:2b59412bb664 3046 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 392:2b59412bb664 3047 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 392:2b59412bb664 3048 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 392:2b59412bb664 3049 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 392:2b59412bb664 3050 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 392:2b59412bb664 3051 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 392:2b59412bb664 3052 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 392:2b59412bb664 3053 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 392:2b59412bb664 3054 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 392:2b59412bb664 3055
mbed_official 392:2b59412bb664 3056 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official 392:2b59412bb664 3057 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official 392:2b59412bb664 3058 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official 392:2b59412bb664 3059 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official 392:2b59412bb664 3060 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official 392:2b59412bb664 3061 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official 392:2b59412bb664 3062 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official 392:2b59412bb664 3063 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official 392:2b59412bb664 3064 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official 392:2b59412bb664 3065 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official 392:2b59412bb664 3066 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official 392:2b59412bb664 3067 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official 392:2b59412bb664 3068 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official 392:2b59412bb664 3069 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official 392:2b59412bb664 3070 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official 392:2b59412bb664 3071 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official 392:2b59412bb664 3072 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official 392:2b59412bb664 3073 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official 392:2b59412bb664 3074 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official 392:2b59412bb664 3075 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official 392:2b59412bb664 3076 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official 392:2b59412bb664 3077 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official 392:2b59412bb664 3078 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official 392:2b59412bb664 3079 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official 392:2b59412bb664 3080 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official 392:2b59412bb664 3081 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official 392:2b59412bb664 3082 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official 392:2b59412bb664 3083 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official 392:2b59412bb664 3084 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official 392:2b59412bb664 3085 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official 392:2b59412bb664 3086 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official 392:2b59412bb664 3087 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official 392:2b59412bb664 3088 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official 392:2b59412bb664 3089 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official 392:2b59412bb664 3090 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official 392:2b59412bb664 3091 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official 392:2b59412bb664 3092 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official 392:2b59412bb664 3093 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official 392:2b59412bb664 3094 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official 392:2b59412bb664 3095 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official 392:2b59412bb664 3096 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official 392:2b59412bb664 3097 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official 392:2b59412bb664 3098 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official 392:2b59412bb664 3099 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official 392:2b59412bb664 3100 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official 392:2b59412bb664 3101 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official 392:2b59412bb664 3102 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official 392:2b59412bb664 3103 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official 392:2b59412bb664 3104 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official 392:2b59412bb664 3105
mbed_official 392:2b59412bb664 3106 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 392:2b59412bb664 3107 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 392:2b59412bb664 3108 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3109 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3110 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 392:2b59412bb664 3111 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3112 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3113 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 392:2b59412bb664 3114 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3115 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3116 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 392:2b59412bb664 3117 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3118 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3119 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 392:2b59412bb664 3120 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3121 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3122 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 392:2b59412bb664 3123 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3124 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3125 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 392:2b59412bb664 3126 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3127 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3128 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 392:2b59412bb664 3129 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3130 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3131 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 392:2b59412bb664 3132 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3133 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3134 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 392:2b59412bb664 3135 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3136 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3137 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 392:2b59412bb664 3138 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3139 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3140 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 392:2b59412bb664 3141 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3142 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 3143 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 392:2b59412bb664 3144 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 392:2b59412bb664 3145 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 392:2b59412bb664 3146 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 392:2b59412bb664 3147 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 392:2b59412bb664 3148 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 392:2b59412bb664 3149 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 392:2b59412bb664 3150 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 392:2b59412bb664 3151 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 392:2b59412bb664 3152 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 392:2b59412bb664 3153 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 392:2b59412bb664 3154 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 392:2b59412bb664 3155
mbed_official 392:2b59412bb664 3156 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 392:2b59412bb664 3157 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3158 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3159 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3160 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3161 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3162 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3163 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3164 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3165 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3166 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3167 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3168 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3169 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3170 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3171 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3172 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3173
mbed_official 392:2b59412bb664 3174 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 392:2b59412bb664 3175 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3176 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3177 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3178 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3179 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3180 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3181 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3182 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3183 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3184 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3185 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3186 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3187 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3188 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3189 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3190 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3191
mbed_official 392:2b59412bb664 3192 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 392:2b59412bb664 3193 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3194 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3195 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3196 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3197 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3198 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3199 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3200 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3201 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3202 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3203 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3204 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3205 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3206 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3207 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3208 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3209 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3210 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3211 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3212 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3213 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3214 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3215 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3216 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 3217 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 392:2b59412bb664 3218 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 392:2b59412bb664 3219 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 392:2b59412bb664 3220 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 392:2b59412bb664 3221 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 392:2b59412bb664 3222 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 392:2b59412bb664 3223 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 392:2b59412bb664 3224 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 392:2b59412bb664 3225
mbed_official 392:2b59412bb664 3226 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 392:2b59412bb664 3227 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3228 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3229 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3230 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3231 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3232 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3233 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3234 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3235 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3236 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3237 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3238 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3239 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3240 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3241 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3242 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3243 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3244
mbed_official 392:2b59412bb664 3245 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 392:2b59412bb664 3246 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 3247 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 392:2b59412bb664 3248 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 3249 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 392:2b59412bb664 3250 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 392:2b59412bb664 3251 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 392:2b59412bb664 3252 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 392:2b59412bb664 3253 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 392:2b59412bb664 3254
mbed_official 392:2b59412bb664 3255 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 392:2b59412bb664 3256 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 3257 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 392:2b59412bb664 3258 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 3259 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 392:2b59412bb664 3260 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 392:2b59412bb664 3261 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 392:2b59412bb664 3262 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 392:2b59412bb664 3263 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 392:2b59412bb664 3264
mbed_official 392:2b59412bb664 3265 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 392:2b59412bb664 3266 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3267 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3268 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3269 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3270 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3271 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3272 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3273 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3274 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3275 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3276 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3277 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3278 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3279 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3280 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3281 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3282
mbed_official 392:2b59412bb664 3283 /******************************************************************************/
mbed_official 392:2b59412bb664 3284 /* */
mbed_official 392:2b59412bb664 3285 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 392:2b59412bb664 3286 /* */
mbed_official 392:2b59412bb664 3287 /******************************************************************************/
mbed_official 392:2b59412bb664 3288
mbed_official 392:2b59412bb664 3289 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 392:2b59412bb664 3290 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 392:2b59412bb664 3291 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 392:2b59412bb664 3292 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 392:2b59412bb664 3293 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 392:2b59412bb664 3294 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 392:2b59412bb664 3295 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 392:2b59412bb664 3296 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 392:2b59412bb664 3297 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 392:2b59412bb664 3298 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 392:2b59412bb664 3299 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 392:2b59412bb664 3300 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 392:2b59412bb664 3301 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 392:2b59412bb664 3302 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 392:2b59412bb664 3303 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 392:2b59412bb664 3304 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 392:2b59412bb664 3305 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 392:2b59412bb664 3306 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 392:2b59412bb664 3307 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 392:2b59412bb664 3308 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 392:2b59412bb664 3309 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 392:2b59412bb664 3310 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 392:2b59412bb664 3311
mbed_official 392:2b59412bb664 3312 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 392:2b59412bb664 3313 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 392:2b59412bb664 3314 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 392:2b59412bb664 3315 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 392:2b59412bb664 3316 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 392:2b59412bb664 3317 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 392:2b59412bb664 3318 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 392:2b59412bb664 3319 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 392:2b59412bb664 3320 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 392:2b59412bb664 3321 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 392:2b59412bb664 3322 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 392:2b59412bb664 3323 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 392:2b59412bb664 3324
mbed_official 392:2b59412bb664 3325 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 392:2b59412bb664 3326 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 392:2b59412bb664 3327 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 392:2b59412bb664 3328 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 392:2b59412bb664 3329
mbed_official 392:2b59412bb664 3330 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 392:2b59412bb664 3331 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 392:2b59412bb664 3332 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 392:2b59412bb664 3333 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 392:2b59412bb664 3334
mbed_official 392:2b59412bb664 3335 /******************* Bit definition for I2C_TIMINGR register ****************/
mbed_official 392:2b59412bb664 3336 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 392:2b59412bb664 3337 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 392:2b59412bb664 3338 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 392:2b59412bb664 3339 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 392:2b59412bb664 3340 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 392:2b59412bb664 3341
mbed_official 392:2b59412bb664 3342 /******************* Bit definition for I2C_TIMEOUTR register ****************/
mbed_official 392:2b59412bb664 3343 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 392:2b59412bb664 3344 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 392:2b59412bb664 3345 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 392:2b59412bb664 3346 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 392:2b59412bb664 3347 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 392:2b59412bb664 3348
mbed_official 392:2b59412bb664 3349 /****************** Bit definition for I2C_ISR register ********************/
mbed_official 392:2b59412bb664 3350 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 392:2b59412bb664 3351 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 392:2b59412bb664 3352 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 392:2b59412bb664 3353 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 392:2b59412bb664 3354 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 392:2b59412bb664 3355 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 392:2b59412bb664 3356 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 392:2b59412bb664 3357 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 392:2b59412bb664 3358 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 392:2b59412bb664 3359 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 392:2b59412bb664 3360 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 392:2b59412bb664 3361 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 392:2b59412bb664 3362 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 392:2b59412bb664 3363 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 392:2b59412bb664 3364 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 392:2b59412bb664 3365 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 392:2b59412bb664 3366 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 392:2b59412bb664 3367
mbed_official 392:2b59412bb664 3368 /****************** Bit definition for I2C_ICR register ********************/
mbed_official 392:2b59412bb664 3369 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 392:2b59412bb664 3370 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 392:2b59412bb664 3371 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 392:2b59412bb664 3372 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 392:2b59412bb664 3373 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 392:2b59412bb664 3374 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 392:2b59412bb664 3375 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 392:2b59412bb664 3376 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 392:2b59412bb664 3377 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 392:2b59412bb664 3378
mbed_official 392:2b59412bb664 3379 /****************** Bit definition for I2C_PECR register *******************/
mbed_official 392:2b59412bb664 3380 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 392:2b59412bb664 3381
mbed_official 392:2b59412bb664 3382 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 392:2b59412bb664 3383 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 392:2b59412bb664 3384
mbed_official 392:2b59412bb664 3385 /****************** Bit definition for I2C_TXDR register *******************/
mbed_official 392:2b59412bb664 3386 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 392:2b59412bb664 3387
mbed_official 392:2b59412bb664 3388 /*****************************************************************************/
mbed_official 392:2b59412bb664 3389 /* */
mbed_official 392:2b59412bb664 3390 /* Independent WATCHDOG (IWDG) */
mbed_official 392:2b59412bb664 3391 /* */
mbed_official 392:2b59412bb664 3392 /*****************************************************************************/
mbed_official 392:2b59412bb664 3393 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 392:2b59412bb664 3394 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
mbed_official 392:2b59412bb664 3395
mbed_official 392:2b59412bb664 3396 /******************* Bit definition for IWDG_PR register *******************/
mbed_official 392:2b59412bb664 3397 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
mbed_official 392:2b59412bb664 3398 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3399 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3400 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3401
mbed_official 392:2b59412bb664 3402 /******************* Bit definition for IWDG_RLR register ******************/
mbed_official 392:2b59412bb664 3403 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
mbed_official 392:2b59412bb664 3404
mbed_official 392:2b59412bb664 3405 /******************* Bit definition for IWDG_SR register *******************/
mbed_official 392:2b59412bb664 3406 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 392:2b59412bb664 3407 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 392:2b59412bb664 3408 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
mbed_official 392:2b59412bb664 3409
mbed_official 392:2b59412bb664 3410 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 392:2b59412bb664 3411 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 392:2b59412bb664 3412
mbed_official 392:2b59412bb664 3413 /*****************************************************************************/
mbed_official 392:2b59412bb664 3414 /* */
mbed_official 392:2b59412bb664 3415 /* Power Control (PWR) */
mbed_official 392:2b59412bb664 3416 /* */
mbed_official 392:2b59412bb664 3417 /*****************************************************************************/
mbed_official 392:2b59412bb664 3418
mbed_official 392:2b59412bb664 3419 /******************** Bit definition for PWR_CR register *******************/
mbed_official 392:2b59412bb664 3420 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 392:2b59412bb664 3421 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 392:2b59412bb664 3422 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 392:2b59412bb664 3423 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 392:2b59412bb664 3424 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 392:2b59412bb664 3425
mbed_official 392:2b59412bb664 3426 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 392:2b59412bb664 3427 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3428 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3429 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3430
mbed_official 392:2b59412bb664 3431 /*!< PVD level configuration */
mbed_official 392:2b59412bb664 3432 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 392:2b59412bb664 3433 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 392:2b59412bb664 3434 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 392:2b59412bb664 3435 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 392:2b59412bb664 3436 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 392:2b59412bb664 3437 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 392:2b59412bb664 3438 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 392:2b59412bb664 3439 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 392:2b59412bb664 3440
mbed_official 392:2b59412bb664 3441 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 392:2b59412bb664 3442
mbed_official 392:2b59412bb664 3443 /******************* Bit definition for PWR_CSR register *******************/
mbed_official 392:2b59412bb664 3444 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 392:2b59412bb664 3445 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 392:2b59412bb664 3446 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 392:2b59412bb664 3447 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 392:2b59412bb664 3448
mbed_official 392:2b59412bb664 3449 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 392:2b59412bb664 3450 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 392:2b59412bb664 3451 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 392:2b59412bb664 3452 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
mbed_official 392:2b59412bb664 3453 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
mbed_official 392:2b59412bb664 3454 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
mbed_official 392:2b59412bb664 3455 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
mbed_official 392:2b59412bb664 3456 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
mbed_official 392:2b59412bb664 3457
mbed_official 392:2b59412bb664 3458 /*****************************************************************************/
mbed_official 392:2b59412bb664 3459 /* */
mbed_official 392:2b59412bb664 3460 /* Reset and Clock Control */
mbed_official 392:2b59412bb664 3461 /* */
mbed_official 392:2b59412bb664 3462 /*****************************************************************************/
mbed_official 392:2b59412bb664 3463
mbed_official 392:2b59412bb664 3464 /******************** Bit definition for RCC_CR register *******************/
mbed_official 392:2b59412bb664 3465 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 392:2b59412bb664 3466 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 392:2b59412bb664 3467
mbed_official 392:2b59412bb664 3468 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
mbed_official 392:2b59412bb664 3469 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 392:2b59412bb664 3470 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 392:2b59412bb664 3471 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 392:2b59412bb664 3472 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
mbed_official 392:2b59412bb664 3473 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
mbed_official 392:2b59412bb664 3474
mbed_official 392:2b59412bb664 3475 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
mbed_official 392:2b59412bb664 3476 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 3477 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 3478 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 392:2b59412bb664 3479 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 392:2b59412bb664 3480 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 392:2b59412bb664 3481 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 392:2b59412bb664 3482 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 392:2b59412bb664 3483 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 392:2b59412bb664 3484
mbed_official 392:2b59412bb664 3485 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 392:2b59412bb664 3486 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 392:2b59412bb664 3487 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 392:2b59412bb664 3488 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
mbed_official 392:2b59412bb664 3489 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 392:2b59412bb664 3490 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 392:2b59412bb664 3491
mbed_official 392:2b59412bb664 3492 /******************** Bit definition for RCC_CFGR register *****************/
mbed_official 392:2b59412bb664 3493 /*!< SW configuration */
mbed_official 392:2b59412bb664 3494 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 392:2b59412bb664 3495 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3496 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3497
mbed_official 392:2b59412bb664 3498 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 392:2b59412bb664 3499 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 392:2b59412bb664 3500 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 392:2b59412bb664 3501 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
mbed_official 392:2b59412bb664 3502
mbed_official 392:2b59412bb664 3503 /*!< SWS configuration */
mbed_official 392:2b59412bb664 3504 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 392:2b59412bb664 3505 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3506 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3507
mbed_official 392:2b59412bb664 3508 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 392:2b59412bb664 3509 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 392:2b59412bb664 3510 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 392:2b59412bb664 3511 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
mbed_official 392:2b59412bb664 3512
mbed_official 392:2b59412bb664 3513 /*!< HPRE configuration */
mbed_official 392:2b59412bb664 3514 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 392:2b59412bb664 3515 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3516 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3517 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3518 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 392:2b59412bb664 3519
mbed_official 392:2b59412bb664 3520 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 392:2b59412bb664 3521 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 392:2b59412bb664 3522 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 392:2b59412bb664 3523 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 392:2b59412bb664 3524 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 392:2b59412bb664 3525 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 392:2b59412bb664 3526 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 392:2b59412bb664 3527 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 392:2b59412bb664 3528 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 392:2b59412bb664 3529
mbed_official 392:2b59412bb664 3530 /*!< PPRE configuration */
mbed_official 392:2b59412bb664 3531 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
mbed_official 392:2b59412bb664 3532 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3533 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3534 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3535
mbed_official 392:2b59412bb664 3536 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 392:2b59412bb664 3537 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 392:2b59412bb664 3538 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 392:2b59412bb664 3539 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 392:2b59412bb664 3540 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 392:2b59412bb664 3541
mbed_official 392:2b59412bb664 3542 /*!< ADCPPRE configuration */
mbed_official 392:2b59412bb664 3543 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
mbed_official 392:2b59412bb664 3544
mbed_official 392:2b59412bb664 3545 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
mbed_official 392:2b59412bb664 3546 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
mbed_official 392:2b59412bb664 3547
mbed_official 392:2b59412bb664 3548 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
mbed_official 392:2b59412bb664 3549 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 392:2b59412bb664 3550 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
mbed_official 392:2b59412bb664 3551 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 392:2b59412bb664 3552 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
mbed_official 392:2b59412bb664 3553
mbed_official 392:2b59412bb664 3554 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 392:2b59412bb664 3555 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 392:2b59412bb664 3556 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 392:2b59412bb664 3557
mbed_official 392:2b59412bb664 3558 /*!< PLLMUL configuration */
mbed_official 392:2b59412bb664 3559 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 392:2b59412bb664 3560 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3561 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3562 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3563 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 3564
mbed_official 392:2b59412bb664 3565 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 392:2b59412bb664 3566 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 392:2b59412bb664 3567 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 392:2b59412bb664 3568 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 392:2b59412bb664 3569 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 392:2b59412bb664 3570 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 392:2b59412bb664 3571 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 392:2b59412bb664 3572 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 392:2b59412bb664 3573 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 392:2b59412bb664 3574 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 392:2b59412bb664 3575 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 392:2b59412bb664 3576 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 392:2b59412bb664 3577 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 392:2b59412bb664 3578 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 392:2b59412bb664 3579 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 392:2b59412bb664 3580
mbed_official 392:2b59412bb664 3581 /*!< USB configuration */
mbed_official 392:2b59412bb664 3582 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
mbed_official 392:2b59412bb664 3583
mbed_official 392:2b59412bb664 3584 /*!< MCO configuration */
mbed_official 392:2b59412bb664 3585 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
mbed_official 392:2b59412bb664 3586 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3587 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3588 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3589 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 3590
mbed_official 392:2b59412bb664 3591 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 392:2b59412bb664 3592 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
mbed_official 392:2b59412bb664 3593 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 392:2b59412bb664 3594 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 392:2b59412bb664 3595 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 392:2b59412bb664 3596 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 392:2b59412bb664 3597 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 392:2b59412bb664 3598 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 392:2b59412bb664 3599 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
mbed_official 392:2b59412bb664 3600
mbed_official 392:2b59412bb664 3601 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
mbed_official 392:2b59412bb664 3602 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
mbed_official 392:2b59412bb664 3603 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
mbed_official 392:2b59412bb664 3604 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
mbed_official 392:2b59412bb664 3605 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
mbed_official 392:2b59412bb664 3606 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
mbed_official 392:2b59412bb664 3607 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
mbed_official 392:2b59412bb664 3608 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
mbed_official 392:2b59412bb664 3609 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
mbed_official 392:2b59412bb664 3610
mbed_official 392:2b59412bb664 3611 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 392:2b59412bb664 3612
mbed_official 392:2b59412bb664 3613 /*!<****************** Bit definition for RCC_CIR register *****************/
mbed_official 392:2b59412bb664 3614 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 392:2b59412bb664 3615 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 392:2b59412bb664 3616 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 392:2b59412bb664 3617 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 392:2b59412bb664 3618 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 392:2b59412bb664 3619 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
mbed_official 392:2b59412bb664 3620 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
mbed_official 392:2b59412bb664 3621 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 392:2b59412bb664 3622 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3623 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3624 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3625 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3626 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3627 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3628 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
mbed_official 392:2b59412bb664 3629 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3630 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3631 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3632 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3633 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3634 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3635 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
mbed_official 392:2b59412bb664 3636 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 392:2b59412bb664 3637
mbed_official 392:2b59412bb664 3638 /***************** Bit definition for RCC_APB2RSTR register ****************/
mbed_official 392:2b59412bb664 3639 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
mbed_official 392:2b59412bb664 3640 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
mbed_official 392:2b59412bb664 3641 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
mbed_official 392:2b59412bb664 3642 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
mbed_official 392:2b59412bb664 3643 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
mbed_official 392:2b59412bb664 3644 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
mbed_official 392:2b59412bb664 3645 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
mbed_official 392:2b59412bb664 3646 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
mbed_official 392:2b59412bb664 3647 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
mbed_official 392:2b59412bb664 3648
mbed_official 392:2b59412bb664 3649 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
mbed_official 392:2b59412bb664 3650 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official 392:2b59412bb664 3651
mbed_official 392:2b59412bb664 3652 /***************** Bit definition for RCC_APB1RSTR register ****************/
mbed_official 392:2b59412bb664 3653 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
mbed_official 392:2b59412bb664 3654 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
mbed_official 392:2b59412bb664 3655 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
mbed_official 392:2b59412bb664 3656 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
mbed_official 392:2b59412bb664 3657 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
mbed_official 392:2b59412bb664 3658 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
mbed_official 392:2b59412bb664 3659 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
mbed_official 392:2b59412bb664 3660 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
mbed_official 392:2b59412bb664 3661 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
mbed_official 392:2b59412bb664 3662 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
mbed_official 392:2b59412bb664 3663 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
mbed_official 392:2b59412bb664 3664 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
mbed_official 392:2b59412bb664 3665 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
mbed_official 392:2b59412bb664 3666 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
mbed_official 392:2b59412bb664 3667 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
mbed_official 392:2b59412bb664 3668 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
mbed_official 392:2b59412bb664 3669 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
mbed_official 392:2b59412bb664 3670 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
mbed_official 392:2b59412bb664 3671
mbed_official 392:2b59412bb664 3672 /****************** Bit definition for RCC_AHBENR register *****************/
mbed_official 392:2b59412bb664 3673 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 392:2b59412bb664 3674 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 392:2b59412bb664 3675 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 392:2b59412bb664 3676 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 392:2b59412bb664 3677 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 392:2b59412bb664 3678 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 392:2b59412bb664 3679 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 392:2b59412bb664 3680 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 392:2b59412bb664 3681 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 392:2b59412bb664 3682 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 392:2b59412bb664 3683 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
mbed_official 392:2b59412bb664 3684
mbed_official 392:2b59412bb664 3685 /* Old Bit definition maintained for legacy purpose */
mbed_official 392:2b59412bb664 3686 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
mbed_official 392:2b59412bb664 3687 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
mbed_official 392:2b59412bb664 3688
mbed_official 392:2b59412bb664 3689 /***************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 392:2b59412bb664 3690 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
mbed_official 392:2b59412bb664 3691 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 392:2b59412bb664 3692 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 392:2b59412bb664 3693 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 392:2b59412bb664 3694 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 392:2b59412bb664 3695 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 392:2b59412bb664 3696 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 392:2b59412bb664 3697 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 392:2b59412bb664 3698 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
mbed_official 392:2b59412bb664 3699
mbed_official 392:2b59412bb664 3700 /* Old Bit definition maintained for legacy purpose */
mbed_official 392:2b59412bb664 3701 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
mbed_official 392:2b59412bb664 3702 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 392:2b59412bb664 3703
mbed_official 392:2b59412bb664 3704 /***************** Bit definition for RCC_APB1ENR register *****************/
mbed_official 392:2b59412bb664 3705 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 392:2b59412bb664 3706 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 392:2b59412bb664 3707 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 392:2b59412bb664 3708 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 392:2b59412bb664 3709 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
mbed_official 392:2b59412bb664 3710 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 392:2b59412bb664 3711 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 392:2b59412bb664 3712 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
mbed_official 392:2b59412bb664 3713 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
mbed_official 392:2b59412bb664 3714 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
mbed_official 392:2b59412bb664 3715 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
mbed_official 392:2b59412bb664 3716 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
mbed_official 392:2b59412bb664 3717 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 392:2b59412bb664 3718 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 392:2b59412bb664 3719 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
mbed_official 392:2b59412bb664 3720 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 392:2b59412bb664 3721 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
mbed_official 392:2b59412bb664 3722 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
mbed_official 392:2b59412bb664 3723
mbed_official 392:2b59412bb664 3724 /******************* Bit definition for RCC_BDCR register ******************/
mbed_official 392:2b59412bb664 3725 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 392:2b59412bb664 3726 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 392:2b59412bb664 3727 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 392:2b59412bb664 3728
mbed_official 392:2b59412bb664 3729 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 392:2b59412bb664 3730 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3731 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3732
mbed_official 392:2b59412bb664 3733 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 392:2b59412bb664 3734 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3735 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3736
mbed_official 392:2b59412bb664 3737 /*!< RTC configuration */
mbed_official 392:2b59412bb664 3738 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 392:2b59412bb664 3739 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 392:2b59412bb664 3740 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 392:2b59412bb664 3741 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
mbed_official 392:2b59412bb664 3742
mbed_official 392:2b59412bb664 3743 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 392:2b59412bb664 3744 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 392:2b59412bb664 3745
mbed_official 392:2b59412bb664 3746 /******************* Bit definition for RCC_CSR register *******************/
mbed_official 392:2b59412bb664 3747 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 392:2b59412bb664 3748 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 392:2b59412bb664 3749 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
mbed_official 392:2b59412bb664 3750 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 392:2b59412bb664 3751 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 392:2b59412bb664 3752 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 392:2b59412bb664 3753 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 392:2b59412bb664 3754 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 392:2b59412bb664 3755 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 392:2b59412bb664 3756 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 392:2b59412bb664 3757 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 392:2b59412bb664 3758
mbed_official 392:2b59412bb664 3759 /* Old Bit definition maintained for legacy purpose */
mbed_official 392:2b59412bb664 3760 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 392:2b59412bb664 3761
mbed_official 392:2b59412bb664 3762 /******************* Bit definition for RCC_AHBRSTR register ***************/
mbed_official 392:2b59412bb664 3763 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
mbed_official 392:2b59412bb664 3764 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
mbed_official 392:2b59412bb664 3765 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
mbed_official 392:2b59412bb664 3766 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
mbed_official 392:2b59412bb664 3767 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
mbed_official 392:2b59412bb664 3768 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
mbed_official 392:2b59412bb664 3769 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
mbed_official 392:2b59412bb664 3770
mbed_official 392:2b59412bb664 3771 /* Old Bit definition maintained for legacy purpose */
mbed_official 392:2b59412bb664 3772 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
mbed_official 392:2b59412bb664 3773
mbed_official 392:2b59412bb664 3774 /******************* Bit definition for RCC_CFGR2 register *****************/
mbed_official 392:2b59412bb664 3775 /*!< PREDIV configuration */
mbed_official 392:2b59412bb664 3776 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 392:2b59412bb664 3777 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3778 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3779 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 392:2b59412bb664 3780 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 392:2b59412bb664 3781
mbed_official 392:2b59412bb664 3782 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 392:2b59412bb664 3783 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 392:2b59412bb664 3784 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 392:2b59412bb664 3785 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 392:2b59412bb664 3786 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 392:2b59412bb664 3787 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 392:2b59412bb664 3788 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 392:2b59412bb664 3789 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 392:2b59412bb664 3790 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 392:2b59412bb664 3791 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 392:2b59412bb664 3792 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 392:2b59412bb664 3793 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 392:2b59412bb664 3794 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 392:2b59412bb664 3795 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 392:2b59412bb664 3796 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 392:2b59412bb664 3797 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 392:2b59412bb664 3798
mbed_official 392:2b59412bb664 3799 /******************* Bit definition for RCC_CFGR3 register *****************/
mbed_official 392:2b59412bb664 3800 /*!< USART1 Clock source selection */
mbed_official 392:2b59412bb664 3801 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 392:2b59412bb664 3802 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3803 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3804
mbed_official 392:2b59412bb664 3805 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
mbed_official 392:2b59412bb664 3806 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 392:2b59412bb664 3807 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 392:2b59412bb664 3808 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 392:2b59412bb664 3809
mbed_official 392:2b59412bb664 3810 /*!< I2C1 Clock source selection */
mbed_official 392:2b59412bb664 3811 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 392:2b59412bb664 3812
mbed_official 392:2b59412bb664 3813 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 392:2b59412bb664 3814 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 392:2b59412bb664 3815
mbed_official 392:2b59412bb664 3816 /*!< CEC Clock source selection */
mbed_official 392:2b59412bb664 3817 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
mbed_official 392:2b59412bb664 3818
mbed_official 392:2b59412bb664 3819 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
mbed_official 392:2b59412bb664 3820 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
mbed_official 392:2b59412bb664 3821
mbed_official 392:2b59412bb664 3822 /*!< USB Clock source selection */
mbed_official 392:2b59412bb664 3823 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
mbed_official 392:2b59412bb664 3824
mbed_official 392:2b59412bb664 3825 #define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
mbed_official 392:2b59412bb664 3826 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
mbed_official 392:2b59412bb664 3827
mbed_official 392:2b59412bb664 3828 /*!< USART2 Clock source selection */
mbed_official 392:2b59412bb664 3829 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 392:2b59412bb664 3830 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 3831 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 3832
mbed_official 392:2b59412bb664 3833 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
mbed_official 392:2b59412bb664 3834 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
mbed_official 392:2b59412bb664 3835 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
mbed_official 392:2b59412bb664 3836 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
mbed_official 392:2b59412bb664 3837
mbed_official 392:2b59412bb664 3838 /******************* Bit definition for RCC_CR2 register *******************/
mbed_official 392:2b59412bb664 3839 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
mbed_official 392:2b59412bb664 3840 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
mbed_official 392:2b59412bb664 3841 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
mbed_official 392:2b59412bb664 3842 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
mbed_official 392:2b59412bb664 3843 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
mbed_official 392:2b59412bb664 3844 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
mbed_official 392:2b59412bb664 3845 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
mbed_official 392:2b59412bb664 3846 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
mbed_official 392:2b59412bb664 3847
mbed_official 392:2b59412bb664 3848 /*****************************************************************************/
mbed_official 392:2b59412bb664 3849 /* */
mbed_official 392:2b59412bb664 3850 /* Real-Time Clock (RTC) */
mbed_official 392:2b59412bb664 3851 /* */
mbed_official 392:2b59412bb664 3852 /*****************************************************************************/
mbed_official 392:2b59412bb664 3853 /******************** Bits definition for RTC_TR register ******************/
mbed_official 392:2b59412bb664 3854 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3855 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 392:2b59412bb664 3856 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3857 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3858 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 392:2b59412bb664 3859 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3860 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3861 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3862 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3863 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 392:2b59412bb664 3864 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3865 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3866 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3867 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 3868 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3869 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3870 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3871 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3872 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 392:2b59412bb664 3873 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3874 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3875 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3876 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 3877 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3878 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3879 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3880 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3881
mbed_official 392:2b59412bb664 3882 /******************** Bits definition for RTC_DR register ******************/
mbed_official 392:2b59412bb664 3883 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 392:2b59412bb664 3884 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3885 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3886 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3887 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 3888 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 392:2b59412bb664 3889 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3890 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3891 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3892 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3893 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 392:2b59412bb664 3894 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3895 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3896 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3897 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3898 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 3899 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3900 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3901 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3902 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3903 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 392:2b59412bb664 3904 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3905 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3906 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 3907 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3908 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3909 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3910 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3911
mbed_official 392:2b59412bb664 3912 /******************** Bits definition for RTC_CR register ******************/
mbed_official 392:2b59412bb664 3913 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 3914 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 392:2b59412bb664 3915 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3916 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3917 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3918 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3919 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3920 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3921 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3922 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 3923 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3924 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3925 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3926 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3927 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3928 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3929 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3930 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3931 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3932 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 392:2b59412bb664 3933 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3934 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 3935 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3936
mbed_official 392:2b59412bb664 3937 /******************** Bits definition for RTC_ISR register *****************/
mbed_official 392:2b59412bb664 3938 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3939 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3940 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3941 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3942 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3943 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3944 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3945 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3946 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3947 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3948 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3949 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3950 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 3951 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 3952 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3953
mbed_official 392:2b59412bb664 3954 /******************** Bits definition for RTC_PRER register ****************/
mbed_official 392:2b59412bb664 3955 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 392:2b59412bb664 3956 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 392:2b59412bb664 3957
mbed_official 392:2b59412bb664 3958 /******************** Bits definition for RTC_WUTR register ****************/
mbed_official 392:2b59412bb664 3959 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 392:2b59412bb664 3960
mbed_official 392:2b59412bb664 3961 /******************** Bits definition for RTC_ALRMAR register **************/
mbed_official 392:2b59412bb664 3962 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 392:2b59412bb664 3963 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 392:2b59412bb664 3964 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 392:2b59412bb664 3965 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 392:2b59412bb664 3966 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 392:2b59412bb664 3967 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 392:2b59412bb664 3968 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 392:2b59412bb664 3969 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 392:2b59412bb664 3970 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 392:2b59412bb664 3971 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 392:2b59412bb664 3972 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 392:2b59412bb664 3973 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 3974 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 392:2b59412bb664 3975 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 3976 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 3977 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 392:2b59412bb664 3978 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 3979 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 3980 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 3981 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 3982 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 3983 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 392:2b59412bb664 3984 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 3985 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 3986 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 3987 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 3988 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 3989 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 3990 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 3991 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 3992 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 3993 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 392:2b59412bb664 3994 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 3995 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 3996 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 3997 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 3998 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 3999 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 4000 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 4001 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 4002
mbed_official 392:2b59412bb664 4003 /******************** Bits definition for RTC_WPR register *****************/
mbed_official 392:2b59412bb664 4004 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 392:2b59412bb664 4005
mbed_official 392:2b59412bb664 4006 /******************** Bits definition for RTC_SSR register *****************/
mbed_official 392:2b59412bb664 4007 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 392:2b59412bb664 4008
mbed_official 392:2b59412bb664 4009 /******************** Bits definition for RTC_SHIFTR register **************/
mbed_official 392:2b59412bb664 4010 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 392:2b59412bb664 4011 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 392:2b59412bb664 4012
mbed_official 392:2b59412bb664 4013 /******************** Bits definition for RTC_TSTR register ****************/
mbed_official 392:2b59412bb664 4014 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 392:2b59412bb664 4015 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 392:2b59412bb664 4016 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 392:2b59412bb664 4017 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 392:2b59412bb664 4018 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 392:2b59412bb664 4019 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 392:2b59412bb664 4020 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 392:2b59412bb664 4021 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 4022 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 392:2b59412bb664 4023 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 392:2b59412bb664 4024 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 4025 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 4026 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 4027 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 4028 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 4029 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 4030 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 4031 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 4032 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 392:2b59412bb664 4033 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 4034 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 4035 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 4036 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 4037 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 4038 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 4039 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 4040 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 4041
mbed_official 392:2b59412bb664 4042 /******************** Bits definition for RTC_TSDR register ****************/
mbed_official 392:2b59412bb664 4043 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 392:2b59412bb664 4044 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 4045 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 4046 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 4047 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 4048 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 392:2b59412bb664 4049 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 4050 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 4051 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 4052 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 4053 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 392:2b59412bb664 4054 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 4055 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 4056 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 392:2b59412bb664 4057 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 4058 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 4059 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 4060 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 4061
mbed_official 392:2b59412bb664 4062 /******************** Bits definition for RTC_TSSSR register ***************/
mbed_official 392:2b59412bb664 4063 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 392:2b59412bb664 4064
mbed_official 392:2b59412bb664 4065 /******************** Bits definition for RTC_CALR register ****************/
mbed_official 392:2b59412bb664 4066 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 4067 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 4068 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 4069 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 392:2b59412bb664 4070 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 4071 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 4072 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 4073 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 4074 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 4075 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 4076 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 4077 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 4078 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 4079
mbed_official 392:2b59412bb664 4080 /******************** Bits definition for RTC_TAFCR register ***************/
mbed_official 392:2b59412bb664 4081 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 392:2b59412bb664 4082 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 392:2b59412bb664 4083 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 392:2b59412bb664 4084 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 392:2b59412bb664 4085 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 392:2b59412bb664 4086 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 392:2b59412bb664 4087 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 392:2b59412bb664 4088 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 392:2b59412bb664 4089 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 392:2b59412bb664 4090 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 392:2b59412bb664 4091 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 392:2b59412bb664 4092 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 392:2b59412bb664 4093 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 392:2b59412bb664 4094 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 392:2b59412bb664 4095 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 392:2b59412bb664 4096 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 392:2b59412bb664 4097 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 392:2b59412bb664 4098 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 392:2b59412bb664 4099 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 392:2b59412bb664 4100 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 392:2b59412bb664 4101
mbed_official 392:2b59412bb664 4102 /******************** Bits definition for RTC_ALRMASSR register ************/
mbed_official 392:2b59412bb664 4103 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 392:2b59412bb664 4104 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 392:2b59412bb664 4105 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 392:2b59412bb664 4106 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 392:2b59412bb664 4107 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 392:2b59412bb664 4108 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 392:2b59412bb664 4109
mbed_official 392:2b59412bb664 4110 /******************** Bits definition for RTC_BKP0R register ***************/
mbed_official 392:2b59412bb664 4111 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 392:2b59412bb664 4112
mbed_official 392:2b59412bb664 4113 /******************** Bits definition for RTC_BKP1R register ***************/
mbed_official 392:2b59412bb664 4114 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 392:2b59412bb664 4115
mbed_official 392:2b59412bb664 4116 /******************** Bits definition for RTC_BKP2R register ***************/
mbed_official 392:2b59412bb664 4117 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 392:2b59412bb664 4118
mbed_official 392:2b59412bb664 4119 /******************** Bits definition for RTC_BKP3R register ***************/
mbed_official 392:2b59412bb664 4120 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 392:2b59412bb664 4121
mbed_official 392:2b59412bb664 4122 /******************** Bits definition for RTC_BKP4R register ***************/
mbed_official 392:2b59412bb664 4123 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 392:2b59412bb664 4124
mbed_official 392:2b59412bb664 4125 /******************** Number of backup registers ******************************/
mbed_official 392:2b59412bb664 4126 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
mbed_official 392:2b59412bb664 4127
mbed_official 392:2b59412bb664 4128 /*****************************************************************************/
mbed_official 392:2b59412bb664 4129 /* */
mbed_official 392:2b59412bb664 4130 /* Serial Peripheral Interface (SPI) */
mbed_official 392:2b59412bb664 4131 /* */
mbed_official 392:2b59412bb664 4132 /*****************************************************************************/
mbed_official 392:2b59412bb664 4133 /******************* Bit definition for SPI_CR1 register *******************/
mbed_official 392:2b59412bb664 4134 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 392:2b59412bb664 4135 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 392:2b59412bb664 4136 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 392:2b59412bb664 4137 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 392:2b59412bb664 4138 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 392:2b59412bb664 4139 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 392:2b59412bb664 4140 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 392:2b59412bb664 4141 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 392:2b59412bb664 4142 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 392:2b59412bb664 4143 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 392:2b59412bb664 4144 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 392:2b59412bb664 4145 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 392:2b59412bb664 4146 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 392:2b59412bb664 4147 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 392:2b59412bb664 4148 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 392:2b59412bb664 4149 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 392:2b59412bb664 4150 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 392:2b59412bb664 4151
mbed_official 392:2b59412bb664 4152 /******************* Bit definition for SPI_CR2 register *******************/
mbed_official 392:2b59412bb664 4153 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 392:2b59412bb664 4154 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 392:2b59412bb664 4155 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 392:2b59412bb664 4156 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 392:2b59412bb664 4157 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 392:2b59412bb664 4158 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 392:2b59412bb664 4159 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 392:2b59412bb664 4160 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 392:2b59412bb664 4161 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 392:2b59412bb664 4162 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 392:2b59412bb664 4163 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 392:2b59412bb664 4164 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 392:2b59412bb664 4165 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 392:2b59412bb664 4166 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 392:2b59412bb664 4167 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 392:2b59412bb664 4168 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 392:2b59412bb664 4169
mbed_official 392:2b59412bb664 4170 /******************** Bit definition for SPI_SR register *******************/
mbed_official 392:2b59412bb664 4171 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 392:2b59412bb664 4172 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 392:2b59412bb664 4173 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 392:2b59412bb664 4174 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 392:2b59412bb664 4175 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 392:2b59412bb664 4176 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 392:2b59412bb664 4177 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 392:2b59412bb664 4178 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 392:2b59412bb664 4179 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 392:2b59412bb664 4180 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 392:2b59412bb664 4181 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 392:2b59412bb664 4182 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 392:2b59412bb664 4183 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 392:2b59412bb664 4184 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 392:2b59412bb664 4185 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 4186
mbed_official 392:2b59412bb664 4187 /******************** Bit definition for SPI_DR register *******************/
mbed_official 392:2b59412bb664 4188 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
mbed_official 392:2b59412bb664 4189
mbed_official 392:2b59412bb664 4190 /******************* Bit definition for SPI_CRCPR register *****************/
mbed_official 392:2b59412bb664 4191 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
mbed_official 392:2b59412bb664 4192
mbed_official 392:2b59412bb664 4193 /****************** Bit definition for SPI_RXCRCR register *****************/
mbed_official 392:2b59412bb664 4194 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
mbed_official 392:2b59412bb664 4195
mbed_official 392:2b59412bb664 4196 /****************** Bit definition for SPI_TXCRCR register *****************/
mbed_official 392:2b59412bb664 4197 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
mbed_official 392:2b59412bb664 4198
mbed_official 392:2b59412bb664 4199 /****************** Bit definition for SPI_I2SCFGR register ****************/
mbed_official 392:2b59412bb664 4200 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 392:2b59412bb664 4201 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 392:2b59412bb664 4202 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4203 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4204 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 392:2b59412bb664 4205 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 392:2b59412bb664 4206 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4207 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4208 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 392:2b59412bb664 4209 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 392:2b59412bb664 4210 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4211 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4212 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 392:2b59412bb664 4213 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 392:2b59412bb664 4214
mbed_official 392:2b59412bb664 4215 /****************** Bit definition for SPI_I2SPR register ******************/
mbed_official 392:2b59412bb664 4216 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 392:2b59412bb664 4217 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 392:2b59412bb664 4218 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 392:2b59412bb664 4219
mbed_official 392:2b59412bb664 4220 /*****************************************************************************/
mbed_official 392:2b59412bb664 4221 /* */
mbed_official 392:2b59412bb664 4222 /* System Configuration (SYSCFG) */
mbed_official 392:2b59412bb664 4223 /* */
mbed_official 392:2b59412bb664 4224 /*****************************************************************************/
mbed_official 392:2b59412bb664 4225 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
mbed_official 392:2b59412bb664 4226 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 392:2b59412bb664 4227 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
mbed_official 392:2b59412bb664 4228 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
mbed_official 392:2b59412bb664 4229
mbed_official 630:825f75ca301e 4230
mbed_official 392:2b59412bb664 4231 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
mbed_official 392:2b59412bb664 4232 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
mbed_official 392:2b59412bb664 4233 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
mbed_official 392:2b59412bb664 4234 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
mbed_official 392:2b59412bb664 4235 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 392:2b59412bb664 4236 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 392:2b59412bb664 4237 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */
mbed_official 392:2b59412bb664 4238 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */
mbed_official 392:2b59412bb664 4239 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap */
mbed_official 392:2b59412bb664 4240 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap */
mbed_official 392:2b59412bb664 4241 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
mbed_official 392:2b59412bb664 4242 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap */
mbed_official 392:2b59412bb664 4243 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap */
mbed_official 392:2b59412bb664 4244 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap */
mbed_official 392:2b59412bb664 4245 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap */
mbed_official 392:2b59412bb664 4246
mbed_official 392:2b59412bb664 4247 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 392:2b59412bb664 4248 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 392:2b59412bb664 4249 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 392:2b59412bb664 4250 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 392:2b59412bb664 4251 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
mbed_official 630:825f75ca301e 4252
mbed_official 392:2b59412bb664 4253 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
mbed_official 392:2b59412bb664 4254
mbed_official 392:2b59412bb664 4255 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
mbed_official 630:825f75ca301e 4256 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 630:825f75ca301e 4257 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 630:825f75ca301e 4258 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 630:825f75ca301e 4259 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 392:2b59412bb664 4260
mbed_official 392:2b59412bb664 4261 /**
mbed_official 392:2b59412bb664 4262 * @brief EXTI0 configuration
mbed_official 392:2b59412bb664 4263 */
mbed_official 630:825f75ca301e 4264 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 630:825f75ca301e 4265 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 630:825f75ca301e 4266 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 630:825f75ca301e 4267 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 630:825f75ca301e 4268 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 630:825f75ca301e 4269 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
mbed_official 392:2b59412bb664 4270
mbed_official 392:2b59412bb664 4271 /**
mbed_official 392:2b59412bb664 4272 * @brief EXTI1 configuration
mbed_official 392:2b59412bb664 4273 */
mbed_official 630:825f75ca301e 4274 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 630:825f75ca301e 4275 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 630:825f75ca301e 4276 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 630:825f75ca301e 4277 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 630:825f75ca301e 4278 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 630:825f75ca301e 4279 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
mbed_official 392:2b59412bb664 4280
mbed_official 392:2b59412bb664 4281 /**
mbed_official 392:2b59412bb664 4282 * @brief EXTI2 configuration
mbed_official 392:2b59412bb664 4283 */
mbed_official 630:825f75ca301e 4284 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 630:825f75ca301e 4285 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 630:825f75ca301e 4286 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 630:825f75ca301e 4287 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 630:825f75ca301e 4288 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 630:825f75ca301e 4289 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
mbed_official 392:2b59412bb664 4290
mbed_official 392:2b59412bb664 4291 /**
mbed_official 392:2b59412bb664 4292 * @brief EXTI3 configuration
mbed_official 392:2b59412bb664 4293 */
mbed_official 630:825f75ca301e 4294 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 630:825f75ca301e 4295 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 630:825f75ca301e 4296 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 630:825f75ca301e 4297 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 630:825f75ca301e 4298 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 630:825f75ca301e 4299 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
mbed_official 392:2b59412bb664 4300
mbed_official 392:2b59412bb664 4301 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
mbed_official 630:825f75ca301e 4302 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 630:825f75ca301e 4303 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 630:825f75ca301e 4304 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 630:825f75ca301e 4305 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 392:2b59412bb664 4306
mbed_official 392:2b59412bb664 4307 /**
mbed_official 392:2b59412bb664 4308 * @brief EXTI4 configuration
mbed_official 392:2b59412bb664 4309 */
mbed_official 630:825f75ca301e 4310 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 630:825f75ca301e 4311 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 630:825f75ca301e 4312 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 630:825f75ca301e 4313 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 630:825f75ca301e 4314 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 630:825f75ca301e 4315 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
mbed_official 392:2b59412bb664 4316
mbed_official 392:2b59412bb664 4317 /**
mbed_official 392:2b59412bb664 4318 * @brief EXTI5 configuration
mbed_official 392:2b59412bb664 4319 */
mbed_official 630:825f75ca301e 4320 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 630:825f75ca301e 4321 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 630:825f75ca301e 4322 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 630:825f75ca301e 4323 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 630:825f75ca301e 4324 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 630:825f75ca301e 4325 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
mbed_official 392:2b59412bb664 4326
mbed_official 392:2b59412bb664 4327 /**
mbed_official 392:2b59412bb664 4328 * @brief EXTI6 configuration
mbed_official 392:2b59412bb664 4329 */
mbed_official 630:825f75ca301e 4330 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 630:825f75ca301e 4331 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 630:825f75ca301e 4332 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 630:825f75ca301e 4333 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 630:825f75ca301e 4334 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 630:825f75ca301e 4335 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
mbed_official 392:2b59412bb664 4336
mbed_official 392:2b59412bb664 4337 /**
mbed_official 392:2b59412bb664 4338 * @brief EXTI7 configuration
mbed_official 392:2b59412bb664 4339 */
mbed_official 630:825f75ca301e 4340 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 630:825f75ca301e 4341 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 630:825f75ca301e 4342 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 630:825f75ca301e 4343 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 630:825f75ca301e 4344 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 630:825f75ca301e 4345 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
mbed_official 392:2b59412bb664 4346
mbed_official 392:2b59412bb664 4347 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
mbed_official 630:825f75ca301e 4348 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 630:825f75ca301e 4349 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 630:825f75ca301e 4350 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 630:825f75ca301e 4351 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 392:2b59412bb664 4352
mbed_official 392:2b59412bb664 4353 /**
mbed_official 392:2b59412bb664 4354 * @brief EXTI8 configuration
mbed_official 392:2b59412bb664 4355 */
mbed_official 630:825f75ca301e 4356 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 630:825f75ca301e 4357 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 630:825f75ca301e 4358 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 630:825f75ca301e 4359 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 630:825f75ca301e 4360 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 392:2b59412bb664 4361
mbed_official 392:2b59412bb664 4362 /**
mbed_official 392:2b59412bb664 4363 * @brief EXTI9 configuration
mbed_official 392:2b59412bb664 4364 */
mbed_official 630:825f75ca301e 4365 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 630:825f75ca301e 4366 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 630:825f75ca301e 4367 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 630:825f75ca301e 4368 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 630:825f75ca301e 4369 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 630:825f75ca301e 4370 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
mbed_official 392:2b59412bb664 4371
mbed_official 392:2b59412bb664 4372 /**
mbed_official 392:2b59412bb664 4373 * @brief EXTI10 configuration
mbed_official 392:2b59412bb664 4374 */
mbed_official 630:825f75ca301e 4375 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 630:825f75ca301e 4376 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 630:825f75ca301e 4377 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 630:825f75ca301e 4378 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
mbed_official 630:825f75ca301e 4379 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
mbed_official 630:825f75ca301e 4380 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
mbed_official 392:2b59412bb664 4381
mbed_official 392:2b59412bb664 4382 /**
mbed_official 392:2b59412bb664 4383 * @brief EXTI11 configuration
mbed_official 392:2b59412bb664 4384 */
mbed_official 630:825f75ca301e 4385 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 630:825f75ca301e 4386 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 630:825f75ca301e 4387 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 630:825f75ca301e 4388 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 630:825f75ca301e 4389 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 392:2b59412bb664 4390
mbed_official 392:2b59412bb664 4391 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
mbed_official 630:825f75ca301e 4392 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 630:825f75ca301e 4393 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 630:825f75ca301e 4394 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 630:825f75ca301e 4395 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 392:2b59412bb664 4396
mbed_official 392:2b59412bb664 4397 /**
mbed_official 392:2b59412bb664 4398 * @brief EXTI12 configuration
mbed_official 392:2b59412bb664 4399 */
mbed_official 630:825f75ca301e 4400 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 630:825f75ca301e 4401 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 630:825f75ca301e 4402 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 630:825f75ca301e 4403 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 630:825f75ca301e 4404 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 392:2b59412bb664 4405
mbed_official 392:2b59412bb664 4406 /**
mbed_official 392:2b59412bb664 4407 * @brief EXTI13 configuration
mbed_official 392:2b59412bb664 4408 */
mbed_official 630:825f75ca301e 4409 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 630:825f75ca301e 4410 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 630:825f75ca301e 4411 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 630:825f75ca301e 4412 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 630:825f75ca301e 4413 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 392:2b59412bb664 4414
mbed_official 392:2b59412bb664 4415 /**
mbed_official 392:2b59412bb664 4416 * @brief EXTI14 configuration
mbed_official 392:2b59412bb664 4417 */
mbed_official 630:825f75ca301e 4418 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 630:825f75ca301e 4419 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 630:825f75ca301e 4420 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 630:825f75ca301e 4421 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 630:825f75ca301e 4422 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 392:2b59412bb664 4423
mbed_official 392:2b59412bb664 4424 /**
mbed_official 392:2b59412bb664 4425 * @brief EXTI15 configuration
mbed_official 392:2b59412bb664 4426 */
mbed_official 630:825f75ca301e 4427 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 630:825f75ca301e 4428 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 630:825f75ca301e 4429 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 630:825f75ca301e 4430 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 630:825f75ca301e 4431 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 392:2b59412bb664 4432
mbed_official 392:2b59412bb664 4433 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
mbed_official 392:2b59412bb664 4434 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
mbed_official 392:2b59412bb664 4435 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
mbed_official 392:2b59412bb664 4436 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
mbed_official 392:2b59412bb664 4437 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 392:2b59412bb664 4438 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
mbed_official 392:2b59412bb664 4439
mbed_official 392:2b59412bb664 4440 /*****************************************************************************/
mbed_official 392:2b59412bb664 4441 /* */
mbed_official 392:2b59412bb664 4442 /* Timers (TIM) */
mbed_official 392:2b59412bb664 4443 /* */
mbed_official 392:2b59412bb664 4444 /*****************************************************************************/
mbed_official 392:2b59412bb664 4445 /******************* Bit definition for TIM_CR1 register *******************/
mbed_official 392:2b59412bb664 4446 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 392:2b59412bb664 4447 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 392:2b59412bb664 4448 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 392:2b59412bb664 4449 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 392:2b59412bb664 4450 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 392:2b59412bb664 4451
mbed_official 392:2b59412bb664 4452 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 392:2b59412bb664 4453 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4454 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4455
mbed_official 392:2b59412bb664 4456 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 392:2b59412bb664 4457
mbed_official 392:2b59412bb664 4458 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 392:2b59412bb664 4459 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4460 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4461
mbed_official 392:2b59412bb664 4462 /******************* Bit definition for TIM_CR2 register *******************/
mbed_official 392:2b59412bb664 4463 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 392:2b59412bb664 4464 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 392:2b59412bb664 4465 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 392:2b59412bb664 4466
mbed_official 392:2b59412bb664 4467 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 392:2b59412bb664 4468 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4469 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4470 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4471
mbed_official 392:2b59412bb664 4472 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 392:2b59412bb664 4473 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 392:2b59412bb664 4474 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 392:2b59412bb664 4475 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 392:2b59412bb664 4476 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 392:2b59412bb664 4477 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 392:2b59412bb664 4478 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 392:2b59412bb664 4479 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 392:2b59412bb664 4480
mbed_official 392:2b59412bb664 4481 /******************* Bit definition for TIM_SMCR register ******************/
mbed_official 392:2b59412bb664 4482 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 392:2b59412bb664 4483 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4484 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4485 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4486
mbed_official 392:2b59412bb664 4487 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 392:2b59412bb664 4488
mbed_official 392:2b59412bb664 4489 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 392:2b59412bb664 4490 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4491 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4492 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4493
mbed_official 392:2b59412bb664 4494 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 392:2b59412bb664 4495
mbed_official 392:2b59412bb664 4496 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 392:2b59412bb664 4497 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4498 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4499 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4500 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4501
mbed_official 392:2b59412bb664 4502 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 392:2b59412bb664 4503 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4504 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4505
mbed_official 392:2b59412bb664 4506 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 392:2b59412bb664 4507 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 392:2b59412bb664 4508
mbed_official 392:2b59412bb664 4509 /******************* Bit definition for TIM_DIER register ******************/
mbed_official 392:2b59412bb664 4510 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 392:2b59412bb664 4511 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 392:2b59412bb664 4512 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 392:2b59412bb664 4513 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 392:2b59412bb664 4514 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 392:2b59412bb664 4515 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 392:2b59412bb664 4516 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 392:2b59412bb664 4517 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 392:2b59412bb664 4518 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 392:2b59412bb664 4519 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 392:2b59412bb664 4520 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 392:2b59412bb664 4521 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 392:2b59412bb664 4522 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 392:2b59412bb664 4523 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 392:2b59412bb664 4524 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 392:2b59412bb664 4525
mbed_official 392:2b59412bb664 4526 /******************** Bit definition for TIM_SR register *******************/
mbed_official 392:2b59412bb664 4527 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 392:2b59412bb664 4528 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 392:2b59412bb664 4529 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 392:2b59412bb664 4530 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 392:2b59412bb664 4531 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 392:2b59412bb664 4532 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 392:2b59412bb664 4533 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 392:2b59412bb664 4534 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 392:2b59412bb664 4535 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 392:2b59412bb664 4536 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 392:2b59412bb664 4537 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 392:2b59412bb664 4538 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 392:2b59412bb664 4539
mbed_official 392:2b59412bb664 4540 /******************* Bit definition for TIM_EGR register *******************/
mbed_official 392:2b59412bb664 4541 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 392:2b59412bb664 4542 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 392:2b59412bb664 4543 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 392:2b59412bb664 4544 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 392:2b59412bb664 4545 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 392:2b59412bb664 4546 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 392:2b59412bb664 4547 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 392:2b59412bb664 4548 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 392:2b59412bb664 4549
mbed_official 392:2b59412bb664 4550 /****************** Bit definition for TIM_CCMR1 register ******************/
mbed_official 392:2b59412bb664 4551 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 392:2b59412bb664 4552 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4553 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4554
mbed_official 392:2b59412bb664 4555 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 392:2b59412bb664 4556 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 392:2b59412bb664 4557
mbed_official 392:2b59412bb664 4558 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 392:2b59412bb664 4559 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4560 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4561 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4562
mbed_official 392:2b59412bb664 4563 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 392:2b59412bb664 4564
mbed_official 392:2b59412bb664 4565 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 392:2b59412bb664 4566 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4567 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4568
mbed_official 392:2b59412bb664 4569 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 392:2b59412bb664 4570 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 392:2b59412bb664 4571
mbed_official 392:2b59412bb664 4572 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 392:2b59412bb664 4573 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4574 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4575 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4576
mbed_official 392:2b59412bb664 4577 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 392:2b59412bb664 4578
mbed_official 392:2b59412bb664 4579 /*---------------------------------------------------------------------------*/
mbed_official 392:2b59412bb664 4580
mbed_official 392:2b59412bb664 4581 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 392:2b59412bb664 4582 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4583 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4584
mbed_official 392:2b59412bb664 4585 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 392:2b59412bb664 4586 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4587 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4588 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4589 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4590
mbed_official 392:2b59412bb664 4591 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 392:2b59412bb664 4592 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4593 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4594
mbed_official 392:2b59412bb664 4595 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 392:2b59412bb664 4596 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4597 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4598 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4599 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4600
mbed_official 392:2b59412bb664 4601 /****************** Bit definition for TIM_CCMR2 register ******************/
mbed_official 392:2b59412bb664 4602 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 392:2b59412bb664 4603 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4604 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4605
mbed_official 392:2b59412bb664 4606 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 392:2b59412bb664 4607 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 392:2b59412bb664 4608
mbed_official 392:2b59412bb664 4609 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 392:2b59412bb664 4610 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4611 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4612 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4613
mbed_official 392:2b59412bb664 4614 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 392:2b59412bb664 4615
mbed_official 392:2b59412bb664 4616 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 392:2b59412bb664 4617 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4618 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4619
mbed_official 392:2b59412bb664 4620 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 392:2b59412bb664 4621 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 392:2b59412bb664 4622
mbed_official 392:2b59412bb664 4623 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 392:2b59412bb664 4624 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4625 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4626 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4627
mbed_official 392:2b59412bb664 4628 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 392:2b59412bb664 4629
mbed_official 392:2b59412bb664 4630 /*---------------------------------------------------------------------------*/
mbed_official 392:2b59412bb664 4631
mbed_official 392:2b59412bb664 4632 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 392:2b59412bb664 4633 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4634 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4635
mbed_official 392:2b59412bb664 4636 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 392:2b59412bb664 4637 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4638 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4639 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4640 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4641
mbed_official 392:2b59412bb664 4642 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 392:2b59412bb664 4643 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4644 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4645
mbed_official 392:2b59412bb664 4646 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 392:2b59412bb664 4647 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4648 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4649 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4650 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4651
mbed_official 392:2b59412bb664 4652 /******************* Bit definition for TIM_CCER register ******************/
mbed_official 392:2b59412bb664 4653 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 392:2b59412bb664 4654 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 392:2b59412bb664 4655 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 392:2b59412bb664 4656 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 392:2b59412bb664 4657 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 392:2b59412bb664 4658 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 392:2b59412bb664 4659 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 392:2b59412bb664 4660 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 392:2b59412bb664 4661 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 392:2b59412bb664 4662 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 392:2b59412bb664 4663 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 392:2b59412bb664 4664 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 392:2b59412bb664 4665 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 392:2b59412bb664 4666 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 392:2b59412bb664 4667 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 392:2b59412bb664 4668
mbed_official 392:2b59412bb664 4669 /******************* Bit definition for TIM_CNT register *******************/
mbed_official 392:2b59412bb664 4670 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 392:2b59412bb664 4671
mbed_official 392:2b59412bb664 4672 /******************* Bit definition for TIM_PSC register *******************/
mbed_official 392:2b59412bb664 4673 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 392:2b59412bb664 4674
mbed_official 392:2b59412bb664 4675 /******************* Bit definition for TIM_ARR register *******************/
mbed_official 392:2b59412bb664 4676 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 392:2b59412bb664 4677
mbed_official 392:2b59412bb664 4678 /******************* Bit definition for TIM_RCR register *******************/
mbed_official 392:2b59412bb664 4679 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 392:2b59412bb664 4680
mbed_official 392:2b59412bb664 4681 /******************* Bit definition for TIM_CCR1 register ******************/
mbed_official 392:2b59412bb664 4682 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 392:2b59412bb664 4683
mbed_official 392:2b59412bb664 4684 /******************* Bit definition for TIM_CCR2 register ******************/
mbed_official 392:2b59412bb664 4685 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 392:2b59412bb664 4686
mbed_official 392:2b59412bb664 4687 /******************* Bit definition for TIM_CCR3 register ******************/
mbed_official 392:2b59412bb664 4688 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 392:2b59412bb664 4689
mbed_official 392:2b59412bb664 4690 /******************* Bit definition for TIM_CCR4 register ******************/
mbed_official 392:2b59412bb664 4691 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 392:2b59412bb664 4692
mbed_official 392:2b59412bb664 4693 /******************* Bit definition for TIM_BDTR register ******************/
mbed_official 392:2b59412bb664 4694 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 392:2b59412bb664 4695 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4696 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4697 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4698 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4699 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 392:2b59412bb664 4700 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 392:2b59412bb664 4701 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 392:2b59412bb664 4702 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 392:2b59412bb664 4703
mbed_official 392:2b59412bb664 4704 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 392:2b59412bb664 4705 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4706 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4707
mbed_official 392:2b59412bb664 4708 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 392:2b59412bb664 4709 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 392:2b59412bb664 4710 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
mbed_official 392:2b59412bb664 4711 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
mbed_official 392:2b59412bb664 4712 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 392:2b59412bb664 4713 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 392:2b59412bb664 4714
mbed_official 392:2b59412bb664 4715 /******************* Bit definition for TIM_DCR register *******************/
mbed_official 392:2b59412bb664 4716 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 392:2b59412bb664 4717 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4718 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4719 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4720 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4721 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 392:2b59412bb664 4722
mbed_official 392:2b59412bb664 4723 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 392:2b59412bb664 4724 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4725 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4726 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4727 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4728 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 392:2b59412bb664 4729
mbed_official 392:2b59412bb664 4730 /******************* Bit definition for TIM_DMAR register ******************/
mbed_official 392:2b59412bb664 4731 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 392:2b59412bb664 4732
mbed_official 392:2b59412bb664 4733 /******************* Bit definition for TIM14_OR register ********************/
mbed_official 392:2b59412bb664 4734 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
mbed_official 392:2b59412bb664 4735 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4736 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4737
mbed_official 392:2b59412bb664 4738 /******************************************************************************/
mbed_official 392:2b59412bb664 4739 /* */
mbed_official 392:2b59412bb664 4740 /* Touch Sensing Controller (TSC) */
mbed_official 392:2b59412bb664 4741 /* */
mbed_official 392:2b59412bb664 4742 /******************************************************************************/
mbed_official 392:2b59412bb664 4743 /******************* Bit definition for TSC_CR register *********************/
mbed_official 392:2b59412bb664 4744 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
mbed_official 392:2b59412bb664 4745 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
mbed_official 392:2b59412bb664 4746 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
mbed_official 392:2b59412bb664 4747 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
mbed_official 392:2b59412bb664 4748 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
mbed_official 392:2b59412bb664 4749
mbed_official 392:2b59412bb664 4750 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 392:2b59412bb664 4751 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4752 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4753 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4754
mbed_official 392:2b59412bb664 4755 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 392:2b59412bb664 4756 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4757 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4758 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4759
mbed_official 392:2b59412bb664 4760 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
mbed_official 392:2b59412bb664 4761 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
mbed_official 392:2b59412bb664 4762
mbed_official 392:2b59412bb664 4763 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 392:2b59412bb664 4764 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4765 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4766 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4767 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4768 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 392:2b59412bb664 4769 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 392:2b59412bb664 4770 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 392:2b59412bb664 4771
mbed_official 392:2b59412bb664 4772 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 392:2b59412bb664 4773 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4774 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4775 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4776 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4777
mbed_official 392:2b59412bb664 4778 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 392:2b59412bb664 4779 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 392:2b59412bb664 4780 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 392:2b59412bb664 4781 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
mbed_official 392:2b59412bb664 4782 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
mbed_official 392:2b59412bb664 4783
mbed_official 392:2b59412bb664 4784 /******************* Bit definition for TSC_IER register ********************/
mbed_official 392:2b59412bb664 4785 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
mbed_official 392:2b59412bb664 4786 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
mbed_official 392:2b59412bb664 4787
mbed_official 392:2b59412bb664 4788 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 392:2b59412bb664 4789 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
mbed_official 392:2b59412bb664 4790 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
mbed_official 392:2b59412bb664 4791
mbed_official 392:2b59412bb664 4792 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 392:2b59412bb664 4793 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
mbed_official 392:2b59412bb664 4794 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
mbed_official 392:2b59412bb664 4795
mbed_official 392:2b59412bb664 4796 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 392:2b59412bb664 4797 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4798 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4799 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4800 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4801 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4802 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4803 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4804 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4805 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4806 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4807 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4808 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4809 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4810 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4811 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4812 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4813 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4814 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4815 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4816 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4817 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4818 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4819 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4820 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4821 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4822 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4823 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4824 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4825 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4826 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4827 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4828 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
mbed_official 392:2b59412bb664 4829
mbed_official 392:2b59412bb664 4830 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 392:2b59412bb664 4831 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4832 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4833 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4834 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4835 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4836 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4837 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4838 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4839 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4840 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4841 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4842 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4843 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4844 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4845 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4846 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4847 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4848 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4849 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4850 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4851 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4852 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4853 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4854 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4855 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4856 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4857 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4858 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4859 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
mbed_official 392:2b59412bb664 4860 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
mbed_official 392:2b59412bb664 4861 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
mbed_official 392:2b59412bb664 4862 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
mbed_official 392:2b59412bb664 4863
mbed_official 392:2b59412bb664 4864 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 392:2b59412bb664 4865 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
mbed_official 392:2b59412bb664 4866 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
mbed_official 392:2b59412bb664 4867 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
mbed_official 392:2b59412bb664 4868 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
mbed_official 392:2b59412bb664 4869 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
mbed_official 392:2b59412bb664 4870 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
mbed_official 392:2b59412bb664 4871 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
mbed_official 392:2b59412bb664 4872 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
mbed_official 392:2b59412bb664 4873 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
mbed_official 392:2b59412bb664 4874 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
mbed_official 392:2b59412bb664 4875 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
mbed_official 392:2b59412bb664 4876 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
mbed_official 392:2b59412bb664 4877 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
mbed_official 392:2b59412bb664 4878 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
mbed_official 392:2b59412bb664 4879 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
mbed_official 392:2b59412bb664 4880 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
mbed_official 392:2b59412bb664 4881 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
mbed_official 392:2b59412bb664 4882 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
mbed_official 392:2b59412bb664 4883 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
mbed_official 392:2b59412bb664 4884 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
mbed_official 392:2b59412bb664 4885 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
mbed_official 392:2b59412bb664 4886 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
mbed_official 392:2b59412bb664 4887 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
mbed_official 392:2b59412bb664 4888 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
mbed_official 392:2b59412bb664 4889 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
mbed_official 392:2b59412bb664 4890 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
mbed_official 392:2b59412bb664 4891 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
mbed_official 392:2b59412bb664 4892 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
mbed_official 392:2b59412bb664 4893 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
mbed_official 392:2b59412bb664 4894 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
mbed_official 392:2b59412bb664 4895 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
mbed_official 392:2b59412bb664 4896 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
mbed_official 392:2b59412bb664 4897
mbed_official 392:2b59412bb664 4898 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 392:2b59412bb664 4899 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
mbed_official 392:2b59412bb664 4900 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
mbed_official 392:2b59412bb664 4901 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
mbed_official 392:2b59412bb664 4902 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
mbed_official 392:2b59412bb664 4903 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
mbed_official 392:2b59412bb664 4904 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
mbed_official 392:2b59412bb664 4905 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
mbed_official 392:2b59412bb664 4906 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
mbed_official 392:2b59412bb664 4907 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
mbed_official 392:2b59412bb664 4908 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
mbed_official 392:2b59412bb664 4909 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
mbed_official 392:2b59412bb664 4910 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
mbed_official 392:2b59412bb664 4911 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
mbed_official 392:2b59412bb664 4912 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
mbed_official 392:2b59412bb664 4913 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
mbed_official 392:2b59412bb664 4914 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
mbed_official 392:2b59412bb664 4915 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
mbed_official 392:2b59412bb664 4916 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
mbed_official 392:2b59412bb664 4917 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
mbed_official 392:2b59412bb664 4918 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
mbed_official 392:2b59412bb664 4919 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
mbed_official 392:2b59412bb664 4920 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
mbed_official 392:2b59412bb664 4921 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
mbed_official 392:2b59412bb664 4922 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
mbed_official 392:2b59412bb664 4923 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
mbed_official 392:2b59412bb664 4924 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
mbed_official 392:2b59412bb664 4925 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
mbed_official 392:2b59412bb664 4926 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
mbed_official 392:2b59412bb664 4927 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
mbed_official 392:2b59412bb664 4928 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
mbed_official 392:2b59412bb664 4929 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
mbed_official 392:2b59412bb664 4930 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
mbed_official 392:2b59412bb664 4931
mbed_official 392:2b59412bb664 4932 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 392:2b59412bb664 4933 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
mbed_official 392:2b59412bb664 4934 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
mbed_official 392:2b59412bb664 4935 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
mbed_official 392:2b59412bb664 4936 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
mbed_official 392:2b59412bb664 4937 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
mbed_official 392:2b59412bb664 4938 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
mbed_official 392:2b59412bb664 4939 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
mbed_official 392:2b59412bb664 4940 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
mbed_official 392:2b59412bb664 4941 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
mbed_official 392:2b59412bb664 4942 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
mbed_official 392:2b59412bb664 4943 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
mbed_official 392:2b59412bb664 4944 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
mbed_official 392:2b59412bb664 4945 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
mbed_official 392:2b59412bb664 4946 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
mbed_official 392:2b59412bb664 4947 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
mbed_official 392:2b59412bb664 4948 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
mbed_official 392:2b59412bb664 4949
mbed_official 392:2b59412bb664 4950 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 392:2b59412bb664 4951 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
mbed_official 392:2b59412bb664 4952
mbed_official 392:2b59412bb664 4953 /******************************************************************************/
mbed_official 392:2b59412bb664 4954 /* */
mbed_official 392:2b59412bb664 4955 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 392:2b59412bb664 4956 /* */
mbed_official 392:2b59412bb664 4957 /******************************************************************************/
mbed_official 392:2b59412bb664 4958 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 392:2b59412bb664 4959 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 392:2b59412bb664 4960 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 392:2b59412bb664 4961 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 392:2b59412bb664 4962 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 392:2b59412bb664 4963 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 392:2b59412bb664 4964 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 392:2b59412bb664 4965 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 392:2b59412bb664 4966 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 392:2b59412bb664 4967 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 392:2b59412bb664 4968 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 392:2b59412bb664 4969 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 392:2b59412bb664 4970 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 392:2b59412bb664 4971 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
mbed_official 392:2b59412bb664 4972 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 392:2b59412bb664 4973 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 392:2b59412bb664 4974 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 392:2b59412bb664 4975 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 392:2b59412bb664 4976 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 4977 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 4978 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 4979 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 4980 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 392:2b59412bb664 4981 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 392:2b59412bb664 4982 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 4983 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 4984 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 4985 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 392:2b59412bb664 4986 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 392:2b59412bb664 4987 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 392:2b59412bb664 4988 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 392:2b59412bb664 4989 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
mbed_official 392:2b59412bb664 4990 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
mbed_official 392:2b59412bb664 4991
mbed_official 392:2b59412bb664 4992 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 392:2b59412bb664 4993 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 392:2b59412bb664 4994 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 392:2b59412bb664 4995 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 392:2b59412bb664 4996 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 392:2b59412bb664 4997 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 392:2b59412bb664 4998 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 392:2b59412bb664 4999 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 392:2b59412bb664 5000 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 392:2b59412bb664 5001 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 5002 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 5003 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 392:2b59412bb664 5004 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 392:2b59412bb664 5005 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 392:2b59412bb664 5006 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 392:2b59412bb664 5007 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 392:2b59412bb664 5008 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 392:2b59412bb664 5009 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 392:2b59412bb664 5010 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 392:2b59412bb664 5011 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 5012 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 5013 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 392:2b59412bb664 5014 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 392:2b59412bb664 5015
mbed_official 392:2b59412bb664 5016 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 392:2b59412bb664 5017 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 392:2b59412bb664 5018 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 392:2b59412bb664 5019 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 392:2b59412bb664 5020 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 392:2b59412bb664 5021 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 392:2b59412bb664 5022 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 392:2b59412bb664 5023 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 392:2b59412bb664 5024 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 392:2b59412bb664 5025 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 392:2b59412bb664 5026 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 392:2b59412bb664 5027 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 392:2b59412bb664 5028 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 392:2b59412bb664 5029 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 392:2b59412bb664 5030 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 392:2b59412bb664 5031 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 392:2b59412bb664 5032 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 392:2b59412bb664 5033 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 392:2b59412bb664 5034 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 5035 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 5036 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 392:2b59412bb664 5037 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 392:2b59412bb664 5038 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 392:2b59412bb664 5039 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 392:2b59412bb664 5040 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 392:2b59412bb664 5041
mbed_official 392:2b59412bb664 5042 /****************** Bit definition for USART_BRR register *******************/
mbed_official 392:2b59412bb664 5043 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 392:2b59412bb664 5044 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 392:2b59412bb664 5045
mbed_official 392:2b59412bb664 5046 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 392:2b59412bb664 5047 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 392:2b59412bb664 5048 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 392:2b59412bb664 5049
mbed_official 392:2b59412bb664 5050
mbed_official 392:2b59412bb664 5051 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 392:2b59412bb664 5052 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 392:2b59412bb664 5053 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 392:2b59412bb664 5054
mbed_official 392:2b59412bb664 5055 /******************* Bit definition for USART_RQR register ******************/
mbed_official 392:2b59412bb664 5056 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
mbed_official 392:2b59412bb664 5057 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
mbed_official 392:2b59412bb664 5058 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
mbed_official 392:2b59412bb664 5059 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
mbed_official 392:2b59412bb664 5060 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
mbed_official 392:2b59412bb664 5061
mbed_official 392:2b59412bb664 5062 /******************* Bit definition for USART_ISR register ******************/
mbed_official 392:2b59412bb664 5063 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 392:2b59412bb664 5064 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 392:2b59412bb664 5065 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 392:2b59412bb664 5066 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 392:2b59412bb664 5067 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 392:2b59412bb664 5068 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 392:2b59412bb664 5069 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 392:2b59412bb664 5070 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 392:2b59412bb664 5071 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 392:2b59412bb664 5072 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 392:2b59412bb664 5073 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 392:2b59412bb664 5074 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 392:2b59412bb664 5075 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 392:2b59412bb664 5076 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 392:2b59412bb664 5077 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 392:2b59412bb664 5078 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 392:2b59412bb664 5079 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 392:2b59412bb664 5080 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 392:2b59412bb664 5081 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 392:2b59412bb664 5082 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 392:2b59412bb664 5083 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 392:2b59412bb664 5084 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 392:2b59412bb664 5085
mbed_official 392:2b59412bb664 5086 /******************* Bit definition for USART_ICR register ******************/
mbed_official 392:2b59412bb664 5087 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 392:2b59412bb664 5088 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 392:2b59412bb664 5089 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 392:2b59412bb664 5090 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 392:2b59412bb664 5091 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 392:2b59412bb664 5092 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 392:2b59412bb664 5093 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 392:2b59412bb664 5094 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 392:2b59412bb664 5095 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 392:2b59412bb664 5096 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 392:2b59412bb664 5097 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 392:2b59412bb664 5098 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 392:2b59412bb664 5099
mbed_official 392:2b59412bb664 5100 /******************* Bit definition for USART_RDR register ******************/
mbed_official 392:2b59412bb664 5101 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 392:2b59412bb664 5102
mbed_official 392:2b59412bb664 5103 /******************* Bit definition for USART_TDR register ******************/
mbed_official 392:2b59412bb664 5104 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 392:2b59412bb664 5105
mbed_official 392:2b59412bb664 5106 /******************************************************************************/
mbed_official 392:2b59412bb664 5107 /* */
mbed_official 392:2b59412bb664 5108 /* USB Device General registers */
mbed_official 392:2b59412bb664 5109 /* */
mbed_official 392:2b59412bb664 5110 /******************************************************************************/
mbed_official 392:2b59412bb664 5111 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
mbed_official 392:2b59412bb664 5112 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
mbed_official 392:2b59412bb664 5113 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
mbed_official 392:2b59412bb664 5114 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
mbed_official 392:2b59412bb664 5115 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
mbed_official 392:2b59412bb664 5116 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
mbed_official 392:2b59412bb664 5117 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
mbed_official 392:2b59412bb664 5118
mbed_official 392:2b59412bb664 5119 /**************************** ISTR interrupt events *************************/
mbed_official 392:2b59412bb664 5120 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
mbed_official 392:2b59412bb664 5121 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
mbed_official 392:2b59412bb664 5122 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
mbed_official 392:2b59412bb664 5123 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
mbed_official 392:2b59412bb664 5124 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
mbed_official 392:2b59412bb664 5125 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
mbed_official 392:2b59412bb664 5126 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
mbed_official 392:2b59412bb664 5127 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
mbed_official 392:2b59412bb664 5128 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
mbed_official 392:2b59412bb664 5129 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
mbed_official 392:2b59412bb664 5130 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
mbed_official 392:2b59412bb664 5131
mbed_official 392:2b59412bb664 5132 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 392:2b59412bb664 5133 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 392:2b59412bb664 5134 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 392:2b59412bb664 5135 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 392:2b59412bb664 5136 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 392:2b59412bb664 5137 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 392:2b59412bb664 5138 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 392:2b59412bb664 5139 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 392:2b59412bb664 5140 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
mbed_official 392:2b59412bb664 5141
mbed_official 392:2b59412bb664 5142 /************************* CNTR control register bits definitions ***********/
mbed_official 392:2b59412bb664 5143 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
mbed_official 392:2b59412bb664 5144 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
mbed_official 392:2b59412bb664 5145 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
mbed_official 392:2b59412bb664 5146 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
mbed_official 392:2b59412bb664 5147 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
mbed_official 392:2b59412bb664 5148 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
mbed_official 392:2b59412bb664 5149 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
mbed_official 392:2b59412bb664 5150 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
mbed_official 392:2b59412bb664 5151 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
mbed_official 392:2b59412bb664 5152 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
mbed_official 392:2b59412bb664 5153 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
mbed_official 392:2b59412bb664 5154 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
mbed_official 392:2b59412bb664 5155 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
mbed_official 392:2b59412bb664 5156 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
mbed_official 392:2b59412bb664 5157 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
mbed_official 392:2b59412bb664 5158
mbed_official 392:2b59412bb664 5159 /************************* BCDR control register bits definitions ***********/
mbed_official 392:2b59412bb664 5160 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
mbed_official 392:2b59412bb664 5161 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
mbed_official 392:2b59412bb664 5162 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
mbed_official 392:2b59412bb664 5163 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
mbed_official 392:2b59412bb664 5164 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
mbed_official 392:2b59412bb664 5165 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
mbed_official 392:2b59412bb664 5166 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
mbed_official 392:2b59412bb664 5167 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
mbed_official 392:2b59412bb664 5168 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
mbed_official 392:2b59412bb664 5169
mbed_official 392:2b59412bb664 5170 /*************************** LPM register bits definitions ******************/
mbed_official 392:2b59412bb664 5171 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
mbed_official 392:2b59412bb664 5172 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
mbed_official 392:2b59412bb664 5173 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
mbed_official 392:2b59412bb664 5174 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
mbed_official 392:2b59412bb664 5175
mbed_official 392:2b59412bb664 5176 /******************** FNR Frame Number Register bit definitions ************/
mbed_official 392:2b59412bb664 5177 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
mbed_official 392:2b59412bb664 5178 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
mbed_official 392:2b59412bb664 5179 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
mbed_official 392:2b59412bb664 5180 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
mbed_official 392:2b59412bb664 5181 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
mbed_official 392:2b59412bb664 5182
mbed_official 392:2b59412bb664 5183 /******************** DADDR Device ADDRess bit definitions ****************/
mbed_official 392:2b59412bb664 5184 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
mbed_official 392:2b59412bb664 5185 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
mbed_official 392:2b59412bb664 5186
mbed_official 392:2b59412bb664 5187 /****************************** Endpoint register *************************/
mbed_official 392:2b59412bb664 5188 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
mbed_official 392:2b59412bb664 5189 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
mbed_official 392:2b59412bb664 5190 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
mbed_official 392:2b59412bb664 5191 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
mbed_official 392:2b59412bb664 5192 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
mbed_official 392:2b59412bb664 5193 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
mbed_official 392:2b59412bb664 5194 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
mbed_official 392:2b59412bb664 5195 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
mbed_official 392:2b59412bb664 5196 /* bit positions */
mbed_official 392:2b59412bb664 5197 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
mbed_official 392:2b59412bb664 5198 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
mbed_official 392:2b59412bb664 5199 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
mbed_official 392:2b59412bb664 5200 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
mbed_official 392:2b59412bb664 5201 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
mbed_official 392:2b59412bb664 5202 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
mbed_official 392:2b59412bb664 5203 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
mbed_official 392:2b59412bb664 5204 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
mbed_official 392:2b59412bb664 5205 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
mbed_official 392:2b59412bb664 5206 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
mbed_official 392:2b59412bb664 5207
mbed_official 392:2b59412bb664 5208 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 392:2b59412bb664 5209 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 392:2b59412bb664 5210 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 392:2b59412bb664 5211 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
mbed_official 392:2b59412bb664 5212 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
mbed_official 392:2b59412bb664 5213 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
mbed_official 392:2b59412bb664 5214 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
mbed_official 392:2b59412bb664 5215 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
mbed_official 392:2b59412bb664 5216 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 392:2b59412bb664 5217
mbed_official 392:2b59412bb664 5218 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 392:2b59412bb664 5219 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 392:2b59412bb664 5220 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
mbed_official 392:2b59412bb664 5221 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
mbed_official 392:2b59412bb664 5222 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
mbed_official 392:2b59412bb664 5223 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
mbed_official 392:2b59412bb664 5224 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 392:2b59412bb664 5225 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 392:2b59412bb664 5226 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 392:2b59412bb664 5227 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 392:2b59412bb664 5228 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
mbed_official 392:2b59412bb664 5229 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
mbed_official 392:2b59412bb664 5230 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
mbed_official 392:2b59412bb664 5231 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
mbed_official 392:2b59412bb664 5232 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 392:2b59412bb664 5233 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 392:2b59412bb664 5234 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 392:2b59412bb664 5235
mbed_official 392:2b59412bb664 5236 /******************************************************************************/
mbed_official 392:2b59412bb664 5237 /* */
mbed_official 392:2b59412bb664 5238 /* Window WATCHDOG (WWDG) */
mbed_official 392:2b59412bb664 5239 /* */
mbed_official 392:2b59412bb664 5240 /******************************************************************************/
mbed_official 392:2b59412bb664 5241 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 392:2b59412bb664 5242 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 392:2b59412bb664 5243 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 392:2b59412bb664 5244 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 392:2b59412bb664 5245 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 392:2b59412bb664 5246 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 392:2b59412bb664 5247 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 392:2b59412bb664 5248 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 392:2b59412bb664 5249 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 392:2b59412bb664 5250
mbed_official 392:2b59412bb664 5251 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 392:2b59412bb664 5252
mbed_official 392:2b59412bb664 5253 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 392:2b59412bb664 5254 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 392:2b59412bb664 5255 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 392:2b59412bb664 5256 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 392:2b59412bb664 5257 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 392:2b59412bb664 5258 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 392:2b59412bb664 5259 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 392:2b59412bb664 5260 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 392:2b59412bb664 5261 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 392:2b59412bb664 5262
mbed_official 392:2b59412bb664 5263 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 392:2b59412bb664 5264 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 392:2b59412bb664 5265 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 392:2b59412bb664 5266
mbed_official 392:2b59412bb664 5267 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 392:2b59412bb664 5268
mbed_official 392:2b59412bb664 5269 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 392:2b59412bb664 5270 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 392:2b59412bb664 5271
mbed_official 392:2b59412bb664 5272 /**
mbed_official 392:2b59412bb664 5273 * @}
mbed_official 392:2b59412bb664 5274 */
mbed_official 392:2b59412bb664 5275
mbed_official 392:2b59412bb664 5276 /**
mbed_official 392:2b59412bb664 5277 * @}
mbed_official 392:2b59412bb664 5278 */
mbed_official 392:2b59412bb664 5279
mbed_official 392:2b59412bb664 5280
mbed_official 392:2b59412bb664 5281 /** @addtogroup Exported_macro
mbed_official 392:2b59412bb664 5282 * @{
mbed_official 392:2b59412bb664 5283 */
mbed_official 392:2b59412bb664 5284
mbed_official 392:2b59412bb664 5285 /****************************** ADC Instances *********************************/
mbed_official 392:2b59412bb664 5286 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 392:2b59412bb664 5287
mbed_official 392:2b59412bb664 5288 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official 392:2b59412bb664 5289
mbed_official 392:2b59412bb664 5290 /******************************* CAN Instances ********************************/
mbed_official 392:2b59412bb664 5291 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official 392:2b59412bb664 5292
mbed_official 392:2b59412bb664 5293 /****************************** COMP Instances *********************************/
mbed_official 392:2b59412bb664 5294 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 392:2b59412bb664 5295 ((INSTANCE) == COMP2))
mbed_official 392:2b59412bb664 5296
mbed_official 392:2b59412bb664 5297 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
mbed_official 392:2b59412bb664 5298
mbed_official 392:2b59412bb664 5299 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
mbed_official 392:2b59412bb664 5300
mbed_official 392:2b59412bb664 5301 /****************************** CEC Instances *********************************/
mbed_official 392:2b59412bb664 5302 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
mbed_official 392:2b59412bb664 5303
mbed_official 392:2b59412bb664 5304 /****************************** CRC Instances *********************************/
mbed_official 392:2b59412bb664 5305 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 392:2b59412bb664 5306
mbed_official 392:2b59412bb664 5307 /******************************* DAC Instances ********************************/
mbed_official 392:2b59412bb664 5308 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 392:2b59412bb664 5309
mbed_official 392:2b59412bb664 5310 /******************************* DMA Instances ******************************/
mbed_official 392:2b59412bb664 5311 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 392:2b59412bb664 5312 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 392:2b59412bb664 5313 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 392:2b59412bb664 5314 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 392:2b59412bb664 5315 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 392:2b59412bb664 5316 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 392:2b59412bb664 5317 ((INSTANCE) == DMA1_Channel7))
mbed_official 392:2b59412bb664 5318
mbed_official 392:2b59412bb664 5319 /****************************** GPIO Instances ********************************/
mbed_official 441:d2c15dda23c1 5320 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 441:d2c15dda23c1 5321 ((INSTANCE) == GPIOB) || \
mbed_official 441:d2c15dda23c1 5322 ((INSTANCE) == GPIOC) || \
mbed_official 441:d2c15dda23c1 5323 ((INSTANCE) == GPIOD) || \
mbed_official 441:d2c15dda23c1 5324 ((INSTANCE) == GPIOE) || \
mbed_official 441:d2c15dda23c1 5325 ((INSTANCE) == GPIOF))
mbed_official 441:d2c15dda23c1 5326
mbed_official 441:d2c15dda23c1 5327 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 441:d2c15dda23c1 5328 ((INSTANCE) == GPIOB) || \
mbed_official 441:d2c15dda23c1 5329 ((INSTANCE) == GPIOC) || \
mbed_official 441:d2c15dda23c1 5330 ((INSTANCE) == GPIOD) || \
mbed_official 441:d2c15dda23c1 5331 ((INSTANCE) == GPIOE))
mbed_official 441:d2c15dda23c1 5332
mbed_official 392:2b59412bb664 5333 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 392:2b59412bb664 5334 ((INSTANCE) == GPIOB))
mbed_official 392:2b59412bb664 5335
mbed_official 392:2b59412bb664 5336 /****************************** I2C Instances *********************************/
mbed_official 392:2b59412bb664 5337 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 392:2b59412bb664 5338 ((INSTANCE) == I2C2))
mbed_official 392:2b59412bb664 5339
mbed_official 392:2b59412bb664 5340 /****************************** I2S Instances *********************************/
mbed_official 392:2b59412bb664 5341 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 392:2b59412bb664 5342 ((INSTANCE) == SPI2))
mbed_official 392:2b59412bb664 5343
mbed_official 392:2b59412bb664 5344 /****************************** IWDG Instances ********************************/
mbed_official 392:2b59412bb664 5345 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 392:2b59412bb664 5346
mbed_official 392:2b59412bb664 5347 /****************************** RTC Instances *********************************/
mbed_official 392:2b59412bb664 5348 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 392:2b59412bb664 5349
mbed_official 392:2b59412bb664 5350 /****************************** SMBUS Instances *********************************/
mbed_official 392:2b59412bb664 5351 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 392:2b59412bb664 5352
mbed_official 392:2b59412bb664 5353 /****************************** SPI Instances *********************************/
mbed_official 392:2b59412bb664 5354 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 392:2b59412bb664 5355 ((INSTANCE) == SPI2))
mbed_official 392:2b59412bb664 5356
mbed_official 392:2b59412bb664 5357 /****************************** TIM Instances *********************************/
mbed_official 392:2b59412bb664 5358 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5359 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5360 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5361 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5362 ((INSTANCE) == TIM6) || \
mbed_official 392:2b59412bb664 5363 ((INSTANCE) == TIM7) || \
mbed_official 392:2b59412bb664 5364 ((INSTANCE) == TIM14) || \
mbed_official 392:2b59412bb664 5365 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5366 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5367 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5368
mbed_official 392:2b59412bb664 5369 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5370 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5371 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5372 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5373 ((INSTANCE) == TIM14) || \
mbed_official 392:2b59412bb664 5374 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5375 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5376 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5377
mbed_official 392:2b59412bb664 5378 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5379 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5380 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5381 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5382 ((INSTANCE) == TIM15))
mbed_official 392:2b59412bb664 5383
mbed_official 392:2b59412bb664 5384 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5385 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5386 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5387 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5388
mbed_official 392:2b59412bb664 5389 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5390 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5391 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5392 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5393
mbed_official 392:2b59412bb664 5394 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5395 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5396 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5397 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5398
mbed_official 392:2b59412bb664 5399 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5400 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5401 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5402 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5403
mbed_official 392:2b59412bb664 5404 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5405 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5406 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5407 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5408 ((INSTANCE) == TIM15))
mbed_official 392:2b59412bb664 5409
mbed_official 392:2b59412bb664 5410 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5411 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5412 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5413 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5414 ((INSTANCE) == TIM15))
mbed_official 392:2b59412bb664 5415
mbed_official 392:2b59412bb664 5416 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5417 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5418 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5419 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5420
mbed_official 392:2b59412bb664 5421 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5422 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5423 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5424 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5425
mbed_official 392:2b59412bb664 5426 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5427 (((INSTANCE) == TIM1))
mbed_official 392:2b59412bb664 5428
mbed_official 392:2b59412bb664 5429 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5430 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5431 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5432 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5433
mbed_official 392:2b59412bb664 5434 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5435 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5436 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5437 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5438 ((INSTANCE) == TIM6) || \
mbed_official 392:2b59412bb664 5439 ((INSTANCE) == TIM7) || \
mbed_official 392:2b59412bb664 5440 ((INSTANCE) == TIM15))
mbed_official 392:2b59412bb664 5441
mbed_official 392:2b59412bb664 5442 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5443 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5444 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5445 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5446 ((INSTANCE) == TIM15))
mbed_official 392:2b59412bb664 5447
mbed_official 392:2b59412bb664 5448 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5449 ((INSTANCE) == TIM2)
mbed_official 392:2b59412bb664 5450
mbed_official 392:2b59412bb664 5451 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5452 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5453 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5454 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5455 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5456 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5457 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5458
mbed_official 392:2b59412bb664 5459 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5460 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5461 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5462 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5463 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5464
mbed_official 392:2b59412bb664 5465 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 392:2b59412bb664 5466 ((((INSTANCE) == TIM1) && \
mbed_official 392:2b59412bb664 5467 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 392:2b59412bb664 5468 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 392:2b59412bb664 5469 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 392:2b59412bb664 5470 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 392:2b59412bb664 5471 || \
mbed_official 392:2b59412bb664 5472 (((INSTANCE) == TIM2) && \
mbed_official 392:2b59412bb664 5473 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 392:2b59412bb664 5474 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 392:2b59412bb664 5475 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 392:2b59412bb664 5476 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 392:2b59412bb664 5477 || \
mbed_official 392:2b59412bb664 5478 (((INSTANCE) == TIM3) && \
mbed_official 392:2b59412bb664 5479 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 392:2b59412bb664 5480 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 392:2b59412bb664 5481 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 392:2b59412bb664 5482 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 392:2b59412bb664 5483 || \
mbed_official 392:2b59412bb664 5484 (((INSTANCE) == TIM14) && \
mbed_official 392:2b59412bb664 5485 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 392:2b59412bb664 5486 || \
mbed_official 392:2b59412bb664 5487 (((INSTANCE) == TIM15) && \
mbed_official 392:2b59412bb664 5488 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 392:2b59412bb664 5489 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 392:2b59412bb664 5490 || \
mbed_official 392:2b59412bb664 5491 (((INSTANCE) == TIM16) && \
mbed_official 392:2b59412bb664 5492 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 392:2b59412bb664 5493 || \
mbed_official 392:2b59412bb664 5494 (((INSTANCE) == TIM17) && \
mbed_official 392:2b59412bb664 5495 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 392:2b59412bb664 5496
mbed_official 392:2b59412bb664 5497 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 392:2b59412bb664 5498 ((((INSTANCE) == TIM1) && \
mbed_official 392:2b59412bb664 5499 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 392:2b59412bb664 5500 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 392:2b59412bb664 5501 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 392:2b59412bb664 5502 || \
mbed_official 392:2b59412bb664 5503 (((INSTANCE) == TIM15) && \
mbed_official 392:2b59412bb664 5504 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 392:2b59412bb664 5505 || \
mbed_official 392:2b59412bb664 5506 (((INSTANCE) == TIM16) && \
mbed_official 392:2b59412bb664 5507 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 392:2b59412bb664 5508 || \
mbed_official 392:2b59412bb664 5509 (((INSTANCE) == TIM17) && \
mbed_official 392:2b59412bb664 5510 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 392:2b59412bb664 5511
mbed_official 392:2b59412bb664 5512 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5513 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5514 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5515 ((INSTANCE) == TIM3))
mbed_official 392:2b59412bb664 5516
mbed_official 392:2b59412bb664 5517 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5518 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5519 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5520 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5521 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5522
mbed_official 392:2b59412bb664 5523 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5524 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5525 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5526 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5527 ((INSTANCE) == TIM14) || \
mbed_official 392:2b59412bb664 5528 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5529 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5530 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5531
mbed_official 392:2b59412bb664 5532 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5533 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5534 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5535 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5536 ((INSTANCE) == TIM6) || \
mbed_official 392:2b59412bb664 5537 ((INSTANCE) == TIM7) || \
mbed_official 392:2b59412bb664 5538 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5539 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5540 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5541
mbed_official 392:2b59412bb664 5542 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5543 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5544 ((INSTANCE) == TIM2) || \
mbed_official 392:2b59412bb664 5545 ((INSTANCE) == TIM3) || \
mbed_official 392:2b59412bb664 5546 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5547 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5548 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5549
mbed_official 392:2b59412bb664 5550 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5551 (((INSTANCE) == TIM1) || \
mbed_official 392:2b59412bb664 5552 ((INSTANCE) == TIM15) || \
mbed_official 392:2b59412bb664 5553 ((INSTANCE) == TIM16) || \
mbed_official 392:2b59412bb664 5554 ((INSTANCE) == TIM17))
mbed_official 392:2b59412bb664 5555
mbed_official 392:2b59412bb664 5556 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 392:2b59412bb664 5557 ((INSTANCE) == TIM14)
mbed_official 392:2b59412bb664 5558
mbed_official 392:2b59412bb664 5559 /****************************** TSC Instances *********************************/
mbed_official 392:2b59412bb664 5560 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official 392:2b59412bb664 5561
mbed_official 392:2b59412bb664 5562 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 392:2b59412bb664 5563 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5564 ((INSTANCE) == USART2))
mbed_official 392:2b59412bb664 5565
mbed_official 392:2b59412bb664 5566 /********************* UART Instances : Smard card mode ***********************/
mbed_official 392:2b59412bb664 5567 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5568 ((INSTANCE) == USART2))
mbed_official 392:2b59412bb664 5569
mbed_official 392:2b59412bb664 5570 /******************** USART Instances : Synchronous mode **********************/
mbed_official 392:2b59412bb664 5571 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5572 ((INSTANCE) == USART2) || \
mbed_official 392:2b59412bb664 5573 ((INSTANCE) == USART3) || \
mbed_official 392:2b59412bb664 5574 ((INSTANCE) == USART4))
mbed_official 392:2b59412bb664 5575
mbed_official 392:2b59412bb664 5576 /******************** USART Instances : auto Baud rate detection **************/
mbed_official 392:2b59412bb664 5577 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5578 ((INSTANCE) == USART2))
mbed_official 392:2b59412bb664 5579
mbed_official 392:2b59412bb664 5580 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 392:2b59412bb664 5581 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5582 ((INSTANCE) == USART2) || \
mbed_official 392:2b59412bb664 5583 ((INSTANCE) == USART3) || \
mbed_official 392:2b59412bb664 5584 ((INSTANCE) == USART4))
mbed_official 392:2b59412bb664 5585
mbed_official 392:2b59412bb664 5586 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 392:2b59412bb664 5587 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5588 ((INSTANCE) == USART2) || \
mbed_official 392:2b59412bb664 5589 ((INSTANCE) == USART3) || \
mbed_official 392:2b59412bb664 5590 ((INSTANCE) == USART4))
mbed_official 392:2b59412bb664 5591
mbed_official 392:2b59412bb664 5592 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 392:2b59412bb664 5593 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5594 ((INSTANCE) == USART2) || \
mbed_official 392:2b59412bb664 5595 ((INSTANCE) == USART3) || \
mbed_official 392:2b59412bb664 5596 ((INSTANCE) == USART4))
mbed_official 392:2b59412bb664 5597
mbed_official 392:2b59412bb664 5598 /****************** UART Instances : LIN mode ********************/
mbed_official 392:2b59412bb664 5599 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5600 ((INSTANCE) == USART2))
mbed_official 392:2b59412bb664 5601
mbed_official 392:2b59412bb664 5602 /****************** UART Instances : wakeup from stop mode ********************/
mbed_official 392:2b59412bb664 5603 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5604 ((INSTANCE) == USART2))
mbed_official 392:2b59412bb664 5605
mbed_official 392:2b59412bb664 5606 /****************** UART Instances : Auto Baud Rate detection ********************/
mbed_official 392:2b59412bb664 5607 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5608 ((INSTANCE) == USART2))
mbed_official 392:2b59412bb664 5609
mbed_official 392:2b59412bb664 5610 /****************** UART Instances : Driver enable detection ********************/
mbed_official 392:2b59412bb664 5611 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 392:2b59412bb664 5612 ((INSTANCE) == USART2) || \
mbed_official 392:2b59412bb664 5613 ((INSTANCE) == USART3) || \
mbed_official 392:2b59412bb664 5614 ((INSTANCE) == USART4))
mbed_official 392:2b59412bb664 5615
mbed_official 392:2b59412bb664 5616 /****************************** USB Instances ********************************/
mbed_official 392:2b59412bb664 5617 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 392:2b59412bb664 5618
mbed_official 392:2b59412bb664 5619 /****************************** WWDG Instances ********************************/
mbed_official 392:2b59412bb664 5620 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 392:2b59412bb664 5621
mbed_official 392:2b59412bb664 5622 /**
mbed_official 392:2b59412bb664 5623 * @}
mbed_official 392:2b59412bb664 5624 */
mbed_official 392:2b59412bb664 5625
mbed_official 392:2b59412bb664 5626
mbed_official 392:2b59412bb664 5627 /******************************************************************************/
mbed_official 392:2b59412bb664 5628 /* For a painless codes migration between the STM32F0xx device product */
mbed_official 392:2b59412bb664 5629 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 392:2b59412bb664 5630 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 392:2b59412bb664 5631 /* No need to update developed interrupt code when moving across */
mbed_official 392:2b59412bb664 5632 /* product lines within the same STM32F0 Family */
mbed_official 392:2b59412bb664 5633 /******************************************************************************/
mbed_official 392:2b59412bb664 5634
mbed_official 392:2b59412bb664 5635 /* Aliases for __IRQn */
mbed_official 392:2b59412bb664 5636 #define PVD_IRQn PVD_VDDIO2_IRQn
mbed_official 392:2b59412bb664 5637 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
mbed_official 392:2b59412bb664 5638 #define RCC_IRQn RCC_CRS_IRQn
mbed_official 392:2b59412bb664 5639 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
mbed_official 392:2b59412bb664 5640 #define ADC1_IRQn ADC1_COMP_IRQn
mbed_official 392:2b59412bb664 5641 #define TIM6_IRQn TIM6_DAC_IRQn
mbed_official 392:2b59412bb664 5642
mbed_official 392:2b59412bb664 5643 /* Aliases for __IRQHandler */
mbed_official 392:2b59412bb664 5644 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official 392:2b59412bb664 5645 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official 392:2b59412bb664 5646 #define RCC_IRQHandler RCC_CRS_IRQHandler
mbed_official 392:2b59412bb664 5647 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
mbed_official 392:2b59412bb664 5648 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
mbed_official 392:2b59412bb664 5649 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
mbed_official 392:2b59412bb664 5650
mbed_official 392:2b59412bb664 5651 #ifdef __cplusplus
mbed_official 392:2b59412bb664 5652 }
mbed_official 392:2b59412bb664 5653 #endif /* __cplusplus */
mbed_official 392:2b59412bb664 5654
mbed_official 392:2b59412bb664 5655 #endif /* __STM32F072xB_H */
mbed_official 392:2b59412bb664 5656
mbed_official 392:2b59412bb664 5657 /**
mbed_official 392:2b59412bb664 5658 * @}
mbed_official 392:2b59412bb664 5659 */
mbed_official 392:2b59412bb664 5660
mbed_official 392:2b59412bb664 5661 /**
mbed_official 392:2b59412bb664 5662 * @}
mbed_official 392:2b59412bb664 5663 */
mbed_official 392:2b59412bb664 5664
mbed_official 392:2b59412bb664 5665 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/