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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_sdmmc.h@610:813dcc80987e, 2015-08-14 (annotated)

Committer:: mbed_official
Date:: Fri Aug 14 13:15:17 2015 +0100
Revision:: 610:813dcc80987e

Synchronized with git revision 6d84db41c6833e0b9b024741eb0616a5f62d5599

Full URL: https://github.com/mbedmicro/mbed/commit/6d84db41c6833e0b9b024741eb0616a5f62d5599/

DISCO_F746NG - Improvements

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	610:813dcc80987e	1	/**
mbed_official	610:813dcc80987e	2	******************************************************************************
mbed_official	610:813dcc80987e	3	* @file stm32l4xx_ll_sdmmc.h
mbed_official	610:813dcc80987e	4	* @author MCD Application Team
mbed_official	610:813dcc80987e	5	* @version V1.0.0
mbed_official	610:813dcc80987e	6	* @date 26-June-2015
mbed_official	610:813dcc80987e	7	* @brief Header file of low layer SDMMC HAL module.
mbed_official	610:813dcc80987e	8	******************************************************************************
mbed_official	610:813dcc80987e	9	* @attention
mbed_official	610:813dcc80987e	10	*
mbed_official	610:813dcc80987e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	610:813dcc80987e	12	*
mbed_official	610:813dcc80987e	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	610:813dcc80987e	14	* are permitted provided that the following conditions are met:
mbed_official	610:813dcc80987e	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	610:813dcc80987e	16	* this list of conditions and the following disclaimer.
mbed_official	610:813dcc80987e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	610:813dcc80987e	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	610:813dcc80987e	19	* and/or other materials provided with the distribution.
mbed_official	610:813dcc80987e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	610:813dcc80987e	21	* may be used to endorse or promote products derived from this software
mbed_official	610:813dcc80987e	22	* without specific prior written permission.
mbed_official	610:813dcc80987e	23	*
mbed_official	610:813dcc80987e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	610:813dcc80987e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	610:813dcc80987e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	610:813dcc80987e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	610:813dcc80987e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	610:813dcc80987e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	610:813dcc80987e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	610:813dcc80987e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	610:813dcc80987e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	610:813dcc80987e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	610:813dcc80987e	34	*
mbed_official	610:813dcc80987e	35	******************************************************************************
mbed_official	610:813dcc80987e	36	*/
mbed_official	610:813dcc80987e	37
mbed_official	610:813dcc80987e	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	610:813dcc80987e	39	#ifndef __STM32L4xx_LL_SDMMC_H
mbed_official	610:813dcc80987e	40	#define __STM32L4xx_LL_SDMMC_H
mbed_official	610:813dcc80987e	41
mbed_official	610:813dcc80987e	42	#ifdef __cplusplus
mbed_official	610:813dcc80987e	43	extern "C" {
mbed_official	610:813dcc80987e	44	#endif
mbed_official	610:813dcc80987e	45
mbed_official	610:813dcc80987e	46	/* Includes ------------------------------------------------------------------*/
mbed_official	610:813dcc80987e	47	#include "stm32l4xx_hal_def.h"
mbed_official	610:813dcc80987e	48
mbed_official	610:813dcc80987e	49	/** @addtogroup STM32L4xx_Driver
mbed_official	610:813dcc80987e	50	* @{
mbed_official	610:813dcc80987e	51	*/
mbed_official	610:813dcc80987e	52
mbed_official	610:813dcc80987e	53	/** @addtogroup SDMMC_LL
mbed_official	610:813dcc80987e	54	* @{
mbed_official	610:813dcc80987e	55	*/
mbed_official	610:813dcc80987e	56
mbed_official	610:813dcc80987e	57	/* Exported types ------------------------------------------------------------*/
mbed_official	610:813dcc80987e	58	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
mbed_official	610:813dcc80987e	59	* @{
mbed_official	610:813dcc80987e	60	*/
mbed_official	610:813dcc80987e	61
mbed_official	610:813dcc80987e	62	/**
mbed_official	610:813dcc80987e	63	* @brief SDMMC Configuration Structure definition
mbed_official	610:813dcc80987e	64	*/
mbed_official	610:813dcc80987e	65	typedef struct
mbed_official	610:813dcc80987e	66	{
mbed_official	610:813dcc80987e	67	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
mbed_official	610:813dcc80987e	68	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
mbed_official	610:813dcc80987e	69
mbed_official	610:813dcc80987e	70	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
mbed_official	610:813dcc80987e	71	enabled or disabled.
mbed_official	610:813dcc80987e	72	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
mbed_official	610:813dcc80987e	73
mbed_official	610:813dcc80987e	74	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
mbed_official	610:813dcc80987e	75	disabled when the bus is idle.
mbed_official	610:813dcc80987e	76	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
mbed_official	610:813dcc80987e	77
mbed_official	610:813dcc80987e	78	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
mbed_official	610:813dcc80987e	79	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
mbed_official	610:813dcc80987e	80
mbed_official	610:813dcc80987e	81	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
mbed_official	610:813dcc80987e	82	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
mbed_official	610:813dcc80987e	83
mbed_official	610:813dcc80987e	84	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
mbed_official	610:813dcc80987e	85	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	610:813dcc80987e	86
mbed_official	610:813dcc80987e	87	}SDMMC_InitTypeDef;
mbed_official	610:813dcc80987e	88
mbed_official	610:813dcc80987e	89
mbed_official	610:813dcc80987e	90	/**
mbed_official	610:813dcc80987e	91	* @brief SDMMC Command Control structure
mbed_official	610:813dcc80987e	92	*/
mbed_official	610:813dcc80987e	93	typedef struct
mbed_official	610:813dcc80987e	94	{
mbed_official	610:813dcc80987e	95	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
mbed_official	610:813dcc80987e	96	to a card as part of a command message. If a command
mbed_official	610:813dcc80987e	97	contains an argument, it must be loaded into this register
mbed_official	610:813dcc80987e	98	before writing the command to the command register. */
mbed_official	610:813dcc80987e	99
mbed_official	610:813dcc80987e	100	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
mbed_official	610:813dcc80987e	101	Max_Data = 64 */
mbed_official	610:813dcc80987e	102
mbed_official	610:813dcc80987e	103	uint32_t Response; /*!< Specifies the SDMMC response type.
mbed_official	610:813dcc80987e	104	This parameter can be a value of @ref SDMMC_LL_Response_Type */
mbed_official	610:813dcc80987e	105
mbed_official	610:813dcc80987e	106	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
mbed_official	610:813dcc80987e	107	enabled or disabled.
mbed_official	610:813dcc80987e	108	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
mbed_official	610:813dcc80987e	109
mbed_official	610:813dcc80987e	110	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
mbed_official	610:813dcc80987e	111	is enabled or disabled.
mbed_official	610:813dcc80987e	112	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
mbed_official	610:813dcc80987e	113	}SDMMC_CmdInitTypeDef;
mbed_official	610:813dcc80987e	114
mbed_official	610:813dcc80987e	115
mbed_official	610:813dcc80987e	116	/**
mbed_official	610:813dcc80987e	117	* @brief SDMMC Data Control structure
mbed_official	610:813dcc80987e	118	*/
mbed_official	610:813dcc80987e	119	typedef struct
mbed_official	610:813dcc80987e	120	{
mbed_official	610:813dcc80987e	121	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
mbed_official	610:813dcc80987e	122
mbed_official	610:813dcc80987e	123	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
mbed_official	610:813dcc80987e	124
mbed_official	610:813dcc80987e	125	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
mbed_official	610:813dcc80987e	126	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
mbed_official	610:813dcc80987e	127
mbed_official	610:813dcc80987e	128	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
mbed_official	610:813dcc80987e	129	is a read or write.
mbed_official	610:813dcc80987e	130	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
mbed_official	610:813dcc80987e	131
mbed_official	610:813dcc80987e	132	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
mbed_official	610:813dcc80987e	133	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
mbed_official	610:813dcc80987e	134
mbed_official	610:813dcc80987e	135	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
mbed_official	610:813dcc80987e	136	is enabled or disabled.
mbed_official	610:813dcc80987e	137	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
mbed_official	610:813dcc80987e	138	}SDMMC_DataInitTypeDef;
mbed_official	610:813dcc80987e	139
mbed_official	610:813dcc80987e	140	/**
mbed_official	610:813dcc80987e	141	* @}
mbed_official	610:813dcc80987e	142	*/
mbed_official	610:813dcc80987e	143
mbed_official	610:813dcc80987e	144	/* Exported constants --------------------------------------------------------*/
mbed_official	610:813dcc80987e	145	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
mbed_official	610:813dcc80987e	146	* @{
mbed_official	610:813dcc80987e	147	*/
mbed_official	610:813dcc80987e	148
mbed_official	610:813dcc80987e	149	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
mbed_official	610:813dcc80987e	150	* @{
mbed_official	610:813dcc80987e	151	*/
mbed_official	610:813dcc80987e	152	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	153	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
mbed_official	610:813dcc80987e	154
mbed_official	610:813dcc80987e	155	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
mbed_official	610:813dcc80987e	156	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
mbed_official	610:813dcc80987e	157	/**
mbed_official	610:813dcc80987e	158	* @}
mbed_official	610:813dcc80987e	159	*/
mbed_official	610:813dcc80987e	160
mbed_official	610:813dcc80987e	161	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
mbed_official	610:813dcc80987e	162	* @{
mbed_official	610:813dcc80987e	163	*/
mbed_official	610:813dcc80987e	164	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	165	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
mbed_official	610:813dcc80987e	166
mbed_official	610:813dcc80987e	167	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
mbed_official	610:813dcc80987e	168	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
mbed_official	610:813dcc80987e	169	/**
mbed_official	610:813dcc80987e	170	* @}
mbed_official	610:813dcc80987e	171	*/
mbed_official	610:813dcc80987e	172
mbed_official	610:813dcc80987e	173	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
mbed_official	610:813dcc80987e	174	* @{
mbed_official	610:813dcc80987e	175	*/
mbed_official	610:813dcc80987e	176	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	177	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
mbed_official	610:813dcc80987e	178
mbed_official	610:813dcc80987e	179	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
mbed_official	610:813dcc80987e	180	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
mbed_official	610:813dcc80987e	181	/**
mbed_official	610:813dcc80987e	182	* @}
mbed_official	610:813dcc80987e	183	*/
mbed_official	610:813dcc80987e	184
mbed_official	610:813dcc80987e	185	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
mbed_official	610:813dcc80987e	186	* @{
mbed_official	610:813dcc80987e	187	*/
mbed_official	610:813dcc80987e	188	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	189	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
mbed_official	610:813dcc80987e	190	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
mbed_official	610:813dcc80987e	191
mbed_official	610:813dcc80987e	192	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
mbed_official	610:813dcc80987e	193	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
mbed_official	610:813dcc80987e	194	((WIDE) == SDMMC_BUS_WIDE_8B))
mbed_official	610:813dcc80987e	195	/**
mbed_official	610:813dcc80987e	196	* @}
mbed_official	610:813dcc80987e	197	*/
mbed_official	610:813dcc80987e	198
mbed_official	610:813dcc80987e	199	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
mbed_official	610:813dcc80987e	200	* @{
mbed_official	610:813dcc80987e	201	*/
mbed_official	610:813dcc80987e	202	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	203	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
mbed_official	610:813dcc80987e	204
mbed_official	610:813dcc80987e	205	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
mbed_official	610:813dcc80987e	206	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
mbed_official	610:813dcc80987e	207	/**
mbed_official	610:813dcc80987e	208	* @}
mbed_official	610:813dcc80987e	209	*/
mbed_official	610:813dcc80987e	210
mbed_official	610:813dcc80987e	211	/** @defgroup SDMMC_LL_Clock_Division Clock Division
mbed_official	610:813dcc80987e	212	* @{
mbed_official	610:813dcc80987e	213	*/
mbed_official	610:813dcc80987e	214	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
mbed_official	610:813dcc80987e	215	/**
mbed_official	610:813dcc80987e	216	* @}
mbed_official	610:813dcc80987e	217	*/
mbed_official	610:813dcc80987e	218
mbed_official	610:813dcc80987e	219	/** @defgroup SDMMC_LL_Command_Index Command Index
mbed_official	610:813dcc80987e	220	* @{
mbed_official	610:813dcc80987e	221	*/
mbed_official	610:813dcc80987e	222	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
mbed_official	610:813dcc80987e	223	/**
mbed_official	610:813dcc80987e	224	* @}
mbed_official	610:813dcc80987e	225	*/
mbed_official	610:813dcc80987e	226
mbed_official	610:813dcc80987e	227	/** @defgroup SDMMC_LL_Response_Type Response Type
mbed_official	610:813dcc80987e	228	* @{
mbed_official	610:813dcc80987e	229	*/
mbed_official	610:813dcc80987e	230	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	231	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
mbed_official	610:813dcc80987e	232	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
mbed_official	610:813dcc80987e	233
mbed_official	610:813dcc80987e	234	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
mbed_official	610:813dcc80987e	235	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
mbed_official	610:813dcc80987e	236	((RESPONSE) == SDMMC_RESPONSE_LONG))
mbed_official	610:813dcc80987e	237	/**
mbed_official	610:813dcc80987e	238	* @}
mbed_official	610:813dcc80987e	239	*/
mbed_official	610:813dcc80987e	240
mbed_official	610:813dcc80987e	241	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
mbed_official	610:813dcc80987e	242	* @{
mbed_official	610:813dcc80987e	243	*/
mbed_official	610:813dcc80987e	244	#define SDMMC_WAIT_NO ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	245	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
mbed_official	610:813dcc80987e	246	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
mbed_official	610:813dcc80987e	247
mbed_official	610:813dcc80987e	248	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
mbed_official	610:813dcc80987e	249	((WAIT) == SDMMC_WAIT_IT) \|\| \
mbed_official	610:813dcc80987e	250	((WAIT) == SDMMC_WAIT_PEND))
mbed_official	610:813dcc80987e	251	/**
mbed_official	610:813dcc80987e	252	* @}
mbed_official	610:813dcc80987e	253	*/
mbed_official	610:813dcc80987e	254
mbed_official	610:813dcc80987e	255	/** @defgroup SDMMC_LL_CPSM_State CPSM State
mbed_official	610:813dcc80987e	256	* @{
mbed_official	610:813dcc80987e	257	*/
mbed_official	610:813dcc80987e	258	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	259	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
mbed_official	610:813dcc80987e	260
mbed_official	610:813dcc80987e	261	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
mbed_official	610:813dcc80987e	262	((CPSM) == SDMMC_CPSM_ENABLE))
mbed_official	610:813dcc80987e	263	/**
mbed_official	610:813dcc80987e	264	* @}
mbed_official	610:813dcc80987e	265	*/
mbed_official	610:813dcc80987e	266
mbed_official	610:813dcc80987e	267	/** @defgroup SDMMC_LL_Response_Registers Response Register
mbed_official	610:813dcc80987e	268	* @{
mbed_official	610:813dcc80987e	269	*/
mbed_official	610:813dcc80987e	270	#define SDMMC_RESP1 ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	271	#define SDMMC_RESP2 ((uint32_t)0x00000004)
mbed_official	610:813dcc80987e	272	#define SDMMC_RESP3 ((uint32_t)0x00000008)
mbed_official	610:813dcc80987e	273	#define SDMMC_RESP4 ((uint32_t)0x0000000C)
mbed_official	610:813dcc80987e	274
mbed_official	610:813dcc80987e	275	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
mbed_official	610:813dcc80987e	276	((RESP) == SDMMC_RESP2) \|\| \
mbed_official	610:813dcc80987e	277	((RESP) == SDMMC_RESP3) \|\| \
mbed_official	610:813dcc80987e	278	((RESP) == SDMMC_RESP4))
mbed_official	610:813dcc80987e	279	/**
mbed_official	610:813dcc80987e	280	* @}
mbed_official	610:813dcc80987e	281	*/
mbed_official	610:813dcc80987e	282
mbed_official	610:813dcc80987e	283	/** @defgroup SDMMC_LL_Data_Length Data Lenght
mbed_official	610:813dcc80987e	284	* @{
mbed_official	610:813dcc80987e	285	*/
mbed_official	610:813dcc80987e	286	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
mbed_official	610:813dcc80987e	287	/**
mbed_official	610:813dcc80987e	288	* @}
mbed_official	610:813dcc80987e	289	*/
mbed_official	610:813dcc80987e	290
mbed_official	610:813dcc80987e	291	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
mbed_official	610:813dcc80987e	292	* @{
mbed_official	610:813dcc80987e	293	*/
mbed_official	610:813dcc80987e	294	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	295	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
mbed_official	610:813dcc80987e	296	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
mbed_official	610:813dcc80987e	297	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
mbed_official	610:813dcc80987e	298	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
mbed_official	610:813dcc80987e	299	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
mbed_official	610:813dcc80987e	300	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
mbed_official	610:813dcc80987e	301	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
mbed_official	610:813dcc80987e	302	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
mbed_official	610:813dcc80987e	303	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official	610:813dcc80987e	304	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official	610:813dcc80987e	305	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official	610:813dcc80987e	306	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official	610:813dcc80987e	307	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official	610:813dcc80987e	308	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
mbed_official	610:813dcc80987e	309
mbed_official	610:813dcc80987e	310	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
mbed_official	610:813dcc80987e	311	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
mbed_official	610:813dcc80987e	312	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
mbed_official	610:813dcc80987e	313	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
mbed_official	610:813dcc80987e	314	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
mbed_official	610:813dcc80987e	315	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
mbed_official	610:813dcc80987e	316	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
mbed_official	610:813dcc80987e	317	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
mbed_official	610:813dcc80987e	318	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
mbed_official	610:813dcc80987e	319	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
mbed_official	610:813dcc80987e	320	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
mbed_official	610:813dcc80987e	321	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
mbed_official	610:813dcc80987e	322	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
mbed_official	610:813dcc80987e	323	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
mbed_official	610:813dcc80987e	324	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
mbed_official	610:813dcc80987e	325	/**
mbed_official	610:813dcc80987e	326	* @}
mbed_official	610:813dcc80987e	327	*/
mbed_official	610:813dcc80987e	328
mbed_official	610:813dcc80987e	329	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
mbed_official	610:813dcc80987e	330	* @{
mbed_official	610:813dcc80987e	331	*/
mbed_official	610:813dcc80987e	332	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	333	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
mbed_official	610:813dcc80987e	334
mbed_official	610:813dcc80987e	335	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
mbed_official	610:813dcc80987e	336	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
mbed_official	610:813dcc80987e	337	/**
mbed_official	610:813dcc80987e	338	* @}
mbed_official	610:813dcc80987e	339	*/
mbed_official	610:813dcc80987e	340
mbed_official	610:813dcc80987e	341	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
mbed_official	610:813dcc80987e	342	* @{
mbed_official	610:813dcc80987e	343	*/
mbed_official	610:813dcc80987e	344	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	345	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
mbed_official	610:813dcc80987e	346
mbed_official	610:813dcc80987e	347	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
mbed_official	610:813dcc80987e	348	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
mbed_official	610:813dcc80987e	349	/**
mbed_official	610:813dcc80987e	350	* @}
mbed_official	610:813dcc80987e	351	*/
mbed_official	610:813dcc80987e	352
mbed_official	610:813dcc80987e	353	/** @defgroup SDMMC_LL_DPSM_State DPSM State
mbed_official	610:813dcc80987e	354	* @{
mbed_official	610:813dcc80987e	355	*/
mbed_official	610:813dcc80987e	356	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	357	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
mbed_official	610:813dcc80987e	358
mbed_official	610:813dcc80987e	359	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
mbed_official	610:813dcc80987e	360	((DPSM) == SDMMC_DPSM_ENABLE))
mbed_official	610:813dcc80987e	361	/**
mbed_official	610:813dcc80987e	362	* @}
mbed_official	610:813dcc80987e	363	*/
mbed_official	610:813dcc80987e	364
mbed_official	610:813dcc80987e	365	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
mbed_official	610:813dcc80987e	366	* @{
mbed_official	610:813dcc80987e	367	*/
mbed_official	610:813dcc80987e	368	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
mbed_official	610:813dcc80987e	369	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
mbed_official	610:813dcc80987e	370
mbed_official	610:813dcc80987e	371	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
mbed_official	610:813dcc80987e	372	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
mbed_official	610:813dcc80987e	373	/**
mbed_official	610:813dcc80987e	374	* @}
mbed_official	610:813dcc80987e	375	*/
mbed_official	610:813dcc80987e	376
mbed_official	610:813dcc80987e	377	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
mbed_official	610:813dcc80987e	378	* @{
mbed_official	610:813dcc80987e	379	*/
mbed_official	610:813dcc80987e	380	#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
mbed_official	610:813dcc80987e	381	#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
mbed_official	610:813dcc80987e	382	#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
mbed_official	610:813dcc80987e	383	#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
mbed_official	610:813dcc80987e	384	#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
mbed_official	610:813dcc80987e	385	#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
mbed_official	610:813dcc80987e	386	#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
mbed_official	610:813dcc80987e	387	#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
mbed_official	610:813dcc80987e	388	#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
mbed_official	610:813dcc80987e	389	#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
mbed_official	610:813dcc80987e	390	#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
mbed_official	610:813dcc80987e	391	#define SDMMC_IT_TXACT SDMMC_STA_TXACT
mbed_official	610:813dcc80987e	392	#define SDMMC_IT_RXACT SDMMC_STA_RXACT
mbed_official	610:813dcc80987e	393	#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
mbed_official	610:813dcc80987e	394	#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
mbed_official	610:813dcc80987e	395	#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
mbed_official	610:813dcc80987e	396	#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
mbed_official	610:813dcc80987e	397	#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
mbed_official	610:813dcc80987e	398	#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
mbed_official	610:813dcc80987e	399	#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
mbed_official	610:813dcc80987e	400	#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
mbed_official	610:813dcc80987e	401	#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
mbed_official	610:813dcc80987e	402	/**
mbed_official	610:813dcc80987e	403	* @}
mbed_official	610:813dcc80987e	404	*/
mbed_official	610:813dcc80987e	405
mbed_official	610:813dcc80987e	406	/** @defgroup SDMMC_LL_Flags Flags
mbed_official	610:813dcc80987e	407	* @{
mbed_official	610:813dcc80987e	408	*/
mbed_official	610:813dcc80987e	409	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
mbed_official	610:813dcc80987e	410	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
mbed_official	610:813dcc80987e	411	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
mbed_official	610:813dcc80987e	412	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
mbed_official	610:813dcc80987e	413	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
mbed_official	610:813dcc80987e	414	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
mbed_official	610:813dcc80987e	415	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
mbed_official	610:813dcc80987e	416	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
mbed_official	610:813dcc80987e	417	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
mbed_official	610:813dcc80987e	418	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
mbed_official	610:813dcc80987e	419	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
mbed_official	610:813dcc80987e	420	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
mbed_official	610:813dcc80987e	421	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
mbed_official	610:813dcc80987e	422	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
mbed_official	610:813dcc80987e	423	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
mbed_official	610:813dcc80987e	424	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
mbed_official	610:813dcc80987e	425	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
mbed_official	610:813dcc80987e	426	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
mbed_official	610:813dcc80987e	427	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
mbed_official	610:813dcc80987e	428	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
mbed_official	610:813dcc80987e	429	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
mbed_official	610:813dcc80987e	430	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
mbed_official	610:813dcc80987e	431	/**
mbed_official	610:813dcc80987e	432	* @}
mbed_official	610:813dcc80987e	433	*/
mbed_official	610:813dcc80987e	434
mbed_official	610:813dcc80987e	435	/**
mbed_official	610:813dcc80987e	436	* @}
mbed_official	610:813dcc80987e	437	*/
mbed_official	610:813dcc80987e	438
mbed_official	610:813dcc80987e	439	/* Exported macro ------------------------------------------------------------*/
mbed_official	610:813dcc80987e	440	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
mbed_official	610:813dcc80987e	441	* @{
mbed_official	610:813dcc80987e	442	*/
mbed_official	610:813dcc80987e	443
mbed_official	610:813dcc80987e	444	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
mbed_official	610:813dcc80987e	445	* @brief SDMMC_LL registers bit address in the alias region
mbed_official	610:813dcc80987e	446	* @{
mbed_official	610:813dcc80987e	447	*/
mbed_official	610:813dcc80987e	448	/* ---------------------- SDMMC registers bit mask --------------------------- */
mbed_official	610:813dcc80987e	449	/* --- CLKCR Register ---*/
mbed_official	610:813dcc80987e	450	/* CLKCR register clear mask */
mbed_official	610:813dcc80987e	451	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
mbed_official	610:813dcc80987e	452	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
mbed_official	610:813dcc80987e	453	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
mbed_official	610:813dcc80987e	454
mbed_official	610:813dcc80987e	455	/* --- DCTRL Register ---*/
mbed_official	610:813dcc80987e	456	/* SDMMC DCTRL Clear Mask */
mbed_official	610:813dcc80987e	457	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
mbed_official	610:813dcc80987e	458	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
mbed_official	610:813dcc80987e	459
mbed_official	610:813dcc80987e	460	/* --- CMD Register ---*/
mbed_official	610:813dcc80987e	461	/* CMD Register clear mask */
mbed_official	610:813dcc80987e	462	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
mbed_official	610:813dcc80987e	463	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
mbed_official	610:813dcc80987e	464	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
mbed_official	610:813dcc80987e	465
mbed_official	610:813dcc80987e	466	/* SDMMC Intialization Frequency (400KHz max) */
mbed_official	610:813dcc80987e	467	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
mbed_official	610:813dcc80987e	468
mbed_official	610:813dcc80987e	469	/* SDMMC Data Transfer Frequency (25MHz max) */
mbed_official	610:813dcc80987e	470	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
mbed_official	610:813dcc80987e	471
mbed_official	610:813dcc80987e	472	/**
mbed_official	610:813dcc80987e	473	* @}
mbed_official	610:813dcc80987e	474	*/
mbed_official	610:813dcc80987e	475
mbed_official	610:813dcc80987e	476	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
mbed_official	610:813dcc80987e	477	* @brief macros to handle interrupts and specific clock configurations
mbed_official	610:813dcc80987e	478	* @{
mbed_official	610:813dcc80987e	479	*/
mbed_official	610:813dcc80987e	480
mbed_official	610:813dcc80987e	481	/**
mbed_official	610:813dcc80987e	482	* @brief Enable the SDMMC device.
mbed_official	610:813dcc80987e	483	* @param __INSTANCE__: SDMMC Instance
mbed_official	610:813dcc80987e	484	* @retval None
mbed_official	610:813dcc80987e	485	*/
mbed_official	610:813dcc80987e	486	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
mbed_official	610:813dcc80987e	487
mbed_official	610:813dcc80987e	488	/**
mbed_official	610:813dcc80987e	489	* @brief Disable the SDMMC device.
mbed_official	610:813dcc80987e	490	* @param __INSTANCE__: SDMMC Instance
mbed_official	610:813dcc80987e	491	* @retval None
mbed_official	610:813dcc80987e	492	*/
mbed_official	610:813dcc80987e	493	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
mbed_official	610:813dcc80987e	494
mbed_official	610:813dcc80987e	495	/**
mbed_official	610:813dcc80987e	496	* @brief Enable the SDMMC DMA transfer.
mbed_official	610:813dcc80987e	497	* @param None
mbed_official	610:813dcc80987e	498	* @retval None
mbed_official	610:813dcc80987e	499	*/
mbed_official	610:813dcc80987e	500	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
mbed_official	610:813dcc80987e	501	/**
mbed_official	610:813dcc80987e	502	* @brief Disable the SDMMC DMA transfer.
mbed_official	610:813dcc80987e	503	* @param None
mbed_official	610:813dcc80987e	504	* @retval None
mbed_official	610:813dcc80987e	505	*/
mbed_official	610:813dcc80987e	506	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
mbed_official	610:813dcc80987e	507
mbed_official	610:813dcc80987e	508	/**
mbed_official	610:813dcc80987e	509	* @brief Enable the SDMMC device interrupt.
mbed_official	610:813dcc80987e	510	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	511	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
mbed_official	610:813dcc80987e	512	* This parameter can be one or a combination of the following values:
mbed_official	610:813dcc80987e	513	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	514	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	515	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official	610:813dcc80987e	516	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official	610:813dcc80987e	517	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official	610:813dcc80987e	518	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official	610:813dcc80987e	519	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	520	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official	610:813dcc80987e	521	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official	610:813dcc80987e	522	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	523	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
mbed_official	610:813dcc80987e	524	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
mbed_official	610:813dcc80987e	525	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
mbed_official	610:813dcc80987e	526	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official	610:813dcc80987e	527	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official	610:813dcc80987e	528	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official	610:813dcc80987e	529	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official	610:813dcc80987e	530	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official	610:813dcc80987e	531	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official	610:813dcc80987e	532	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official	610:813dcc80987e	533	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official	610:813dcc80987e	534	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official	610:813dcc80987e	535	* @retval None
mbed_official	610:813dcc80987e	536	*/
mbed_official	610:813dcc80987e	537	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
mbed_official	610:813dcc80987e	538
mbed_official	610:813dcc80987e	539	/**
mbed_official	610:813dcc80987e	540	* @brief Disable the SDMMC device interrupt.
mbed_official	610:813dcc80987e	541	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	542	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
mbed_official	610:813dcc80987e	543	* This parameter can be one or a combination of the following values:
mbed_official	610:813dcc80987e	544	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	545	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	546	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official	610:813dcc80987e	547	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official	610:813dcc80987e	548	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official	610:813dcc80987e	549	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official	610:813dcc80987e	550	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	551	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official	610:813dcc80987e	552	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official	610:813dcc80987e	553	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	554	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
mbed_official	610:813dcc80987e	555	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
mbed_official	610:813dcc80987e	556	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
mbed_official	610:813dcc80987e	557	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official	610:813dcc80987e	558	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official	610:813dcc80987e	559	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official	610:813dcc80987e	560	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official	610:813dcc80987e	561	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official	610:813dcc80987e	562	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official	610:813dcc80987e	563	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official	610:813dcc80987e	564	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official	610:813dcc80987e	565	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official	610:813dcc80987e	566	* @retval None
mbed_official	610:813dcc80987e	567	*/
mbed_official	610:813dcc80987e	568	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
mbed_official	610:813dcc80987e	569
mbed_official	610:813dcc80987e	570	/**
mbed_official	610:813dcc80987e	571	* @brief Checks whether the specified SDMMC flag is set or not.
mbed_official	610:813dcc80987e	572	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	573	* @param __FLAG__: specifies the flag to check.
mbed_official	610:813dcc80987e	574	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	575	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official	610:813dcc80987e	576	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official	610:813dcc80987e	577	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
mbed_official	610:813dcc80987e	578	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
mbed_official	610:813dcc80987e	579	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official	610:813dcc80987e	580	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
mbed_official	610:813dcc80987e	581	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official	610:813dcc80987e	582	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
mbed_official	610:813dcc80987e	583	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official	610:813dcc80987e	584	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official	610:813dcc80987e	585	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
mbed_official	610:813dcc80987e	586	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
mbed_official	610:813dcc80987e	587	* @arg SDMMC_FLAG_RXACT: Data receive in progress
mbed_official	610:813dcc80987e	588	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
mbed_official	610:813dcc80987e	589	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
mbed_official	610:813dcc80987e	590	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
mbed_official	610:813dcc80987e	591	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
mbed_official	610:813dcc80987e	592	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
mbed_official	610:813dcc80987e	593	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
mbed_official	610:813dcc80987e	594	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
mbed_official	610:813dcc80987e	595	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
mbed_official	610:813dcc80987e	596	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
mbed_official	610:813dcc80987e	597	* @retval The new state of SDMMC_FLAG (SET or RESET).
mbed_official	610:813dcc80987e	598	*/
mbed_official	610:813dcc80987e	599	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
mbed_official	610:813dcc80987e	600
mbed_official	610:813dcc80987e	601
mbed_official	610:813dcc80987e	602	/**
mbed_official	610:813dcc80987e	603	* @brief Clears the SDMMC pending flags.
mbed_official	610:813dcc80987e	604	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	605	* @param __FLAG__: specifies the flag to clear.
mbed_official	610:813dcc80987e	606	* This parameter can be one or a combination of the following values:
mbed_official	610:813dcc80987e	607	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official	610:813dcc80987e	608	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official	610:813dcc80987e	609	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
mbed_official	610:813dcc80987e	610	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
mbed_official	610:813dcc80987e	611	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official	610:813dcc80987e	612	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
mbed_official	610:813dcc80987e	613	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official	610:813dcc80987e	614	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
mbed_official	610:813dcc80987e	615	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official	610:813dcc80987e	616	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official	610:813dcc80987e	617	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
mbed_official	610:813dcc80987e	618	* @retval None
mbed_official	610:813dcc80987e	619	*/
mbed_official	610:813dcc80987e	620	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
mbed_official	610:813dcc80987e	621
mbed_official	610:813dcc80987e	622	/**
mbed_official	610:813dcc80987e	623	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
mbed_official	610:813dcc80987e	624	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	625	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
mbed_official	610:813dcc80987e	626	* This parameter can be one of the following values:
mbed_official	610:813dcc80987e	627	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	628	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	629	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official	610:813dcc80987e	630	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official	610:813dcc80987e	631	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official	610:813dcc80987e	632	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official	610:813dcc80987e	633	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	634	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official	610:813dcc80987e	635	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official	610:813dcc80987e	636	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	637	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
mbed_official	610:813dcc80987e	638	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
mbed_official	610:813dcc80987e	639	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
mbed_official	610:813dcc80987e	640	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official	610:813dcc80987e	641	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official	610:813dcc80987e	642	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official	610:813dcc80987e	643	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official	610:813dcc80987e	644	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official	610:813dcc80987e	645	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official	610:813dcc80987e	646	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official	610:813dcc80987e	647	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official	610:813dcc80987e	648	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official	610:813dcc80987e	649	* @retval The new state of SDMMC_IT (SET or RESET).
mbed_official	610:813dcc80987e	650	*/
mbed_official	610:813dcc80987e	651	#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	610:813dcc80987e	652
mbed_official	610:813dcc80987e	653	/**
mbed_official	610:813dcc80987e	654	* @brief Clears the SDMMC's interrupt pending bits.
mbed_official	610:813dcc80987e	655	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	656	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	610:813dcc80987e	657	* This parameter can be one or a combination of the following values:
mbed_official	610:813dcc80987e	658	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	659	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official	610:813dcc80987e	660	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
mbed_official	610:813dcc80987e	661	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
mbed_official	610:813dcc80987e	662	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official	610:813dcc80987e	663	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official	610:813dcc80987e	664	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official	610:813dcc80987e	665	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official	610:813dcc80987e	666	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
mbed_official	610:813dcc80987e	667	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official	610:813dcc80987e	668	* @retval None
mbed_official	610:813dcc80987e	669	*/
mbed_official	610:813dcc80987e	670	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
mbed_official	610:813dcc80987e	671
mbed_official	610:813dcc80987e	672	/**
mbed_official	610:813dcc80987e	673	* @brief Enable Start the SD I/O Read Wait operation.
mbed_official	610:813dcc80987e	674	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	675	* @retval None
mbed_official	610:813dcc80987e	676	*/
mbed_official	610:813dcc80987e	677	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
mbed_official	610:813dcc80987e	678
mbed_official	610:813dcc80987e	679	/**
mbed_official	610:813dcc80987e	680	* @brief Disable Start the SD I/O Read Wait operations.
mbed_official	610:813dcc80987e	681	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	682	* @retval None
mbed_official	610:813dcc80987e	683	*/
mbed_official	610:813dcc80987e	684	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
mbed_official	610:813dcc80987e	685
mbed_official	610:813dcc80987e	686	/**
mbed_official	610:813dcc80987e	687	* @brief Enable Start the SD I/O Read Wait operation.
mbed_official	610:813dcc80987e	688	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	689	* @retval None
mbed_official	610:813dcc80987e	690	*/
mbed_official	610:813dcc80987e	691	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
mbed_official	610:813dcc80987e	692
mbed_official	610:813dcc80987e	693	/**
mbed_official	610:813dcc80987e	694	* @brief Disable Stop the SD I/O Read Wait operations.
mbed_official	610:813dcc80987e	695	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	696	* @retval None
mbed_official	610:813dcc80987e	697	*/
mbed_official	610:813dcc80987e	698	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
mbed_official	610:813dcc80987e	699
mbed_official	610:813dcc80987e	700	/**
mbed_official	610:813dcc80987e	701	* @brief Enable the SD I/O Mode Operation.
mbed_official	610:813dcc80987e	702	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	703	* @retval None
mbed_official	610:813dcc80987e	704	*/
mbed_official	610:813dcc80987e	705	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
mbed_official	610:813dcc80987e	706
mbed_official	610:813dcc80987e	707	/**
mbed_official	610:813dcc80987e	708	* @brief Disable the SD I/O Mode Operation.
mbed_official	610:813dcc80987e	709	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	710	* @retval None
mbed_official	610:813dcc80987e	711	*/
mbed_official	610:813dcc80987e	712	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
mbed_official	610:813dcc80987e	713
mbed_official	610:813dcc80987e	714	/**
mbed_official	610:813dcc80987e	715	* @brief Enable the SD I/O Suspend command sending.
mbed_official	610:813dcc80987e	716	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	717	* @retval None
mbed_official	610:813dcc80987e	718	*/
mbed_official	610:813dcc80987e	719	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
mbed_official	610:813dcc80987e	720
mbed_official	610:813dcc80987e	721	/**
mbed_official	610:813dcc80987e	722	* @brief Disable the SD I/O Suspend command sending.
mbed_official	610:813dcc80987e	723	* @param __INSTANCE__: Pointer to SDMMC register base
mbed_official	610:813dcc80987e	724	* @retval None
mbed_official	610:813dcc80987e	725	*/
mbed_official	610:813dcc80987e	726	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
mbed_official	610:813dcc80987e	727
mbed_official	610:813dcc80987e	728	/**
mbed_official	610:813dcc80987e	729	* @}
mbed_official	610:813dcc80987e	730	*/
mbed_official	610:813dcc80987e	731
mbed_official	610:813dcc80987e	732	/**
mbed_official	610:813dcc80987e	733	* @}
mbed_official	610:813dcc80987e	734	*/
mbed_official	610:813dcc80987e	735
mbed_official	610:813dcc80987e	736	/* Exported functions --------------------------------------------------------*/
mbed_official	610:813dcc80987e	737	/** @addtogroup SDMMC_LL_Exported_Functions
mbed_official	610:813dcc80987e	738	* @{
mbed_official	610:813dcc80987e	739	*/
mbed_official	610:813dcc80987e	740
mbed_official	610:813dcc80987e	741	/* Initialization/de-initialization functions **********************************/
mbed_official	610:813dcc80987e	742	/** @addtogroup HAL_SDMMC_LL_Group1
mbed_official	610:813dcc80987e	743	* @{
mbed_official	610:813dcc80987e	744	*/
mbed_official	610:813dcc80987e	745	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
mbed_official	610:813dcc80987e	746	/**
mbed_official	610:813dcc80987e	747	* @}
mbed_official	610:813dcc80987e	748	*/
mbed_official	610:813dcc80987e	749
mbed_official	610:813dcc80987e	750	/* I/O operation functions *****************************************************/
mbed_official	610:813dcc80987e	751	/** @addtogroup HAL_SDMMC_LL_Group2
mbed_official	610:813dcc80987e	752	* @{
mbed_official	610:813dcc80987e	753	*/
mbed_official	610:813dcc80987e	754	/* Blocking mode: Polling */
mbed_official	610:813dcc80987e	755	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	756	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
mbed_official	610:813dcc80987e	757	/**
mbed_official	610:813dcc80987e	758	* @}
mbed_official	610:813dcc80987e	759	*/
mbed_official	610:813dcc80987e	760
mbed_official	610:813dcc80987e	761	/* Peripheral Control functions ************************************************/
mbed_official	610:813dcc80987e	762	/** @addtogroup HAL_SDMMC_LL_Group3
mbed_official	610:813dcc80987e	763	* @{
mbed_official	610:813dcc80987e	764	*/
mbed_official	610:813dcc80987e	765	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	766	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	767	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	768
mbed_official	610:813dcc80987e	769	/* Command path state machine (CPSM) management functions */
mbed_official	610:813dcc80987e	770	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
mbed_official	610:813dcc80987e	771	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	772	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
mbed_official	610:813dcc80987e	773
mbed_official	610:813dcc80987e	774	/* Data path state machine (DPSM) management functions */
mbed_official	610:813dcc80987e	775	HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
mbed_official	610:813dcc80987e	776	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	777	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
mbed_official	610:813dcc80987e	778
mbed_official	610:813dcc80987e	779	/* SDMMC Cards mode management functions */
mbed_official	610:813dcc80987e	780	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
mbed_official	610:813dcc80987e	781
mbed_official	610:813dcc80987e	782	/**
mbed_official	610:813dcc80987e	783	* @}
mbed_official	610:813dcc80987e	784	*/
mbed_official	610:813dcc80987e	785
mbed_official	610:813dcc80987e	786	/**
mbed_official	610:813dcc80987e	787	* @}
mbed_official	610:813dcc80987e	788	*/
mbed_official	610:813dcc80987e	789
mbed_official	610:813dcc80987e	790	/**
mbed_official	610:813dcc80987e	791	* @}
mbed_official	610:813dcc80987e	792	*/
mbed_official	610:813dcc80987e	793
mbed_official	610:813dcc80987e	794	/**
mbed_official	610:813dcc80987e	795	* @}
mbed_official	610:813dcc80987e	796	*/
mbed_official	610:813dcc80987e	797
mbed_official	610:813dcc80987e	798	#ifdef __cplusplus
mbed_official	610:813dcc80987e	799	}
mbed_official	610:813dcc80987e	800	#endif
mbed_official	610:813dcc80987e	801
mbed_official	610:813dcc80987e	802	#endif /* __STM32L4xx_LL_SDMMC_H */
mbed_official	610:813dcc80987e	803
mbed_official	610:813dcc80987e	804	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/