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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c@600:7d17ca308cd1, 2015-07-31 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 31 14:15:09 2015 +0100
- Revision:
- 600:7d17ca308cd1
- Parent:
- 472:7bbab527289d
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0
Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/
Enable LPC8xx usart when configuring it
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 359:275f0f27ea18 | 1 | /****************************************************************************** |
| mbed_official | 359:275f0f27ea18 | 2 | * @file: system_LPC8xx.c |
| mbed_official | 359:275f0f27ea18 | 3 | * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File |
| mbed_official | 359:275f0f27ea18 | 4 | * for the NXP LPC8xx Device Series |
| mbed_official | 359:275f0f27ea18 | 5 | * @version: V1.0 |
| mbed_official | 359:275f0f27ea18 | 6 | * @date: 16. Aug. 2012 |
| mbed_official | 359:275f0f27ea18 | 7 | *---------------------------------------------------------------------------- |
| mbed_official | 359:275f0f27ea18 | 8 | * |
| mbed_official | 359:275f0f27ea18 | 9 | * Copyright (C) 2012 ARM Limited. All rights reserved. |
| mbed_official | 359:275f0f27ea18 | 10 | * |
| mbed_official | 359:275f0f27ea18 | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ |
| mbed_official | 359:275f0f27ea18 | 12 | * processor based microcontrollers. This file can be freely distributed |
| mbed_official | 359:275f0f27ea18 | 13 | * within development tools that are supporting such ARM based processors. |
| mbed_official | 359:275f0f27ea18 | 14 | * |
| mbed_official | 359:275f0f27ea18 | 15 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| mbed_official | 359:275f0f27ea18 | 16 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| mbed_official | 359:275f0f27ea18 | 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| mbed_official | 359:275f0f27ea18 | 18 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| mbed_official | 359:275f0f27ea18 | 19 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| mbed_official | 359:275f0f27ea18 | 20 | * |
| mbed_official | 359:275f0f27ea18 | 21 | ******************************************************************************/ |
| mbed_official | 359:275f0f27ea18 | 22 | #include <stdint.h> |
| mbed_official | 359:275f0f27ea18 | 23 | #include "LPC82x.h" |
| mbed_official | 359:275f0f27ea18 | 24 | |
| mbed_official | 359:275f0f27ea18 | 25 | /* |
| mbed_official | 359:275f0f27ea18 | 26 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| mbed_official | 359:275f0f27ea18 | 27 | */ |
| mbed_official | 359:275f0f27ea18 | 28 | |
| mbed_official | 359:275f0f27ea18 | 29 | /*--------------------- Clock Configuration ----------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 30 | // |
| mbed_official | 359:275f0f27ea18 | 31 | // <e> Clock Configuration |
| mbed_official | 359:275f0f27ea18 | 32 | #define CLOCK_SETUP 1 |
| mbed_official | 359:275f0f27ea18 | 33 | // <h> System Oscillator Control Register (SYSOSCCTRL) |
| mbed_official | 359:275f0f27ea18 | 34 | // <o.0> BYPASS: System Oscillator Bypass Enable |
| mbed_official | 359:275f0f27ea18 | 35 | // <i> If enabled then PLL input (sys_osc_clk) is fed |
| mbed_official | 359:275f0f27ea18 | 36 | // <i> directly from XTALIN and XTALOUT pins. |
| mbed_official | 359:275f0f27ea18 | 37 | // <o.1> FREQRANGE: System Oscillator Frequency Range |
| mbed_official | 359:275f0f27ea18 | 38 | // <i> Determines frequency range for Low-power oscillator. |
| mbed_official | 359:275f0f27ea18 | 39 | // <0=> 1 - 20 MHz |
| mbed_official | 359:275f0f27ea18 | 40 | // <1=> 15 - 25 MHz |
| mbed_official | 359:275f0f27ea18 | 41 | // </h> |
| mbed_official | 359:275f0f27ea18 | 42 | #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 43 | // |
| mbed_official | 359:275f0f27ea18 | 44 | // <h> Watchdog Oscillator Control Register (WDTOSCCTRL) |
| mbed_official | 359:275f0f27ea18 | 45 | // <o.0..4> DIVSEL: Select Divider for Fclkana |
| mbed_official | 359:275f0f27ea18 | 46 | // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) |
| mbed_official | 359:275f0f27ea18 | 47 | // <0-31> |
| mbed_official | 359:275f0f27ea18 | 48 | // <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) |
| mbed_official | 359:275f0f27ea18 | 49 | // <0=> Undefined |
| mbed_official | 359:275f0f27ea18 | 50 | // <1=> 0.6 MHz |
| mbed_official | 359:275f0f27ea18 | 51 | // <2=> 1.05 MHz |
| mbed_official | 359:275f0f27ea18 | 52 | // <3=> 1.4 MHz |
| mbed_official | 359:275f0f27ea18 | 53 | // <4=> 1.75 MHz |
| mbed_official | 359:275f0f27ea18 | 54 | // <5=> 2.1 MHz |
| mbed_official | 359:275f0f27ea18 | 55 | // <6=> 2.4 MHz |
| mbed_official | 359:275f0f27ea18 | 56 | // <7=> 2.7 MHz |
| mbed_official | 359:275f0f27ea18 | 57 | // <8=> 3.0 MHz |
| mbed_official | 359:275f0f27ea18 | 58 | // <9=> 3.25 MHz |
| mbed_official | 359:275f0f27ea18 | 59 | // <10=> 3.5 MHz |
| mbed_official | 359:275f0f27ea18 | 60 | // <11=> 3.75 MHz |
| mbed_official | 359:275f0f27ea18 | 61 | // <12=> 4.0 MHz |
| mbed_official | 359:275f0f27ea18 | 62 | // <13=> 4.2 MHz |
| mbed_official | 359:275f0f27ea18 | 63 | // <14=> 4.4 MHz |
| mbed_official | 359:275f0f27ea18 | 64 | // <15=> 4.6 MHz |
| mbed_official | 359:275f0f27ea18 | 65 | #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 66 | // </h> |
| mbed_official | 359:275f0f27ea18 | 67 | // <h> System PLL Control Register (SYSPLLCTRL) |
| mbed_official | 359:275f0f27ea18 | 68 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| mbed_official | 359:275f0f27ea18 | 69 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| mbed_official | 359:275f0f27ea18 | 70 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| mbed_official | 359:275f0f27ea18 | 71 | // <o.0..4> MSEL: Feedback Divider Selection |
| mbed_official | 359:275f0f27ea18 | 72 | // <i> M = MSEL + 1 |
| mbed_official | 359:275f0f27ea18 | 73 | // <0-31> |
| mbed_official | 359:275f0f27ea18 | 74 | // <o.5..6> PSEL: Post Divider Selection |
| mbed_official | 359:275f0f27ea18 | 75 | // <0=> P = 1 |
| mbed_official | 359:275f0f27ea18 | 76 | // <1=> P = 2 |
| mbed_official | 359:275f0f27ea18 | 77 | // <2=> P = 4 |
| mbed_official | 359:275f0f27ea18 | 78 | // <3=> P = 8 |
| mbed_official | 359:275f0f27ea18 | 79 | // </h> |
| mbed_official | 359:275f0f27ea18 | 80 | #define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 81 | // |
| mbed_official | 359:275f0f27ea18 | 82 | // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL) |
| mbed_official | 359:275f0f27ea18 | 83 | // <o.0..1> SEL: System PLL Clock Source |
| mbed_official | 359:275f0f27ea18 | 84 | // <0=> IRC |
| mbed_official | 359:275f0f27ea18 | 85 | // <1=> Crystal Oscillator |
| mbed_official | 359:275f0f27ea18 | 86 | // <2=> Reserved |
| mbed_official | 359:275f0f27ea18 | 87 | // <3=> CLKIN. External clock input. |
| mbed_official | 359:275f0f27ea18 | 88 | // </h> |
| mbed_official | 472:7bbab527289d | 89 | #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 90 | // |
| mbed_official | 359:275f0f27ea18 | 91 | // <h> Main Clock Source Select Register (MAINCLKSEL) |
| mbed_official | 359:275f0f27ea18 | 92 | // <o.0..1> SEL: Clock Source for Main Clock |
| mbed_official | 359:275f0f27ea18 | 93 | // <0=> IRC Oscillator |
| mbed_official | 359:275f0f27ea18 | 94 | // <1=> PLL input |
| mbed_official | 359:275f0f27ea18 | 95 | // <2=> Watchdog Oscillator |
| mbed_official | 359:275f0f27ea18 | 96 | // <3=> PLL output |
| mbed_official | 359:275f0f27ea18 | 97 | // </h> |
| mbed_official | 359:275f0f27ea18 | 98 | #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 99 | // <h> System AHB Clock Divider Register (SYSAHBCLKDIV) |
| mbed_official | 359:275f0f27ea18 | 100 | // <o.0..7> DIV: System AHB Clock Divider |
| mbed_official | 359:275f0f27ea18 | 101 | // <i> Divides main clock to provide system clock to core, memories, and peripherals. |
| mbed_official | 359:275f0f27ea18 | 102 | // <i> 0 = is disabled |
| mbed_official | 359:275f0f27ea18 | 103 | // <0-255> |
| mbed_official | 359:275f0f27ea18 | 104 | // </h> |
| mbed_official | 359:275f0f27ea18 | 105 | #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 |
| mbed_official | 359:275f0f27ea18 | 106 | // </e> |
| mbed_official | 359:275f0f27ea18 | 107 | |
| mbed_official | 359:275f0f27ea18 | 108 | //#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: |
| mbed_official | 359:275f0f27ea18 | 109 | |
| mbed_official | 359:275f0f27ea18 | 110 | /* |
| mbed_official | 359:275f0f27ea18 | 111 | #if (CLOCK_SETUP == 0) |
| mbed_official | 359:275f0f27ea18 | 112 | #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 113 | #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 114 | #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 115 | #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 116 | #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 117 | #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 |
| mbed_official | 359:275f0f27ea18 | 118 | #elif (CLOCK_SETUP == 2) |
| mbed_official | 359:275f0f27ea18 | 119 | // #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 120 | #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 121 | #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 122 | #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 123 | #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 |
| mbed_official | 359:275f0f27ea18 | 124 | #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 |
| mbed_official | 359:275f0f27ea18 | 125 | #endif |
| mbed_official | 359:275f0f27ea18 | 126 | */ |
| mbed_official | 359:275f0f27ea18 | 127 | |
| mbed_official | 359:275f0f27ea18 | 128 | /* |
| mbed_official | 359:275f0f27ea18 | 129 | //-------- <<< end of configuration section >>> ------------------------------ |
| mbed_official | 359:275f0f27ea18 | 130 | */ |
| mbed_official | 359:275f0f27ea18 | 131 | |
| mbed_official | 359:275f0f27ea18 | 132 | /*---------------------------------------------------------------------------- |
| mbed_official | 359:275f0f27ea18 | 133 | Check the register settings |
| mbed_official | 359:275f0f27ea18 | 134 | *----------------------------------------------------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 135 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
| mbed_official | 359:275f0f27ea18 | 136 | #define CHECK_RSVD(val, mask) (val & mask) |
| mbed_official | 359:275f0f27ea18 | 137 | |
| mbed_official | 359:275f0f27ea18 | 138 | /* Clock Configuration -------------------------------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 139 | #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) |
| mbed_official | 359:275f0f27ea18 | 140 | #error "SYSOSCCTRL: Invalid values of reserved bits!" |
| mbed_official | 359:275f0f27ea18 | 141 | #endif |
| mbed_official | 359:275f0f27ea18 | 142 | |
| mbed_official | 359:275f0f27ea18 | 143 | #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) |
| mbed_official | 359:275f0f27ea18 | 144 | #error "WDTOSCCTRL: Invalid values of reserved bits!" |
| mbed_official | 359:275f0f27ea18 | 145 | #endif |
| mbed_official | 359:275f0f27ea18 | 146 | |
| mbed_official | 359:275f0f27ea18 | 147 | #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) |
| mbed_official | 359:275f0f27ea18 | 148 | #error "SYSPLLCLKSEL: Value out of range!" |
| mbed_official | 359:275f0f27ea18 | 149 | #endif |
| mbed_official | 359:275f0f27ea18 | 150 | |
| mbed_official | 359:275f0f27ea18 | 151 | #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) |
| mbed_official | 359:275f0f27ea18 | 152 | #error "SYSPLLCTRL: Invalid values of reserved bits!" |
| mbed_official | 359:275f0f27ea18 | 153 | #endif |
| mbed_official | 359:275f0f27ea18 | 154 | |
| mbed_official | 359:275f0f27ea18 | 155 | #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) |
| mbed_official | 359:275f0f27ea18 | 156 | #error "MAINCLKSEL: Invalid values of reserved bits!" |
| mbed_official | 359:275f0f27ea18 | 157 | #endif |
| mbed_official | 359:275f0f27ea18 | 158 | |
| mbed_official | 359:275f0f27ea18 | 159 | #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) |
| mbed_official | 359:275f0f27ea18 | 160 | #error "SYSAHBCLKDIV: Value out of range!" |
| mbed_official | 359:275f0f27ea18 | 161 | #endif |
| mbed_official | 359:275f0f27ea18 | 162 | |
| mbed_official | 359:275f0f27ea18 | 163 | |
| mbed_official | 359:275f0f27ea18 | 164 | /*---------------------------------------------------------------------------- |
| mbed_official | 359:275f0f27ea18 | 165 | DEFINES |
| mbed_official | 359:275f0f27ea18 | 166 | *----------------------------------------------------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 167 | |
| mbed_official | 359:275f0f27ea18 | 168 | /*---------------------------------------------------------------------------- |
| mbed_official | 359:275f0f27ea18 | 169 | Define clocks |
| mbed_official | 359:275f0f27ea18 | 170 | *----------------------------------------------------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 171 | #define __XTAL (12000000UL) /* Oscillator frequency */ |
| mbed_official | 359:275f0f27ea18 | 172 | #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ |
| mbed_official | 359:275f0f27ea18 | 173 | #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ |
| mbed_official | 359:275f0f27ea18 | 174 | #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ |
| mbed_official | 359:275f0f27ea18 | 175 | |
| mbed_official | 359:275f0f27ea18 | 176 | |
| mbed_official | 359:275f0f27ea18 | 177 | #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) |
| mbed_official | 359:275f0f27ea18 | 178 | #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) |
| mbed_official | 359:275f0f27ea18 | 179 | |
| mbed_official | 359:275f0f27ea18 | 180 | #if (CLOCK_SETUP) /* Clock Setup */ |
| mbed_official | 359:275f0f27ea18 | 181 | #if (__FREQSEL == 0) |
| mbed_official | 359:275f0f27ea18 | 182 | #define __WDT_OSC_CLK ( 0) /* undefined */ |
| mbed_official | 359:275f0f27ea18 | 183 | #elif (__FREQSEL == 1) |
| mbed_official | 359:275f0f27ea18 | 184 | #define __WDT_OSC_CLK ( 500000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 185 | #elif (__FREQSEL == 2) |
| mbed_official | 359:275f0f27ea18 | 186 | #define __WDT_OSC_CLK ( 800000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 187 | #elif (__FREQSEL == 3) |
| mbed_official | 359:275f0f27ea18 | 188 | #define __WDT_OSC_CLK (1100000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 189 | #elif (__FREQSEL == 4) |
| mbed_official | 359:275f0f27ea18 | 190 | #define __WDT_OSC_CLK (1400000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 191 | #elif (__FREQSEL == 5) |
| mbed_official | 359:275f0f27ea18 | 192 | #define __WDT_OSC_CLK (1600000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 193 | #elif (__FREQSEL == 6) |
| mbed_official | 359:275f0f27ea18 | 194 | #define __WDT_OSC_CLK (1800000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 195 | #elif (__FREQSEL == 7) |
| mbed_official | 359:275f0f27ea18 | 196 | #define __WDT_OSC_CLK (2000000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 197 | #elif (__FREQSEL == 8) |
| mbed_official | 359:275f0f27ea18 | 198 | #define __WDT_OSC_CLK (2200000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 199 | #elif (__FREQSEL == 9) |
| mbed_official | 359:275f0f27ea18 | 200 | #define __WDT_OSC_CLK (2400000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 201 | #elif (__FREQSEL == 10) |
| mbed_official | 359:275f0f27ea18 | 202 | #define __WDT_OSC_CLK (2600000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 203 | #elif (__FREQSEL == 11) |
| mbed_official | 359:275f0f27ea18 | 204 | #define __WDT_OSC_CLK (2700000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 205 | #elif (__FREQSEL == 12) |
| mbed_official | 359:275f0f27ea18 | 206 | #define __WDT_OSC_CLK (2900000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 207 | #elif (__FREQSEL == 13) |
| mbed_official | 359:275f0f27ea18 | 208 | #define __WDT_OSC_CLK (3100000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 209 | #elif (__FREQSEL == 14) |
| mbed_official | 359:275f0f27ea18 | 210 | #define __WDT_OSC_CLK (3200000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 211 | #else |
| mbed_official | 359:275f0f27ea18 | 212 | #define __WDT_OSC_CLK (3400000 / __DIVSEL) |
| mbed_official | 359:275f0f27ea18 | 213 | #endif |
| mbed_official | 359:275f0f27ea18 | 214 | |
| mbed_official | 359:275f0f27ea18 | 215 | /* sys_pllclkin calculation */ |
| mbed_official | 359:275f0f27ea18 | 216 | #if ((SYSPLLCLKSEL_Val & 0x03) == 0) |
| mbed_official | 359:275f0f27ea18 | 217 | #define __SYS_PLLCLKIN (__IRC_OSC_CLK) |
| mbed_official | 359:275f0f27ea18 | 218 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) |
| mbed_official | 359:275f0f27ea18 | 219 | #define __SYS_PLLCLKIN (__SYS_OSC_CLK) |
| mbed_official | 359:275f0f27ea18 | 220 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) |
| mbed_official | 359:275f0f27ea18 | 221 | #define __SYS_PLLCLKIN (__CLKIN_CLK) |
| mbed_official | 359:275f0f27ea18 | 222 | #else |
| mbed_official | 359:275f0f27ea18 | 223 | #define __SYS_PLLCLKIN (0) |
| mbed_official | 359:275f0f27ea18 | 224 | #endif |
| mbed_official | 359:275f0f27ea18 | 225 | |
| mbed_official | 359:275f0f27ea18 | 226 | #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) |
| mbed_official | 359:275f0f27ea18 | 227 | |
| mbed_official | 359:275f0f27ea18 | 228 | /* main clock calculation */ |
| mbed_official | 359:275f0f27ea18 | 229 | #if ((MAINCLKSEL_Val & 0x03) == 0) |
| mbed_official | 359:275f0f27ea18 | 230 | #define __MAIN_CLOCK (__IRC_OSC_CLK) |
| mbed_official | 359:275f0f27ea18 | 231 | #elif ((MAINCLKSEL_Val & 0x03) == 1) |
| mbed_official | 359:275f0f27ea18 | 232 | #define __MAIN_CLOCK (__SYS_PLLCLKIN) |
| mbed_official | 359:275f0f27ea18 | 233 | #elif ((MAINCLKSEL_Val & 0x03) == 2) |
| mbed_official | 359:275f0f27ea18 | 234 | #if (__FREQSEL == 0) |
| mbed_official | 359:275f0f27ea18 | 235 | #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" |
| mbed_official | 359:275f0f27ea18 | 236 | #else |
| mbed_official | 359:275f0f27ea18 | 237 | #define __MAIN_CLOCK (__WDT_OSC_CLK) |
| mbed_official | 359:275f0f27ea18 | 238 | #endif |
| mbed_official | 359:275f0f27ea18 | 239 | #elif ((MAINCLKSEL_Val & 0x03) == 3) |
| mbed_official | 359:275f0f27ea18 | 240 | #define __MAIN_CLOCK (__SYS_PLLCLKOUT) |
| mbed_official | 359:275f0f27ea18 | 241 | #else |
| mbed_official | 359:275f0f27ea18 | 242 | #define __MAIN_CLOCK (0) |
| mbed_official | 359:275f0f27ea18 | 243 | #endif |
| mbed_official | 359:275f0f27ea18 | 244 | |
| mbed_official | 359:275f0f27ea18 | 245 | #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) |
| mbed_official | 359:275f0f27ea18 | 246 | |
| mbed_official | 359:275f0f27ea18 | 247 | #else |
| mbed_official | 359:275f0f27ea18 | 248 | #define __SYSTEM_CLOCK (__IRC_OSC_CLK) |
| mbed_official | 359:275f0f27ea18 | 249 | #endif // CLOCK_SETUP |
| mbed_official | 359:275f0f27ea18 | 250 | |
| mbed_official | 359:275f0f27ea18 | 251 | |
| mbed_official | 359:275f0f27ea18 | 252 | /*---------------------------------------------------------------------------- |
| mbed_official | 359:275f0f27ea18 | 253 | Clock Variable definitions |
| mbed_official | 359:275f0f27ea18 | 254 | *----------------------------------------------------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 255 | uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ |
| mbed_official | 359:275f0f27ea18 | 256 | uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ |
| mbed_official | 359:275f0f27ea18 | 257 | |
| mbed_official | 359:275f0f27ea18 | 258 | /*---------------------------------------------------------------------------- |
| mbed_official | 359:275f0f27ea18 | 259 | Clock functions |
| mbed_official | 359:275f0f27ea18 | 260 | *----------------------------------------------------------------------------*/ |
| mbed_official | 359:275f0f27ea18 | 261 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
| mbed_official | 359:275f0f27ea18 | 262 | { |
| mbed_official | 359:275f0f27ea18 | 263 | uint32_t wdt_osc = 0; |
| mbed_official | 359:275f0f27ea18 | 264 | |
| mbed_official | 359:275f0f27ea18 | 265 | /* Determine clock frequency according to clock register values */ |
| mbed_official | 359:275f0f27ea18 | 266 | switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { |
| mbed_official | 359:275f0f27ea18 | 267 | case 0: wdt_osc = 0; break; |
| mbed_official | 359:275f0f27ea18 | 268 | case 1: wdt_osc = 500000; break; |
| mbed_official | 359:275f0f27ea18 | 269 | case 2: wdt_osc = 800000; break; |
| mbed_official | 359:275f0f27ea18 | 270 | case 3: wdt_osc = 1100000; break; |
| mbed_official | 359:275f0f27ea18 | 271 | case 4: wdt_osc = 1400000; break; |
| mbed_official | 359:275f0f27ea18 | 272 | case 5: wdt_osc = 1600000; break; |
| mbed_official | 359:275f0f27ea18 | 273 | case 6: wdt_osc = 1800000; break; |
| mbed_official | 359:275f0f27ea18 | 274 | case 7: wdt_osc = 2000000; break; |
| mbed_official | 359:275f0f27ea18 | 275 | case 8: wdt_osc = 2200000; break; |
| mbed_official | 359:275f0f27ea18 | 276 | case 9: wdt_osc = 2400000; break; |
| mbed_official | 359:275f0f27ea18 | 277 | case 10: wdt_osc = 2600000; break; |
| mbed_official | 359:275f0f27ea18 | 278 | case 11: wdt_osc = 2700000; break; |
| mbed_official | 359:275f0f27ea18 | 279 | case 12: wdt_osc = 2900000; break; |
| mbed_official | 359:275f0f27ea18 | 280 | case 13: wdt_osc = 3100000; break; |
| mbed_official | 359:275f0f27ea18 | 281 | case 14: wdt_osc = 3200000; break; |
| mbed_official | 359:275f0f27ea18 | 282 | case 15: wdt_osc = 3400000; break; |
| mbed_official | 359:275f0f27ea18 | 283 | } |
| mbed_official | 359:275f0f27ea18 | 284 | wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; |
| mbed_official | 359:275f0f27ea18 | 285 | |
| mbed_official | 359:275f0f27ea18 | 286 | switch (LPC_SYSCON->MAINCLKSEL & 0x03) { |
| mbed_official | 359:275f0f27ea18 | 287 | case 0: /* Internal RC oscillator */ |
| mbed_official | 359:275f0f27ea18 | 288 | SystemCoreClock = __IRC_OSC_CLK; |
| mbed_official | 359:275f0f27ea18 | 289 | break; |
| mbed_official | 359:275f0f27ea18 | 290 | case 1: /* Input Clock to System PLL */ |
| mbed_official | 359:275f0f27ea18 | 291 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
| mbed_official | 359:275f0f27ea18 | 292 | case 0: /* Internal RC oscillator */ |
| mbed_official | 359:275f0f27ea18 | 293 | SystemCoreClock = __IRC_OSC_CLK; |
| mbed_official | 359:275f0f27ea18 | 294 | break; |
| mbed_official | 359:275f0f27ea18 | 295 | case 1: /* System oscillator */ |
| mbed_official | 359:275f0f27ea18 | 296 | SystemCoreClock = __SYS_OSC_CLK; |
| mbed_official | 359:275f0f27ea18 | 297 | break; |
| mbed_official | 359:275f0f27ea18 | 298 | case 2: /* Reserved */ |
| mbed_official | 359:275f0f27ea18 | 299 | SystemCoreClock = 0; |
| mbed_official | 359:275f0f27ea18 | 300 | break; |
| mbed_official | 359:275f0f27ea18 | 301 | case 3: /* CLKIN pin */ |
| mbed_official | 359:275f0f27ea18 | 302 | SystemCoreClock = __CLKIN_CLK; |
| mbed_official | 359:275f0f27ea18 | 303 | break; |
| mbed_official | 359:275f0f27ea18 | 304 | } |
| mbed_official | 359:275f0f27ea18 | 305 | break; |
| mbed_official | 359:275f0f27ea18 | 306 | case 2: /* WDT Oscillator */ |
| mbed_official | 359:275f0f27ea18 | 307 | SystemCoreClock = wdt_osc; |
| mbed_official | 359:275f0f27ea18 | 308 | break; |
| mbed_official | 359:275f0f27ea18 | 309 | case 3: /* System PLL Clock Out */ |
| mbed_official | 359:275f0f27ea18 | 310 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
| mbed_official | 359:275f0f27ea18 | 311 | case 0: /* Internal RC oscillator */ |
| mbed_official | 359:275f0f27ea18 | 312 | SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 359:275f0f27ea18 | 313 | break; |
| mbed_official | 359:275f0f27ea18 | 314 | case 1: /* System oscillator */ |
| mbed_official | 359:275f0f27ea18 | 315 | SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 359:275f0f27ea18 | 316 | break; |
| mbed_official | 359:275f0f27ea18 | 317 | case 2: /* Reserved */ |
| mbed_official | 359:275f0f27ea18 | 318 | SystemCoreClock = 0; |
| mbed_official | 359:275f0f27ea18 | 319 | break; |
| mbed_official | 359:275f0f27ea18 | 320 | case 3: /* CLKIN pin */ |
| mbed_official | 359:275f0f27ea18 | 321 | SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 359:275f0f27ea18 | 322 | break; |
| mbed_official | 359:275f0f27ea18 | 323 | } |
| mbed_official | 359:275f0f27ea18 | 324 | break; |
| mbed_official | 359:275f0f27ea18 | 325 | } |
| mbed_official | 359:275f0f27ea18 | 326 | |
| mbed_official | 359:275f0f27ea18 | 327 | SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; |
| mbed_official | 359:275f0f27ea18 | 328 | |
| mbed_official | 359:275f0f27ea18 | 329 | } |
| mbed_official | 359:275f0f27ea18 | 330 | |
| mbed_official | 359:275f0f27ea18 | 331 | /** |
| mbed_official | 359:275f0f27ea18 | 332 | * Initialize the system |
| mbed_official | 359:275f0f27ea18 | 333 | * |
| mbed_official | 359:275f0f27ea18 | 334 | * @param none |
| mbed_official | 359:275f0f27ea18 | 335 | * @return none |
| mbed_official | 359:275f0f27ea18 | 336 | * |
| mbed_official | 359:275f0f27ea18 | 337 | * @brief Setup the microcontroller system. |
| mbed_official | 359:275f0f27ea18 | 338 | * Initialize the System. |
| mbed_official | 359:275f0f27ea18 | 339 | */ |
| mbed_official | 359:275f0f27ea18 | 340 | void SystemInit (void) { |
| mbed_official | 359:275f0f27ea18 | 341 | volatile uint32_t i; |
| mbed_official | 359:275f0f27ea18 | 342 | |
| mbed_official | 359:275f0f27ea18 | 343 | /* System clock to the IOCON & the SWM need to be enabled or |
| mbed_official | 359:275f0f27ea18 | 344 | most of the I/O related peripherals won't work. */ |
| mbed_official | 359:275f0f27ea18 | 345 | LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); |
| mbed_official | 359:275f0f27ea18 | 346 | |
| mbed_official | 359:275f0f27ea18 | 347 | #if (CLOCK_SETUP) /* Clock Setup */ |
| mbed_official | 359:275f0f27ea18 | 348 | |
| mbed_official | 359:275f0f27ea18 | 349 | #if ((SYSPLLCLKSEL_Val & 0x03) == 1) |
| mbed_official | 359:275f0f27ea18 | 350 | LPC_IOCON->PIO0_8 &= ~(0x3 << 3); |
| mbed_official | 359:275f0f27ea18 | 351 | LPC_IOCON->PIO0_9 &= ~(0x3 << 3); |
| mbed_official | 359:275f0f27ea18 | 352 | LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */ |
| mbed_official | 359:275f0f27ea18 | 353 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ |
| mbed_official | 359:275f0f27ea18 | 354 | for (i = 0; i < 200; i++) __NOP(); |
| mbed_official | 359:275f0f27ea18 | 355 | LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; |
| mbed_official | 359:275f0f27ea18 | 356 | #endif |
| mbed_official | 359:275f0f27ea18 | 357 | |
| mbed_official | 359:275f0f27ea18 | 358 | #if ((SYSPLLCLKSEL_Val & 0x03) == 3) |
| mbed_official | 359:275f0f27ea18 | 359 | LPC_IOCON->PIO0_1 &= ~(0x3 << 3); |
| mbed_official | 359:275f0f27ea18 | 360 | LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */ |
| mbed_official | 359:275f0f27ea18 | 361 | for (i = 0; i < 200; i++) __NOP(); |
| mbed_official | 359:275f0f27ea18 | 362 | #endif |
| mbed_official | 359:275f0f27ea18 | 363 | |
| mbed_official | 359:275f0f27ea18 | 364 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */ |
| mbed_official | 359:275f0f27ea18 | 365 | LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ |
| mbed_official | 359:275f0f27ea18 | 366 | LPC_SYSCON->SYSPLLCLKUEN = 0; |
| mbed_official | 359:275f0f27ea18 | 367 | LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */ |
| mbed_official | 359:275f0f27ea18 | 368 | while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 359:275f0f27ea18 | 369 | |
| mbed_official | 359:275f0f27ea18 | 370 | #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ |
| mbed_official | 359:275f0f27ea18 | 371 | LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; |
| mbed_official | 359:275f0f27ea18 | 372 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ |
| mbed_official | 359:275f0f27ea18 | 373 | while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
| mbed_official | 359:275f0f27ea18 | 374 | #endif |
| mbed_official | 359:275f0f27ea18 | 375 | |
| mbed_official | 359:275f0f27ea18 | 376 | #if (((MAINCLKSEL_Val & 0x03) == 2) ) |
| mbed_official | 359:275f0f27ea18 | 377 | LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; |
| mbed_official | 359:275f0f27ea18 | 378 | LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ |
| mbed_official | 359:275f0f27ea18 | 379 | for (i = 0; i < 200; i++) __NOP(); |
| mbed_official | 359:275f0f27ea18 | 380 | #endif |
| mbed_official | 359:275f0f27ea18 | 381 | |
| mbed_official | 359:275f0f27ea18 | 382 | LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ |
| mbed_official | 359:275f0f27ea18 | 383 | LPC_SYSCON->MAINCLKUEN = 0; |
| mbed_official | 359:275f0f27ea18 | 384 | LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */ |
| mbed_official | 359:275f0f27ea18 | 385 | while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 359:275f0f27ea18 | 386 | |
| mbed_official | 359:275f0f27ea18 | 387 | LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; |
| mbed_official | 359:275f0f27ea18 | 388 | #endif |
| mbed_official | 359:275f0f27ea18 | 389 | } |
