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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c@600:7d17ca308cd1, 2015-07-31 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 31 14:15:09 2015 +0100
- Revision:
- 600:7d17ca308cd1
- Parent:
- 234:37acebda271b
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0
Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/
Enable LPC8xx usart when configuring it
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 174:8bb9f3a33240 | 1 | /**************************************************************************//** |
| mbed_official | 174:8bb9f3a33240 | 2 | * @file system_LPC11U6x.c |
| mbed_official | 174:8bb9f3a33240 | 3 | * @brief CMSIS Cortex-M3 Device System Source File for |
| mbed_official | 174:8bb9f3a33240 | 4 | * NXP LPC11U6x Device Series |
| mbed_official | 174:8bb9f3a33240 | 5 | * @version V1.00 |
| mbed_official | 174:8bb9f3a33240 | 6 | * @date 19. July 2013 |
| mbed_official | 174:8bb9f3a33240 | 7 | * |
| mbed_official | 174:8bb9f3a33240 | 8 | * @note |
| mbed_official | 174:8bb9f3a33240 | 9 | * Copyright (C) 2013 ARM Limited. All rights reserved. |
| mbed_official | 174:8bb9f3a33240 | 10 | * |
| mbed_official | 174:8bb9f3a33240 | 11 | * @par |
| mbed_official | 174:8bb9f3a33240 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| mbed_official | 174:8bb9f3a33240 | 13 | * processor based microcontrollers. This file can be freely distributed |
| mbed_official | 174:8bb9f3a33240 | 14 | * within development tools that are supporting such ARM based processors. |
| mbed_official | 174:8bb9f3a33240 | 15 | * |
| mbed_official | 174:8bb9f3a33240 | 16 | * @par |
| mbed_official | 174:8bb9f3a33240 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| mbed_official | 174:8bb9f3a33240 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| mbed_official | 174:8bb9f3a33240 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| mbed_official | 174:8bb9f3a33240 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| mbed_official | 174:8bb9f3a33240 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| mbed_official | 174:8bb9f3a33240 | 22 | * |
| mbed_official | 174:8bb9f3a33240 | 23 | ******************************************************************************/ |
| mbed_official | 174:8bb9f3a33240 | 24 | |
| mbed_official | 174:8bb9f3a33240 | 25 | |
| mbed_official | 174:8bb9f3a33240 | 26 | #include <stdint.h> |
| mbed_official | 174:8bb9f3a33240 | 27 | #include "LPC11U6x.h" |
| mbed_official | 174:8bb9f3a33240 | 28 | |
| mbed_official | 174:8bb9f3a33240 | 29 | /* |
| mbed_official | 174:8bb9f3a33240 | 30 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| mbed_official | 174:8bb9f3a33240 | 31 | */ |
| mbed_official | 174:8bb9f3a33240 | 32 | |
| mbed_official | 174:8bb9f3a33240 | 33 | /*- SystemCoreClock Configuration -------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 34 | // <e0> SystemCoreClock Configuration |
| mbed_official | 174:8bb9f3a33240 | 35 | #define CLOCK_SETUP 1 |
| mbed_official | 174:8bb9f3a33240 | 36 | // |
| mbed_official | 174:8bb9f3a33240 | 37 | // <h> System Oscillator Control (SYSOSCCTRL) |
| mbed_official | 174:8bb9f3a33240 | 38 | // <o.0> BYPASS: System Oscillator Bypass Enable |
| mbed_official | 174:8bb9f3a33240 | 39 | // <i> If enabled then PLL input (sys_osc_clk) is fed |
| mbed_official | 174:8bb9f3a33240 | 40 | // <i> directly from XTALIN and XTALOUT pins. |
| mbed_official | 174:8bb9f3a33240 | 41 | // <o.1> FREQRANGE: System Oscillator Frequency Range |
| mbed_official | 174:8bb9f3a33240 | 42 | // <i> Determines frequency range for Low-power oscillator. |
| mbed_official | 174:8bb9f3a33240 | 43 | // <0=> 1 - 20 MHz |
| mbed_official | 174:8bb9f3a33240 | 44 | // <1=> 15 - 25 MHz |
| mbed_official | 174:8bb9f3a33240 | 45 | // </h> |
| mbed_official | 174:8bb9f3a33240 | 46 | #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 47 | // |
| mbed_official | 174:8bb9f3a33240 | 48 | // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL) |
| mbed_official | 174:8bb9f3a33240 | 49 | // <0=> IRC Oscillator |
| mbed_official | 174:8bb9f3a33240 | 50 | // <1=> Crystal Oscillator (SYSOSC) |
| mbed_official | 174:8bb9f3a33240 | 51 | // <3=> RTC Oscillator (32 kHz) |
| mbed_official | 174:8bb9f3a33240 | 52 | #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 53 | // |
| mbed_official | 174:8bb9f3a33240 | 54 | // <e> Clock Configuration (Manual) |
| mbed_official | 174:8bb9f3a33240 | 55 | #define CLOCK_SETUP_REG 1 |
| mbed_official | 174:8bb9f3a33240 | 56 | // |
| mbed_official | 174:8bb9f3a33240 | 57 | // <h> WD Oscillator Setting (WDTOSCCTRL) |
| mbed_official | 174:8bb9f3a33240 | 58 | // <o.0..4> DIVSEL: Select Divider for Fclkana |
| mbed_official | 174:8bb9f3a33240 | 59 | // <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL)) |
| mbed_official | 174:8bb9f3a33240 | 60 | // <0-31> |
| mbed_official | 174:8bb9f3a33240 | 61 | // <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana) |
| mbed_official | 174:8bb9f3a33240 | 62 | // <1=> 0.5 MHz |
| mbed_official | 174:8bb9f3a33240 | 63 | // <2=> 0.8 MHz |
| mbed_official | 174:8bb9f3a33240 | 64 | // <3=> 1.1 MHz |
| mbed_official | 174:8bb9f3a33240 | 65 | // <4=> 1.4 MHz |
| mbed_official | 174:8bb9f3a33240 | 66 | // <5=> 1.6 MHz |
| mbed_official | 174:8bb9f3a33240 | 67 | // <6=> 1.8 MHz |
| mbed_official | 174:8bb9f3a33240 | 68 | // <7=> 2.0 MHz |
| mbed_official | 174:8bb9f3a33240 | 69 | // <8=> 2.2 MHz |
| mbed_official | 174:8bb9f3a33240 | 70 | // <9=> 2.4 MHz |
| mbed_official | 174:8bb9f3a33240 | 71 | // <10=> 2.6 MHz |
| mbed_official | 174:8bb9f3a33240 | 72 | // <11=> 2.7 MHz |
| mbed_official | 174:8bb9f3a33240 | 73 | // <12=> 2.9 MHz |
| mbed_official | 174:8bb9f3a33240 | 74 | // <13=> 3.1 MHz |
| mbed_official | 174:8bb9f3a33240 | 75 | // <14=> 3.2 MHz |
| mbed_official | 174:8bb9f3a33240 | 76 | // <15=> 3.4 MHz |
| mbed_official | 174:8bb9f3a33240 | 77 | // </h> |
| mbed_official | 174:8bb9f3a33240 | 78 | #define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0 |
| mbed_official | 174:8bb9f3a33240 | 79 | // |
| mbed_official | 174:8bb9f3a33240 | 80 | // <h> System PLL Setting (SYSPLLCTRL) |
| mbed_official | 174:8bb9f3a33240 | 81 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| mbed_official | 174:8bb9f3a33240 | 82 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| mbed_official | 174:8bb9f3a33240 | 83 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| mbed_official | 174:8bb9f3a33240 | 84 | // <o.0..4> MSEL: Feedback Divider Selection |
| mbed_official | 174:8bb9f3a33240 | 85 | // <i> M = MSEL + 1 |
| mbed_official | 174:8bb9f3a33240 | 86 | // <0-31> |
| mbed_official | 174:8bb9f3a33240 | 87 | // <o.5..6> PSEL: Post Divider Selection |
| mbed_official | 174:8bb9f3a33240 | 88 | // <i> Post divider ratio P. Division ratio is 2 * P |
| mbed_official | 174:8bb9f3a33240 | 89 | // <0=> P = 1 |
| mbed_official | 174:8bb9f3a33240 | 90 | // <1=> P = 2 |
| mbed_official | 174:8bb9f3a33240 | 91 | // <2=> P = 4 |
| mbed_official | 174:8bb9f3a33240 | 92 | // <3=> P = 8 |
| mbed_official | 174:8bb9f3a33240 | 93 | // </h> |
| mbed_official | 186:2e805bf06ee4 | 94 | #define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 95 | // |
| mbed_official | 174:8bb9f3a33240 | 96 | // <o.0..1> Main Clock Source Select (MAINCLKSEL) |
| mbed_official | 174:8bb9f3a33240 | 97 | // <0=> IRC Oscillator |
| mbed_official | 174:8bb9f3a33240 | 98 | // <1=> PLL Input |
| mbed_official | 174:8bb9f3a33240 | 99 | // <2=> WD Oscillator |
| mbed_official | 174:8bb9f3a33240 | 100 | // <3=> PLL Output |
| mbed_official | 174:8bb9f3a33240 | 101 | #define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 102 | // |
| mbed_official | 174:8bb9f3a33240 | 103 | // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV) |
| mbed_official | 174:8bb9f3a33240 | 104 | // <i> Divides main clock to provide system clock to core, memories, and peripherals. |
| mbed_official | 174:8bb9f3a33240 | 105 | // <i> 0 = is disabled |
| mbed_official | 174:8bb9f3a33240 | 106 | // <0-255> |
| mbed_official | 174:8bb9f3a33240 | 107 | #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001 |
| mbed_official | 174:8bb9f3a33240 | 108 | // </e> |
| mbed_official | 174:8bb9f3a33240 | 109 | // |
| mbed_official | 174:8bb9f3a33240 | 110 | // <e> Clock Configuration (via ROM PLL API) |
| mbed_official | 174:8bb9f3a33240 | 111 | #define CLOCK_SETUP_API 0 |
| mbed_official | 174:8bb9f3a33240 | 112 | // |
| mbed_official | 174:8bb9f3a33240 | 113 | // <o> PLL API Mode Select |
| mbed_official | 174:8bb9f3a33240 | 114 | // <0=> Exact |
| mbed_official | 174:8bb9f3a33240 | 115 | // <1=> Less than or equal |
| mbed_official | 174:8bb9f3a33240 | 116 | // <2=> Greater than or equal |
| mbed_official | 174:8bb9f3a33240 | 117 | // <3=> As close as possible |
| mbed_official | 174:8bb9f3a33240 | 118 | #define PLL_API_MODE_Val 0 |
| mbed_official | 174:8bb9f3a33240 | 119 | // |
| mbed_official | 174:8bb9f3a33240 | 120 | // <o> CPU Frequency [Hz] <1000000-50000000:1000> |
| mbed_official | 174:8bb9f3a33240 | 121 | #define PLL_API_FREQ_Val 48000000 |
| mbed_official | 174:8bb9f3a33240 | 122 | // </e> |
| mbed_official | 174:8bb9f3a33240 | 123 | // |
| mbed_official | 174:8bb9f3a33240 | 124 | // <e> USB Clock Configuration |
| mbed_official | 174:8bb9f3a33240 | 125 | #define USB_CLOCK_SETUP 1 |
| mbed_official | 174:8bb9f3a33240 | 126 | // <h> USB PLL Control (USBPLLCTRL) |
| mbed_official | 174:8bb9f3a33240 | 127 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| mbed_official | 174:8bb9f3a33240 | 128 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| mbed_official | 174:8bb9f3a33240 | 129 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| mbed_official | 174:8bb9f3a33240 | 130 | // <o.0..4> MSEL: Feedback Divider Selection |
| mbed_official | 174:8bb9f3a33240 | 131 | // <i> M = MSEL + 1 |
| mbed_official | 174:8bb9f3a33240 | 132 | // <0-31> |
| mbed_official | 174:8bb9f3a33240 | 133 | // <o.5..6> PSEL: Post Divider Selection |
| mbed_official | 174:8bb9f3a33240 | 134 | // <i> Post divider ratio P. Division ratio is 2 * P |
| mbed_official | 174:8bb9f3a33240 | 135 | // <0=> P = 1 |
| mbed_official | 174:8bb9f3a33240 | 136 | // <1=> P = 2 |
| mbed_official | 174:8bb9f3a33240 | 137 | // <2=> P = 4 |
| mbed_official | 174:8bb9f3a33240 | 138 | // <3=> P = 8 |
| mbed_official | 174:8bb9f3a33240 | 139 | // </h> |
| mbed_official | 174:8bb9f3a33240 | 140 | #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 141 | // |
| mbed_official | 174:8bb9f3a33240 | 142 | // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL) |
| mbed_official | 174:8bb9f3a33240 | 143 | // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation |
| mbed_official | 174:8bb9f3a33240 | 144 | // <0=> IRC Oscillator |
| mbed_official | 174:8bb9f3a33240 | 145 | // <1=> System Oscillator |
| mbed_official | 174:8bb9f3a33240 | 146 | #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 147 | // |
| mbed_official | 174:8bb9f3a33240 | 148 | // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL) |
| mbed_official | 174:8bb9f3a33240 | 149 | // <0=> USB PLL out |
| mbed_official | 174:8bb9f3a33240 | 150 | // <1=> Main clock |
| mbed_official | 174:8bb9f3a33240 | 151 | #define USBCLKSEL_Val 0x00000000 // Reset value: 0x000 |
| mbed_official | 174:8bb9f3a33240 | 152 | // |
| mbed_official | 174:8bb9f3a33240 | 153 | // <o.0..7> USB Clock Divider (USBCLKDIV.DIV) |
| mbed_official | 174:8bb9f3a33240 | 154 | // <i> Divides USB clock to 48 MHz. |
| mbed_official | 174:8bb9f3a33240 | 155 | // <i> 0 = is disabled |
| mbed_official | 174:8bb9f3a33240 | 156 | // <0-255> |
| mbed_official | 174:8bb9f3a33240 | 157 | #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001 |
| mbed_official | 174:8bb9f3a33240 | 158 | // </e> |
| mbed_official | 174:8bb9f3a33240 | 159 | // |
| mbed_official | 174:8bb9f3a33240 | 160 | // </e> |
| mbed_official | 174:8bb9f3a33240 | 161 | // |
| mbed_official | 174:8bb9f3a33240 | 162 | // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000> |
| mbed_official | 174:8bb9f3a33240 | 163 | // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz |
| mbed_official | 174:8bb9f3a33240 | 164 | // |
| mbed_official | 174:8bb9f3a33240 | 165 | #define XTAL_CLK_Val 12000000 |
| mbed_official | 174:8bb9f3a33240 | 166 | |
| mbed_official | 174:8bb9f3a33240 | 167 | /* |
| mbed_official | 174:8bb9f3a33240 | 168 | //-------- <<< end of configuration section >>> ------------------------------ |
| mbed_official | 174:8bb9f3a33240 | 169 | */ |
| mbed_official | 174:8bb9f3a33240 | 170 | |
| mbed_official | 174:8bb9f3a33240 | 171 | /*---------------------------------------------------------------------------- |
| mbed_official | 174:8bb9f3a33240 | 172 | Define clocks |
| mbed_official | 174:8bb9f3a33240 | 173 | *----------------------------------------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 174 | #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */ |
| mbed_official | 174:8bb9f3a33240 | 175 | #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */ |
| mbed_official | 174:8bb9f3a33240 | 176 | #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */ |
| mbed_official | 174:8bb9f3a33240 | 177 | #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */ |
| mbed_official | 174:8bb9f3a33240 | 178 | |
| mbed_official | 174:8bb9f3a33240 | 179 | /*---------------------------------------------------------------------------- |
| mbed_official | 174:8bb9f3a33240 | 180 | Check the register settings |
| mbed_official | 174:8bb9f3a33240 | 181 | *----------------------------------------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 182 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
| mbed_official | 174:8bb9f3a33240 | 183 | #define CHECK_RSVD(val, mask) (val & mask) |
| mbed_official | 174:8bb9f3a33240 | 184 | |
| mbed_official | 174:8bb9f3a33240 | 185 | #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) |
| mbed_official | 174:8bb9f3a33240 | 186 | #error "SYSOSCCTRL: Invalid values of reserved bits!" |
| mbed_official | 174:8bb9f3a33240 | 187 | #endif |
| mbed_official | 174:8bb9f3a33240 | 188 | |
| mbed_official | 174:8bb9f3a33240 | 189 | #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) |
| mbed_official | 174:8bb9f3a33240 | 190 | #error "WDTOSCCTRL: Invalid values of reserved bits!" |
| mbed_official | 174:8bb9f3a33240 | 191 | #endif |
| mbed_official | 174:8bb9f3a33240 | 192 | |
| mbed_official | 174:8bb9f3a33240 | 193 | #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) |
| mbed_official | 174:8bb9f3a33240 | 194 | #error "SYSPLLCLKSEL: Value out of range!" |
| mbed_official | 174:8bb9f3a33240 | 195 | #endif |
| mbed_official | 174:8bb9f3a33240 | 196 | |
| mbed_official | 174:8bb9f3a33240 | 197 | #if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input |
| mbed_official | 174:8bb9f3a33240 | 198 | #if (CLOCK_SETUP_API == 1) |
| mbed_official | 174:8bb9f3a33240 | 199 | #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!" |
| mbed_official | 174:8bb9f3a33240 | 200 | #endif |
| mbed_official | 174:8bb9f3a33240 | 201 | #if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input |
| mbed_official | 174:8bb9f3a33240 | 202 | #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!" |
| mbed_official | 174:8bb9f3a33240 | 203 | #endif |
| mbed_official | 174:8bb9f3a33240 | 204 | #endif |
| mbed_official | 174:8bb9f3a33240 | 205 | |
| mbed_official | 174:8bb9f3a33240 | 206 | #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F)) |
| mbed_official | 174:8bb9f3a33240 | 207 | #error "SYSPLLCTRL: Invalid values of reserved bits!" |
| mbed_official | 174:8bb9f3a33240 | 208 | #endif |
| mbed_official | 174:8bb9f3a33240 | 209 | |
| mbed_official | 174:8bb9f3a33240 | 210 | #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) |
| mbed_official | 174:8bb9f3a33240 | 211 | #error "MAINCLKSEL: Invalid values of reserved bits!" |
| mbed_official | 174:8bb9f3a33240 | 212 | #endif |
| mbed_official | 174:8bb9f3a33240 | 213 | |
| mbed_official | 174:8bb9f3a33240 | 214 | #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) |
| mbed_official | 174:8bb9f3a33240 | 215 | #error "SYSAHBCLKDIV: Value out of range!" |
| mbed_official | 174:8bb9f3a33240 | 216 | #endif |
| mbed_official | 174:8bb9f3a33240 | 217 | |
| mbed_official | 174:8bb9f3a33240 | 218 | #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API ) |
| mbed_official | 174:8bb9f3a33240 | 219 | #error "You must select either manual or API based Clock Configuration!" |
| mbed_official | 174:8bb9f3a33240 | 220 | #endif |
| mbed_official | 174:8bb9f3a33240 | 221 | |
| mbed_official | 174:8bb9f3a33240 | 222 | #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) |
| mbed_official | 174:8bb9f3a33240 | 223 | #error "USBPLLCLKSEL: Value out of range!" |
| mbed_official | 174:8bb9f3a33240 | 224 | #endif |
| mbed_official | 174:8bb9f3a33240 | 225 | |
| mbed_official | 174:8bb9f3a33240 | 226 | #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F)) |
| mbed_official | 174:8bb9f3a33240 | 227 | #error "USBPLLCTRL: Invalid values of reserved bits!" |
| mbed_official | 174:8bb9f3a33240 | 228 | #endif |
| mbed_official | 174:8bb9f3a33240 | 229 | |
| mbed_official | 174:8bb9f3a33240 | 230 | #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1)) |
| mbed_official | 174:8bb9f3a33240 | 231 | #error "USBCLKSEL: Value out of range!" |
| mbed_official | 174:8bb9f3a33240 | 232 | #endif |
| mbed_official | 174:8bb9f3a33240 | 233 | |
| mbed_official | 174:8bb9f3a33240 | 234 | #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255)) |
| mbed_official | 174:8bb9f3a33240 | 235 | #error "USBCLKDIV: Value out of range!" |
| mbed_official | 174:8bb9f3a33240 | 236 | #endif |
| mbed_official | 174:8bb9f3a33240 | 237 | |
| mbed_official | 174:8bb9f3a33240 | 238 | #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000)) |
| mbed_official | 174:8bb9f3a33240 | 239 | #error "XTAL frequency is out of bounds" |
| mbed_official | 174:8bb9f3a33240 | 240 | #endif |
| mbed_official | 174:8bb9f3a33240 | 241 | |
| mbed_official | 174:8bb9f3a33240 | 242 | #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3)) |
| mbed_official | 174:8bb9f3a33240 | 243 | #error "PLL API Mode Select not valid" |
| mbed_official | 174:8bb9f3a33240 | 244 | #endif |
| mbed_official | 174:8bb9f3a33240 | 245 | |
| mbed_official | 174:8bb9f3a33240 | 246 | #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000)) |
| mbed_official | 174:8bb9f3a33240 | 247 | #error "CPU Frequency (API mode) not valid" |
| mbed_official | 174:8bb9f3a33240 | 248 | #endif |
| mbed_official | 174:8bb9f3a33240 | 249 | |
| mbed_official | 174:8bb9f3a33240 | 250 | |
| mbed_official | 174:8bb9f3a33240 | 251 | |
| mbed_official | 174:8bb9f3a33240 | 252 | /*---------------------------------------------------------------------------- |
| mbed_official | 174:8bb9f3a33240 | 253 | Calculate system core clock |
| mbed_official | 174:8bb9f3a33240 | 254 | *----------------------------------------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 255 | #if (CLOCK_SETUP) /* Clock Setup */ |
| mbed_official | 174:8bb9f3a33240 | 256 | |
| mbed_official | 174:8bb9f3a33240 | 257 | /* sys_pllclkin calculation */ |
| mbed_official | 174:8bb9f3a33240 | 258 | #if ((SYSPLLCLKSEL_Val & 0x03) == 0) |
| mbed_official | 174:8bb9f3a33240 | 259 | #define __SYS_PLLCLKIN (__IRC_OSC_CLK) |
| mbed_official | 174:8bb9f3a33240 | 260 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) |
| mbed_official | 174:8bb9f3a33240 | 261 | #define __SYS_PLLCLKIN (__SYS_OSC_CLK) |
| mbed_official | 174:8bb9f3a33240 | 262 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) |
| mbed_official | 174:8bb9f3a33240 | 263 | #define __SYS_PLLCLKIN (__RTC_OSC_CLK) |
| mbed_official | 174:8bb9f3a33240 | 264 | #else |
| mbed_official | 174:8bb9f3a33240 | 265 | #error "Oops" |
| mbed_official | 174:8bb9f3a33240 | 266 | #endif |
| mbed_official | 174:8bb9f3a33240 | 267 | |
| mbed_official | 174:8bb9f3a33240 | 268 | #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ |
| mbed_official | 174:8bb9f3a33240 | 269 | |
| mbed_official | 174:8bb9f3a33240 | 270 | #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) |
| mbed_official | 174:8bb9f3a33240 | 271 | #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) |
| mbed_official | 174:8bb9f3a33240 | 272 | |
| mbed_official | 174:8bb9f3a33240 | 273 | #if (__FREQSEL == 0) |
| mbed_official | 174:8bb9f3a33240 | 274 | #error "WDTOSCCTRL.FREQSEL undefined!" |
| mbed_official | 174:8bb9f3a33240 | 275 | #elif (__FREQSEL == 1) |
| mbed_official | 174:8bb9f3a33240 | 276 | #define __OSC_CLK ( 500000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 277 | #elif (__FREQSEL == 2) |
| mbed_official | 174:8bb9f3a33240 | 278 | #define __OSC_CLK ( 800000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 279 | #elif (__FREQSEL == 3) |
| mbed_official | 174:8bb9f3a33240 | 280 | #define __OSC_CLK (1100000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 281 | #elif (__FREQSEL == 4) |
| mbed_official | 174:8bb9f3a33240 | 282 | #define __OSC_CLK (1400000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 283 | #elif (__FREQSEL == 5) |
| mbed_official | 174:8bb9f3a33240 | 284 | #define __OSC_CLK (1600000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 285 | #elif (__FREQSEL == 6) |
| mbed_official | 174:8bb9f3a33240 | 286 | #define __OSC_CLK (1800000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 287 | #elif (__FREQSEL == 7) |
| mbed_official | 174:8bb9f3a33240 | 288 | #define __OSC_CLK (2000000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 289 | #elif (__FREQSEL == 8) |
| mbed_official | 174:8bb9f3a33240 | 290 | #define __OSC_CLK (2200000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 291 | #elif (__FREQSEL == 9) |
| mbed_official | 174:8bb9f3a33240 | 292 | #define __OSC_CLK (2400000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 293 | #elif (__FREQSEL == 10) |
| mbed_official | 174:8bb9f3a33240 | 294 | #define __OSC_CLK (2600000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 295 | #elif (__FREQSEL == 11) |
| mbed_official | 174:8bb9f3a33240 | 296 | #define __OSC_CLK (2700000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 297 | #elif (__FREQSEL == 12) |
| mbed_official | 174:8bb9f3a33240 | 298 | #define __OSC_CLK (2900000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 299 | #elif (__FREQSEL == 13) |
| mbed_official | 174:8bb9f3a33240 | 300 | #define __OSC_CLK (3100000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 301 | #elif (__FREQSEL == 14) |
| mbed_official | 174:8bb9f3a33240 | 302 | #define __OSC_CLK (3200000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 303 | #else |
| mbed_official | 174:8bb9f3a33240 | 304 | #define __OSC_CLK (3400000 / __DIVSEL) |
| mbed_official | 174:8bb9f3a33240 | 305 | #endif |
| mbed_official | 174:8bb9f3a33240 | 306 | |
| mbed_official | 174:8bb9f3a33240 | 307 | #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) |
| mbed_official | 174:8bb9f3a33240 | 308 | |
| mbed_official | 174:8bb9f3a33240 | 309 | /* main clock calculation */ |
| mbed_official | 174:8bb9f3a33240 | 310 | #if ((MAINCLKSEL_Val & 0x03) == 0) |
| mbed_official | 174:8bb9f3a33240 | 311 | #define __MAIN_CLOCK (__IRC_OSC_CLK) |
| mbed_official | 174:8bb9f3a33240 | 312 | #elif ((MAINCLKSEL_Val & 0x03) == 1) |
| mbed_official | 174:8bb9f3a33240 | 313 | #define __MAIN_CLOCK (__SYS_PLLCLKIN) |
| mbed_official | 174:8bb9f3a33240 | 314 | #elif ((MAINCLKSEL_Val & 0x03) == 2) |
| mbed_official | 174:8bb9f3a33240 | 315 | #define __MAIN_CLOCK (__OSC_CLK) |
| mbed_official | 174:8bb9f3a33240 | 316 | #elif ((MAINCLKSEL_Val & 0x03) == 3) |
| mbed_official | 174:8bb9f3a33240 | 317 | #define __MAIN_CLOCK (__SYS_PLLCLKOUT) |
| mbed_official | 174:8bb9f3a33240 | 318 | #else |
| mbed_official | 174:8bb9f3a33240 | 319 | #error "Oops" |
| mbed_official | 174:8bb9f3a33240 | 320 | #endif |
| mbed_official | 174:8bb9f3a33240 | 321 | |
| mbed_official | 174:8bb9f3a33240 | 322 | #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) |
| mbed_official | 174:8bb9f3a33240 | 323 | #endif /* Clock Setup via Register */ |
| mbed_official | 174:8bb9f3a33240 | 324 | |
| mbed_official | 174:8bb9f3a33240 | 325 | #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */ |
| mbed_official | 174:8bb9f3a33240 | 326 | #define __SYSTEM_CLOCK (PLL_API_FREQ_Val) |
| mbed_official | 174:8bb9f3a33240 | 327 | #endif /* Clock Setup via PLL API */ |
| mbed_official | 174:8bb9f3a33240 | 328 | |
| mbed_official | 174:8bb9f3a33240 | 329 | #else |
| mbed_official | 174:8bb9f3a33240 | 330 | #define __SYSTEM_CLOCK (__IRC_OSC_CLK) |
| mbed_official | 174:8bb9f3a33240 | 331 | #endif /* CLOCK_SETUP */ |
| mbed_official | 174:8bb9f3a33240 | 332 | |
| mbed_official | 174:8bb9f3a33240 | 333 | |
| mbed_official | 174:8bb9f3a33240 | 334 | |
| mbed_official | 174:8bb9f3a33240 | 335 | #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */ |
| mbed_official | 174:8bb9f3a33240 | 336 | #include "power_api.h" |
| mbed_official | 174:8bb9f3a33240 | 337 | |
| mbed_official | 174:8bb9f3a33240 | 338 | typedef struct _ROM { |
| mbed_official | 174:8bb9f3a33240 | 339 | const unsigned p_dev0; |
| mbed_official | 174:8bb9f3a33240 | 340 | const unsigned p_dev1; |
| mbed_official | 174:8bb9f3a33240 | 341 | const unsigned p_dev2; |
| mbed_official | 174:8bb9f3a33240 | 342 | const PWRD * pPWRD; /* ROM Power Management API */ |
| mbed_official | 174:8bb9f3a33240 | 343 | const unsigned p_dev4; |
| mbed_official | 174:8bb9f3a33240 | 344 | const unsigned p_dev5; |
| mbed_official | 174:8bb9f3a33240 | 345 | const unsigned p_dev6; |
| mbed_official | 174:8bb9f3a33240 | 346 | const unsigned p_dev7; |
| mbed_official | 174:8bb9f3a33240 | 347 | } ROM; |
| mbed_official | 174:8bb9f3a33240 | 348 | |
| mbed_official | 174:8bb9f3a33240 | 349 | /*---------------------------------------------------------------------------- |
| mbed_official | 174:8bb9f3a33240 | 350 | PLL API Function |
| mbed_official | 174:8bb9f3a33240 | 351 | *----------------------------------------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 352 | static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq) |
| mbed_official | 174:8bb9f3a33240 | 353 | { |
| mbed_official | 174:8bb9f3a33240 | 354 | uint32_t cmd[5], res[5]; |
| mbed_official | 174:8bb9f3a33240 | 355 | ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */ |
| mbed_official | 174:8bb9f3a33240 | 356 | |
| mbed_official | 174:8bb9f3a33240 | 357 | cmd[0] = pllInFreq; /* PLL's input freq in KHz */ |
| mbed_official | 174:8bb9f3a33240 | 358 | cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */ |
| mbed_official | 174:8bb9f3a33240 | 359 | cmd[2] = pllMode; |
| mbed_official | 174:8bb9f3a33240 | 360 | cmd[3] = 0; /* no timeout for PLL to lock */ |
| mbed_official | 174:8bb9f3a33240 | 361 | |
| mbed_official | 174:8bb9f3a33240 | 362 | /* Execute API call */ |
| mbed_official | 174:8bb9f3a33240 | 363 | (*rom)->pPWRD->set_pll(cmd, res); /* call API function */ |
| mbed_official | 174:8bb9f3a33240 | 364 | if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */ |
| mbed_official | 174:8bb9f3a33240 | 365 | while(1); /* ... stay here */ |
| mbed_official | 174:8bb9f3a33240 | 366 | } |
| mbed_official | 174:8bb9f3a33240 | 367 | } |
| mbed_official | 174:8bb9f3a33240 | 368 | #endif |
| mbed_official | 174:8bb9f3a33240 | 369 | |
| mbed_official | 174:8bb9f3a33240 | 370 | |
| mbed_official | 174:8bb9f3a33240 | 371 | |
| mbed_official | 174:8bb9f3a33240 | 372 | |
| mbed_official | 174:8bb9f3a33240 | 373 | /*---------------------------------------------------------------------------- |
| mbed_official | 174:8bb9f3a33240 | 374 | Clock Variable definitions |
| mbed_official | 174:8bb9f3a33240 | 375 | *----------------------------------------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 376 | uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */ |
| mbed_official | 174:8bb9f3a33240 | 377 | |
| mbed_official | 174:8bb9f3a33240 | 378 | |
| mbed_official | 174:8bb9f3a33240 | 379 | /*---------------------------------------------------------------------------- |
| mbed_official | 174:8bb9f3a33240 | 380 | Clock functions |
| mbed_official | 174:8bb9f3a33240 | 381 | *----------------------------------------------------------------------------*/ |
| mbed_official | 174:8bb9f3a33240 | 382 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
| mbed_official | 174:8bb9f3a33240 | 383 | { |
| mbed_official | 174:8bb9f3a33240 | 384 | uint32_t oscClk = 0; |
| mbed_official | 174:8bb9f3a33240 | 385 | |
| mbed_official | 174:8bb9f3a33240 | 386 | /* Determine clock frequency according to clock register values */ |
| mbed_official | 174:8bb9f3a33240 | 387 | switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { |
| mbed_official | 174:8bb9f3a33240 | 388 | case 0: oscClk = 0; break; |
| mbed_official | 174:8bb9f3a33240 | 389 | case 1: oscClk = 500000; break; |
| mbed_official | 174:8bb9f3a33240 | 390 | case 2: oscClk = 800000; break; |
| mbed_official | 174:8bb9f3a33240 | 391 | case 3: oscClk = 1100000; break; |
| mbed_official | 174:8bb9f3a33240 | 392 | case 4: oscClk = 1400000; break; |
| mbed_official | 174:8bb9f3a33240 | 393 | case 5: oscClk = 1600000; break; |
| mbed_official | 174:8bb9f3a33240 | 394 | case 6: oscClk = 1800000; break; |
| mbed_official | 174:8bb9f3a33240 | 395 | case 7: oscClk = 2000000; break; |
| mbed_official | 174:8bb9f3a33240 | 396 | case 8: oscClk = 2200000; break; |
| mbed_official | 174:8bb9f3a33240 | 397 | case 9: oscClk = 2400000; break; |
| mbed_official | 174:8bb9f3a33240 | 398 | case 10: oscClk = 2600000; break; |
| mbed_official | 174:8bb9f3a33240 | 399 | case 11: oscClk = 2700000; break; |
| mbed_official | 174:8bb9f3a33240 | 400 | case 12: oscClk = 2900000; break; |
| mbed_official | 174:8bb9f3a33240 | 401 | case 13: oscClk = 3100000; break; |
| mbed_official | 174:8bb9f3a33240 | 402 | case 14: oscClk = 3200000; break; |
| mbed_official | 174:8bb9f3a33240 | 403 | case 15: oscClk = 3400000; break; |
| mbed_official | 174:8bb9f3a33240 | 404 | } |
| mbed_official | 174:8bb9f3a33240 | 405 | oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; |
| mbed_official | 174:8bb9f3a33240 | 406 | |
| mbed_official | 174:8bb9f3a33240 | 407 | switch (LPC_SYSCON->MAINCLKSEL & 0x03) { |
| mbed_official | 174:8bb9f3a33240 | 408 | case 0: /* Internal RC oscillator */ |
| mbed_official | 174:8bb9f3a33240 | 409 | SystemCoreClock = __IRC_OSC_CLK; |
| mbed_official | 174:8bb9f3a33240 | 410 | break; |
| mbed_official | 174:8bb9f3a33240 | 411 | case 1: /* Input Clock to System PLL */ |
| mbed_official | 174:8bb9f3a33240 | 412 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
| mbed_official | 174:8bb9f3a33240 | 413 | case 0: /* Internal RC oscillator */ |
| mbed_official | 174:8bb9f3a33240 | 414 | SystemCoreClock = __IRC_OSC_CLK; |
| mbed_official | 174:8bb9f3a33240 | 415 | break; |
| mbed_official | 174:8bb9f3a33240 | 416 | case 1: /* System oscillator */ |
| mbed_official | 174:8bb9f3a33240 | 417 | SystemCoreClock = __SYS_OSC_CLK; |
| mbed_official | 174:8bb9f3a33240 | 418 | break; |
| mbed_official | 174:8bb9f3a33240 | 419 | case 2: /* Reserved */ |
| mbed_official | 174:8bb9f3a33240 | 420 | case 3: /* Reserved */ |
| mbed_official | 174:8bb9f3a33240 | 421 | SystemCoreClock = 0; |
| mbed_official | 174:8bb9f3a33240 | 422 | break; |
| mbed_official | 174:8bb9f3a33240 | 423 | } |
| mbed_official | 174:8bb9f3a33240 | 424 | break; |
| mbed_official | 174:8bb9f3a33240 | 425 | case 2: /* WDT Oscillator */ |
| mbed_official | 174:8bb9f3a33240 | 426 | SystemCoreClock = oscClk; |
| mbed_official | 174:8bb9f3a33240 | 427 | break; |
| mbed_official | 174:8bb9f3a33240 | 428 | case 3: /* System PLL Clock Out */ |
| mbed_official | 174:8bb9f3a33240 | 429 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
| mbed_official | 174:8bb9f3a33240 | 430 | case 0: /* Internal RC oscillator */ |
| mbed_official | 174:8bb9f3a33240 | 431 | SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 174:8bb9f3a33240 | 432 | break; |
| mbed_official | 174:8bb9f3a33240 | 433 | case 1: /* System oscillator */ |
| mbed_official | 174:8bb9f3a33240 | 434 | SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 174:8bb9f3a33240 | 435 | break; |
| mbed_official | 174:8bb9f3a33240 | 436 | case 2: /* Reserved */ |
| mbed_official | 174:8bb9f3a33240 | 437 | case 3: /* Reserved */ |
| mbed_official | 174:8bb9f3a33240 | 438 | SystemCoreClock = 0; |
| mbed_official | 174:8bb9f3a33240 | 439 | break; |
| mbed_official | 174:8bb9f3a33240 | 440 | } |
| mbed_official | 174:8bb9f3a33240 | 441 | break; |
| mbed_official | 174:8bb9f3a33240 | 442 | } |
| mbed_official | 174:8bb9f3a33240 | 443 | |
| mbed_official | 174:8bb9f3a33240 | 444 | SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; |
| mbed_official | 174:8bb9f3a33240 | 445 | |
| mbed_official | 174:8bb9f3a33240 | 446 | } |
| mbed_official | 174:8bb9f3a33240 | 447 | |
| mbed_official | 186:2e805bf06ee4 | 448 | #define PDRUN_VALID_BITS 0x000025FFL |
| mbed_official | 186:2e805bf06ee4 | 449 | #define PDRUN_RESERVED_ONE 0x0000C800L |
| mbed_official | 186:2e805bf06ee4 | 450 | |
| mbed_official | 186:2e805bf06ee4 | 451 | static void power_down_config(uint32_t val) |
| mbed_official | 186:2e805bf06ee4 | 452 | { |
| mbed_official | 186:2e805bf06ee4 | 453 | volatile uint32_t tmp; |
| mbed_official | 186:2e805bf06ee4 | 454 | tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS); |
| mbed_official | 186:2e805bf06ee4 | 455 | tmp |= (val & PDRUN_VALID_BITS); |
| mbed_official | 186:2e805bf06ee4 | 456 | LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE); |
| mbed_official | 186:2e805bf06ee4 | 457 | } |
| mbed_official | 186:2e805bf06ee4 | 458 | |
| mbed_official | 186:2e805bf06ee4 | 459 | static void power_up_config(uint32_t val) |
| mbed_official | 186:2e805bf06ee4 | 460 | { |
| mbed_official | 186:2e805bf06ee4 | 461 | volatile uint32_t tmp; |
| mbed_official | 186:2e805bf06ee4 | 462 | tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS); |
| mbed_official | 186:2e805bf06ee4 | 463 | tmp &= ~(val & PDRUN_VALID_BITS); |
| mbed_official | 186:2e805bf06ee4 | 464 | LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE); |
| mbed_official | 186:2e805bf06ee4 | 465 | } |
| mbed_official | 186:2e805bf06ee4 | 466 | |
| mbed_official | 174:8bb9f3a33240 | 467 | /** |
| mbed_official | 174:8bb9f3a33240 | 468 | * Initialize the system |
| mbed_official | 174:8bb9f3a33240 | 469 | * |
| mbed_official | 174:8bb9f3a33240 | 470 | * @param none |
| mbed_official | 174:8bb9f3a33240 | 471 | * @return none |
| mbed_official | 174:8bb9f3a33240 | 472 | * |
| mbed_official | 174:8bb9f3a33240 | 473 | * @brief Setup the microcontroller system. |
| mbed_official | 174:8bb9f3a33240 | 474 | */ |
| mbed_official | 174:8bb9f3a33240 | 475 | void SystemInit (void) { |
| mbed_official | 174:8bb9f3a33240 | 476 | #if (CLOCK_SETUP) |
| mbed_official | 234:37acebda271b | 477 | volatile uint32_t i; |
| mbed_official | 174:8bb9f3a33240 | 478 | #endif |
| mbed_official | 174:8bb9f3a33240 | 479 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); |
| mbed_official | 174:8bb9f3a33240 | 480 | LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; |
| mbed_official | 174:8bb9f3a33240 | 481 | |
| mbed_official | 174:8bb9f3a33240 | 482 | #if (CLOCK_SETUP) /* Clock Setup */ |
| mbed_official | 174:8bb9f3a33240 | 483 | |
| mbed_official | 174:8bb9f3a33240 | 484 | #if ((SYSPLLCLKSEL_Val & 0x03) == 1) |
| mbed_official | 186:2e805bf06ee4 | 485 | // Initialize XTALIN/XTALOUT pins |
| mbed_official | 186:2e805bf06ee4 | 486 | LPC_IOCON->PIO2_0 = 0x01; |
| mbed_official | 186:2e805bf06ee4 | 487 | LPC_IOCON->PIO2_1 = 0x01; |
| mbed_official | 186:2e805bf06ee4 | 488 | |
| mbed_official | 174:8bb9f3a33240 | 489 | LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; |
| mbed_official | 186:2e805bf06ee4 | 490 | power_up_config(1<<5); /* Power-up sysosc */ |
| mbed_official | 186:2e805bf06ee4 | 491 | for (i = 0; i < 2500; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 174:8bb9f3a33240 | 492 | #endif |
| mbed_official | 186:2e805bf06ee4 | 493 | |
| mbed_official | 174:8bb9f3a33240 | 494 | #if ((SYSPLLCLKSEL_Val & 0x03) == 3) |
| mbed_official | 174:8bb9f3a33240 | 495 | LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */ |
| mbed_official | 174:8bb9f3a33240 | 496 | for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 174:8bb9f3a33240 | 497 | #endif |
| mbed_official | 174:8bb9f3a33240 | 498 | |
| mbed_official | 174:8bb9f3a33240 | 499 | LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ |
| mbed_official | 186:2e805bf06ee4 | 500 | LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ |
| mbed_official | 174:8bb9f3a33240 | 501 | LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ |
| mbed_official | 174:8bb9f3a33240 | 502 | LPC_SYSCON->SYSPLLCLKUEN = 0x01; |
| mbed_official | 174:8bb9f3a33240 | 503 | while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 174:8bb9f3a33240 | 504 | |
| mbed_official | 174:8bb9f3a33240 | 505 | #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ |
| mbed_official | 174:8bb9f3a33240 | 506 | |
| mbed_official | 174:8bb9f3a33240 | 507 | #if (((MAINCLKSEL_Val & 0x03) == 2) ) |
| mbed_official | 174:8bb9f3a33240 | 508 | LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; |
| mbed_official | 174:8bb9f3a33240 | 509 | LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ |
| mbed_official | 186:2e805bf06ee4 | 510 | for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 174:8bb9f3a33240 | 511 | #endif |
| mbed_official | 174:8bb9f3a33240 | 512 | |
| mbed_official | 174:8bb9f3a33240 | 513 | #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ |
| mbed_official | 186:2e805bf06ee4 | 514 | power_down_config(1<<7); /* Power-down SYSPLL */ |
| mbed_official | 174:8bb9f3a33240 | 515 | LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; |
| mbed_official | 186:2e805bf06ee4 | 516 | power_up_config(1<<7); /* Power-up SYSPLL */ |
| mbed_official | 174:8bb9f3a33240 | 517 | while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
| mbed_official | 174:8bb9f3a33240 | 518 | #endif |
| mbed_official | 174:8bb9f3a33240 | 519 | |
| mbed_official | 174:8bb9f3a33240 | 520 | LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */ |
| mbed_official | 174:8bb9f3a33240 | 521 | LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ |
| mbed_official | 174:8bb9f3a33240 | 522 | LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ |
| mbed_official | 174:8bb9f3a33240 | 523 | LPC_SYSCON->MAINCLKUEN = 0x01; |
| mbed_official | 174:8bb9f3a33240 | 524 | while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 174:8bb9f3a33240 | 525 | |
| mbed_official | 174:8bb9f3a33240 | 526 | LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; |
| mbed_official | 174:8bb9f3a33240 | 527 | #endif /* Clock Setup via Register */ |
| mbed_official | 174:8bb9f3a33240 | 528 | |
| mbed_official | 174:8bb9f3a33240 | 529 | #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */ |
| mbed_official | 174:8bb9f3a33240 | 530 | // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */ |
| mbed_official | 174:8bb9f3a33240 | 531 | // LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ |
| mbed_official | 174:8bb9f3a33240 | 532 | // LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ |
| mbed_official | 174:8bb9f3a33240 | 533 | // LPC_SYSCON->SYSPLLCLKUEN = 0x01; |
| mbed_official | 174:8bb9f3a33240 | 534 | // while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 174:8bb9f3a33240 | 535 | |
| mbed_official | 174:8bb9f3a33240 | 536 | LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */ |
| mbed_official | 174:8bb9f3a33240 | 537 | LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ |
| mbed_official | 174:8bb9f3a33240 | 538 | LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ |
| mbed_official | 174:8bb9f3a33240 | 539 | LPC_SYSCON->MAINCLKUEN = 0x01; |
| mbed_official | 174:8bb9f3a33240 | 540 | while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 174:8bb9f3a33240 | 541 | |
| mbed_official | 174:8bb9f3a33240 | 542 | LPC_SYSCON->SYSAHBCLKDIV = 1; |
| mbed_official | 174:8bb9f3a33240 | 543 | |
| mbed_official | 174:8bb9f3a33240 | 544 | setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000); |
| mbed_official | 174:8bb9f3a33240 | 545 | #endif /* Clock Setup via PLL API */ |
| mbed_official | 174:8bb9f3a33240 | 546 | |
| mbed_official | 174:8bb9f3a33240 | 547 | #if (USB_CLOCK_SETUP == 1) /* USB clock is used */ |
| mbed_official | 174:8bb9f3a33240 | 548 | LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ |
| mbed_official | 174:8bb9f3a33240 | 549 | |
| mbed_official | 174:8bb9f3a33240 | 550 | #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */ |
| mbed_official | 174:8bb9f3a33240 | 551 | LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ |
| mbed_official | 174:8bb9f3a33240 | 552 | LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ |
| mbed_official | 174:8bb9f3a33240 | 553 | LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ |
| mbed_official | 174:8bb9f3a33240 | 554 | LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ |
| mbed_official | 174:8bb9f3a33240 | 555 | LPC_SYSCON->USBPLLCLKUEN = 0x01; |
| mbed_official | 174:8bb9f3a33240 | 556 | while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ |
| mbed_official | 174:8bb9f3a33240 | 557 | |
| mbed_official | 174:8bb9f3a33240 | 558 | LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; |
| mbed_official | 174:8bb9f3a33240 | 559 | while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
| mbed_official | 174:8bb9f3a33240 | 560 | |
| mbed_official | 174:8bb9f3a33240 | 561 | LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ |
| mbed_official | 174:8bb9f3a33240 | 562 | #endif |
| mbed_official | 174:8bb9f3a33240 | 563 | |
| mbed_official | 174:8bb9f3a33240 | 564 | LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ |
| mbed_official | 174:8bb9f3a33240 | 565 | LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ |
| mbed_official | 174:8bb9f3a33240 | 566 | |
| mbed_official | 174:8bb9f3a33240 | 567 | #else /* USB clock is not used */ |
| mbed_official | 174:8bb9f3a33240 | 568 | LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ |
| mbed_official | 174:8bb9f3a33240 | 569 | LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ |
| mbed_official | 174:8bb9f3a33240 | 570 | #endif |
| mbed_official | 174:8bb9f3a33240 | 571 | |
| mbed_official | 174:8bb9f3a33240 | 572 | #endif /* Clock Setup */ |
| mbed_official | 174:8bb9f3a33240 | 573 | |
| mbed_official | 174:8bb9f3a33240 | 574 | } |
