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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h@600:7d17ca308cd1, 2015-07-31 (annotated)

Committer:
mbed_official
Date:
Fri Jul 31 14:15:09 2015 +0100
Revision:
600:7d17ca308cd1
Parent:
514:7668256dbe61 
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0



Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/



Enable LPC8xx usart when configuring it

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 514:7668256dbe61 1 /*******************************************************************************
mbed_official 514:7668256dbe61 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
mbed_official 514:7668256dbe61 3 *
mbed_official 514:7668256dbe61 4 * Permission is hereby granted, free of charge, to any person obtaining a
mbed_official 514:7668256dbe61 5 * copy of this software and associated documentation files (the "Software"),
mbed_official 514:7668256dbe61 6 * to deal in the Software without restriction, including without limitation
mbed_official 514:7668256dbe61 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
mbed_official 514:7668256dbe61 8 * and/or sell copies of the Software, and to permit persons to whom the
mbed_official 514:7668256dbe61 9 * Software is furnished to do so, subject to the following conditions:
mbed_official 514:7668256dbe61 10 *
mbed_official 514:7668256dbe61 11 * The above copyright notice and this permission notice shall be included
mbed_official 514:7668256dbe61 12 * in all copies or substantial portions of the Software.
mbed_official 514:7668256dbe61 13 *
mbed_official 514:7668256dbe61 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
mbed_official 514:7668256dbe61 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
mbed_official 514:7668256dbe61 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
mbed_official 514:7668256dbe61 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
mbed_official 514:7668256dbe61 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
mbed_official 514:7668256dbe61 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
mbed_official 514:7668256dbe61 20 * OTHER DEALINGS IN THE SOFTWARE.
mbed_official 514:7668256dbe61 21 *
mbed_official 514:7668256dbe61 22 * Except as contained in this notice, the name of Maxim Integrated
mbed_official 514:7668256dbe61 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
mbed_official 514:7668256dbe61 24 * Products, Inc. Branding Policy.
mbed_official 514:7668256dbe61 25 *
mbed_official 514:7668256dbe61 26 * The mere transfer of this software does not imply any licenses
mbed_official 514:7668256dbe61 27 * of trade secrets, proprietary technology, copyrights, patents,
mbed_official 514:7668256dbe61 28 * trademarks, maskwork rights, or any other form of intellectual
mbed_official 514:7668256dbe61 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
mbed_official 514:7668256dbe61 30 * ownership rights.
mbed_official 514:7668256dbe61 31 *******************************************************************************
mbed_official 514:7668256dbe61 32 */
mbed_official 514:7668256dbe61 33
mbed_official 514:7668256dbe61 34 #ifndef _MXC_ADC_REGS_H
mbed_official 514:7668256dbe61 35 #define _MXC_ADC_REGS_H
mbed_official 514:7668256dbe61 36
mbed_official 514:7668256dbe61 37 #ifdef __cplusplus
mbed_official 514:7668256dbe61 38 extern "C" {
mbed_official 514:7668256dbe61 39 #endif
mbed_official 514:7668256dbe61 40
mbed_official 514:7668256dbe61 41 #include <stdint.h>
mbed_official 514:7668256dbe61 42
mbed_official 514:7668256dbe61 43 /**
mbed_official 514:7668256dbe61 44 * @file adc_regs.h
mbed_official 514:7668256dbe61 45 * @addtogroup adc ADC
mbed_official 514:7668256dbe61 46 * @{
mbed_official 514:7668256dbe61 47 */
mbed_official 514:7668256dbe61 48
mbed_official 514:7668256dbe61 49 /**
mbed_official 514:7668256dbe61 50 * @brief Defines ADC Modes.
mbed_official 514:7668256dbe61 51 */
mbed_official 514:7668256dbe61 52 typedef enum {
mbed_official 514:7668256dbe61 53 /** Single Mode Full Rate */
mbed_official 514:7668256dbe61 54 MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
mbed_official 514:7668256dbe61 55 /** Single Mode Low Power */
mbed_official 514:7668256dbe61 56 MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
mbed_official 514:7668256dbe61 57 /** Continuous Mode Full Rate */
mbed_official 514:7668256dbe61 58 MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
mbed_official 514:7668256dbe61 59 /** Continuous Mode Low Power */
mbed_official 514:7668256dbe61 60 MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
mbed_official 514:7668256dbe61 61 /** Single Mode Full Rate with Scan Enabled */
mbed_official 514:7668256dbe61 62 MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
mbed_official 514:7668256dbe61 63 /** Single Mode Low Power with Scan Enabled */
mbed_official 514:7668256dbe61 64 MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
mbed_official 514:7668256dbe61 65 /** Continuous Mode Full Rate with Scan Enabled */
mbed_official 514:7668256dbe61 66 MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
mbed_official 514:7668256dbe61 67 /** Continuous Mode Low Power with Scan Enabled */
mbed_official 514:7668256dbe61 68 MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
mbed_official 514:7668256dbe61 69 } mxc_adc_mode_t;
mbed_official 514:7668256dbe61 70
mbed_official 514:7668256dbe61 71 /**
mbed_official 514:7668256dbe61 72 * @brief Defines ADC Range Control.
mbed_official 514:7668256dbe61 73 */
mbed_official 514:7668256dbe61 74 typedef enum {
mbed_official 514:7668256dbe61 75 /** Bi-polar Operation (-Vref/2 -> Vref/2) */
mbed_official 514:7668256dbe61 76 MXC_E_ADC_RANGE_HALF = 0,
mbed_official 514:7668256dbe61 77 /** Bi-polar Operation (-Vref -> Vref) */
mbed_official 514:7668256dbe61 78 MXC_E_ADC_RANGE_FULL
mbed_official 514:7668256dbe61 79 } mxc_adc_range_t;
mbed_official 514:7668256dbe61 80
mbed_official 514:7668256dbe61 81 /**
mbed_official 514:7668256dbe61 82 * @brief Defines ADC Bipolar operation.
mbed_official 514:7668256dbe61 83 */
mbed_official 514:7668256dbe61 84 typedef enum {
mbed_official 514:7668256dbe61 85 /** Uni-polar operation (0 -> Vref) */
mbed_official 514:7668256dbe61 86 MXC_E_ADC_BI_POL_UNIPOLAR = 0,
mbed_official 514:7668256dbe61 87 /** Bi-polar operation see ADC Range Control */
mbed_official 514:7668256dbe61 88 MXC_E_ADC_BI_POL_BIPOLAR
mbed_official 514:7668256dbe61 89 } mxc_adc_bi_pol_t;
mbed_official 514:7668256dbe61 90
mbed_official 514:7668256dbe61 91 /**
mbed_official 514:7668256dbe61 92 * @brief Defines Decimation Filter Modes.
mbed_official 514:7668256dbe61 93 */
mbed_official 514:7668256dbe61 94 typedef enum {
mbed_official 514:7668256dbe61 95 /** Decimation Filter ByPassed */
mbed_official 514:7668256dbe61 96 MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
mbed_official 514:7668256dbe61 97 /** Output Average Only*/
mbed_official 514:7668256dbe61 98 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
mbed_official 514:7668256dbe61 99 /** Output Average and Raw Data (Test Mode Only) */
mbed_official 514:7668256dbe61 100 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
mbed_official 514:7668256dbe61 101 } mxc_adc_avg_mode_t;
mbed_official 514:7668256dbe61 102
mbed_official 514:7668256dbe61 103 /**
mbed_official 514:7668256dbe61 104 * @brief Defines ADC StartMode Modes.
mbed_official 514:7668256dbe61 105 */
mbed_official 514:7668256dbe61 106 typedef enum {
mbed_official 514:7668256dbe61 107 /** StarMode via Software */
mbed_official 514:7668256dbe61 108 MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
mbed_official 514:7668256dbe61 109 /** StarMode via PulseTrain */
mbed_official 514:7668256dbe61 110 MXC_E_ADC_STRT_MODE_PULSETRAIN
mbed_official 514:7668256dbe61 111 } mxc_adc_strt_mode_t;
mbed_official 514:7668256dbe61 112
mbed_official 514:7668256dbe61 113 /**
mbed_official 514:7668256dbe61 114 * @brief Defines Mux Channel Select for the Positive Input to the ADC.
mbed_official 514:7668256dbe61 115 */
mbed_official 514:7668256dbe61 116 typedef enum {
mbed_official 514:7668256dbe61 117 /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
mbed_official 514:7668256dbe61 118 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
mbed_official 514:7668256dbe61 119 /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
mbed_official 514:7668256dbe61 120 MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
mbed_official 514:7668256dbe61 121 /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
mbed_official 514:7668256dbe61 122 MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
mbed_official 514:7668256dbe61 123 /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
mbed_official 514:7668256dbe61 124 MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
mbed_official 514:7668256dbe61 125 /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
mbed_official 514:7668256dbe61 126 MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
mbed_official 514:7668256dbe61 127 /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
mbed_official 514:7668256dbe61 128 MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
mbed_official 514:7668256dbe61 129 /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
mbed_official 514:7668256dbe61 130 MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
mbed_official 514:7668256dbe61 131 /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
mbed_official 514:7668256dbe61 132 MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
mbed_official 514:7668256dbe61 133 /** Single Mode Input AIN8+ */
mbed_official 514:7668256dbe61 134 MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
mbed_official 514:7668256dbe61 135 /** Single Mode Input AIN9+ */
mbed_official 514:7668256dbe61 136 MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
mbed_official 514:7668256dbe61 137 /** Single Mode Input AIN10+ */
mbed_official 514:7668256dbe61 138 MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
mbed_official 514:7668256dbe61 139 /** Single Mode Input AIN11+ */
mbed_official 514:7668256dbe61 140 MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
mbed_official 514:7668256dbe61 141 /** Single Mode Input AIN12+ */
mbed_official 514:7668256dbe61 142 MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
mbed_official 514:7668256dbe61 143 /** Single Mode Input AIN13+ */
mbed_official 514:7668256dbe61 144 MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
mbed_official 514:7668256dbe61 145 /** Single Mode Input AIN14+ */
mbed_official 514:7668256dbe61 146 MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
mbed_official 514:7668256dbe61 147 /** Single Mode Input AIN15+ */
mbed_official 514:7668256dbe61 148 MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
mbed_official 514:7668256dbe61 149 /** Positive Input VSSADC */
mbed_official 514:7668256dbe61 150 MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
mbed_official 514:7668256dbe61 151 /** Positive Input TMON_R */
mbed_official 514:7668256dbe61 152 MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
mbed_official 514:7668256dbe61 153 /** Positive Input VDDA/4 */
mbed_official 514:7668256dbe61 154 MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
mbed_official 514:7668256dbe61 155 /** Positive Input PWRMAN_TST */
mbed_official 514:7668256dbe61 156 MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
mbed_official 514:7668256dbe61 157 /** Positive Input Ain0Div */
mbed_official 514:7668256dbe61 158 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
mbed_official 514:7668256dbe61 159 /** Positive Input OpAmp OUTA */
mbed_official 514:7668256dbe61 160 MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
mbed_official 514:7668256dbe61 161 /** Positive Input OpAmp OUTB */
mbed_official 514:7668256dbe61 162 MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
mbed_official 514:7668256dbe61 163 /** Positive Input OpAmp OUTC */
mbed_official 514:7668256dbe61 164 MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
mbed_official 514:7668256dbe61 165 /** Positive Input OpAmp OUTD */
mbed_official 514:7668256dbe61 166 MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
mbed_official 514:7668256dbe61 167 /** Positive INA+ */
mbed_official 514:7668256dbe61 168 MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
mbed_official 514:7668256dbe61 169 /** Positive SNO_or */
mbed_official 514:7668256dbe61 170 MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
mbed_official 514:7668256dbe61 171 /** Positive SCM_or */
mbed_official 514:7668256dbe61 172 MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
mbed_official 514:7668256dbe61 173 /** Positive TPROBE_sense */
mbed_official 514:7668256dbe61 174 MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
mbed_official 514:7668256dbe61 175 /** Positive VREFDAC */
mbed_official 514:7668256dbe61 176 MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
mbed_official 514:7668256dbe61 177 /** Positive VREFADJ */
mbed_official 514:7668256dbe61 178 MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
mbed_official 514:7668256dbe61 179 /** Positive Vdd3xtal */
mbed_official 514:7668256dbe61 180 MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
mbed_official 514:7668256dbe61 181 } mxc_adc_pga_mux_ch_sel_t;
mbed_official 514:7668256dbe61 182
mbed_official 514:7668256dbe61 183 /**
mbed_official 514:7668256dbe61 184 * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
mbed_official 514:7668256dbe61 185 */
mbed_official 514:7668256dbe61 186 typedef enum {
mbed_official 514:7668256dbe61 187 /** Differential Mode Disabled */
mbed_official 514:7668256dbe61 188 MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
mbed_official 514:7668256dbe61 189 /** Differential Mode Enabled */
mbed_official 514:7668256dbe61 190 MXC_E_ADC_PGA_MUX_DIFF_ENABLE
mbed_official 514:7668256dbe61 191 } mxc_adc_pga_mux_diff_t;
mbed_official 514:7668256dbe61 192
mbed_official 514:7668256dbe61 193 /**
mbed_official 514:7668256dbe61 194 * @brief Defines the PGA Gain Options.
mbed_official 514:7668256dbe61 195 */
mbed_official 514:7668256dbe61 196 typedef enum {
mbed_official 514:7668256dbe61 197 /** PGA Gain = 1 */
mbed_official 514:7668256dbe61 198 MXC_E_ADC_PGA_GAIN_1 = 0,
mbed_official 514:7668256dbe61 199 /** PGA Gain = 2 */
mbed_official 514:7668256dbe61 200 MXC_E_ADC_PGA_GAIN_2,
mbed_official 514:7668256dbe61 201 /** PGA Gain = 4 */
mbed_official 514:7668256dbe61 202 MXC_E_ADC_PGA_GAIN_4,
mbed_official 514:7668256dbe61 203 /** PGA Gain = 8 */
mbed_official 514:7668256dbe61 204 MXC_E_ADC_PGA_GAIN_8,
mbed_official 514:7668256dbe61 205 } mxc_adc_pga_gain_t;
mbed_official 514:7668256dbe61 206
mbed_official 514:7668256dbe61 207 /**
mbed_official 514:7668256dbe61 208 * @brief Defines the Switch Control Mode.
mbed_official 514:7668256dbe61 209 */
mbed_official 514:7668256dbe61 210 typedef enum {
mbed_official 514:7668256dbe61 211 /** Switch Control Mode = Software */
mbed_official 514:7668256dbe61 212 MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
mbed_official 514:7668256dbe61 213 /** Switch Control Mode = Pulse Train */
mbed_official 514:7668256dbe61 214 MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
mbed_official 514:7668256dbe61 215 } mxc_adc_spst_sw_ctrl_t;
mbed_official 514:7668256dbe61 216
mbed_official 514:7668256dbe61 217 /**
mbed_official 514:7668256dbe61 218 * @brief Defines the number of channels to scan when Scan Mode is enabled.
mbed_official 514:7668256dbe61 219 */
mbed_official 514:7668256dbe61 220 typedef enum {
mbed_official 514:7668256dbe61 221 /** Number of Channels to Scan = 1 */
mbed_official 514:7668256dbe61 222 MXC_E_ADC_SCAN_CNT_1 = 0,
mbed_official 514:7668256dbe61 223 /** Number of Channels to Scan = 2 */
mbed_official 514:7668256dbe61 224 MXC_E_ADC_SCAN_CNT_2,
mbed_official 514:7668256dbe61 225 /** Number of Channels to Scan = 3 */
mbed_official 514:7668256dbe61 226 MXC_E_ADC_SCAN_CNT_3,
mbed_official 514:7668256dbe61 227 /** Number of Channels to Scan = 4 */
mbed_official 514:7668256dbe61 228 MXC_E_ADC_SCAN_CNT_4,
mbed_official 514:7668256dbe61 229 /** Number of Channels to Scan = 5 */
mbed_official 514:7668256dbe61 230 MXC_E_ADC_SCAN_CNT_5,
mbed_official 514:7668256dbe61 231 /** Number of Channels to Scan = 6 */
mbed_official 514:7668256dbe61 232 MXC_E_ADC_SCAN_CNT_6,
mbed_official 514:7668256dbe61 233 /** Number of Channels to Scan = 7 */
mbed_official 514:7668256dbe61 234 MXC_E_ADC_SCAN_CNT_7,
mbed_official 514:7668256dbe61 235 /** Number of Channels to Scan = 8 */
mbed_official 514:7668256dbe61 236 MXC_E_ADC_SCAN_CNT_8,
mbed_official 514:7668256dbe61 237 } mxc_adc_scan_cnt_t;
mbed_official 514:7668256dbe61 238
mbed_official 514:7668256dbe61 239 /* Offset Register Description
mbed_official 514:7668256dbe61 240 ====== =================================================== */
mbed_official 514:7668256dbe61 241 typedef struct {
mbed_official 514:7668256dbe61 242 __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
mbed_official 514:7668256dbe61 243 __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
mbed_official 514:7668256dbe61 244 __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
mbed_official 514:7668256dbe61 245 __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
mbed_official 514:7668256dbe61 246 __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
mbed_official 514:7668256dbe61 247 __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
mbed_official 514:7668256dbe61 248 __IO uint32_t out; /* 0x0018 ADC Output Register */
mbed_official 514:7668256dbe61 249 } mxc_adc_regs_t;
mbed_official 514:7668256dbe61 250
mbed_official 514:7668256dbe61 251 /* Offset Register Description
mbed_official 514:7668256dbe61 252 ====== =================================================== */
mbed_official 514:7668256dbe61 253 typedef struct {
mbed_official 514:7668256dbe61 254 __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
mbed_official 514:7668256dbe61 255 __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
mbed_official 514:7668256dbe61 256 __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
mbed_official 514:7668256dbe61 257 __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
mbed_official 514:7668256dbe61 258 __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
mbed_official 514:7668256dbe61 259 } mxc_adccfg_regs_t;
mbed_official 514:7668256dbe61 260
mbed_official 514:7668256dbe61 261 typedef struct {
mbed_official 514:7668256dbe61 262 __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
mbed_official 514:7668256dbe61 263 } mxc_adc_fifo_regs_t;
mbed_official 514:7668256dbe61 264
mbed_official 514:7668256dbe61 265 /*
mbed_official 514:7668256dbe61 266 Register offsets for module ADC, ADCCFG, ADC_FIFO
mbed_official 514:7668256dbe61 267 */
mbed_official 514:7668256dbe61 268 #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
mbed_official 514:7668256dbe61 269 #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
mbed_official 514:7668256dbe61 270 #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
mbed_official 514:7668256dbe61 271 #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
mbed_official 514:7668256dbe61 272 #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
mbed_official 514:7668256dbe61 273 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
mbed_official 514:7668256dbe61 274 #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
mbed_official 514:7668256dbe61 275
mbed_official 514:7668256dbe61 276 #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
mbed_official 514:7668256dbe61 277 #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
mbed_official 514:7668256dbe61 278 #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
mbed_official 514:7668256dbe61 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
mbed_official 514:7668256dbe61 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
mbed_official 514:7668256dbe61 281 #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
mbed_official 514:7668256dbe61 282
mbed_official 514:7668256dbe61 283 /*
mbed_official 514:7668256dbe61 284 Field positions and masks for module ADC.
mbed_official 514:7668256dbe61 285 */
mbed_official 514:7668256dbe61 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
mbed_official 514:7668256dbe61 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
mbed_official 514:7668256dbe61 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
mbed_official 514:7668256dbe61 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
mbed_official 514:7668256dbe61 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
mbed_official 514:7668256dbe61 291 #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
mbed_official 514:7668256dbe61 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
mbed_official 514:7668256dbe61 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
mbed_official 514:7668256dbe61 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
mbed_official 514:7668256dbe61 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
mbed_official 514:7668256dbe61 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS 9
mbed_official 514:7668256dbe61 297 #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
mbed_official 514:7668256dbe61 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
mbed_official 514:7668256dbe61 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
mbed_official 514:7668256dbe61 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
mbed_official 514:7668256dbe61 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
mbed_official 514:7668256dbe61 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
mbed_official 514:7668256dbe61 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
mbed_official 514:7668256dbe61 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
mbed_official 514:7668256dbe61 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
mbed_official 514:7668256dbe61 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
mbed_official 514:7668256dbe61 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
mbed_official 514:7668256dbe61 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
mbed_official 514:7668256dbe61 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
mbed_official 514:7668256dbe61 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
mbed_official 514:7668256dbe61 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
mbed_official 514:7668256dbe61 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
mbed_official 514:7668256dbe61 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
mbed_official 514:7668256dbe61 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
mbed_official 514:7668256dbe61 315 #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
mbed_official 514:7668256dbe61 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
mbed_official 514:7668256dbe61 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
mbed_official 514:7668256dbe61 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
mbed_official 514:7668256dbe61 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
mbed_official 514:7668256dbe61 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
mbed_official 514:7668256dbe61 321 #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
mbed_official 514:7668256dbe61 322
mbed_official 514:7668256dbe61 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
mbed_official 514:7668256dbe61 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
mbed_official 514:7668256dbe61 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
mbed_official 514:7668256dbe61 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
mbed_official 514:7668256dbe61 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
mbed_official 514:7668256dbe61 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
mbed_official 514:7668256dbe61 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
mbed_official 514:7668256dbe61 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
mbed_official 514:7668256dbe61 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
mbed_official 514:7668256dbe61 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
mbed_official 514:7668256dbe61 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
mbed_official 514:7668256dbe61 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
mbed_official 514:7668256dbe61 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
mbed_official 514:7668256dbe61 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
mbed_official 514:7668256dbe61 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
mbed_official 514:7668256dbe61 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
mbed_official 514:7668256dbe61 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
mbed_official 514:7668256dbe61 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
mbed_official 514:7668256dbe61 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
mbed_official 514:7668256dbe61 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
mbed_official 514:7668256dbe61 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
mbed_official 514:7668256dbe61 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
mbed_official 514:7668256dbe61 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
mbed_official 514:7668256dbe61 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
mbed_official 514:7668256dbe61 347
mbed_official 514:7668256dbe61 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
mbed_official 514:7668256dbe61 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
mbed_official 514:7668256dbe61 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
mbed_official 514:7668256dbe61 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
mbed_official 514:7668256dbe61 352
mbed_official 514:7668256dbe61 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
mbed_official 514:7668256dbe61 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
mbed_official 514:7668256dbe61 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
mbed_official 514:7668256dbe61 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
mbed_official 514:7668256dbe61 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
mbed_official 514:7668256dbe61 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
mbed_official 514:7668256dbe61 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
mbed_official 514:7668256dbe61 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
mbed_official 514:7668256dbe61 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
mbed_official 514:7668256dbe61 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
mbed_official 514:7668256dbe61 363
mbed_official 514:7668256dbe61 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
mbed_official 514:7668256dbe61 365 #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
mbed_official 514:7668256dbe61 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
mbed_official 514:7668256dbe61 367 #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
mbed_official 514:7668256dbe61 368
mbed_official 514:7668256dbe61 369 #define MXC_F_ADC_INTR_FIFO_AF_POS 6
mbed_official 514:7668256dbe61 370 #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
mbed_official 514:7668256dbe61 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
mbed_official 514:7668256dbe61 372 #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
mbed_official 514:7668256dbe61 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
mbed_official 514:7668256dbe61 374 #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
mbed_official 514:7668256dbe61 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
mbed_official 514:7668256dbe61 376 #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
mbed_official 514:7668256dbe61 377 #define MXC_F_ADC_INTR_DONE_IF_POS 10
mbed_official 514:7668256dbe61 378 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
mbed_official 514:7668256dbe61 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
mbed_official 514:7668256dbe61 380 #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
mbed_official 514:7668256dbe61 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
mbed_official 514:7668256dbe61 382 #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
mbed_official 514:7668256dbe61 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
mbed_official 514:7668256dbe61 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
mbed_official 514:7668256dbe61 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
mbed_official 514:7668256dbe61 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
mbed_official 514:7668256dbe61 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
mbed_official 514:7668256dbe61 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
mbed_official 514:7668256dbe61 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
mbed_official 514:7668256dbe61 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
mbed_official 514:7668256dbe61 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
mbed_official 514:7668256dbe61 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
mbed_official 514:7668256dbe61 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
mbed_official 514:7668256dbe61 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
mbed_official 514:7668256dbe61 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
mbed_official 514:7668256dbe61 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
mbed_official 514:7668256dbe61 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
mbed_official 514:7668256dbe61 398 #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
mbed_official 514:7668256dbe61 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
mbed_official 514:7668256dbe61 400 #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
mbed_official 514:7668256dbe61 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
mbed_official 514:7668256dbe61 402 #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
mbed_official 514:7668256dbe61 403 #define MXC_F_ADC_INTR_DONE_IE_POS 26
mbed_official 514:7668256dbe61 404 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
mbed_official 514:7668256dbe61 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
mbed_official 514:7668256dbe61 406 #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
mbed_official 514:7668256dbe61 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
mbed_official 514:7668256dbe61 408 #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
mbed_official 514:7668256dbe61 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
mbed_official 514:7668256dbe61 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
mbed_official 514:7668256dbe61 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
mbed_official 514:7668256dbe61 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
mbed_official 514:7668256dbe61 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
mbed_official 514:7668256dbe61 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
mbed_official 514:7668256dbe61 415
mbed_official 514:7668256dbe61 416 #define MXC_F_ADC_OUT_DATA_REG_POS 0
mbed_official 514:7668256dbe61 417 #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
mbed_official 514:7668256dbe61 418
mbed_official 514:7668256dbe61 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
mbed_official 514:7668256dbe61 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
mbed_official 514:7668256dbe61 421
mbed_official 514:7668256dbe61 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
mbed_official 514:7668256dbe61 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
mbed_official 514:7668256dbe61 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
mbed_official 514:7668256dbe61 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
mbed_official 514:7668256dbe61 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
mbed_official 514:7668256dbe61 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
mbed_official 514:7668256dbe61 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
mbed_official 514:7668256dbe61 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
mbed_official 514:7668256dbe61 430
mbed_official 514:7668256dbe61 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
mbed_official 514:7668256dbe61 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
mbed_official 514:7668256dbe61 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
mbed_official 514:7668256dbe61 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
mbed_official 514:7668256dbe61 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
mbed_official 514:7668256dbe61 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
mbed_official 514:7668256dbe61 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
mbed_official 514:7668256dbe61 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
mbed_official 514:7668256dbe61 439
mbed_official 514:7668256dbe61 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
mbed_official 514:7668256dbe61 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
mbed_official 514:7668256dbe61 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
mbed_official 514:7668256dbe61 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
mbed_official 514:7668256dbe61 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
mbed_official 514:7668256dbe61 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
mbed_official 514:7668256dbe61 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
mbed_official 514:7668256dbe61 447 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
mbed_official 514:7668256dbe61 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
mbed_official 514:7668256dbe61 449 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
mbed_official 514:7668256dbe61 450
mbed_official 514:7668256dbe61 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
mbed_official 514:7668256dbe61 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
mbed_official 514:7668256dbe61 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
mbed_official 514:7668256dbe61 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
mbed_official 514:7668256dbe61 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
mbed_official 514:7668256dbe61 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
mbed_official 514:7668256dbe61 457
mbed_official 514:7668256dbe61 458 #ifdef __cplusplus
mbed_official 514:7668256dbe61 459 }
mbed_official 514:7668256dbe61 460 #endif
mbed_official 514:7668256dbe61 461
mbed_official 514:7668256dbe61 462 /**
mbed_official 514:7668256dbe61 463 * @}
mbed_official 514:7668256dbe61 464 */
mbed_official 514:7668256dbe61 465
mbed_official 514:7668256dbe61 466 #endif /* _MXC_ADC_REGS_H */