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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/MKL26Z4.h@600:7d17ca308cd1, 2015-07-31 (annotated)

Committer:
mbed_official
Date:
Fri Jul 31 14:15:09 2015 +0100
Revision:
600:7d17ca308cd1
Parent:
585:a1ed5b41f74f 
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0



Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/



Enable LPC8xx usart when configuring it

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 585:a1ed5b41f74f 1 /*
mbed_official 585:a1ed5b41f74f 2 ** ###################################################################
mbed_official 585:a1ed5b41f74f 3 ** Processors: MKL26Z128VFM4
mbed_official 585:a1ed5b41f74f 4 ** MKL26Z64VFM4
mbed_official 585:a1ed5b41f74f 5 ** MKL26Z32VM4
mbed_official 585:a1ed5b41f74f 6 ** MKL26Z128VFT4
mbed_official 585:a1ed5b41f74f 7 ** MKL26Z64VFT4
mbed_official 585:a1ed5b41f74f 8 ** MKL26Z32VFT4
mbed_official 585:a1ed5b41f74f 9 ** MKL26Z256VLH4
mbed_official 585:a1ed5b41f74f 10 ** MKL26Z128VLH4
mbed_official 585:a1ed5b41f74f 11 ** MKL26Z64VLH4
mbed_official 585:a1ed5b41f74f 12 ** MKL26Z32VLH4
mbed_official 585:a1ed5b41f74f 13 ** MKL26Z256VLK4
mbed_official 585:a1ed5b41f74f 14 ** MKL26Z256VLL4
mbed_official 585:a1ed5b41f74f 15 ** MKL26Z128VLL4
mbed_official 585:a1ed5b41f74f 16 ** MKL26Z256VMC4
mbed_official 585:a1ed5b41f74f 17 ** MKL26Z128VMC4
mbed_official 585:a1ed5b41f74f 18 **
mbed_official 585:a1ed5b41f74f 19 ** Compilers: ARM Compiler
mbed_official 585:a1ed5b41f74f 20 ** Freescale C/C++ for Embedded ARM
mbed_official 585:a1ed5b41f74f 21 ** GNU C Compiler
mbed_official 585:a1ed5b41f74f 22 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 585:a1ed5b41f74f 23 **
mbed_official 585:a1ed5b41f74f 24 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
mbed_official 585:a1ed5b41f74f 25 ** Version: rev. 1.0, 2012-12-12
mbed_official 585:a1ed5b41f74f 26 **
mbed_official 585:a1ed5b41f74f 27 ** Abstract:
mbed_official 585:a1ed5b41f74f 28 ** CMSIS Peripheral Access Layer for MKL26Z4
mbed_official 585:a1ed5b41f74f 29 **
mbed_official 585:a1ed5b41f74f 30 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
mbed_official 585:a1ed5b41f74f 31 **
mbed_official 585:a1ed5b41f74f 32 ** http: www.freescale.com
mbed_official 585:a1ed5b41f74f 33 ** mail: support@freescale.com
mbed_official 585:a1ed5b41f74f 34 **
mbed_official 585:a1ed5b41f74f 35 ** Revisions:
mbed_official 585:a1ed5b41f74f 36 ** - rev. 1.0 (2012-12-12)
mbed_official 585:a1ed5b41f74f 37 ** Initial version.
mbed_official 585:a1ed5b41f74f 38 **
mbed_official 585:a1ed5b41f74f 39 ** ###################################################################
mbed_official 585:a1ed5b41f74f 40 */
mbed_official 585:a1ed5b41f74f 41
mbed_official 585:a1ed5b41f74f 42 /**
mbed_official 585:a1ed5b41f74f 43 * @file MKL26Z4.h
mbed_official 585:a1ed5b41f74f 44 * @version 1.0
mbed_official 585:a1ed5b41f74f 45 * @date 2012-12-12
mbed_official 585:a1ed5b41f74f 46 * @brief CMSIS Peripheral Access Layer for MKL26Z4
mbed_official 585:a1ed5b41f74f 47 *
mbed_official 585:a1ed5b41f74f 48 * CMSIS Peripheral Access Layer for MKL26Z4
mbed_official 585:a1ed5b41f74f 49 */
mbed_official 585:a1ed5b41f74f 50
mbed_official 585:a1ed5b41f74f 51 #if !defined(MKL26Z4_H_)
mbed_official 585:a1ed5b41f74f 52 #define MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
mbed_official 585:a1ed5b41f74f 53
mbed_official 585:a1ed5b41f74f 54 /** Memory map major version (memory maps with equal major version number are
mbed_official 585:a1ed5b41f74f 55 * compatible) */
mbed_official 585:a1ed5b41f74f 56 #define MCU_MEM_MAP_VERSION 0x0100u
mbed_official 585:a1ed5b41f74f 57 /** Memory map minor version */
mbed_official 585:a1ed5b41f74f 58 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
mbed_official 585:a1ed5b41f74f 59
mbed_official 585:a1ed5b41f74f 60
mbed_official 585:a1ed5b41f74f 61 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 62 -- Interrupt vector numbers
mbed_official 585:a1ed5b41f74f 63 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 64
mbed_official 585:a1ed5b41f74f 65 /**
mbed_official 585:a1ed5b41f74f 66 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 585:a1ed5b41f74f 67 * @{
mbed_official 585:a1ed5b41f74f 68 */
mbed_official 585:a1ed5b41f74f 69
mbed_official 585:a1ed5b41f74f 70 /** Interrupt Number Definitions */
mbed_official 585:a1ed5b41f74f 71 typedef enum IRQn {
mbed_official 585:a1ed5b41f74f 72 /* Core interrupts */
mbed_official 585:a1ed5b41f74f 73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 585:a1ed5b41f74f 74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
mbed_official 585:a1ed5b41f74f 75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
mbed_official 585:a1ed5b41f74f 76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
mbed_official 585:a1ed5b41f74f 77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
mbed_official 585:a1ed5b41f74f 78
mbed_official 585:a1ed5b41f74f 79 /* Device specific interrupts */
mbed_official 585:a1ed5b41f74f 80 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
mbed_official 585:a1ed5b41f74f 81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
mbed_official 585:a1ed5b41f74f 82 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
mbed_official 585:a1ed5b41f74f 83 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
mbed_official 585:a1ed5b41f74f 84 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
mbed_official 585:a1ed5b41f74f 85 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
mbed_official 585:a1ed5b41f74f 86 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 585:a1ed5b41f74f 87 LLW_IRQn = 7, /**< Low Leakage Wakeup */
mbed_official 585:a1ed5b41f74f 88 I2C0_IRQn = 8, /**< I2C0 interrupt */
mbed_official 585:a1ed5b41f74f 89 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
mbed_official 585:a1ed5b41f74f 90 SPI0_IRQn = 10, /**< SPI0 interrupt */
mbed_official 585:a1ed5b41f74f 91 SPI1_IRQn = 11, /**< SPI1 interrupt */
mbed_official 585:a1ed5b41f74f 92 UART0_IRQn = 12, /**< UART0 status/error interrupt */
mbed_official 585:a1ed5b41f74f 93 UART1_IRQn = 13, /**< UART1 status/error interrupt */
mbed_official 585:a1ed5b41f74f 94 UART2_IRQn = 14, /**< UART2 status/error interrupt */
mbed_official 585:a1ed5b41f74f 95 ADC0_IRQn = 15, /**< ADC0 interrupt */
mbed_official 585:a1ed5b41f74f 96 CMP0_IRQn = 16, /**< CMP0 interrupt */
mbed_official 585:a1ed5b41f74f 97 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
mbed_official 585:a1ed5b41f74f 98 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
mbed_official 585:a1ed5b41f74f 99 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
mbed_official 585:a1ed5b41f74f 100 RTC_IRQn = 20, /**< RTC interrupt */
mbed_official 585:a1ed5b41f74f 101 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
mbed_official 585:a1ed5b41f74f 102 PIT_IRQn = 22, /**< PIT timer interrupt */
mbed_official 585:a1ed5b41f74f 103 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
mbed_official 585:a1ed5b41f74f 104 USB0_IRQn = 24, /**< USB0 interrupt */
mbed_official 585:a1ed5b41f74f 105 DAC0_IRQn = 25, /**< DAC0 interrupt */
mbed_official 585:a1ed5b41f74f 106 TSI0_IRQn = 26, /**< TSI0 interrupt */
mbed_official 585:a1ed5b41f74f 107 MCG_IRQn = 27, /**< MCG interrupt */
mbed_official 585:a1ed5b41f74f 108 LPTimer_IRQn = 28, /**< LPTimer interrupt */
mbed_official 585:a1ed5b41f74f 109 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
mbed_official 585:a1ed5b41f74f 110 PORTA_IRQn = 30, /**< Port A interrupt */
mbed_official 585:a1ed5b41f74f 111 PORTD_IRQn = 31 /**< Port D interrupt */
mbed_official 585:a1ed5b41f74f 112 } IRQn_Type;
mbed_official 585:a1ed5b41f74f 113
mbed_official 585:a1ed5b41f74f 114 /**
mbed_official 585:a1ed5b41f74f 115 * @}
mbed_official 585:a1ed5b41f74f 116 */ /* end of group Interrupt_vector_numbers */
mbed_official 585:a1ed5b41f74f 117
mbed_official 585:a1ed5b41f74f 118
mbed_official 585:a1ed5b41f74f 119 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 120 -- Cortex M0 Core Configuration
mbed_official 585:a1ed5b41f74f 121 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 122
mbed_official 585:a1ed5b41f74f 123 /**
mbed_official 585:a1ed5b41f74f 124 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
mbed_official 585:a1ed5b41f74f 125 * @{
mbed_official 585:a1ed5b41f74f 126 */
mbed_official 585:a1ed5b41f74f 127
mbed_official 585:a1ed5b41f74f 128 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
mbed_official 585:a1ed5b41f74f 129 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 585:a1ed5b41f74f 130 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
mbed_official 585:a1ed5b41f74f 131 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
mbed_official 585:a1ed5b41f74f 132 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 585:a1ed5b41f74f 133
mbed_official 585:a1ed5b41f74f 134 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
mbed_official 585:a1ed5b41f74f 135 #include "system_MKL26Z4.h" /* Device specific configuration file */
mbed_official 585:a1ed5b41f74f 136
mbed_official 585:a1ed5b41f74f 137 /**
mbed_official 585:a1ed5b41f74f 138 * @}
mbed_official 585:a1ed5b41f74f 139 */ /* end of group Cortex_Core_Configuration */
mbed_official 585:a1ed5b41f74f 140
mbed_official 585:a1ed5b41f74f 141
mbed_official 585:a1ed5b41f74f 142 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 143 -- Device Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 144 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 145
mbed_official 585:a1ed5b41f74f 146 /**
mbed_official 585:a1ed5b41f74f 147 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 148 * @{
mbed_official 585:a1ed5b41f74f 149 */
mbed_official 585:a1ed5b41f74f 150
mbed_official 585:a1ed5b41f74f 151
mbed_official 585:a1ed5b41f74f 152 /*
mbed_official 585:a1ed5b41f74f 153 ** Start of section using anonymous unions
mbed_official 585:a1ed5b41f74f 154 */
mbed_official 585:a1ed5b41f74f 155
mbed_official 585:a1ed5b41f74f 156 #if defined(__ARMCC_VERSION)
mbed_official 585:a1ed5b41f74f 157 #pragma push
mbed_official 585:a1ed5b41f74f 158 #pragma anon_unions
mbed_official 585:a1ed5b41f74f 159 #elif defined(__CWCC__)
mbed_official 585:a1ed5b41f74f 160 #pragma push
mbed_official 585:a1ed5b41f74f 161 #pragma cpp_extensions on
mbed_official 585:a1ed5b41f74f 162 #elif defined(__GNUC__)
mbed_official 585:a1ed5b41f74f 163 /* anonymous unions are enabled by default */
mbed_official 585:a1ed5b41f74f 164 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 585:a1ed5b41f74f 165 #pragma language=extended
mbed_official 585:a1ed5b41f74f 166 #else
mbed_official 585:a1ed5b41f74f 167 #error Not supported compiler type
mbed_official 585:a1ed5b41f74f 168 #endif
mbed_official 585:a1ed5b41f74f 169
mbed_official 585:a1ed5b41f74f 170 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 171 -- ADC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 172 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 173
mbed_official 585:a1ed5b41f74f 174 /**
mbed_official 585:a1ed5b41f74f 175 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 176 * @{
mbed_official 585:a1ed5b41f74f 177 */
mbed_official 585:a1ed5b41f74f 178
mbed_official 585:a1ed5b41f74f 179 /** ADC - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 180 typedef struct {
mbed_official 585:a1ed5b41f74f 181 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 182 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 183 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 585:a1ed5b41f74f 184 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 185 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 585:a1ed5b41f74f 186 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 585:a1ed5b41f74f 187 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 585:a1ed5b41f74f 188 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 585:a1ed5b41f74f 189 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 585:a1ed5b41f74f 190 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 585:a1ed5b41f74f 191 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mbed_official 585:a1ed5b41f74f 192 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 585:a1ed5b41f74f 193 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 585:a1ed5b41f74f 194 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 585:a1ed5b41f74f 195 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 585:a1ed5b41f74f 196 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 585:a1ed5b41f74f 197 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 585:a1ed5b41f74f 198 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 585:a1ed5b41f74f 199 uint8_t RESERVED_0[4];
mbed_official 585:a1ed5b41f74f 200 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mbed_official 585:a1ed5b41f74f 201 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mbed_official 585:a1ed5b41f74f 202 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mbed_official 585:a1ed5b41f74f 203 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mbed_official 585:a1ed5b41f74f 204 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mbed_official 585:a1ed5b41f74f 205 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mbed_official 585:a1ed5b41f74f 206 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mbed_official 585:a1ed5b41f74f 207 } ADC_Type;
mbed_official 585:a1ed5b41f74f 208
mbed_official 585:a1ed5b41f74f 209 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 210 -- ADC Register Masks
mbed_official 585:a1ed5b41f74f 211 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 212
mbed_official 585:a1ed5b41f74f 213 /**
mbed_official 585:a1ed5b41f74f 214 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 585:a1ed5b41f74f 215 * @{
mbed_official 585:a1ed5b41f74f 216 */
mbed_official 585:a1ed5b41f74f 217
mbed_official 585:a1ed5b41f74f 218 /* SC1 Bit Fields */
mbed_official 585:a1ed5b41f74f 219 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 220 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 585:a1ed5b41f74f 221 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 585:a1ed5b41f74f 222 #define ADC_SC1_DIFF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 223 #define ADC_SC1_DIFF_SHIFT 5
mbed_official 585:a1ed5b41f74f 224 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 225 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 226 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 585:a1ed5b41f74f 227 #define ADC_SC1_COCO_SHIFT 7
mbed_official 585:a1ed5b41f74f 228 /* CFG1 Bit Fields */
mbed_official 585:a1ed5b41f74f 229 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 585:a1ed5b41f74f 230 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 585:a1ed5b41f74f 231 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 585:a1ed5b41f74f 232 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 585:a1ed5b41f74f 233 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 585:a1ed5b41f74f 234 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 585:a1ed5b41f74f 235 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 585:a1ed5b41f74f 236 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 585:a1ed5b41f74f 237 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 585:a1ed5b41f74f 238 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 585:a1ed5b41f74f 239 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 585:a1ed5b41f74f 240 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 585:a1ed5b41f74f 241 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 585:a1ed5b41f74f 242 /* CFG2 Bit Fields */
mbed_official 585:a1ed5b41f74f 243 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 585:a1ed5b41f74f 244 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 585:a1ed5b41f74f 245 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 585:a1ed5b41f74f 246 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 585:a1ed5b41f74f 247 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 585:a1ed5b41f74f 248 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 249 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 250 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 251 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 585:a1ed5b41f74f 252 /* R Bit Fields */
mbed_official 585:a1ed5b41f74f 253 #define ADC_R_D_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 254 #define ADC_R_D_SHIFT 0
mbed_official 585:a1ed5b41f74f 255 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 585:a1ed5b41f74f 256 /* CV1 Bit Fields */
mbed_official 585:a1ed5b41f74f 257 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 258 #define ADC_CV1_CV_SHIFT 0
mbed_official 585:a1ed5b41f74f 259 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 585:a1ed5b41f74f 260 /* CV2 Bit Fields */
mbed_official 585:a1ed5b41f74f 261 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 262 #define ADC_CV2_CV_SHIFT 0
mbed_official 585:a1ed5b41f74f 263 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 585:a1ed5b41f74f 264 /* SC2 Bit Fields */
mbed_official 585:a1ed5b41f74f 265 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 585:a1ed5b41f74f 266 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 267 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 585:a1ed5b41f74f 268 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 269 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 585:a1ed5b41f74f 270 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 271 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 585:a1ed5b41f74f 272 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 585:a1ed5b41f74f 273 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 585:a1ed5b41f74f 274 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 275 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 585:a1ed5b41f74f 276 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 585:a1ed5b41f74f 277 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 585:a1ed5b41f74f 278 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 585:a1ed5b41f74f 279 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 585:a1ed5b41f74f 280 /* SC3 Bit Fields */
mbed_official 585:a1ed5b41f74f 281 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 585:a1ed5b41f74f 282 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 585:a1ed5b41f74f 283 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 585:a1ed5b41f74f 284 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 285 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 585:a1ed5b41f74f 286 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 585:a1ed5b41f74f 287 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 585:a1ed5b41f74f 288 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 585:a1ed5b41f74f 289 #define ADC_SC3_CALF_SHIFT 6
mbed_official 585:a1ed5b41f74f 290 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 585:a1ed5b41f74f 291 #define ADC_SC3_CAL_SHIFT 7
mbed_official 585:a1ed5b41f74f 292 /* OFS Bit Fields */
mbed_official 585:a1ed5b41f74f 293 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 294 #define ADC_OFS_OFS_SHIFT 0
mbed_official 585:a1ed5b41f74f 295 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 585:a1ed5b41f74f 296 /* PG Bit Fields */
mbed_official 585:a1ed5b41f74f 297 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 298 #define ADC_PG_PG_SHIFT 0
mbed_official 585:a1ed5b41f74f 299 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 585:a1ed5b41f74f 300 /* MG Bit Fields */
mbed_official 585:a1ed5b41f74f 301 #define ADC_MG_MG_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 302 #define ADC_MG_MG_SHIFT 0
mbed_official 585:a1ed5b41f74f 303 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mbed_official 585:a1ed5b41f74f 304 /* CLPD Bit Fields */
mbed_official 585:a1ed5b41f74f 305 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 306 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 585:a1ed5b41f74f 307 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 585:a1ed5b41f74f 308 /* CLPS Bit Fields */
mbed_official 585:a1ed5b41f74f 309 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 310 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 585:a1ed5b41f74f 311 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 585:a1ed5b41f74f 312 /* CLP4 Bit Fields */
mbed_official 585:a1ed5b41f74f 313 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 585:a1ed5b41f74f 314 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 585:a1ed5b41f74f 315 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 585:a1ed5b41f74f 316 /* CLP3 Bit Fields */
mbed_official 585:a1ed5b41f74f 317 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 585:a1ed5b41f74f 318 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 585:a1ed5b41f74f 319 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 585:a1ed5b41f74f 320 /* CLP2 Bit Fields */
mbed_official 585:a1ed5b41f74f 321 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 322 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 585:a1ed5b41f74f 323 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 585:a1ed5b41f74f 324 /* CLP1 Bit Fields */
mbed_official 585:a1ed5b41f74f 325 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 585:a1ed5b41f74f 326 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 585:a1ed5b41f74f 327 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 585:a1ed5b41f74f 328 /* CLP0 Bit Fields */
mbed_official 585:a1ed5b41f74f 329 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 330 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 585:a1ed5b41f74f 331 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 585:a1ed5b41f74f 332 /* CLMD Bit Fields */
mbed_official 585:a1ed5b41f74f 333 #define ADC_CLMD_CLMD_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 334 #define ADC_CLMD_CLMD_SHIFT 0
mbed_official 585:a1ed5b41f74f 335 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mbed_official 585:a1ed5b41f74f 336 /* CLMS Bit Fields */
mbed_official 585:a1ed5b41f74f 337 #define ADC_CLMS_CLMS_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 338 #define ADC_CLMS_CLMS_SHIFT 0
mbed_official 585:a1ed5b41f74f 339 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mbed_official 585:a1ed5b41f74f 340 /* CLM4 Bit Fields */
mbed_official 585:a1ed5b41f74f 341 #define ADC_CLM4_CLM4_MASK 0x3FFu
mbed_official 585:a1ed5b41f74f 342 #define ADC_CLM4_CLM4_SHIFT 0
mbed_official 585:a1ed5b41f74f 343 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mbed_official 585:a1ed5b41f74f 344 /* CLM3 Bit Fields */
mbed_official 585:a1ed5b41f74f 345 #define ADC_CLM3_CLM3_MASK 0x1FFu
mbed_official 585:a1ed5b41f74f 346 #define ADC_CLM3_CLM3_SHIFT 0
mbed_official 585:a1ed5b41f74f 347 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mbed_official 585:a1ed5b41f74f 348 /* CLM2 Bit Fields */
mbed_official 585:a1ed5b41f74f 349 #define ADC_CLM2_CLM2_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 350 #define ADC_CLM2_CLM2_SHIFT 0
mbed_official 585:a1ed5b41f74f 351 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mbed_official 585:a1ed5b41f74f 352 /* CLM1 Bit Fields */
mbed_official 585:a1ed5b41f74f 353 #define ADC_CLM1_CLM1_MASK 0x7Fu
mbed_official 585:a1ed5b41f74f 354 #define ADC_CLM1_CLM1_SHIFT 0
mbed_official 585:a1ed5b41f74f 355 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mbed_official 585:a1ed5b41f74f 356 /* CLM0 Bit Fields */
mbed_official 585:a1ed5b41f74f 357 #define ADC_CLM0_CLM0_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 358 #define ADC_CLM0_CLM0_SHIFT 0
mbed_official 585:a1ed5b41f74f 359 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mbed_official 585:a1ed5b41f74f 360
mbed_official 585:a1ed5b41f74f 361 /**
mbed_official 585:a1ed5b41f74f 362 * @}
mbed_official 585:a1ed5b41f74f 363 */ /* end of group ADC_Register_Masks */
mbed_official 585:a1ed5b41f74f 364
mbed_official 585:a1ed5b41f74f 365
mbed_official 585:a1ed5b41f74f 366 /* ADC - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 367 /** Peripheral ADC0 base address */
mbed_official 585:a1ed5b41f74f 368 #define ADC0_BASE (0x4003B000u)
mbed_official 585:a1ed5b41f74f 369 /** Peripheral ADC0 base pointer */
mbed_official 585:a1ed5b41f74f 370 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 585:a1ed5b41f74f 371 /** Array initializer of ADC peripheral base pointers */
mbed_official 585:a1ed5b41f74f 372 #define ADC_BASES { ADC0 }
mbed_official 585:a1ed5b41f74f 373
mbed_official 585:a1ed5b41f74f 374 /**
mbed_official 585:a1ed5b41f74f 375 * @}
mbed_official 585:a1ed5b41f74f 376 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 377
mbed_official 585:a1ed5b41f74f 378
mbed_official 585:a1ed5b41f74f 379 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 380 -- CMP Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 381 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 382
mbed_official 585:a1ed5b41f74f 383 /**
mbed_official 585:a1ed5b41f74f 384 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 385 * @{
mbed_official 585:a1ed5b41f74f 386 */
mbed_official 585:a1ed5b41f74f 387
mbed_official 585:a1ed5b41f74f 388 /** CMP - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 389 typedef struct {
mbed_official 585:a1ed5b41f74f 390 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 391 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 392 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 393 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 394 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 395 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 396 } CMP_Type;
mbed_official 585:a1ed5b41f74f 397
mbed_official 585:a1ed5b41f74f 398 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 399 -- CMP Register Masks
mbed_official 585:a1ed5b41f74f 400 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 401
mbed_official 585:a1ed5b41f74f 402 /**
mbed_official 585:a1ed5b41f74f 403 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 585:a1ed5b41f74f 404 * @{
mbed_official 585:a1ed5b41f74f 405 */
mbed_official 585:a1ed5b41f74f 406
mbed_official 585:a1ed5b41f74f 407 /* CR0 Bit Fields */
mbed_official 585:a1ed5b41f74f 408 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 585:a1ed5b41f74f 409 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 585:a1ed5b41f74f 410 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 585:a1ed5b41f74f 411 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 585:a1ed5b41f74f 412 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 585:a1ed5b41f74f 413 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 585:a1ed5b41f74f 414 /* CR1 Bit Fields */
mbed_official 585:a1ed5b41f74f 415 #define CMP_CR1_EN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 416 #define CMP_CR1_EN_SHIFT 0
mbed_official 585:a1ed5b41f74f 417 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 418 #define CMP_CR1_OPE_SHIFT 1
mbed_official 585:a1ed5b41f74f 419 #define CMP_CR1_COS_MASK 0x4u
mbed_official 585:a1ed5b41f74f 420 #define CMP_CR1_COS_SHIFT 2
mbed_official 585:a1ed5b41f74f 421 #define CMP_CR1_INV_MASK 0x8u
mbed_official 585:a1ed5b41f74f 422 #define CMP_CR1_INV_SHIFT 3
mbed_official 585:a1ed5b41f74f 423 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 424 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 585:a1ed5b41f74f 425 #define CMP_CR1_TRIGM_MASK 0x20u
mbed_official 585:a1ed5b41f74f 426 #define CMP_CR1_TRIGM_SHIFT 5
mbed_official 585:a1ed5b41f74f 427 #define CMP_CR1_WE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 428 #define CMP_CR1_WE_SHIFT 6
mbed_official 585:a1ed5b41f74f 429 #define CMP_CR1_SE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 430 #define CMP_CR1_SE_SHIFT 7
mbed_official 585:a1ed5b41f74f 431 /* FPR Bit Fields */
mbed_official 585:a1ed5b41f74f 432 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 433 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 585:a1ed5b41f74f 434 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 585:a1ed5b41f74f 435 /* SCR Bit Fields */
mbed_official 585:a1ed5b41f74f 436 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 585:a1ed5b41f74f 437 #define CMP_SCR_COUT_SHIFT 0
mbed_official 585:a1ed5b41f74f 438 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 585:a1ed5b41f74f 439 #define CMP_SCR_CFF_SHIFT 1
mbed_official 585:a1ed5b41f74f 440 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 585:a1ed5b41f74f 441 #define CMP_SCR_CFR_SHIFT 2
mbed_official 585:a1ed5b41f74f 442 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 585:a1ed5b41f74f 443 #define CMP_SCR_IEF_SHIFT 3
mbed_official 585:a1ed5b41f74f 444 #define CMP_SCR_IER_MASK 0x10u
mbed_official 585:a1ed5b41f74f 445 #define CMP_SCR_IER_SHIFT 4
mbed_official 585:a1ed5b41f74f 446 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 447 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 448 /* DACCR Bit Fields */
mbed_official 585:a1ed5b41f74f 449 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 450 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 451 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 585:a1ed5b41f74f 452 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 585:a1ed5b41f74f 453 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 585:a1ed5b41f74f 454 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 455 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 456 /* MUXCR Bit Fields */
mbed_official 585:a1ed5b41f74f 457 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 585:a1ed5b41f74f 458 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 459 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 585:a1ed5b41f74f 460 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 585:a1ed5b41f74f 461 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 585:a1ed5b41f74f 462 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 585:a1ed5b41f74f 463 #define CMP_MUXCR_PSTM_MASK 0x80u
mbed_official 585:a1ed5b41f74f 464 #define CMP_MUXCR_PSTM_SHIFT 7
mbed_official 585:a1ed5b41f74f 465
mbed_official 585:a1ed5b41f74f 466 /**
mbed_official 585:a1ed5b41f74f 467 * @}
mbed_official 585:a1ed5b41f74f 468 */ /* end of group CMP_Register_Masks */
mbed_official 585:a1ed5b41f74f 469
mbed_official 585:a1ed5b41f74f 470
mbed_official 585:a1ed5b41f74f 471 /* CMP - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 472 /** Peripheral CMP0 base address */
mbed_official 585:a1ed5b41f74f 473 #define CMP0_BASE (0x40073000u)
mbed_official 585:a1ed5b41f74f 474 /** Peripheral CMP0 base pointer */
mbed_official 585:a1ed5b41f74f 475 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 585:a1ed5b41f74f 476 /** Array initializer of CMP peripheral base pointers */
mbed_official 585:a1ed5b41f74f 477 #define CMP_BASES { CMP0 }
mbed_official 585:a1ed5b41f74f 478
mbed_official 585:a1ed5b41f74f 479 /**
mbed_official 585:a1ed5b41f74f 480 * @}
mbed_official 585:a1ed5b41f74f 481 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 482
mbed_official 585:a1ed5b41f74f 483
mbed_official 585:a1ed5b41f74f 484 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 485 -- DAC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 486 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 487
mbed_official 585:a1ed5b41f74f 488 /**
mbed_official 585:a1ed5b41f74f 489 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 490 * @{
mbed_official 585:a1ed5b41f74f 491 */
mbed_official 585:a1ed5b41f74f 492
mbed_official 585:a1ed5b41f74f 493 /** DAC - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 494 typedef struct {
mbed_official 585:a1ed5b41f74f 495 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 585:a1ed5b41f74f 496 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 585:a1ed5b41f74f 497 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 585:a1ed5b41f74f 498 } DAT[2];
mbed_official 585:a1ed5b41f74f 499 uint8_t RESERVED_0[28];
mbed_official 585:a1ed5b41f74f 500 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 585:a1ed5b41f74f 501 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 585:a1ed5b41f74f 502 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 585:a1ed5b41f74f 503 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 585:a1ed5b41f74f 504 } DAC_Type;
mbed_official 585:a1ed5b41f74f 505
mbed_official 585:a1ed5b41f74f 506 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 507 -- DAC Register Masks
mbed_official 585:a1ed5b41f74f 508 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 509
mbed_official 585:a1ed5b41f74f 510 /**
mbed_official 585:a1ed5b41f74f 511 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 585:a1ed5b41f74f 512 * @{
mbed_official 585:a1ed5b41f74f 513 */
mbed_official 585:a1ed5b41f74f 514
mbed_official 585:a1ed5b41f74f 515 /* DATL Bit Fields */
mbed_official 585:a1ed5b41f74f 516 #define DAC_DATL_DATA0_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 517 #define DAC_DATL_DATA0_SHIFT 0
mbed_official 585:a1ed5b41f74f 518 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mbed_official 585:a1ed5b41f74f 519 /* DATH Bit Fields */
mbed_official 585:a1ed5b41f74f 520 #define DAC_DATH_DATA1_MASK 0xFu
mbed_official 585:a1ed5b41f74f 521 #define DAC_DATH_DATA1_SHIFT 0
mbed_official 585:a1ed5b41f74f 522 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mbed_official 585:a1ed5b41f74f 523 /* SR Bit Fields */
mbed_official 585:a1ed5b41f74f 524 #define DAC_SR_DACBFRPBF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 525 #define DAC_SR_DACBFRPBF_SHIFT 0
mbed_official 585:a1ed5b41f74f 526 #define DAC_SR_DACBFRPTF_MASK 0x2u
mbed_official 585:a1ed5b41f74f 527 #define DAC_SR_DACBFRPTF_SHIFT 1
mbed_official 585:a1ed5b41f74f 528 /* C0 Bit Fields */
mbed_official 585:a1ed5b41f74f 529 #define DAC_C0_DACBBIEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 530 #define DAC_C0_DACBBIEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 531 #define DAC_C0_DACBTIEN_MASK 0x2u
mbed_official 585:a1ed5b41f74f 532 #define DAC_C0_DACBTIEN_SHIFT 1
mbed_official 585:a1ed5b41f74f 533 #define DAC_C0_LPEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 534 #define DAC_C0_LPEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 535 #define DAC_C0_DACSWTRG_MASK 0x10u
mbed_official 585:a1ed5b41f74f 536 #define DAC_C0_DACSWTRG_SHIFT 4
mbed_official 585:a1ed5b41f74f 537 #define DAC_C0_DACTRGSEL_MASK 0x20u
mbed_official 585:a1ed5b41f74f 538 #define DAC_C0_DACTRGSEL_SHIFT 5
mbed_official 585:a1ed5b41f74f 539 #define DAC_C0_DACRFS_MASK 0x40u
mbed_official 585:a1ed5b41f74f 540 #define DAC_C0_DACRFS_SHIFT 6
mbed_official 585:a1ed5b41f74f 541 #define DAC_C0_DACEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 542 #define DAC_C0_DACEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 543 /* C1 Bit Fields */
mbed_official 585:a1ed5b41f74f 544 #define DAC_C1_DACBFEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 545 #define DAC_C1_DACBFEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 546 #define DAC_C1_DACBFMD_MASK 0x4u
mbed_official 585:a1ed5b41f74f 547 #define DAC_C1_DACBFMD_SHIFT 2
mbed_official 585:a1ed5b41f74f 548 #define DAC_C1_DMAEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 549 #define DAC_C1_DMAEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 550 /* C2 Bit Fields */
mbed_official 585:a1ed5b41f74f 551 #define DAC_C2_DACBFUP_MASK 0x1u
mbed_official 585:a1ed5b41f74f 552 #define DAC_C2_DACBFUP_SHIFT 0
mbed_official 585:a1ed5b41f74f 553 #define DAC_C2_DACBFRP_MASK 0x10u
mbed_official 585:a1ed5b41f74f 554 #define DAC_C2_DACBFRP_SHIFT 4
mbed_official 585:a1ed5b41f74f 555
mbed_official 585:a1ed5b41f74f 556 /**
mbed_official 585:a1ed5b41f74f 557 * @}
mbed_official 585:a1ed5b41f74f 558 */ /* end of group DAC_Register_Masks */
mbed_official 585:a1ed5b41f74f 559
mbed_official 585:a1ed5b41f74f 560
mbed_official 585:a1ed5b41f74f 561 /* DAC - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 562 /** Peripheral DAC0 base address */
mbed_official 585:a1ed5b41f74f 563 #define DAC0_BASE (0x4003F000u)
mbed_official 585:a1ed5b41f74f 564 /** Peripheral DAC0 base pointer */
mbed_official 585:a1ed5b41f74f 565 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 585:a1ed5b41f74f 566 /** Array initializer of DAC peripheral base pointers */
mbed_official 585:a1ed5b41f74f 567 #define DAC_BASES { DAC0 }
mbed_official 585:a1ed5b41f74f 568
mbed_official 585:a1ed5b41f74f 569 /**
mbed_official 585:a1ed5b41f74f 570 * @}
mbed_official 585:a1ed5b41f74f 571 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 572
mbed_official 585:a1ed5b41f74f 573
mbed_official 585:a1ed5b41f74f 574 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 575 -- DMA Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 576 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 577
mbed_official 585:a1ed5b41f74f 578 /**
mbed_official 585:a1ed5b41f74f 579 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 580 * @{
mbed_official 585:a1ed5b41f74f 581 */
mbed_official 585:a1ed5b41f74f 582
mbed_official 585:a1ed5b41f74f 583 /** DMA - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 584 typedef struct {
mbed_official 585:a1ed5b41f74f 585 uint8_t RESERVED_0[256];
mbed_official 585:a1ed5b41f74f 586 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 587 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 588 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 589 union { /* offset: 0x108, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 590 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 591 struct { /* offset: 0x108, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 592 uint8_t RESERVED_0[3];
mbed_official 585:a1ed5b41f74f 593 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 594 } DMA_DSR_ACCESS8BIT;
mbed_official 585:a1ed5b41f74f 595 };
mbed_official 585:a1ed5b41f74f 596 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 597 } DMA[4];
mbed_official 585:a1ed5b41f74f 598 } DMA_Type;
mbed_official 585:a1ed5b41f74f 599
mbed_official 585:a1ed5b41f74f 600 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 601 -- DMA Register Masks
mbed_official 585:a1ed5b41f74f 602 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 603
mbed_official 585:a1ed5b41f74f 604 /**
mbed_official 585:a1ed5b41f74f 605 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 585:a1ed5b41f74f 606 * @{
mbed_official 585:a1ed5b41f74f 607 */
mbed_official 585:a1ed5b41f74f 608
mbed_official 585:a1ed5b41f74f 609 /* SAR Bit Fields */
mbed_official 585:a1ed5b41f74f 610 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 611 #define DMA_SAR_SAR_SHIFT 0
mbed_official 585:a1ed5b41f74f 612 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
mbed_official 585:a1ed5b41f74f 613 /* DAR Bit Fields */
mbed_official 585:a1ed5b41f74f 614 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 615 #define DMA_DAR_DAR_SHIFT 0
mbed_official 585:a1ed5b41f74f 616 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
mbed_official 585:a1ed5b41f74f 617 /* DSR_BCR Bit Fields */
mbed_official 585:a1ed5b41f74f 618 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
mbed_official 585:a1ed5b41f74f 619 #define DMA_DSR_BCR_BCR_SHIFT 0
mbed_official 585:a1ed5b41f74f 620 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
mbed_official 585:a1ed5b41f74f 621 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 622 #define DMA_DSR_BCR_DONE_SHIFT 24
mbed_official 585:a1ed5b41f74f 623 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 624 #define DMA_DSR_BCR_BSY_SHIFT 25
mbed_official 585:a1ed5b41f74f 625 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
mbed_official 585:a1ed5b41f74f 626 #define DMA_DSR_BCR_REQ_SHIFT 26
mbed_official 585:a1ed5b41f74f 627 #define DMA_DSR_BCR_BED_MASK 0x10000000u
mbed_official 585:a1ed5b41f74f 628 #define DMA_DSR_BCR_BED_SHIFT 28
mbed_official 585:a1ed5b41f74f 629 #define DMA_DSR_BCR_BES_MASK 0x20000000u
mbed_official 585:a1ed5b41f74f 630 #define DMA_DSR_BCR_BES_SHIFT 29
mbed_official 585:a1ed5b41f74f 631 #define DMA_DSR_BCR_CE_MASK 0x40000000u
mbed_official 585:a1ed5b41f74f 632 #define DMA_DSR_BCR_CE_SHIFT 30
mbed_official 585:a1ed5b41f74f 633 /* DCR Bit Fields */
mbed_official 585:a1ed5b41f74f 634 #define DMA_DCR_LCH2_MASK 0x3u
mbed_official 585:a1ed5b41f74f 635 #define DMA_DCR_LCH2_SHIFT 0
mbed_official 585:a1ed5b41f74f 636 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
mbed_official 585:a1ed5b41f74f 637 #define DMA_DCR_LCH1_MASK 0xCu
mbed_official 585:a1ed5b41f74f 638 #define DMA_DCR_LCH1_SHIFT 2
mbed_official 585:a1ed5b41f74f 639 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
mbed_official 585:a1ed5b41f74f 640 #define DMA_DCR_LINKCC_MASK 0x30u
mbed_official 585:a1ed5b41f74f 641 #define DMA_DCR_LINKCC_SHIFT 4
mbed_official 585:a1ed5b41f74f 642 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
mbed_official 585:a1ed5b41f74f 643 #define DMA_DCR_D_REQ_MASK 0x80u
mbed_official 585:a1ed5b41f74f 644 #define DMA_DCR_D_REQ_SHIFT 7
mbed_official 585:a1ed5b41f74f 645 #define DMA_DCR_DMOD_MASK 0xF00u
mbed_official 585:a1ed5b41f74f 646 #define DMA_DCR_DMOD_SHIFT 8
mbed_official 585:a1ed5b41f74f 647 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
mbed_official 585:a1ed5b41f74f 648 #define DMA_DCR_SMOD_MASK 0xF000u
mbed_official 585:a1ed5b41f74f 649 #define DMA_DCR_SMOD_SHIFT 12
mbed_official 585:a1ed5b41f74f 650 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
mbed_official 585:a1ed5b41f74f 651 #define DMA_DCR_START_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 652 #define DMA_DCR_START_SHIFT 16
mbed_official 585:a1ed5b41f74f 653 #define DMA_DCR_DSIZE_MASK 0x60000u
mbed_official 585:a1ed5b41f74f 654 #define DMA_DCR_DSIZE_SHIFT 17
mbed_official 585:a1ed5b41f74f 655 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
mbed_official 585:a1ed5b41f74f 656 #define DMA_DCR_DINC_MASK 0x80000u
mbed_official 585:a1ed5b41f74f 657 #define DMA_DCR_DINC_SHIFT 19
mbed_official 585:a1ed5b41f74f 658 #define DMA_DCR_SSIZE_MASK 0x300000u
mbed_official 585:a1ed5b41f74f 659 #define DMA_DCR_SSIZE_SHIFT 20
mbed_official 585:a1ed5b41f74f 660 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
mbed_official 585:a1ed5b41f74f 661 #define DMA_DCR_SINC_MASK 0x400000u
mbed_official 585:a1ed5b41f74f 662 #define DMA_DCR_SINC_SHIFT 22
mbed_official 585:a1ed5b41f74f 663 #define DMA_DCR_EADREQ_MASK 0x800000u
mbed_official 585:a1ed5b41f74f 664 #define DMA_DCR_EADREQ_SHIFT 23
mbed_official 585:a1ed5b41f74f 665 #define DMA_DCR_AA_MASK 0x10000000u
mbed_official 585:a1ed5b41f74f 666 #define DMA_DCR_AA_SHIFT 28
mbed_official 585:a1ed5b41f74f 667 #define DMA_DCR_CS_MASK 0x20000000u
mbed_official 585:a1ed5b41f74f 668 #define DMA_DCR_CS_SHIFT 29
mbed_official 585:a1ed5b41f74f 669 #define DMA_DCR_ERQ_MASK 0x40000000u
mbed_official 585:a1ed5b41f74f 670 #define DMA_DCR_ERQ_SHIFT 30
mbed_official 585:a1ed5b41f74f 671 #define DMA_DCR_EINT_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 672 #define DMA_DCR_EINT_SHIFT 31
mbed_official 585:a1ed5b41f74f 673
mbed_official 585:a1ed5b41f74f 674 /**
mbed_official 585:a1ed5b41f74f 675 * @}
mbed_official 585:a1ed5b41f74f 676 */ /* end of group DMA_Register_Masks */
mbed_official 585:a1ed5b41f74f 677
mbed_official 585:a1ed5b41f74f 678
mbed_official 585:a1ed5b41f74f 679 /* DMA - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 680 /** Peripheral DMA base address */
mbed_official 585:a1ed5b41f74f 681 #define DMA_BASE (0x40008000u)
mbed_official 585:a1ed5b41f74f 682 /** Peripheral DMA base pointer */
mbed_official 585:a1ed5b41f74f 683 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 585:a1ed5b41f74f 684 /** Array initializer of DMA peripheral base pointers */
mbed_official 585:a1ed5b41f74f 685 #define DMA_BASES { DMA0 }
mbed_official 585:a1ed5b41f74f 686
mbed_official 585:a1ed5b41f74f 687 /**
mbed_official 585:a1ed5b41f74f 688 * @}
mbed_official 585:a1ed5b41f74f 689 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 690
mbed_official 585:a1ed5b41f74f 691
mbed_official 585:a1ed5b41f74f 692 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 693 -- DMAMUX Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 694 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 695
mbed_official 585:a1ed5b41f74f 696 /**
mbed_official 585:a1ed5b41f74f 697 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 698 * @{
mbed_official 585:a1ed5b41f74f 699 */
mbed_official 585:a1ed5b41f74f 700
mbed_official 585:a1ed5b41f74f 701 /** DMAMUX - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 702 typedef struct {
mbed_official 585:a1ed5b41f74f 703 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 585:a1ed5b41f74f 704 } DMAMUX_Type;
mbed_official 585:a1ed5b41f74f 705
mbed_official 585:a1ed5b41f74f 706 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 707 -- DMAMUX Register Masks
mbed_official 585:a1ed5b41f74f 708 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 709
mbed_official 585:a1ed5b41f74f 710 /**
mbed_official 585:a1ed5b41f74f 711 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 585:a1ed5b41f74f 712 * @{
mbed_official 585:a1ed5b41f74f 713 */
mbed_official 585:a1ed5b41f74f 714
mbed_official 585:a1ed5b41f74f 715 /* CHCFG Bit Fields */
mbed_official 585:a1ed5b41f74f 716 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 717 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 585:a1ed5b41f74f 718 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 585:a1ed5b41f74f 719 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 585:a1ed5b41f74f 720 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 585:a1ed5b41f74f 721 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 585:a1ed5b41f74f 722 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 585:a1ed5b41f74f 723
mbed_official 585:a1ed5b41f74f 724 /**
mbed_official 585:a1ed5b41f74f 725 * @}
mbed_official 585:a1ed5b41f74f 726 */ /* end of group DMAMUX_Register_Masks */
mbed_official 585:a1ed5b41f74f 727
mbed_official 585:a1ed5b41f74f 728
mbed_official 585:a1ed5b41f74f 729 /* DMAMUX - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 730 /** Peripheral DMAMUX0 base address */
mbed_official 585:a1ed5b41f74f 731 #define DMAMUX0_BASE (0x40021000u)
mbed_official 585:a1ed5b41f74f 732 /** Peripheral DMAMUX0 base pointer */
mbed_official 585:a1ed5b41f74f 733 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
mbed_official 585:a1ed5b41f74f 734 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 585:a1ed5b41f74f 735 #define DMAMUX_BASES { DMAMUX0 }
mbed_official 585:a1ed5b41f74f 736
mbed_official 585:a1ed5b41f74f 737 /**
mbed_official 585:a1ed5b41f74f 738 * @}
mbed_official 585:a1ed5b41f74f 739 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 740
mbed_official 585:a1ed5b41f74f 741
mbed_official 585:a1ed5b41f74f 742 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 743 -- FGPIO Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 744 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 745
mbed_official 585:a1ed5b41f74f 746 /**
mbed_official 585:a1ed5b41f74f 747 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 748 * @{
mbed_official 585:a1ed5b41f74f 749 */
mbed_official 585:a1ed5b41f74f 750
mbed_official 585:a1ed5b41f74f 751 /** FGPIO - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 752 typedef struct {
mbed_official 585:a1ed5b41f74f 753 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 754 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 755 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 756 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 757 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 585:a1ed5b41f74f 758 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 585:a1ed5b41f74f 759 } FGPIO_Type;
mbed_official 585:a1ed5b41f74f 760
mbed_official 585:a1ed5b41f74f 761 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 762 -- FGPIO Register Masks
mbed_official 585:a1ed5b41f74f 763 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 764
mbed_official 585:a1ed5b41f74f 765 /**
mbed_official 585:a1ed5b41f74f 766 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
mbed_official 585:a1ed5b41f74f 767 * @{
mbed_official 585:a1ed5b41f74f 768 */
mbed_official 585:a1ed5b41f74f 769
mbed_official 585:a1ed5b41f74f 770 /* PDOR Bit Fields */
mbed_official 585:a1ed5b41f74f 771 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 772 #define FGPIO_PDOR_PDO_SHIFT 0
mbed_official 585:a1ed5b41f74f 773 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
mbed_official 585:a1ed5b41f74f 774 /* PSOR Bit Fields */
mbed_official 585:a1ed5b41f74f 775 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 776 #define FGPIO_PSOR_PTSO_SHIFT 0
mbed_official 585:a1ed5b41f74f 777 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
mbed_official 585:a1ed5b41f74f 778 /* PCOR Bit Fields */
mbed_official 585:a1ed5b41f74f 779 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 780 #define FGPIO_PCOR_PTCO_SHIFT 0
mbed_official 585:a1ed5b41f74f 781 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
mbed_official 585:a1ed5b41f74f 782 /* PTOR Bit Fields */
mbed_official 585:a1ed5b41f74f 783 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 784 #define FGPIO_PTOR_PTTO_SHIFT 0
mbed_official 585:a1ed5b41f74f 785 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
mbed_official 585:a1ed5b41f74f 786 /* PDIR Bit Fields */
mbed_official 585:a1ed5b41f74f 787 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 788 #define FGPIO_PDIR_PDI_SHIFT 0
mbed_official 585:a1ed5b41f74f 789 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
mbed_official 585:a1ed5b41f74f 790 /* PDDR Bit Fields */
mbed_official 585:a1ed5b41f74f 791 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 792 #define FGPIO_PDDR_PDD_SHIFT 0
mbed_official 585:a1ed5b41f74f 793 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
mbed_official 585:a1ed5b41f74f 794
mbed_official 585:a1ed5b41f74f 795 /**
mbed_official 585:a1ed5b41f74f 796 * @}
mbed_official 585:a1ed5b41f74f 797 */ /* end of group FGPIO_Register_Masks */
mbed_official 585:a1ed5b41f74f 798
mbed_official 585:a1ed5b41f74f 799
mbed_official 585:a1ed5b41f74f 800 /* FGPIO - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 801 /** Peripheral FPTA base address */
mbed_official 585:a1ed5b41f74f 802 #define FPTA_BASE (0xF80FF000u)
mbed_official 585:a1ed5b41f74f 803 /** Peripheral FPTA base pointer */
mbed_official 585:a1ed5b41f74f 804 #define FPTA ((FGPIO_Type *)FPTA_BASE)
mbed_official 585:a1ed5b41f74f 805 /** Peripheral FPTB base address */
mbed_official 585:a1ed5b41f74f 806 #define FPTB_BASE (0xF80FF040u)
mbed_official 585:a1ed5b41f74f 807 /** Peripheral FPTB base pointer */
mbed_official 585:a1ed5b41f74f 808 #define FPTB ((FGPIO_Type *)FPTB_BASE)
mbed_official 585:a1ed5b41f74f 809 /** Peripheral FPTC base address */
mbed_official 585:a1ed5b41f74f 810 #define FPTC_BASE (0xF80FF080u)
mbed_official 585:a1ed5b41f74f 811 /** Peripheral FPTC base pointer */
mbed_official 585:a1ed5b41f74f 812 #define FPTC ((FGPIO_Type *)FPTC_BASE)
mbed_official 585:a1ed5b41f74f 813 /** Peripheral FPTD base address */
mbed_official 585:a1ed5b41f74f 814 #define FPTD_BASE (0xF80FF0C0u)
mbed_official 585:a1ed5b41f74f 815 /** Peripheral FPTD base pointer */
mbed_official 585:a1ed5b41f74f 816 #define FPTD ((FGPIO_Type *)FPTD_BASE)
mbed_official 585:a1ed5b41f74f 817 /** Peripheral FPTE base address */
mbed_official 585:a1ed5b41f74f 818 #define FPTE_BASE (0xF80FF100u)
mbed_official 585:a1ed5b41f74f 819 /** Peripheral FPTE base pointer */
mbed_official 585:a1ed5b41f74f 820 #define FPTE ((FGPIO_Type *)FPTE_BASE)
mbed_official 585:a1ed5b41f74f 821 /** Array initializer of FGPIO peripheral base pointers */
mbed_official 585:a1ed5b41f74f 822 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
mbed_official 585:a1ed5b41f74f 823
mbed_official 585:a1ed5b41f74f 824 /**
mbed_official 585:a1ed5b41f74f 825 * @}
mbed_official 585:a1ed5b41f74f 826 */ /* end of group FGPIO_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 827
mbed_official 585:a1ed5b41f74f 828
mbed_official 585:a1ed5b41f74f 829 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 830 -- FTFA Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 831 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 832
mbed_official 585:a1ed5b41f74f 833 /**
mbed_official 585:a1ed5b41f74f 834 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 835 * @{
mbed_official 585:a1ed5b41f74f 836 */
mbed_official 585:a1ed5b41f74f 837
mbed_official 585:a1ed5b41f74f 838 /** FTFA - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 839 typedef struct {
mbed_official 585:a1ed5b41f74f 840 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 841 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 842 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 843 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 844 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 845 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 846 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 847 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 585:a1ed5b41f74f 848 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 849 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 585:a1ed5b41f74f 850 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 585:a1ed5b41f74f 851 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 585:a1ed5b41f74f 852 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 585:a1ed5b41f74f 853 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 585:a1ed5b41f74f 854 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 585:a1ed5b41f74f 855 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 585:a1ed5b41f74f 856 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 585:a1ed5b41f74f 857 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 585:a1ed5b41f74f 858 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 585:a1ed5b41f74f 859 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 585:a1ed5b41f74f 860 } FTFA_Type;
mbed_official 585:a1ed5b41f74f 861
mbed_official 585:a1ed5b41f74f 862 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 863 -- FTFA Register Masks
mbed_official 585:a1ed5b41f74f 864 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 865
mbed_official 585:a1ed5b41f74f 866 /**
mbed_official 585:a1ed5b41f74f 867 * @addtogroup FTFA_Register_Masks FTFA Register Masks
mbed_official 585:a1ed5b41f74f 868 * @{
mbed_official 585:a1ed5b41f74f 869 */
mbed_official 585:a1ed5b41f74f 870
mbed_official 585:a1ed5b41f74f 871 /* FSTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 872 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 873 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
mbed_official 585:a1ed5b41f74f 874 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 875 #define FTFA_FSTAT_FPVIOL_SHIFT 4
mbed_official 585:a1ed5b41f74f 876 #define FTFA_FSTAT_ACCERR_MASK 0x20u
mbed_official 585:a1ed5b41f74f 877 #define FTFA_FSTAT_ACCERR_SHIFT 5
mbed_official 585:a1ed5b41f74f 878 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 585:a1ed5b41f74f 879 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
mbed_official 585:a1ed5b41f74f 880 #define FTFA_FSTAT_CCIF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 881 #define FTFA_FSTAT_CCIF_SHIFT 7
mbed_official 585:a1ed5b41f74f 882 /* FCNFG Bit Fields */
mbed_official 585:a1ed5b41f74f 883 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 585:a1ed5b41f74f 884 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
mbed_official 585:a1ed5b41f74f 885 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 585:a1ed5b41f74f 886 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
mbed_official 585:a1ed5b41f74f 887 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 888 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 889 #define FTFA_FCNFG_CCIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 890 #define FTFA_FCNFG_CCIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 891 /* FSEC Bit Fields */
mbed_official 585:a1ed5b41f74f 892 #define FTFA_FSEC_SEC_MASK 0x3u
mbed_official 585:a1ed5b41f74f 893 #define FTFA_FSEC_SEC_SHIFT 0
mbed_official 585:a1ed5b41f74f 894 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
mbed_official 585:a1ed5b41f74f 895 #define FTFA_FSEC_FSLACC_MASK 0xCu
mbed_official 585:a1ed5b41f74f 896 #define FTFA_FSEC_FSLACC_SHIFT 2
mbed_official 585:a1ed5b41f74f 897 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
mbed_official 585:a1ed5b41f74f 898 #define FTFA_FSEC_MEEN_MASK 0x30u
mbed_official 585:a1ed5b41f74f 899 #define FTFA_FSEC_MEEN_SHIFT 4
mbed_official 585:a1ed5b41f74f 900 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
mbed_official 585:a1ed5b41f74f 901 #define FTFA_FSEC_KEYEN_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 902 #define FTFA_FSEC_KEYEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 903 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
mbed_official 585:a1ed5b41f74f 904 /* FOPT Bit Fields */
mbed_official 585:a1ed5b41f74f 905 #define FTFA_FOPT_OPT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 906 #define FTFA_FOPT_OPT_SHIFT 0
mbed_official 585:a1ed5b41f74f 907 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
mbed_official 585:a1ed5b41f74f 908 /* FCCOB3 Bit Fields */
mbed_official 585:a1ed5b41f74f 909 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 910 #define FTFA_FCCOB3_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 911 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 912 /* FCCOB2 Bit Fields */
mbed_official 585:a1ed5b41f74f 913 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 914 #define FTFA_FCCOB2_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 915 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 916 /* FCCOB1 Bit Fields */
mbed_official 585:a1ed5b41f74f 917 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 918 #define FTFA_FCCOB1_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 919 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 920 /* FCCOB0 Bit Fields */
mbed_official 585:a1ed5b41f74f 921 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 922 #define FTFA_FCCOB0_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 923 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 924 /* FCCOB7 Bit Fields */
mbed_official 585:a1ed5b41f74f 925 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 926 #define FTFA_FCCOB7_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 927 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 928 /* FCCOB6 Bit Fields */
mbed_official 585:a1ed5b41f74f 929 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 930 #define FTFA_FCCOB6_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 931 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 932 /* FCCOB5 Bit Fields */
mbed_official 585:a1ed5b41f74f 933 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 934 #define FTFA_FCCOB5_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 935 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 936 /* FCCOB4 Bit Fields */
mbed_official 585:a1ed5b41f74f 937 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 938 #define FTFA_FCCOB4_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 939 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 940 /* FCCOBB Bit Fields */
mbed_official 585:a1ed5b41f74f 941 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 942 #define FTFA_FCCOBB_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 943 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 944 /* FCCOBA Bit Fields */
mbed_official 585:a1ed5b41f74f 945 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 946 #define FTFA_FCCOBA_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 947 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 948 /* FCCOB9 Bit Fields */
mbed_official 585:a1ed5b41f74f 949 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 950 #define FTFA_FCCOB9_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 951 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 952 /* FCCOB8 Bit Fields */
mbed_official 585:a1ed5b41f74f 953 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 954 #define FTFA_FCCOB8_CCOBn_SHIFT 0
mbed_official 585:a1ed5b41f74f 955 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
mbed_official 585:a1ed5b41f74f 956 /* FPROT3 Bit Fields */
mbed_official 585:a1ed5b41f74f 957 #define FTFA_FPROT3_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 958 #define FTFA_FPROT3_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 959 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
mbed_official 585:a1ed5b41f74f 960 /* FPROT2 Bit Fields */
mbed_official 585:a1ed5b41f74f 961 #define FTFA_FPROT2_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 962 #define FTFA_FPROT2_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 963 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
mbed_official 585:a1ed5b41f74f 964 /* FPROT1 Bit Fields */
mbed_official 585:a1ed5b41f74f 965 #define FTFA_FPROT1_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 966 #define FTFA_FPROT1_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 967 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
mbed_official 585:a1ed5b41f74f 968 /* FPROT0 Bit Fields */
mbed_official 585:a1ed5b41f74f 969 #define FTFA_FPROT0_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 970 #define FTFA_FPROT0_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 971 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
mbed_official 585:a1ed5b41f74f 972
mbed_official 585:a1ed5b41f74f 973 /**
mbed_official 585:a1ed5b41f74f 974 * @}
mbed_official 585:a1ed5b41f74f 975 */ /* end of group FTFA_Register_Masks */
mbed_official 585:a1ed5b41f74f 976
mbed_official 585:a1ed5b41f74f 977
mbed_official 585:a1ed5b41f74f 978 /* FTFA - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 979 /** Peripheral FTFA base address */
mbed_official 585:a1ed5b41f74f 980 #define FTFA_BASE (0x40020000u)
mbed_official 585:a1ed5b41f74f 981 /** Peripheral FTFA base pointer */
mbed_official 585:a1ed5b41f74f 982 #define FTFA ((FTFA_Type *)FTFA_BASE)
mbed_official 585:a1ed5b41f74f 983 /** Array initializer of FTFA peripheral base pointers */
mbed_official 585:a1ed5b41f74f 984 #define FTFA_BASES { FTFA }
mbed_official 585:a1ed5b41f74f 985
mbed_official 585:a1ed5b41f74f 986 /**
mbed_official 585:a1ed5b41f74f 987 * @}
mbed_official 585:a1ed5b41f74f 988 */ /* end of group FTFA_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 989
mbed_official 585:a1ed5b41f74f 990
mbed_official 585:a1ed5b41f74f 991 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 992 -- GPIO Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 993 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 994
mbed_official 585:a1ed5b41f74f 995 /**
mbed_official 585:a1ed5b41f74f 996 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 997 * @{
mbed_official 585:a1ed5b41f74f 998 */
mbed_official 585:a1ed5b41f74f 999
mbed_official 585:a1ed5b41f74f 1000 /** GPIO - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1001 typedef struct {
mbed_official 585:a1ed5b41f74f 1002 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1003 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 1004 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1005 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 1006 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 585:a1ed5b41f74f 1007 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 585:a1ed5b41f74f 1008 } GPIO_Type;
mbed_official 585:a1ed5b41f74f 1009
mbed_official 585:a1ed5b41f74f 1010 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1011 -- GPIO Register Masks
mbed_official 585:a1ed5b41f74f 1012 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1013
mbed_official 585:a1ed5b41f74f 1014 /**
mbed_official 585:a1ed5b41f74f 1015 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 585:a1ed5b41f74f 1016 * @{
mbed_official 585:a1ed5b41f74f 1017 */
mbed_official 585:a1ed5b41f74f 1018
mbed_official 585:a1ed5b41f74f 1019 /* PDOR Bit Fields */
mbed_official 585:a1ed5b41f74f 1020 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1021 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 585:a1ed5b41f74f 1022 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 585:a1ed5b41f74f 1023 /* PSOR Bit Fields */
mbed_official 585:a1ed5b41f74f 1024 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1025 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 585:a1ed5b41f74f 1026 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 585:a1ed5b41f74f 1027 /* PCOR Bit Fields */
mbed_official 585:a1ed5b41f74f 1028 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1029 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 585:a1ed5b41f74f 1030 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 585:a1ed5b41f74f 1031 /* PTOR Bit Fields */
mbed_official 585:a1ed5b41f74f 1032 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1033 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 585:a1ed5b41f74f 1034 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 585:a1ed5b41f74f 1035 /* PDIR Bit Fields */
mbed_official 585:a1ed5b41f74f 1036 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1037 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 585:a1ed5b41f74f 1038 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 585:a1ed5b41f74f 1039 /* PDDR Bit Fields */
mbed_official 585:a1ed5b41f74f 1040 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1041 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 585:a1ed5b41f74f 1042 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 585:a1ed5b41f74f 1043
mbed_official 585:a1ed5b41f74f 1044 /**
mbed_official 585:a1ed5b41f74f 1045 * @}
mbed_official 585:a1ed5b41f74f 1046 */ /* end of group GPIO_Register_Masks */
mbed_official 585:a1ed5b41f74f 1047
mbed_official 585:a1ed5b41f74f 1048
mbed_official 585:a1ed5b41f74f 1049 /* GPIO - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1050 /** Peripheral PTA base address */
mbed_official 585:a1ed5b41f74f 1051 #define PTA_BASE (0x400FF000u)
mbed_official 585:a1ed5b41f74f 1052 /** Peripheral PTA base pointer */
mbed_official 585:a1ed5b41f74f 1053 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 585:a1ed5b41f74f 1054 /** Peripheral PTB base address */
mbed_official 585:a1ed5b41f74f 1055 #define PTB_BASE (0x400FF040u)
mbed_official 585:a1ed5b41f74f 1056 /** Peripheral PTB base pointer */
mbed_official 585:a1ed5b41f74f 1057 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 585:a1ed5b41f74f 1058 /** Peripheral PTC base address */
mbed_official 585:a1ed5b41f74f 1059 #define PTC_BASE (0x400FF080u)
mbed_official 585:a1ed5b41f74f 1060 /** Peripheral PTC base pointer */
mbed_official 585:a1ed5b41f74f 1061 #define PTC ((GPIO_Type *)PTC_BASE)
mbed_official 585:a1ed5b41f74f 1062 /** Peripheral PTD base address */
mbed_official 585:a1ed5b41f74f 1063 #define PTD_BASE (0x400FF0C0u)
mbed_official 585:a1ed5b41f74f 1064 /** Peripheral PTD base pointer */
mbed_official 585:a1ed5b41f74f 1065 #define PTD ((GPIO_Type *)PTD_BASE)
mbed_official 585:a1ed5b41f74f 1066 /** Peripheral PTE base address */
mbed_official 585:a1ed5b41f74f 1067 #define PTE_BASE (0x400FF100u)
mbed_official 585:a1ed5b41f74f 1068 /** Peripheral PTE base pointer */
mbed_official 585:a1ed5b41f74f 1069 #define PTE ((GPIO_Type *)PTE_BASE)
mbed_official 585:a1ed5b41f74f 1070 /** Array initializer of GPIO peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1071 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
mbed_official 585:a1ed5b41f74f 1072
mbed_official 585:a1ed5b41f74f 1073 /**
mbed_official 585:a1ed5b41f74f 1074 * @}
mbed_official 585:a1ed5b41f74f 1075 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1076
mbed_official 585:a1ed5b41f74f 1077
mbed_official 585:a1ed5b41f74f 1078 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1079 -- I2C Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1080 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1081
mbed_official 585:a1ed5b41f74f 1082 /**
mbed_official 585:a1ed5b41f74f 1083 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1084 * @{
mbed_official 585:a1ed5b41f74f 1085 */
mbed_official 585:a1ed5b41f74f 1086
mbed_official 585:a1ed5b41f74f 1087 /** I2C - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1088 typedef struct {
mbed_official 585:a1ed5b41f74f 1089 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1090 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 1091 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 1092 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 1093 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 1094 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 1095 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 1096 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 585:a1ed5b41f74f 1097 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1098 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 585:a1ed5b41f74f 1099 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 585:a1ed5b41f74f 1100 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 585:a1ed5b41f74f 1101 } I2C_Type;
mbed_official 585:a1ed5b41f74f 1102
mbed_official 585:a1ed5b41f74f 1103 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1104 -- I2C Register Masks
mbed_official 585:a1ed5b41f74f 1105 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1106
mbed_official 585:a1ed5b41f74f 1107 /**
mbed_official 585:a1ed5b41f74f 1108 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 585:a1ed5b41f74f 1109 * @{
mbed_official 585:a1ed5b41f74f 1110 */
mbed_official 585:a1ed5b41f74f 1111
mbed_official 585:a1ed5b41f74f 1112 /* A1 Bit Fields */
mbed_official 585:a1ed5b41f74f 1113 #define I2C_A1_AD_MASK 0xFEu
mbed_official 585:a1ed5b41f74f 1114 #define I2C_A1_AD_SHIFT 1
mbed_official 585:a1ed5b41f74f 1115 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 585:a1ed5b41f74f 1116 /* F Bit Fields */
mbed_official 585:a1ed5b41f74f 1117 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 1118 #define I2C_F_ICR_SHIFT 0
mbed_official 585:a1ed5b41f74f 1119 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 585:a1ed5b41f74f 1120 #define I2C_F_MULT_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 1121 #define I2C_F_MULT_SHIFT 6
mbed_official 585:a1ed5b41f74f 1122 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 585:a1ed5b41f74f 1123 /* C1 Bit Fields */
mbed_official 585:a1ed5b41f74f 1124 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1125 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 1126 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1127 #define I2C_C1_WUEN_SHIFT 1
mbed_official 585:a1ed5b41f74f 1128 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1129 #define I2C_C1_RSTA_SHIFT 2
mbed_official 585:a1ed5b41f74f 1130 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1131 #define I2C_C1_TXAK_SHIFT 3
mbed_official 585:a1ed5b41f74f 1132 #define I2C_C1_TX_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1133 #define I2C_C1_TX_SHIFT 4
mbed_official 585:a1ed5b41f74f 1134 #define I2C_C1_MST_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1135 #define I2C_C1_MST_SHIFT 5
mbed_official 585:a1ed5b41f74f 1136 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1137 #define I2C_C1_IICIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 1138 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1139 #define I2C_C1_IICEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 1140 /* S Bit Fields */
mbed_official 585:a1ed5b41f74f 1141 #define I2C_S_RXAK_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1142 #define I2C_S_RXAK_SHIFT 0
mbed_official 585:a1ed5b41f74f 1143 #define I2C_S_IICIF_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1144 #define I2C_S_IICIF_SHIFT 1
mbed_official 585:a1ed5b41f74f 1145 #define I2C_S_SRW_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1146 #define I2C_S_SRW_SHIFT 2
mbed_official 585:a1ed5b41f74f 1147 #define I2C_S_RAM_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1148 #define I2C_S_RAM_SHIFT 3
mbed_official 585:a1ed5b41f74f 1149 #define I2C_S_ARBL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1150 #define I2C_S_ARBL_SHIFT 4
mbed_official 585:a1ed5b41f74f 1151 #define I2C_S_BUSY_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1152 #define I2C_S_BUSY_SHIFT 5
mbed_official 585:a1ed5b41f74f 1153 #define I2C_S_IAAS_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1154 #define I2C_S_IAAS_SHIFT 6
mbed_official 585:a1ed5b41f74f 1155 #define I2C_S_TCF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1156 #define I2C_S_TCF_SHIFT 7
mbed_official 585:a1ed5b41f74f 1157 /* D Bit Fields */
mbed_official 585:a1ed5b41f74f 1158 #define I2C_D_DATA_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1159 #define I2C_D_DATA_SHIFT 0
mbed_official 585:a1ed5b41f74f 1160 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 585:a1ed5b41f74f 1161 /* C2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1162 #define I2C_C2_AD_MASK 0x7u
mbed_official 585:a1ed5b41f74f 1163 #define I2C_C2_AD_SHIFT 0
mbed_official 585:a1ed5b41f74f 1164 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 585:a1ed5b41f74f 1165 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1166 #define I2C_C2_RMEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 1167 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1168 #define I2C_C2_SBRC_SHIFT 4
mbed_official 585:a1ed5b41f74f 1169 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1170 #define I2C_C2_HDRS_SHIFT 5
mbed_official 585:a1ed5b41f74f 1171 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1172 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 585:a1ed5b41f74f 1173 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1174 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 1175 /* FLT Bit Fields */
mbed_official 585:a1ed5b41f74f 1176 #define I2C_FLT_FLT_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 1177 #define I2C_FLT_FLT_SHIFT 0
mbed_official 585:a1ed5b41f74f 1178 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 585:a1ed5b41f74f 1179 #define I2C_FLT_STOPIE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1180 #define I2C_FLT_STOPIE_SHIFT 5
mbed_official 585:a1ed5b41f74f 1181 #define I2C_FLT_STOPF_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1182 #define I2C_FLT_STOPF_SHIFT 6
mbed_official 585:a1ed5b41f74f 1183 #define I2C_FLT_SHEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1184 #define I2C_FLT_SHEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 1185 /* RA Bit Fields */
mbed_official 585:a1ed5b41f74f 1186 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 585:a1ed5b41f74f 1187 #define I2C_RA_RAD_SHIFT 1
mbed_official 585:a1ed5b41f74f 1188 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 585:a1ed5b41f74f 1189 /* SMB Bit Fields */
mbed_official 585:a1ed5b41f74f 1190 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1191 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 585:a1ed5b41f74f 1192 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1193 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 585:a1ed5b41f74f 1194 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1195 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 585:a1ed5b41f74f 1196 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1197 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 585:a1ed5b41f74f 1198 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1199 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 585:a1ed5b41f74f 1200 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1201 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 1202 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1203 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 1204 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1205 #define I2C_SMB_FACK_SHIFT 7
mbed_official 585:a1ed5b41f74f 1206 /* A2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1207 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 585:a1ed5b41f74f 1208 #define I2C_A2_SAD_SHIFT 1
mbed_official 585:a1ed5b41f74f 1209 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 585:a1ed5b41f74f 1210 /* SLTH Bit Fields */
mbed_official 585:a1ed5b41f74f 1211 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1212 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 585:a1ed5b41f74f 1213 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 585:a1ed5b41f74f 1214 /* SLTL Bit Fields */
mbed_official 585:a1ed5b41f74f 1215 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1216 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 585:a1ed5b41f74f 1217 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 585:a1ed5b41f74f 1218
mbed_official 585:a1ed5b41f74f 1219 /**
mbed_official 585:a1ed5b41f74f 1220 * @}
mbed_official 585:a1ed5b41f74f 1221 */ /* end of group I2C_Register_Masks */
mbed_official 585:a1ed5b41f74f 1222
mbed_official 585:a1ed5b41f74f 1223
mbed_official 585:a1ed5b41f74f 1224 /* I2C - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1225 /** Peripheral I2C0 base address */
mbed_official 585:a1ed5b41f74f 1226 #define I2C0_BASE (0x40066000u)
mbed_official 585:a1ed5b41f74f 1227 /** Peripheral I2C0 base pointer */
mbed_official 585:a1ed5b41f74f 1228 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 585:a1ed5b41f74f 1229 /** Peripheral I2C1 base address */
mbed_official 585:a1ed5b41f74f 1230 #define I2C1_BASE (0x40067000u)
mbed_official 585:a1ed5b41f74f 1231 /** Peripheral I2C1 base pointer */
mbed_official 585:a1ed5b41f74f 1232 #define I2C1 ((I2C_Type *)I2C1_BASE)
mbed_official 585:a1ed5b41f74f 1233 /** Array initializer of I2C peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1234 #define I2C_BASES { I2C0, I2C1 }
mbed_official 585:a1ed5b41f74f 1235
mbed_official 585:a1ed5b41f74f 1236 /**
mbed_official 585:a1ed5b41f74f 1237 * @}
mbed_official 585:a1ed5b41f74f 1238 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1239
mbed_official 585:a1ed5b41f74f 1240
mbed_official 585:a1ed5b41f74f 1241 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1242 -- I2S Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1243 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1244
mbed_official 585:a1ed5b41f74f 1245 /**
mbed_official 585:a1ed5b41f74f 1246 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1247 * @{
mbed_official 585:a1ed5b41f74f 1248 */
mbed_official 585:a1ed5b41f74f 1249
mbed_official 585:a1ed5b41f74f 1250 /** I2S - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1251 typedef struct {
mbed_official 585:a1ed5b41f74f 1252 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1253 uint8_t RESERVED_0[4];
mbed_official 585:a1ed5b41f74f 1254 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1255 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 1256 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 585:a1ed5b41f74f 1257 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 585:a1ed5b41f74f 1258 uint8_t RESERVED_1[8];
mbed_official 585:a1ed5b41f74f 1259 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 1260 uint8_t RESERVED_2[60];
mbed_official 585:a1ed5b41f74f 1261 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 585:a1ed5b41f74f 1262 uint8_t RESERVED_3[28];
mbed_official 585:a1ed5b41f74f 1263 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 585:a1ed5b41f74f 1264 uint8_t RESERVED_4[4];
mbed_official 585:a1ed5b41f74f 1265 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 585:a1ed5b41f74f 1266 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 585:a1ed5b41f74f 1267 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 585:a1ed5b41f74f 1268 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 585:a1ed5b41f74f 1269 uint8_t RESERVED_5[8];
mbed_official 585:a1ed5b41f74f 1270 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 1271 uint8_t RESERVED_6[60];
mbed_official 585:a1ed5b41f74f 1272 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 585:a1ed5b41f74f 1273 uint8_t RESERVED_7[28];
mbed_official 585:a1ed5b41f74f 1274 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 585:a1ed5b41f74f 1275 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
mbed_official 585:a1ed5b41f74f 1276 } I2S_Type;
mbed_official 585:a1ed5b41f74f 1277
mbed_official 585:a1ed5b41f74f 1278 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1279 -- I2S Register Masks
mbed_official 585:a1ed5b41f74f 1280 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1281
mbed_official 585:a1ed5b41f74f 1282 /**
mbed_official 585:a1ed5b41f74f 1283 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 585:a1ed5b41f74f 1284 * @{
mbed_official 585:a1ed5b41f74f 1285 */
mbed_official 585:a1ed5b41f74f 1286
mbed_official 585:a1ed5b41f74f 1287 /* TCSR Bit Fields */
mbed_official 585:a1ed5b41f74f 1288 #define I2S_TCSR_FWDE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1289 #define I2S_TCSR_FWDE_SHIFT 1
mbed_official 585:a1ed5b41f74f 1290 #define I2S_TCSR_FWIE_MASK 0x200u
mbed_official 585:a1ed5b41f74f 1291 #define I2S_TCSR_FWIE_SHIFT 9
mbed_official 585:a1ed5b41f74f 1292 #define I2S_TCSR_FEIE_MASK 0x400u
mbed_official 585:a1ed5b41f74f 1293 #define I2S_TCSR_FEIE_SHIFT 10
mbed_official 585:a1ed5b41f74f 1294 #define I2S_TCSR_SEIE_MASK 0x800u
mbed_official 585:a1ed5b41f74f 1295 #define I2S_TCSR_SEIE_SHIFT 11
mbed_official 585:a1ed5b41f74f 1296 #define I2S_TCSR_WSIE_MASK 0x1000u
mbed_official 585:a1ed5b41f74f 1297 #define I2S_TCSR_WSIE_SHIFT 12
mbed_official 585:a1ed5b41f74f 1298 #define I2S_TCSR_FWF_MASK 0x20000u
mbed_official 585:a1ed5b41f74f 1299 #define I2S_TCSR_FWF_SHIFT 17
mbed_official 585:a1ed5b41f74f 1300 #define I2S_TCSR_FEF_MASK 0x40000u
mbed_official 585:a1ed5b41f74f 1301 #define I2S_TCSR_FEF_SHIFT 18
mbed_official 585:a1ed5b41f74f 1302 #define I2S_TCSR_SEF_MASK 0x80000u
mbed_official 585:a1ed5b41f74f 1303 #define I2S_TCSR_SEF_SHIFT 19
mbed_official 585:a1ed5b41f74f 1304 #define I2S_TCSR_WSF_MASK 0x100000u
mbed_official 585:a1ed5b41f74f 1305 #define I2S_TCSR_WSF_SHIFT 20
mbed_official 585:a1ed5b41f74f 1306 #define I2S_TCSR_SR_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 1307 #define I2S_TCSR_SR_SHIFT 24
mbed_official 585:a1ed5b41f74f 1308 #define I2S_TCSR_FR_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 1309 #define I2S_TCSR_FR_SHIFT 25
mbed_official 585:a1ed5b41f74f 1310 #define I2S_TCSR_BCE_MASK 0x10000000u
mbed_official 585:a1ed5b41f74f 1311 #define I2S_TCSR_BCE_SHIFT 28
mbed_official 585:a1ed5b41f74f 1312 #define I2S_TCSR_DBGE_MASK 0x20000000u
mbed_official 585:a1ed5b41f74f 1313 #define I2S_TCSR_DBGE_SHIFT 29
mbed_official 585:a1ed5b41f74f 1314 #define I2S_TCSR_STOPE_MASK 0x40000000u
mbed_official 585:a1ed5b41f74f 1315 #define I2S_TCSR_STOPE_SHIFT 30
mbed_official 585:a1ed5b41f74f 1316 #define I2S_TCSR_TE_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 1317 #define I2S_TCSR_TE_SHIFT 31
mbed_official 585:a1ed5b41f74f 1318 /* TCR2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1319 #define I2S_TCR2_DIV_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1320 #define I2S_TCR2_DIV_SHIFT 0
mbed_official 585:a1ed5b41f74f 1321 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mbed_official 585:a1ed5b41f74f 1322 #define I2S_TCR2_BCD_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 1323 #define I2S_TCR2_BCD_SHIFT 24
mbed_official 585:a1ed5b41f74f 1324 #define I2S_TCR2_BCP_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 1325 #define I2S_TCR2_BCP_SHIFT 25
mbed_official 585:a1ed5b41f74f 1326 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
mbed_official 585:a1ed5b41f74f 1327 #define I2S_TCR2_CLKMODE_SHIFT 26
mbed_official 585:a1ed5b41f74f 1328 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
mbed_official 585:a1ed5b41f74f 1329 /* TCR3 Bit Fields */
mbed_official 585:a1ed5b41f74f 1330 #define I2S_TCR3_WDFL_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1331 #define I2S_TCR3_WDFL_SHIFT 0
mbed_official 585:a1ed5b41f74f 1332 #define I2S_TCR3_TCE_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 1333 #define I2S_TCR3_TCE_SHIFT 16
mbed_official 585:a1ed5b41f74f 1334 /* TCR4 Bit Fields */
mbed_official 585:a1ed5b41f74f 1335 #define I2S_TCR4_FSD_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1336 #define I2S_TCR4_FSD_SHIFT 0
mbed_official 585:a1ed5b41f74f 1337 #define I2S_TCR4_FSP_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1338 #define I2S_TCR4_FSP_SHIFT 1
mbed_official 585:a1ed5b41f74f 1339 #define I2S_TCR4_FSE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1340 #define I2S_TCR4_FSE_SHIFT 3
mbed_official 585:a1ed5b41f74f 1341 #define I2S_TCR4_MF_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1342 #define I2S_TCR4_MF_SHIFT 4
mbed_official 585:a1ed5b41f74f 1343 #define I2S_TCR4_SYWD_MASK 0x1F00u
mbed_official 585:a1ed5b41f74f 1344 #define I2S_TCR4_SYWD_SHIFT 8
mbed_official 585:a1ed5b41f74f 1345 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mbed_official 585:a1ed5b41f74f 1346 #define I2S_TCR4_FRSZ_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 1347 #define I2S_TCR4_FRSZ_SHIFT 16
mbed_official 585:a1ed5b41f74f 1348 /* TCR5 Bit Fields */
mbed_official 585:a1ed5b41f74f 1349 #define I2S_TCR5_FBT_MASK 0x1F00u
mbed_official 585:a1ed5b41f74f 1350 #define I2S_TCR5_FBT_SHIFT 8
mbed_official 585:a1ed5b41f74f 1351 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mbed_official 585:a1ed5b41f74f 1352 #define I2S_TCR5_W0W_MASK 0x1F0000u
mbed_official 585:a1ed5b41f74f 1353 #define I2S_TCR5_W0W_SHIFT 16
mbed_official 585:a1ed5b41f74f 1354 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mbed_official 585:a1ed5b41f74f 1355 #define I2S_TCR5_WNW_MASK 0x1F000000u
mbed_official 585:a1ed5b41f74f 1356 #define I2S_TCR5_WNW_SHIFT 24
mbed_official 585:a1ed5b41f74f 1357 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mbed_official 585:a1ed5b41f74f 1358 /* TDR Bit Fields */
mbed_official 585:a1ed5b41f74f 1359 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1360 #define I2S_TDR_TDR_SHIFT 0
mbed_official 585:a1ed5b41f74f 1361 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mbed_official 585:a1ed5b41f74f 1362 /* TMR Bit Fields */
mbed_official 585:a1ed5b41f74f 1363 #define I2S_TMR_TWM_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1364 #define I2S_TMR_TWM_SHIFT 0
mbed_official 585:a1ed5b41f74f 1365 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mbed_official 585:a1ed5b41f74f 1366 /* RCSR Bit Fields */
mbed_official 585:a1ed5b41f74f 1367 #define I2S_RCSR_FWDE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1368 #define I2S_RCSR_FWDE_SHIFT 1
mbed_official 585:a1ed5b41f74f 1369 #define I2S_RCSR_FWIE_MASK 0x200u
mbed_official 585:a1ed5b41f74f 1370 #define I2S_RCSR_FWIE_SHIFT 9
mbed_official 585:a1ed5b41f74f 1371 #define I2S_RCSR_FEIE_MASK 0x400u
mbed_official 585:a1ed5b41f74f 1372 #define I2S_RCSR_FEIE_SHIFT 10
mbed_official 585:a1ed5b41f74f 1373 #define I2S_RCSR_SEIE_MASK 0x800u
mbed_official 585:a1ed5b41f74f 1374 #define I2S_RCSR_SEIE_SHIFT 11
mbed_official 585:a1ed5b41f74f 1375 #define I2S_RCSR_WSIE_MASK 0x1000u
mbed_official 585:a1ed5b41f74f 1376 #define I2S_RCSR_WSIE_SHIFT 12
mbed_official 585:a1ed5b41f74f 1377 #define I2S_RCSR_FWF_MASK 0x20000u
mbed_official 585:a1ed5b41f74f 1378 #define I2S_RCSR_FWF_SHIFT 17
mbed_official 585:a1ed5b41f74f 1379 #define I2S_RCSR_FEF_MASK 0x40000u
mbed_official 585:a1ed5b41f74f 1380 #define I2S_RCSR_FEF_SHIFT 18
mbed_official 585:a1ed5b41f74f 1381 #define I2S_RCSR_SEF_MASK 0x80000u
mbed_official 585:a1ed5b41f74f 1382 #define I2S_RCSR_SEF_SHIFT 19
mbed_official 585:a1ed5b41f74f 1383 #define I2S_RCSR_WSF_MASK 0x100000u
mbed_official 585:a1ed5b41f74f 1384 #define I2S_RCSR_WSF_SHIFT 20
mbed_official 585:a1ed5b41f74f 1385 #define I2S_RCSR_SR_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 1386 #define I2S_RCSR_SR_SHIFT 24
mbed_official 585:a1ed5b41f74f 1387 #define I2S_RCSR_FR_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 1388 #define I2S_RCSR_FR_SHIFT 25
mbed_official 585:a1ed5b41f74f 1389 #define I2S_RCSR_BCE_MASK 0x10000000u
mbed_official 585:a1ed5b41f74f 1390 #define I2S_RCSR_BCE_SHIFT 28
mbed_official 585:a1ed5b41f74f 1391 #define I2S_RCSR_DBGE_MASK 0x20000000u
mbed_official 585:a1ed5b41f74f 1392 #define I2S_RCSR_DBGE_SHIFT 29
mbed_official 585:a1ed5b41f74f 1393 #define I2S_RCSR_STOPE_MASK 0x40000000u
mbed_official 585:a1ed5b41f74f 1394 #define I2S_RCSR_STOPE_SHIFT 30
mbed_official 585:a1ed5b41f74f 1395 #define I2S_RCSR_RE_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 1396 #define I2S_RCSR_RE_SHIFT 31
mbed_official 585:a1ed5b41f74f 1397 /* RCR2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1398 #define I2S_RCR2_DIV_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1399 #define I2S_RCR2_DIV_SHIFT 0
mbed_official 585:a1ed5b41f74f 1400 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mbed_official 585:a1ed5b41f74f 1401 #define I2S_RCR2_BCD_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 1402 #define I2S_RCR2_BCD_SHIFT 24
mbed_official 585:a1ed5b41f74f 1403 #define I2S_RCR2_BCP_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 1404 #define I2S_RCR2_BCP_SHIFT 25
mbed_official 585:a1ed5b41f74f 1405 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
mbed_official 585:a1ed5b41f74f 1406 #define I2S_RCR2_CLKMODE_SHIFT 26
mbed_official 585:a1ed5b41f74f 1407 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
mbed_official 585:a1ed5b41f74f 1408 /* RCR3 Bit Fields */
mbed_official 585:a1ed5b41f74f 1409 #define I2S_RCR3_WDFL_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1410 #define I2S_RCR3_WDFL_SHIFT 0
mbed_official 585:a1ed5b41f74f 1411 #define I2S_RCR3_RCE_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 1412 #define I2S_RCR3_RCE_SHIFT 16
mbed_official 585:a1ed5b41f74f 1413 /* RCR4 Bit Fields */
mbed_official 585:a1ed5b41f74f 1414 #define I2S_RCR4_FSD_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1415 #define I2S_RCR4_FSD_SHIFT 0
mbed_official 585:a1ed5b41f74f 1416 #define I2S_RCR4_FSP_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1417 #define I2S_RCR4_FSP_SHIFT 1
mbed_official 585:a1ed5b41f74f 1418 #define I2S_RCR4_FSE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1419 #define I2S_RCR4_FSE_SHIFT 3
mbed_official 585:a1ed5b41f74f 1420 #define I2S_RCR4_MF_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1421 #define I2S_RCR4_MF_SHIFT 4
mbed_official 585:a1ed5b41f74f 1422 #define I2S_RCR4_SYWD_MASK 0x1F00u
mbed_official 585:a1ed5b41f74f 1423 #define I2S_RCR4_SYWD_SHIFT 8
mbed_official 585:a1ed5b41f74f 1424 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mbed_official 585:a1ed5b41f74f 1425 #define I2S_RCR4_FRSZ_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 1426 #define I2S_RCR4_FRSZ_SHIFT 16
mbed_official 585:a1ed5b41f74f 1427 /* RCR5 Bit Fields */
mbed_official 585:a1ed5b41f74f 1428 #define I2S_RCR5_FBT_MASK 0x1F00u
mbed_official 585:a1ed5b41f74f 1429 #define I2S_RCR5_FBT_SHIFT 8
mbed_official 585:a1ed5b41f74f 1430 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mbed_official 585:a1ed5b41f74f 1431 #define I2S_RCR5_W0W_MASK 0x1F0000u
mbed_official 585:a1ed5b41f74f 1432 #define I2S_RCR5_W0W_SHIFT 16
mbed_official 585:a1ed5b41f74f 1433 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mbed_official 585:a1ed5b41f74f 1434 #define I2S_RCR5_WNW_MASK 0x1F000000u
mbed_official 585:a1ed5b41f74f 1435 #define I2S_RCR5_WNW_SHIFT 24
mbed_official 585:a1ed5b41f74f 1436 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mbed_official 585:a1ed5b41f74f 1437 /* RDR Bit Fields */
mbed_official 585:a1ed5b41f74f 1438 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 1439 #define I2S_RDR_RDR_SHIFT 0
mbed_official 585:a1ed5b41f74f 1440 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mbed_official 585:a1ed5b41f74f 1441 /* RMR Bit Fields */
mbed_official 585:a1ed5b41f74f 1442 #define I2S_RMR_RWM_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1443 #define I2S_RMR_RWM_SHIFT 0
mbed_official 585:a1ed5b41f74f 1444 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mbed_official 585:a1ed5b41f74f 1445 /* MCR Bit Fields */
mbed_official 585:a1ed5b41f74f 1446 #define I2S_MCR_MICS_MASK 0x3000000u
mbed_official 585:a1ed5b41f74f 1447 #define I2S_MCR_MICS_SHIFT 24
mbed_official 585:a1ed5b41f74f 1448 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mbed_official 585:a1ed5b41f74f 1449 #define I2S_MCR_MOE_MASK 0x40000000u
mbed_official 585:a1ed5b41f74f 1450 #define I2S_MCR_MOE_SHIFT 30
mbed_official 585:a1ed5b41f74f 1451 #define I2S_MCR_DUF_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 1452 #define I2S_MCR_DUF_SHIFT 31
mbed_official 585:a1ed5b41f74f 1453 /* MDR Bit Fields */
mbed_official 585:a1ed5b41f74f 1454 #define I2S_MDR_DIVIDE_MASK 0xFFFu
mbed_official 585:a1ed5b41f74f 1455 #define I2S_MDR_DIVIDE_SHIFT 0
mbed_official 585:a1ed5b41f74f 1456 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
mbed_official 585:a1ed5b41f74f 1457 #define I2S_MDR_FRACT_MASK 0xFF000u
mbed_official 585:a1ed5b41f74f 1458 #define I2S_MDR_FRACT_SHIFT 12
mbed_official 585:a1ed5b41f74f 1459 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
mbed_official 585:a1ed5b41f74f 1460
mbed_official 585:a1ed5b41f74f 1461 /**
mbed_official 585:a1ed5b41f74f 1462 * @}
mbed_official 585:a1ed5b41f74f 1463 */ /* end of group I2S_Register_Masks */
mbed_official 585:a1ed5b41f74f 1464
mbed_official 585:a1ed5b41f74f 1465
mbed_official 585:a1ed5b41f74f 1466 /* I2S - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1467 /** Peripheral I2S0 base address */
mbed_official 585:a1ed5b41f74f 1468 #define I2S0_BASE (0x4002F000u)
mbed_official 585:a1ed5b41f74f 1469 /** Peripheral I2S0 base pointer */
mbed_official 585:a1ed5b41f74f 1470 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 585:a1ed5b41f74f 1471 /** Array initializer of I2S peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1472 #define I2S_BASES { I2S0 }
mbed_official 585:a1ed5b41f74f 1473
mbed_official 585:a1ed5b41f74f 1474 /**
mbed_official 585:a1ed5b41f74f 1475 * @}
mbed_official 585:a1ed5b41f74f 1476 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1477
mbed_official 585:a1ed5b41f74f 1478
mbed_official 585:a1ed5b41f74f 1479 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1480 -- LLWU Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1481 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1482
mbed_official 585:a1ed5b41f74f 1483 /**
mbed_official 585:a1ed5b41f74f 1484 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1485 * @{
mbed_official 585:a1ed5b41f74f 1486 */
mbed_official 585:a1ed5b41f74f 1487
mbed_official 585:a1ed5b41f74f 1488 /** LLWU - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1489 typedef struct {
mbed_official 585:a1ed5b41f74f 1490 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1491 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 1492 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 1493 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 1494 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 1495 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 1496 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 1497 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mbed_official 585:a1ed5b41f74f 1498 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1499 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mbed_official 585:a1ed5b41f74f 1500 } LLWU_Type;
mbed_official 585:a1ed5b41f74f 1501
mbed_official 585:a1ed5b41f74f 1502 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1503 -- LLWU Register Masks
mbed_official 585:a1ed5b41f74f 1504 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1505
mbed_official 585:a1ed5b41f74f 1506 /**
mbed_official 585:a1ed5b41f74f 1507 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 585:a1ed5b41f74f 1508 * @{
mbed_official 585:a1ed5b41f74f 1509 */
mbed_official 585:a1ed5b41f74f 1510
mbed_official 585:a1ed5b41f74f 1511 /* PE1 Bit Fields */
mbed_official 585:a1ed5b41f74f 1512 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1513 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1514 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 585:a1ed5b41f74f 1515 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 585:a1ed5b41f74f 1516 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 585:a1ed5b41f74f 1517 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 585:a1ed5b41f74f 1518 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 585:a1ed5b41f74f 1519 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 585:a1ed5b41f74f 1520 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 585:a1ed5b41f74f 1521 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 1522 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 585:a1ed5b41f74f 1523 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 585:a1ed5b41f74f 1524 /* PE2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1525 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1526 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 585:a1ed5b41f74f 1527 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 585:a1ed5b41f74f 1528 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 585:a1ed5b41f74f 1529 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 585:a1ed5b41f74f 1530 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 585:a1ed5b41f74f 1531 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 585:a1ed5b41f74f 1532 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 585:a1ed5b41f74f 1533 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 585:a1ed5b41f74f 1534 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 1535 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 585:a1ed5b41f74f 1536 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 585:a1ed5b41f74f 1537 /* PE3 Bit Fields */
mbed_official 585:a1ed5b41f74f 1538 #define LLWU_PE3_WUPE8_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1539 #define LLWU_PE3_WUPE8_SHIFT 0
mbed_official 585:a1ed5b41f74f 1540 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mbed_official 585:a1ed5b41f74f 1541 #define LLWU_PE3_WUPE9_MASK 0xCu
mbed_official 585:a1ed5b41f74f 1542 #define LLWU_PE3_WUPE9_SHIFT 2
mbed_official 585:a1ed5b41f74f 1543 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mbed_official 585:a1ed5b41f74f 1544 #define LLWU_PE3_WUPE10_MASK 0x30u
mbed_official 585:a1ed5b41f74f 1545 #define LLWU_PE3_WUPE10_SHIFT 4
mbed_official 585:a1ed5b41f74f 1546 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mbed_official 585:a1ed5b41f74f 1547 #define LLWU_PE3_WUPE11_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 1548 #define LLWU_PE3_WUPE11_SHIFT 6
mbed_official 585:a1ed5b41f74f 1549 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mbed_official 585:a1ed5b41f74f 1550 /* PE4 Bit Fields */
mbed_official 585:a1ed5b41f74f 1551 #define LLWU_PE4_WUPE12_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1552 #define LLWU_PE4_WUPE12_SHIFT 0
mbed_official 585:a1ed5b41f74f 1553 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mbed_official 585:a1ed5b41f74f 1554 #define LLWU_PE4_WUPE13_MASK 0xCu
mbed_official 585:a1ed5b41f74f 1555 #define LLWU_PE4_WUPE13_SHIFT 2
mbed_official 585:a1ed5b41f74f 1556 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mbed_official 585:a1ed5b41f74f 1557 #define LLWU_PE4_WUPE14_MASK 0x30u
mbed_official 585:a1ed5b41f74f 1558 #define LLWU_PE4_WUPE14_SHIFT 4
mbed_official 585:a1ed5b41f74f 1559 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mbed_official 585:a1ed5b41f74f 1560 #define LLWU_PE4_WUPE15_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 1561 #define LLWU_PE4_WUPE15_SHIFT 6
mbed_official 585:a1ed5b41f74f 1562 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mbed_official 585:a1ed5b41f74f 1563 /* ME Bit Fields */
mbed_official 585:a1ed5b41f74f 1564 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1565 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1566 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1567 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 585:a1ed5b41f74f 1568 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1569 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 585:a1ed5b41f74f 1570 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1571 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 585:a1ed5b41f74f 1572 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1573 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 585:a1ed5b41f74f 1574 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1575 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 585:a1ed5b41f74f 1576 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1577 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 585:a1ed5b41f74f 1578 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1579 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 585:a1ed5b41f74f 1580 /* F1 Bit Fields */
mbed_official 585:a1ed5b41f74f 1581 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1582 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1583 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1584 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 585:a1ed5b41f74f 1585 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1586 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 585:a1ed5b41f74f 1587 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1588 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 585:a1ed5b41f74f 1589 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1590 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 585:a1ed5b41f74f 1591 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1592 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 585:a1ed5b41f74f 1593 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1594 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 585:a1ed5b41f74f 1595 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1596 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 585:a1ed5b41f74f 1597 /* F2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1598 #define LLWU_F2_WUF8_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1599 #define LLWU_F2_WUF8_SHIFT 0
mbed_official 585:a1ed5b41f74f 1600 #define LLWU_F2_WUF9_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1601 #define LLWU_F2_WUF9_SHIFT 1
mbed_official 585:a1ed5b41f74f 1602 #define LLWU_F2_WUF10_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1603 #define LLWU_F2_WUF10_SHIFT 2
mbed_official 585:a1ed5b41f74f 1604 #define LLWU_F2_WUF11_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1605 #define LLWU_F2_WUF11_SHIFT 3
mbed_official 585:a1ed5b41f74f 1606 #define LLWU_F2_WUF12_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1607 #define LLWU_F2_WUF12_SHIFT 4
mbed_official 585:a1ed5b41f74f 1608 #define LLWU_F2_WUF13_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1609 #define LLWU_F2_WUF13_SHIFT 5
mbed_official 585:a1ed5b41f74f 1610 #define LLWU_F2_WUF14_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1611 #define LLWU_F2_WUF14_SHIFT 6
mbed_official 585:a1ed5b41f74f 1612 #define LLWU_F2_WUF15_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1613 #define LLWU_F2_WUF15_SHIFT 7
mbed_official 585:a1ed5b41f74f 1614 /* F3 Bit Fields */
mbed_official 585:a1ed5b41f74f 1615 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1616 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1617 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1618 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 585:a1ed5b41f74f 1619 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1620 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 585:a1ed5b41f74f 1621 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1622 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 585:a1ed5b41f74f 1623 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1624 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 585:a1ed5b41f74f 1625 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1626 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 585:a1ed5b41f74f 1627 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1628 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 585:a1ed5b41f74f 1629 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1630 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 585:a1ed5b41f74f 1631 /* FILT1 Bit Fields */
mbed_official 585:a1ed5b41f74f 1632 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 585:a1ed5b41f74f 1633 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 1634 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 585:a1ed5b41f74f 1635 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 585:a1ed5b41f74f 1636 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 585:a1ed5b41f74f 1637 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 585:a1ed5b41f74f 1638 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1639 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 585:a1ed5b41f74f 1640 /* FILT2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1641 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 585:a1ed5b41f74f 1642 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 1643 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 585:a1ed5b41f74f 1644 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 585:a1ed5b41f74f 1645 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 585:a1ed5b41f74f 1646 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 585:a1ed5b41f74f 1647 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1648 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 585:a1ed5b41f74f 1649
mbed_official 585:a1ed5b41f74f 1650 /**
mbed_official 585:a1ed5b41f74f 1651 * @}
mbed_official 585:a1ed5b41f74f 1652 */ /* end of group LLWU_Register_Masks */
mbed_official 585:a1ed5b41f74f 1653
mbed_official 585:a1ed5b41f74f 1654
mbed_official 585:a1ed5b41f74f 1655 /* LLWU - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1656 /** Peripheral LLWU base address */
mbed_official 585:a1ed5b41f74f 1657 #define LLWU_BASE (0x4007C000u)
mbed_official 585:a1ed5b41f74f 1658 /** Peripheral LLWU base pointer */
mbed_official 585:a1ed5b41f74f 1659 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 585:a1ed5b41f74f 1660 /** Array initializer of LLWU peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1661 #define LLWU_BASES { LLWU }
mbed_official 585:a1ed5b41f74f 1662
mbed_official 585:a1ed5b41f74f 1663 /**
mbed_official 585:a1ed5b41f74f 1664 * @}
mbed_official 585:a1ed5b41f74f 1665 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1666
mbed_official 585:a1ed5b41f74f 1667
mbed_official 585:a1ed5b41f74f 1668 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1669 -- LPTMR Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1670 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1671
mbed_official 585:a1ed5b41f74f 1672 /**
mbed_official 585:a1ed5b41f74f 1673 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1674 * @{
mbed_official 585:a1ed5b41f74f 1675 */
mbed_official 585:a1ed5b41f74f 1676
mbed_official 585:a1ed5b41f74f 1677 /** LPTMR - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1678 typedef struct {
mbed_official 585:a1ed5b41f74f 1679 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1680 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 1681 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1682 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 1683 } LPTMR_Type;
mbed_official 585:a1ed5b41f74f 1684
mbed_official 585:a1ed5b41f74f 1685 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1686 -- LPTMR Register Masks
mbed_official 585:a1ed5b41f74f 1687 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1688
mbed_official 585:a1ed5b41f74f 1689 /**
mbed_official 585:a1ed5b41f74f 1690 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 585:a1ed5b41f74f 1691 * @{
mbed_official 585:a1ed5b41f74f 1692 */
mbed_official 585:a1ed5b41f74f 1693
mbed_official 585:a1ed5b41f74f 1694 /* CSR Bit Fields */
mbed_official 585:a1ed5b41f74f 1695 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1696 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 1697 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1698 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 585:a1ed5b41f74f 1699 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1700 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 585:a1ed5b41f74f 1701 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1702 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 585:a1ed5b41f74f 1703 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 585:a1ed5b41f74f 1704 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 585:a1ed5b41f74f 1705 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 585:a1ed5b41f74f 1706 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1707 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 1708 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1709 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 585:a1ed5b41f74f 1710 /* PSR Bit Fields */
mbed_official 585:a1ed5b41f74f 1711 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 585:a1ed5b41f74f 1712 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 585:a1ed5b41f74f 1713 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 585:a1ed5b41f74f 1714 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1715 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 585:a1ed5b41f74f 1716 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 585:a1ed5b41f74f 1717 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 585:a1ed5b41f74f 1718 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 585:a1ed5b41f74f 1719 /* CMR Bit Fields */
mbed_official 585:a1ed5b41f74f 1720 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 1721 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 585:a1ed5b41f74f 1722 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 585:a1ed5b41f74f 1723 /* CNR Bit Fields */
mbed_official 585:a1ed5b41f74f 1724 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 1725 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 585:a1ed5b41f74f 1726 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 585:a1ed5b41f74f 1727
mbed_official 585:a1ed5b41f74f 1728 /**
mbed_official 585:a1ed5b41f74f 1729 * @}
mbed_official 585:a1ed5b41f74f 1730 */ /* end of group LPTMR_Register_Masks */
mbed_official 585:a1ed5b41f74f 1731
mbed_official 585:a1ed5b41f74f 1732
mbed_official 585:a1ed5b41f74f 1733 /* LPTMR - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1734 /** Peripheral LPTMR0 base address */
mbed_official 585:a1ed5b41f74f 1735 #define LPTMR0_BASE (0x40040000u)
mbed_official 585:a1ed5b41f74f 1736 /** Peripheral LPTMR0 base pointer */
mbed_official 585:a1ed5b41f74f 1737 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 585:a1ed5b41f74f 1738 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1739 #define LPTMR_BASES { LPTMR0 }
mbed_official 585:a1ed5b41f74f 1740
mbed_official 585:a1ed5b41f74f 1741 /**
mbed_official 585:a1ed5b41f74f 1742 * @}
mbed_official 585:a1ed5b41f74f 1743 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1744
mbed_official 585:a1ed5b41f74f 1745
mbed_official 585:a1ed5b41f74f 1746 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1747 -- MCG Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1748 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1749
mbed_official 585:a1ed5b41f74f 1750 /**
mbed_official 585:a1ed5b41f74f 1751 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1752 * @{
mbed_official 585:a1ed5b41f74f 1753 */
mbed_official 585:a1ed5b41f74f 1754
mbed_official 585:a1ed5b41f74f 1755 /** MCG - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1756 typedef struct {
mbed_official 585:a1ed5b41f74f 1757 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1758 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 1759 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 1760 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 1761 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 1762 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 1763 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 1764 uint8_t RESERVED_0[1];
mbed_official 585:a1ed5b41f74f 1765 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1766 uint8_t RESERVED_1[1];
mbed_official 585:a1ed5b41f74f 1767 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 585:a1ed5b41f74f 1768 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 585:a1ed5b41f74f 1769 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 1770 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mbed_official 585:a1ed5b41f74f 1771 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
mbed_official 585:a1ed5b41f74f 1772 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
mbed_official 585:a1ed5b41f74f 1773 } MCG_Type;
mbed_official 585:a1ed5b41f74f 1774
mbed_official 585:a1ed5b41f74f 1775 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1776 -- MCG Register Masks
mbed_official 585:a1ed5b41f74f 1777 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1778
mbed_official 585:a1ed5b41f74f 1779 /**
mbed_official 585:a1ed5b41f74f 1780 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 585:a1ed5b41f74f 1781 * @{
mbed_official 585:a1ed5b41f74f 1782 */
mbed_official 585:a1ed5b41f74f 1783
mbed_official 585:a1ed5b41f74f 1784 /* C1 Bit Fields */
mbed_official 585:a1ed5b41f74f 1785 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1786 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 1787 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1788 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 585:a1ed5b41f74f 1789 #define MCG_C1_IREFS_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1790 #define MCG_C1_IREFS_SHIFT 2
mbed_official 585:a1ed5b41f74f 1791 #define MCG_C1_FRDIV_MASK 0x38u
mbed_official 585:a1ed5b41f74f 1792 #define MCG_C1_FRDIV_SHIFT 3
mbed_official 585:a1ed5b41f74f 1793 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mbed_official 585:a1ed5b41f74f 1794 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 1795 #define MCG_C1_CLKS_SHIFT 6
mbed_official 585:a1ed5b41f74f 1796 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 585:a1ed5b41f74f 1797 /* C2 Bit Fields */
mbed_official 585:a1ed5b41f74f 1798 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1799 #define MCG_C2_IRCS_SHIFT 0
mbed_official 585:a1ed5b41f74f 1800 #define MCG_C2_LP_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1801 #define MCG_C2_LP_SHIFT 1
mbed_official 585:a1ed5b41f74f 1802 #define MCG_C2_EREFS0_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1803 #define MCG_C2_EREFS0_SHIFT 2
mbed_official 585:a1ed5b41f74f 1804 #define MCG_C2_HGO0_MASK 0x8u
mbed_official 585:a1ed5b41f74f 1805 #define MCG_C2_HGO0_SHIFT 3
mbed_official 585:a1ed5b41f74f 1806 #define MCG_C2_RANGE0_MASK 0x30u
mbed_official 585:a1ed5b41f74f 1807 #define MCG_C2_RANGE0_SHIFT 4
mbed_official 585:a1ed5b41f74f 1808 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
mbed_official 585:a1ed5b41f74f 1809 #define MCG_C2_FCFTRIM_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1810 #define MCG_C2_FCFTRIM_SHIFT 6
mbed_official 585:a1ed5b41f74f 1811 #define MCG_C2_LOCRE0_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1812 #define MCG_C2_LOCRE0_SHIFT 7
mbed_official 585:a1ed5b41f74f 1813 /* C3 Bit Fields */
mbed_official 585:a1ed5b41f74f 1814 #define MCG_C3_SCTRIM_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1815 #define MCG_C3_SCTRIM_SHIFT 0
mbed_official 585:a1ed5b41f74f 1816 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mbed_official 585:a1ed5b41f74f 1817 /* C4 Bit Fields */
mbed_official 585:a1ed5b41f74f 1818 #define MCG_C4_SCFTRIM_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1819 #define MCG_C4_SCFTRIM_SHIFT 0
mbed_official 585:a1ed5b41f74f 1820 #define MCG_C4_FCTRIM_MASK 0x1Eu
mbed_official 585:a1ed5b41f74f 1821 #define MCG_C4_FCTRIM_SHIFT 1
mbed_official 585:a1ed5b41f74f 1822 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mbed_official 585:a1ed5b41f74f 1823 #define MCG_C4_DRST_DRS_MASK 0x60u
mbed_official 585:a1ed5b41f74f 1824 #define MCG_C4_DRST_DRS_SHIFT 5
mbed_official 585:a1ed5b41f74f 1825 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mbed_official 585:a1ed5b41f74f 1826 #define MCG_C4_DMX32_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1827 #define MCG_C4_DMX32_SHIFT 7
mbed_official 585:a1ed5b41f74f 1828 /* C5 Bit Fields */
mbed_official 585:a1ed5b41f74f 1829 #define MCG_C5_PRDIV0_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 1830 #define MCG_C5_PRDIV0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1831 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
mbed_official 585:a1ed5b41f74f 1832 #define MCG_C5_PLLSTEN0_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1833 #define MCG_C5_PLLSTEN0_SHIFT 5
mbed_official 585:a1ed5b41f74f 1834 #define MCG_C5_PLLCLKEN0_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1835 #define MCG_C5_PLLCLKEN0_SHIFT 6
mbed_official 585:a1ed5b41f74f 1836 /* C6 Bit Fields */
mbed_official 585:a1ed5b41f74f 1837 #define MCG_C6_VDIV0_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 1838 #define MCG_C6_VDIV0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1839 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
mbed_official 585:a1ed5b41f74f 1840 #define MCG_C6_CME0_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1841 #define MCG_C6_CME0_SHIFT 5
mbed_official 585:a1ed5b41f74f 1842 #define MCG_C6_PLLS_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1843 #define MCG_C6_PLLS_SHIFT 6
mbed_official 585:a1ed5b41f74f 1844 #define MCG_C6_LOLIE0_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1845 #define MCG_C6_LOLIE0_SHIFT 7
mbed_official 585:a1ed5b41f74f 1846 /* S Bit Fields */
mbed_official 585:a1ed5b41f74f 1847 #define MCG_S_IRCST_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1848 #define MCG_S_IRCST_SHIFT 0
mbed_official 585:a1ed5b41f74f 1849 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1850 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 585:a1ed5b41f74f 1851 #define MCG_S_CLKST_MASK 0xCu
mbed_official 585:a1ed5b41f74f 1852 #define MCG_S_CLKST_SHIFT 2
mbed_official 585:a1ed5b41f74f 1853 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 585:a1ed5b41f74f 1854 #define MCG_S_IREFST_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1855 #define MCG_S_IREFST_SHIFT 4
mbed_official 585:a1ed5b41f74f 1856 #define MCG_S_PLLST_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1857 #define MCG_S_PLLST_SHIFT 5
mbed_official 585:a1ed5b41f74f 1858 #define MCG_S_LOCK0_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1859 #define MCG_S_LOCK0_SHIFT 6
mbed_official 585:a1ed5b41f74f 1860 #define MCG_S_LOLS_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1861 #define MCG_S_LOLS_SHIFT 7
mbed_official 585:a1ed5b41f74f 1862 /* SC Bit Fields */
mbed_official 585:a1ed5b41f74f 1863 #define MCG_SC_LOCS0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1864 #define MCG_SC_LOCS0_SHIFT 0
mbed_official 585:a1ed5b41f74f 1865 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 585:a1ed5b41f74f 1866 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 585:a1ed5b41f74f 1867 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 585:a1ed5b41f74f 1868 #define MCG_SC_FLTPRSRV_MASK 0x10u
mbed_official 585:a1ed5b41f74f 1869 #define MCG_SC_FLTPRSRV_SHIFT 4
mbed_official 585:a1ed5b41f74f 1870 #define MCG_SC_ATMF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 1871 #define MCG_SC_ATMF_SHIFT 5
mbed_official 585:a1ed5b41f74f 1872 #define MCG_SC_ATMS_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1873 #define MCG_SC_ATMS_SHIFT 6
mbed_official 585:a1ed5b41f74f 1874 #define MCG_SC_ATME_MASK 0x80u
mbed_official 585:a1ed5b41f74f 1875 #define MCG_SC_ATME_SHIFT 7
mbed_official 585:a1ed5b41f74f 1876 /* ATCVH Bit Fields */
mbed_official 585:a1ed5b41f74f 1877 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1878 #define MCG_ATCVH_ATCVH_SHIFT 0
mbed_official 585:a1ed5b41f74f 1879 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mbed_official 585:a1ed5b41f74f 1880 /* ATCVL Bit Fields */
mbed_official 585:a1ed5b41f74f 1881 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1882 #define MCG_ATCVL_ATCVL_SHIFT 0
mbed_official 585:a1ed5b41f74f 1883 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mbed_official 585:a1ed5b41f74f 1884 /* C8 Bit Fields */
mbed_official 585:a1ed5b41f74f 1885 #define MCG_C8_LOLRE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 1886 #define MCG_C8_LOLRE_SHIFT 6
mbed_official 585:a1ed5b41f74f 1887
mbed_official 585:a1ed5b41f74f 1888 /**
mbed_official 585:a1ed5b41f74f 1889 * @}
mbed_official 585:a1ed5b41f74f 1890 */ /* end of group MCG_Register_Masks */
mbed_official 585:a1ed5b41f74f 1891
mbed_official 585:a1ed5b41f74f 1892
mbed_official 585:a1ed5b41f74f 1893 /* MCG - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1894 /** Peripheral MCG base address */
mbed_official 585:a1ed5b41f74f 1895 #define MCG_BASE (0x40064000u)
mbed_official 585:a1ed5b41f74f 1896 /** Peripheral MCG base pointer */
mbed_official 585:a1ed5b41f74f 1897 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 585:a1ed5b41f74f 1898 /** Array initializer of MCG peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1899 #define MCG_BASES { MCG }
mbed_official 585:a1ed5b41f74f 1900
mbed_official 585:a1ed5b41f74f 1901 /**
mbed_official 585:a1ed5b41f74f 1902 * @}
mbed_official 585:a1ed5b41f74f 1903 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1904
mbed_official 585:a1ed5b41f74f 1905
mbed_official 585:a1ed5b41f74f 1906 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1907 -- MCM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1908 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1909
mbed_official 585:a1ed5b41f74f 1910 /**
mbed_official 585:a1ed5b41f74f 1911 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1912 * @{
mbed_official 585:a1ed5b41f74f 1913 */
mbed_official 585:a1ed5b41f74f 1914
mbed_official 585:a1ed5b41f74f 1915 /** MCM - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1916 typedef struct {
mbed_official 585:a1ed5b41f74f 1917 uint8_t RESERVED_0[8];
mbed_official 585:a1ed5b41f74f 1918 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1919 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 585:a1ed5b41f74f 1920 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 1921 uint8_t RESERVED_1[48];
mbed_official 585:a1ed5b41f74f 1922 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
mbed_official 585:a1ed5b41f74f 1923 } MCM_Type;
mbed_official 585:a1ed5b41f74f 1924
mbed_official 585:a1ed5b41f74f 1925 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1926 -- MCM Register Masks
mbed_official 585:a1ed5b41f74f 1927 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1928
mbed_official 585:a1ed5b41f74f 1929 /**
mbed_official 585:a1ed5b41f74f 1930 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 585:a1ed5b41f74f 1931 * @{
mbed_official 585:a1ed5b41f74f 1932 */
mbed_official 585:a1ed5b41f74f 1933
mbed_official 585:a1ed5b41f74f 1934 /* PLASC Bit Fields */
mbed_official 585:a1ed5b41f74f 1935 #define MCM_PLASC_ASC_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1936 #define MCM_PLASC_ASC_SHIFT 0
mbed_official 585:a1ed5b41f74f 1937 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mbed_official 585:a1ed5b41f74f 1938 /* PLAMC Bit Fields */
mbed_official 585:a1ed5b41f74f 1939 #define MCM_PLAMC_AMC_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 1940 #define MCM_PLAMC_AMC_SHIFT 0
mbed_official 585:a1ed5b41f74f 1941 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mbed_official 585:a1ed5b41f74f 1942 /* PLACR Bit Fields */
mbed_official 585:a1ed5b41f74f 1943 #define MCM_PLACR_ARB_MASK 0x200u
mbed_official 585:a1ed5b41f74f 1944 #define MCM_PLACR_ARB_SHIFT 9
mbed_official 585:a1ed5b41f74f 1945 #define MCM_PLACR_CFCC_MASK 0x400u
mbed_official 585:a1ed5b41f74f 1946 #define MCM_PLACR_CFCC_SHIFT 10
mbed_official 585:a1ed5b41f74f 1947 #define MCM_PLACR_DFCDA_MASK 0x800u
mbed_official 585:a1ed5b41f74f 1948 #define MCM_PLACR_DFCDA_SHIFT 11
mbed_official 585:a1ed5b41f74f 1949 #define MCM_PLACR_DFCIC_MASK 0x1000u
mbed_official 585:a1ed5b41f74f 1950 #define MCM_PLACR_DFCIC_SHIFT 12
mbed_official 585:a1ed5b41f74f 1951 #define MCM_PLACR_DFCC_MASK 0x2000u
mbed_official 585:a1ed5b41f74f 1952 #define MCM_PLACR_DFCC_SHIFT 13
mbed_official 585:a1ed5b41f74f 1953 #define MCM_PLACR_EFDS_MASK 0x4000u
mbed_official 585:a1ed5b41f74f 1954 #define MCM_PLACR_EFDS_SHIFT 14
mbed_official 585:a1ed5b41f74f 1955 #define MCM_PLACR_DFCS_MASK 0x8000u
mbed_official 585:a1ed5b41f74f 1956 #define MCM_PLACR_DFCS_SHIFT 15
mbed_official 585:a1ed5b41f74f 1957 #define MCM_PLACR_ESFC_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 1958 #define MCM_PLACR_ESFC_SHIFT 16
mbed_official 585:a1ed5b41f74f 1959 /* CPO Bit Fields */
mbed_official 585:a1ed5b41f74f 1960 #define MCM_CPO_CPOREQ_MASK 0x1u
mbed_official 585:a1ed5b41f74f 1961 #define MCM_CPO_CPOREQ_SHIFT 0
mbed_official 585:a1ed5b41f74f 1962 #define MCM_CPO_CPOACK_MASK 0x2u
mbed_official 585:a1ed5b41f74f 1963 #define MCM_CPO_CPOACK_SHIFT 1
mbed_official 585:a1ed5b41f74f 1964 #define MCM_CPO_CPOWOI_MASK 0x4u
mbed_official 585:a1ed5b41f74f 1965 #define MCM_CPO_CPOWOI_SHIFT 2
mbed_official 585:a1ed5b41f74f 1966
mbed_official 585:a1ed5b41f74f 1967 /**
mbed_official 585:a1ed5b41f74f 1968 * @}
mbed_official 585:a1ed5b41f74f 1969 */ /* end of group MCM_Register_Masks */
mbed_official 585:a1ed5b41f74f 1970
mbed_official 585:a1ed5b41f74f 1971
mbed_official 585:a1ed5b41f74f 1972 /* MCM - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 1973 /** Peripheral MCM base address */
mbed_official 585:a1ed5b41f74f 1974 #define MCM_BASE (0xF0003000u)
mbed_official 585:a1ed5b41f74f 1975 /** Peripheral MCM base pointer */
mbed_official 585:a1ed5b41f74f 1976 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 585:a1ed5b41f74f 1977 /** Array initializer of MCM peripheral base pointers */
mbed_official 585:a1ed5b41f74f 1978 #define MCM_BASES { MCM }
mbed_official 585:a1ed5b41f74f 1979
mbed_official 585:a1ed5b41f74f 1980 /**
mbed_official 585:a1ed5b41f74f 1981 * @}
mbed_official 585:a1ed5b41f74f 1982 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 1983
mbed_official 585:a1ed5b41f74f 1984
mbed_official 585:a1ed5b41f74f 1985 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 1986 -- MTB Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1987 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 1988
mbed_official 585:a1ed5b41f74f 1989 /**
mbed_official 585:a1ed5b41f74f 1990 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 1991 * @{
mbed_official 585:a1ed5b41f74f 1992 */
mbed_official 585:a1ed5b41f74f 1993
mbed_official 585:a1ed5b41f74f 1994 /** MTB - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 1995 typedef struct {
mbed_official 585:a1ed5b41f74f 1996 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 1997 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 1998 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 1999 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 2000 uint8_t RESERVED_0[3824];
mbed_official 585:a1ed5b41f74f 2001 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
mbed_official 585:a1ed5b41f74f 2002 uint8_t RESERVED_1[156];
mbed_official 585:a1ed5b41f74f 2003 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
mbed_official 585:a1ed5b41f74f 2004 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
mbed_official 585:a1ed5b41f74f 2005 uint8_t RESERVED_2[8];
mbed_official 585:a1ed5b41f74f 2006 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
mbed_official 585:a1ed5b41f74f 2007 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
mbed_official 585:a1ed5b41f74f 2008 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
mbed_official 585:a1ed5b41f74f 2009 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
mbed_official 585:a1ed5b41f74f 2010 uint8_t RESERVED_3[8];
mbed_official 585:a1ed5b41f74f 2011 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 585:a1ed5b41f74f 2012 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 585:a1ed5b41f74f 2013 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2014 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2015 } MTB_Type;
mbed_official 585:a1ed5b41f74f 2016
mbed_official 585:a1ed5b41f74f 2017 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2018 -- MTB Register Masks
mbed_official 585:a1ed5b41f74f 2019 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2020
mbed_official 585:a1ed5b41f74f 2021 /**
mbed_official 585:a1ed5b41f74f 2022 * @addtogroup MTB_Register_Masks MTB Register Masks
mbed_official 585:a1ed5b41f74f 2023 * @{
mbed_official 585:a1ed5b41f74f 2024 */
mbed_official 585:a1ed5b41f74f 2025
mbed_official 585:a1ed5b41f74f 2026 /* POSITION Bit Fields */
mbed_official 585:a1ed5b41f74f 2027 #define MTB_POSITION_WRAP_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2028 #define MTB_POSITION_WRAP_SHIFT 2
mbed_official 585:a1ed5b41f74f 2029 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
mbed_official 585:a1ed5b41f74f 2030 #define MTB_POSITION_POINTER_SHIFT 3
mbed_official 585:a1ed5b41f74f 2031 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
mbed_official 585:a1ed5b41f74f 2032 /* MASTER Bit Fields */
mbed_official 585:a1ed5b41f74f 2033 #define MTB_MASTER_MASK_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 2034 #define MTB_MASTER_MASK_SHIFT 0
mbed_official 585:a1ed5b41f74f 2035 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
mbed_official 585:a1ed5b41f74f 2036 #define MTB_MASTER_TSTARTEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2037 #define MTB_MASTER_TSTARTEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 2038 #define MTB_MASTER_TSTOPEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 2039 #define MTB_MASTER_TSTOPEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 2040 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
mbed_official 585:a1ed5b41f74f 2041 #define MTB_MASTER_SFRWPRIV_SHIFT 7
mbed_official 585:a1ed5b41f74f 2042 #define MTB_MASTER_RAMPRIV_MASK 0x100u
mbed_official 585:a1ed5b41f74f 2043 #define MTB_MASTER_RAMPRIV_SHIFT 8
mbed_official 585:a1ed5b41f74f 2044 #define MTB_MASTER_HALTREQ_MASK 0x200u
mbed_official 585:a1ed5b41f74f 2045 #define MTB_MASTER_HALTREQ_SHIFT 9
mbed_official 585:a1ed5b41f74f 2046 #define MTB_MASTER_EN_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 2047 #define MTB_MASTER_EN_SHIFT 31
mbed_official 585:a1ed5b41f74f 2048 /* FLOW Bit Fields */
mbed_official 585:a1ed5b41f74f 2049 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2050 #define MTB_FLOW_AUTOSTOP_SHIFT 0
mbed_official 585:a1ed5b41f74f 2051 #define MTB_FLOW_AUTOHALT_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2052 #define MTB_FLOW_AUTOHALT_SHIFT 1
mbed_official 585:a1ed5b41f74f 2053 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
mbed_official 585:a1ed5b41f74f 2054 #define MTB_FLOW_WATERMARK_SHIFT 3
mbed_official 585:a1ed5b41f74f 2055 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
mbed_official 585:a1ed5b41f74f 2056 /* BASE Bit Fields */
mbed_official 585:a1ed5b41f74f 2057 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2058 #define MTB_BASE_BASEADDR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2059 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
mbed_official 585:a1ed5b41f74f 2060 /* MODECTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 2061 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2062 #define MTB_MODECTRL_MODECTRL_SHIFT 0
mbed_official 585:a1ed5b41f74f 2063 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
mbed_official 585:a1ed5b41f74f 2064 /* TAGSET Bit Fields */
mbed_official 585:a1ed5b41f74f 2065 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2066 #define MTB_TAGSET_TAGSET_SHIFT 0
mbed_official 585:a1ed5b41f74f 2067 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
mbed_official 585:a1ed5b41f74f 2068 /* TAGCLEAR Bit Fields */
mbed_official 585:a1ed5b41f74f 2069 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2070 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2071 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
mbed_official 585:a1ed5b41f74f 2072 /* LOCKACCESS Bit Fields */
mbed_official 585:a1ed5b41f74f 2073 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2074 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
mbed_official 585:a1ed5b41f74f 2075 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
mbed_official 585:a1ed5b41f74f 2076 /* LOCKSTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 2077 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2078 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
mbed_official 585:a1ed5b41f74f 2079 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
mbed_official 585:a1ed5b41f74f 2080 /* AUTHSTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 2081 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2082 #define MTB_AUTHSTAT_BIT0_SHIFT 0
mbed_official 585:a1ed5b41f74f 2083 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2084 #define MTB_AUTHSTAT_BIT1_SHIFT 1
mbed_official 585:a1ed5b41f74f 2085 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2086 #define MTB_AUTHSTAT_BIT2_SHIFT 2
mbed_official 585:a1ed5b41f74f 2087 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2088 #define MTB_AUTHSTAT_BIT3_SHIFT 3
mbed_official 585:a1ed5b41f74f 2089 /* DEVICEARCH Bit Fields */
mbed_official 585:a1ed5b41f74f 2090 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2091 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
mbed_official 585:a1ed5b41f74f 2092 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
mbed_official 585:a1ed5b41f74f 2093 /* DEVICECFG Bit Fields */
mbed_official 585:a1ed5b41f74f 2094 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2095 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 585:a1ed5b41f74f 2096 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
mbed_official 585:a1ed5b41f74f 2097 /* DEVICETYPID Bit Fields */
mbed_official 585:a1ed5b41f74f 2098 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2099 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2100 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 585:a1ed5b41f74f 2101 /* PERIPHID Bit Fields */
mbed_official 585:a1ed5b41f74f 2102 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2103 #define MTB_PERIPHID_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2104 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2105 /* COMPID Bit Fields */
mbed_official 585:a1ed5b41f74f 2106 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2107 #define MTB_COMPID_COMPID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2108 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
mbed_official 585:a1ed5b41f74f 2109
mbed_official 585:a1ed5b41f74f 2110 /**
mbed_official 585:a1ed5b41f74f 2111 * @}
mbed_official 585:a1ed5b41f74f 2112 */ /* end of group MTB_Register_Masks */
mbed_official 585:a1ed5b41f74f 2113
mbed_official 585:a1ed5b41f74f 2114
mbed_official 585:a1ed5b41f74f 2115 /* MTB - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2116 /** Peripheral MTB base address */
mbed_official 585:a1ed5b41f74f 2117 #define MTB_BASE (0xF0000000u)
mbed_official 585:a1ed5b41f74f 2118 /** Peripheral MTB base pointer */
mbed_official 585:a1ed5b41f74f 2119 #define MTB ((MTB_Type *)MTB_BASE)
mbed_official 585:a1ed5b41f74f 2120 /** Array initializer of MTB peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2121 #define MTB_BASES { MTB }
mbed_official 585:a1ed5b41f74f 2122
mbed_official 585:a1ed5b41f74f 2123 /**
mbed_official 585:a1ed5b41f74f 2124 * @}
mbed_official 585:a1ed5b41f74f 2125 */ /* end of group MTB_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2126
mbed_official 585:a1ed5b41f74f 2127
mbed_official 585:a1ed5b41f74f 2128 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2129 -- MTBDWT Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2130 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2131
mbed_official 585:a1ed5b41f74f 2132 /**
mbed_official 585:a1ed5b41f74f 2133 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2134 * @{
mbed_official 585:a1ed5b41f74f 2135 */
mbed_official 585:a1ed5b41f74f 2136
mbed_official 585:a1ed5b41f74f 2137 /** MTBDWT - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2138 typedef struct {
mbed_official 585:a1ed5b41f74f 2139 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2140 uint8_t RESERVED_0[28];
mbed_official 585:a1ed5b41f74f 2141 struct { /* offset: 0x20, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2142 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2143 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2144 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2145 uint8_t RESERVED_0[4];
mbed_official 585:a1ed5b41f74f 2146 } COMPARATOR[2];
mbed_official 585:a1ed5b41f74f 2147 uint8_t RESERVED_1[448];
mbed_official 585:a1ed5b41f74f 2148 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
mbed_official 585:a1ed5b41f74f 2149 uint8_t RESERVED_2[3524];
mbed_official 585:a1ed5b41f74f 2150 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 585:a1ed5b41f74f 2151 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 585:a1ed5b41f74f 2152 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2153 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2154 } MTBDWT_Type;
mbed_official 585:a1ed5b41f74f 2155
mbed_official 585:a1ed5b41f74f 2156 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2157 -- MTBDWT Register Masks
mbed_official 585:a1ed5b41f74f 2158 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2159
mbed_official 585:a1ed5b41f74f 2160 /**
mbed_official 585:a1ed5b41f74f 2161 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
mbed_official 585:a1ed5b41f74f 2162 * @{
mbed_official 585:a1ed5b41f74f 2163 */
mbed_official 585:a1ed5b41f74f 2164
mbed_official 585:a1ed5b41f74f 2165 /* CTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 2166 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
mbed_official 585:a1ed5b41f74f 2167 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
mbed_official 585:a1ed5b41f74f 2168 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
mbed_official 585:a1ed5b41f74f 2169 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
mbed_official 585:a1ed5b41f74f 2170 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
mbed_official 585:a1ed5b41f74f 2171 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
mbed_official 585:a1ed5b41f74f 2172 /* COMP Bit Fields */
mbed_official 585:a1ed5b41f74f 2173 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2174 #define MTBDWT_COMP_COMP_SHIFT 0
mbed_official 585:a1ed5b41f74f 2175 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
mbed_official 585:a1ed5b41f74f 2176 /* MASK Bit Fields */
mbed_official 585:a1ed5b41f74f 2177 #define MTBDWT_MASK_MASK_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 2178 #define MTBDWT_MASK_MASK_SHIFT 0
mbed_official 585:a1ed5b41f74f 2179 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
mbed_official 585:a1ed5b41f74f 2180 /* FCT Bit Fields */
mbed_official 585:a1ed5b41f74f 2181 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
mbed_official 585:a1ed5b41f74f 2182 #define MTBDWT_FCT_FUNCTION_SHIFT 0
mbed_official 585:a1ed5b41f74f 2183 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
mbed_official 585:a1ed5b41f74f 2184 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
mbed_official 585:a1ed5b41f74f 2185 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
mbed_official 585:a1ed5b41f74f 2186 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
mbed_official 585:a1ed5b41f74f 2187 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
mbed_official 585:a1ed5b41f74f 2188 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
mbed_official 585:a1ed5b41f74f 2189 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
mbed_official 585:a1ed5b41f74f 2190 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
mbed_official 585:a1ed5b41f74f 2191 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
mbed_official 585:a1ed5b41f74f 2192 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 2193 #define MTBDWT_FCT_MATCHED_SHIFT 24
mbed_official 585:a1ed5b41f74f 2194 /* TBCTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 2195 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2196 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
mbed_official 585:a1ed5b41f74f 2197 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2198 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
mbed_official 585:a1ed5b41f74f 2199 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
mbed_official 585:a1ed5b41f74f 2200 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
mbed_official 585:a1ed5b41f74f 2201 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
mbed_official 585:a1ed5b41f74f 2202 /* DEVICECFG Bit Fields */
mbed_official 585:a1ed5b41f74f 2203 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2204 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 585:a1ed5b41f74f 2205 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
mbed_official 585:a1ed5b41f74f 2206 /* DEVICETYPID Bit Fields */
mbed_official 585:a1ed5b41f74f 2207 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2208 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2209 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 585:a1ed5b41f74f 2210 /* PERIPHID Bit Fields */
mbed_official 585:a1ed5b41f74f 2211 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2212 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2213 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2214 /* COMPID Bit Fields */
mbed_official 585:a1ed5b41f74f 2215 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2216 #define MTBDWT_COMPID_COMPID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2217 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
mbed_official 585:a1ed5b41f74f 2218
mbed_official 585:a1ed5b41f74f 2219 /**
mbed_official 585:a1ed5b41f74f 2220 * @}
mbed_official 585:a1ed5b41f74f 2221 */ /* end of group MTBDWT_Register_Masks */
mbed_official 585:a1ed5b41f74f 2222
mbed_official 585:a1ed5b41f74f 2223
mbed_official 585:a1ed5b41f74f 2224 /* MTBDWT - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2225 /** Peripheral MTBDWT base address */
mbed_official 585:a1ed5b41f74f 2226 #define MTBDWT_BASE (0xF0001000u)
mbed_official 585:a1ed5b41f74f 2227 /** Peripheral MTBDWT base pointer */
mbed_official 585:a1ed5b41f74f 2228 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
mbed_official 585:a1ed5b41f74f 2229 /** Array initializer of MTBDWT peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2230 #define MTBDWT_BASES { MTBDWT }
mbed_official 585:a1ed5b41f74f 2231
mbed_official 585:a1ed5b41f74f 2232 /**
mbed_official 585:a1ed5b41f74f 2233 * @}
mbed_official 585:a1ed5b41f74f 2234 */ /* end of group MTBDWT_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2235
mbed_official 585:a1ed5b41f74f 2236
mbed_official 585:a1ed5b41f74f 2237 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2238 -- NV Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2239 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2240
mbed_official 585:a1ed5b41f74f 2241 /**
mbed_official 585:a1ed5b41f74f 2242 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2243 * @{
mbed_official 585:a1ed5b41f74f 2244 */
mbed_official 585:a1ed5b41f74f 2245
mbed_official 585:a1ed5b41f74f 2246 /** NV - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2247 typedef struct {
mbed_official 585:a1ed5b41f74f 2248 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2249 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 585:a1ed5b41f74f 2250 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 585:a1ed5b41f74f 2251 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 585:a1ed5b41f74f 2252 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 585:a1ed5b41f74f 2253 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 585:a1ed5b41f74f 2254 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 585:a1ed5b41f74f 2255 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 585:a1ed5b41f74f 2256 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 2257 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 585:a1ed5b41f74f 2258 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 585:a1ed5b41f74f 2259 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 585:a1ed5b41f74f 2260 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 2261 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 585:a1ed5b41f74f 2262 } NV_Type;
mbed_official 585:a1ed5b41f74f 2263
mbed_official 585:a1ed5b41f74f 2264 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2265 -- NV Register Masks
mbed_official 585:a1ed5b41f74f 2266 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2267
mbed_official 585:a1ed5b41f74f 2268 /**
mbed_official 585:a1ed5b41f74f 2269 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 585:a1ed5b41f74f 2270 * @{
mbed_official 585:a1ed5b41f74f 2271 */
mbed_official 585:a1ed5b41f74f 2272
mbed_official 585:a1ed5b41f74f 2273 /* BACKKEY3 Bit Fields */
mbed_official 585:a1ed5b41f74f 2274 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2275 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2276 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2277 /* BACKKEY2 Bit Fields */
mbed_official 585:a1ed5b41f74f 2278 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2279 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2280 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2281 /* BACKKEY1 Bit Fields */
mbed_official 585:a1ed5b41f74f 2282 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2283 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2284 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2285 /* BACKKEY0 Bit Fields */
mbed_official 585:a1ed5b41f74f 2286 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2287 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2288 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2289 /* BACKKEY7 Bit Fields */
mbed_official 585:a1ed5b41f74f 2290 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2291 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2292 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2293 /* BACKKEY6 Bit Fields */
mbed_official 585:a1ed5b41f74f 2294 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2295 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2296 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2297 /* BACKKEY5 Bit Fields */
mbed_official 585:a1ed5b41f74f 2298 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2299 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2300 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2301 /* BACKKEY4 Bit Fields */
mbed_official 585:a1ed5b41f74f 2302 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2303 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2304 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 585:a1ed5b41f74f 2305 /* FPROT3 Bit Fields */
mbed_official 585:a1ed5b41f74f 2306 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2307 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 2308 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 585:a1ed5b41f74f 2309 /* FPROT2 Bit Fields */
mbed_official 585:a1ed5b41f74f 2310 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2311 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 2312 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 585:a1ed5b41f74f 2313 /* FPROT1 Bit Fields */
mbed_official 585:a1ed5b41f74f 2314 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2315 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 2316 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 585:a1ed5b41f74f 2317 /* FPROT0 Bit Fields */
mbed_official 585:a1ed5b41f74f 2318 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2319 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 585:a1ed5b41f74f 2320 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 585:a1ed5b41f74f 2321 /* FSEC Bit Fields */
mbed_official 585:a1ed5b41f74f 2322 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 585:a1ed5b41f74f 2323 #define NV_FSEC_SEC_SHIFT 0
mbed_official 585:a1ed5b41f74f 2324 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 585:a1ed5b41f74f 2325 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 585:a1ed5b41f74f 2326 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 585:a1ed5b41f74f 2327 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 585:a1ed5b41f74f 2328 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 585:a1ed5b41f74f 2329 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 585:a1ed5b41f74f 2330 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 585:a1ed5b41f74f 2331 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 2332 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 2333 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 585:a1ed5b41f74f 2334 /* FOPT Bit Fields */
mbed_official 585:a1ed5b41f74f 2335 #define NV_FOPT_LPBOOT0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2336 #define NV_FOPT_LPBOOT0_SHIFT 0
mbed_official 585:a1ed5b41f74f 2337 #define NV_FOPT_NMI_DIS_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2338 #define NV_FOPT_NMI_DIS_SHIFT 2
mbed_official 585:a1ed5b41f74f 2339 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2340 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
mbed_official 585:a1ed5b41f74f 2341 #define NV_FOPT_LPBOOT1_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2342 #define NV_FOPT_LPBOOT1_SHIFT 4
mbed_official 585:a1ed5b41f74f 2343 #define NV_FOPT_FAST_INIT_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2344 #define NV_FOPT_FAST_INIT_SHIFT 5
mbed_official 585:a1ed5b41f74f 2345
mbed_official 585:a1ed5b41f74f 2346 /**
mbed_official 585:a1ed5b41f74f 2347 * @}
mbed_official 585:a1ed5b41f74f 2348 */ /* end of group NV_Register_Masks */
mbed_official 585:a1ed5b41f74f 2349
mbed_official 585:a1ed5b41f74f 2350
mbed_official 585:a1ed5b41f74f 2351 /* NV - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2352 /** Peripheral FTFA_FlashConfig base address */
mbed_official 585:a1ed5b41f74f 2353 #define FTFA_FlashConfig_BASE (0x400u)
mbed_official 585:a1ed5b41f74f 2354 /** Peripheral FTFA_FlashConfig base pointer */
mbed_official 585:a1ed5b41f74f 2355 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
mbed_official 585:a1ed5b41f74f 2356 /** Array initializer of NV peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2357 #define NV_BASES { FTFA_FlashConfig }
mbed_official 585:a1ed5b41f74f 2358
mbed_official 585:a1ed5b41f74f 2359 /**
mbed_official 585:a1ed5b41f74f 2360 * @}
mbed_official 585:a1ed5b41f74f 2361 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2362
mbed_official 585:a1ed5b41f74f 2363
mbed_official 585:a1ed5b41f74f 2364 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2365 -- OSC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2366 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2367
mbed_official 585:a1ed5b41f74f 2368 /**
mbed_official 585:a1ed5b41f74f 2369 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2370 * @{
mbed_official 585:a1ed5b41f74f 2371 */
mbed_official 585:a1ed5b41f74f 2372
mbed_official 585:a1ed5b41f74f 2373 /** OSC - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2374 typedef struct {
mbed_official 585:a1ed5b41f74f 2375 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2376 } OSC_Type;
mbed_official 585:a1ed5b41f74f 2377
mbed_official 585:a1ed5b41f74f 2378 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2379 -- OSC Register Masks
mbed_official 585:a1ed5b41f74f 2380 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2381
mbed_official 585:a1ed5b41f74f 2382 /**
mbed_official 585:a1ed5b41f74f 2383 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 585:a1ed5b41f74f 2384 * @{
mbed_official 585:a1ed5b41f74f 2385 */
mbed_official 585:a1ed5b41f74f 2386
mbed_official 585:a1ed5b41f74f 2387 /* CR Bit Fields */
mbed_official 585:a1ed5b41f74f 2388 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2389 #define OSC_CR_SC16P_SHIFT 0
mbed_official 585:a1ed5b41f74f 2390 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2391 #define OSC_CR_SC8P_SHIFT 1
mbed_official 585:a1ed5b41f74f 2392 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2393 #define OSC_CR_SC4P_SHIFT 2
mbed_official 585:a1ed5b41f74f 2394 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2395 #define OSC_CR_SC2P_SHIFT 3
mbed_official 585:a1ed5b41f74f 2396 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2397 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 2398 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 2399 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 2400
mbed_official 585:a1ed5b41f74f 2401 /**
mbed_official 585:a1ed5b41f74f 2402 * @}
mbed_official 585:a1ed5b41f74f 2403 */ /* end of group OSC_Register_Masks */
mbed_official 585:a1ed5b41f74f 2404
mbed_official 585:a1ed5b41f74f 2405
mbed_official 585:a1ed5b41f74f 2406 /* OSC - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2407 /** Peripheral OSC0 base address */
mbed_official 585:a1ed5b41f74f 2408 #define OSC0_BASE (0x40065000u)
mbed_official 585:a1ed5b41f74f 2409 /** Peripheral OSC0 base pointer */
mbed_official 585:a1ed5b41f74f 2410 #define OSC0 ((OSC_Type *)OSC0_BASE)
mbed_official 585:a1ed5b41f74f 2411 /** Array initializer of OSC peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2412 #define OSC_BASES { OSC0 }
mbed_official 585:a1ed5b41f74f 2413
mbed_official 585:a1ed5b41f74f 2414 /**
mbed_official 585:a1ed5b41f74f 2415 * @}
mbed_official 585:a1ed5b41f74f 2416 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2417
mbed_official 585:a1ed5b41f74f 2418
mbed_official 585:a1ed5b41f74f 2419 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2420 -- PIT Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2421 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2422
mbed_official 585:a1ed5b41f74f 2423 /**
mbed_official 585:a1ed5b41f74f 2424 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2425 * @{
mbed_official 585:a1ed5b41f74f 2426 */
mbed_official 585:a1ed5b41f74f 2427
mbed_official 585:a1ed5b41f74f 2428 /** PIT - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2429 typedef struct {
mbed_official 585:a1ed5b41f74f 2430 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2431 uint8_t RESERVED_0[220];
mbed_official 585:a1ed5b41f74f 2432 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
mbed_official 585:a1ed5b41f74f 2433 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
mbed_official 585:a1ed5b41f74f 2434 uint8_t RESERVED_1[24];
mbed_official 585:a1ed5b41f74f 2435 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2436 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2437 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2438 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2439 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 585:a1ed5b41f74f 2440 } CHANNEL[2];
mbed_official 585:a1ed5b41f74f 2441 } PIT_Type;
mbed_official 585:a1ed5b41f74f 2442
mbed_official 585:a1ed5b41f74f 2443 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2444 -- PIT Register Masks
mbed_official 585:a1ed5b41f74f 2445 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2446
mbed_official 585:a1ed5b41f74f 2447 /**
mbed_official 585:a1ed5b41f74f 2448 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 585:a1ed5b41f74f 2449 * @{
mbed_official 585:a1ed5b41f74f 2450 */
mbed_official 585:a1ed5b41f74f 2451
mbed_official 585:a1ed5b41f74f 2452 /* MCR Bit Fields */
mbed_official 585:a1ed5b41f74f 2453 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2454 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 585:a1ed5b41f74f 2455 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2456 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 585:a1ed5b41f74f 2457 /* LTMR64H Bit Fields */
mbed_official 585:a1ed5b41f74f 2458 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2459 #define PIT_LTMR64H_LTH_SHIFT 0
mbed_official 585:a1ed5b41f74f 2460 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
mbed_official 585:a1ed5b41f74f 2461 /* LTMR64L Bit Fields */
mbed_official 585:a1ed5b41f74f 2462 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2463 #define PIT_LTMR64L_LTL_SHIFT 0
mbed_official 585:a1ed5b41f74f 2464 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
mbed_official 585:a1ed5b41f74f 2465 /* LDVAL Bit Fields */
mbed_official 585:a1ed5b41f74f 2466 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2467 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 585:a1ed5b41f74f 2468 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 585:a1ed5b41f74f 2469 /* CVAL Bit Fields */
mbed_official 585:a1ed5b41f74f 2470 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2471 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 585:a1ed5b41f74f 2472 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 585:a1ed5b41f74f 2473 /* TCTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 2474 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2475 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 2476 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2477 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 585:a1ed5b41f74f 2478 #define PIT_TCTRL_CHN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2479 #define PIT_TCTRL_CHN_SHIFT 2
mbed_official 585:a1ed5b41f74f 2480 /* TFLG Bit Fields */
mbed_official 585:a1ed5b41f74f 2481 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2482 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 585:a1ed5b41f74f 2483
mbed_official 585:a1ed5b41f74f 2484 /**
mbed_official 585:a1ed5b41f74f 2485 * @}
mbed_official 585:a1ed5b41f74f 2486 */ /* end of group PIT_Register_Masks */
mbed_official 585:a1ed5b41f74f 2487
mbed_official 585:a1ed5b41f74f 2488
mbed_official 585:a1ed5b41f74f 2489 /* PIT - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2490 /** Peripheral PIT base address */
mbed_official 585:a1ed5b41f74f 2491 #define PIT_BASE (0x40037000u)
mbed_official 585:a1ed5b41f74f 2492 /** Peripheral PIT base pointer */
mbed_official 585:a1ed5b41f74f 2493 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 585:a1ed5b41f74f 2494 /** Array initializer of PIT peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2495 #define PIT_BASES { PIT }
mbed_official 585:a1ed5b41f74f 2496
mbed_official 585:a1ed5b41f74f 2497 /**
mbed_official 585:a1ed5b41f74f 2498 * @}
mbed_official 585:a1ed5b41f74f 2499 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2500
mbed_official 585:a1ed5b41f74f 2501
mbed_official 585:a1ed5b41f74f 2502 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2503 -- PMC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2504 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2505
mbed_official 585:a1ed5b41f74f 2506 /**
mbed_official 585:a1ed5b41f74f 2507 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2508 * @{
mbed_official 585:a1ed5b41f74f 2509 */
mbed_official 585:a1ed5b41f74f 2510
mbed_official 585:a1ed5b41f74f 2511 /** PMC - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2512 typedef struct {
mbed_official 585:a1ed5b41f74f 2513 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2514 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 2515 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 2516 } PMC_Type;
mbed_official 585:a1ed5b41f74f 2517
mbed_official 585:a1ed5b41f74f 2518 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2519 -- PMC Register Masks
mbed_official 585:a1ed5b41f74f 2520 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2521
mbed_official 585:a1ed5b41f74f 2522 /**
mbed_official 585:a1ed5b41f74f 2523 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 585:a1ed5b41f74f 2524 * @{
mbed_official 585:a1ed5b41f74f 2525 */
mbed_official 585:a1ed5b41f74f 2526
mbed_official 585:a1ed5b41f74f 2527 /* LVDSC1 Bit Fields */
mbed_official 585:a1ed5b41f74f 2528 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 585:a1ed5b41f74f 2529 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 585:a1ed5b41f74f 2530 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 585:a1ed5b41f74f 2531 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2532 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 585:a1ed5b41f74f 2533 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2534 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 585:a1ed5b41f74f 2535 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 585:a1ed5b41f74f 2536 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 585:a1ed5b41f74f 2537 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 2538 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 585:a1ed5b41f74f 2539 /* LVDSC2 Bit Fields */
mbed_official 585:a1ed5b41f74f 2540 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 585:a1ed5b41f74f 2541 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 585:a1ed5b41f74f 2542 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 585:a1ed5b41f74f 2543 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2544 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 585:a1ed5b41f74f 2545 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 585:a1ed5b41f74f 2546 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 585:a1ed5b41f74f 2547 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 2548 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 585:a1ed5b41f74f 2549 /* REGSC Bit Fields */
mbed_official 585:a1ed5b41f74f 2550 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2551 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 585:a1ed5b41f74f 2552 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2553 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 585:a1ed5b41f74f 2554 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2555 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 585:a1ed5b41f74f 2556 #define PMC_REGSC_BGEN_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2557 #define PMC_REGSC_BGEN_SHIFT 4
mbed_official 585:a1ed5b41f74f 2558
mbed_official 585:a1ed5b41f74f 2559 /**
mbed_official 585:a1ed5b41f74f 2560 * @}
mbed_official 585:a1ed5b41f74f 2561 */ /* end of group PMC_Register_Masks */
mbed_official 585:a1ed5b41f74f 2562
mbed_official 585:a1ed5b41f74f 2563
mbed_official 585:a1ed5b41f74f 2564 /* PMC - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2565 /** Peripheral PMC base address */
mbed_official 585:a1ed5b41f74f 2566 #define PMC_BASE (0x4007D000u)
mbed_official 585:a1ed5b41f74f 2567 /** Peripheral PMC base pointer */
mbed_official 585:a1ed5b41f74f 2568 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 585:a1ed5b41f74f 2569 /** Array initializer of PMC peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2570 #define PMC_BASES { PMC }
mbed_official 585:a1ed5b41f74f 2571
mbed_official 585:a1ed5b41f74f 2572 /**
mbed_official 585:a1ed5b41f74f 2573 * @}
mbed_official 585:a1ed5b41f74f 2574 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2575
mbed_official 585:a1ed5b41f74f 2576
mbed_official 585:a1ed5b41f74f 2577 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2578 -- PORT Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2579 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2580
mbed_official 585:a1ed5b41f74f 2581 /**
mbed_official 585:a1ed5b41f74f 2582 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2583 * @{
mbed_official 585:a1ed5b41f74f 2584 */
mbed_official 585:a1ed5b41f74f 2585
mbed_official 585:a1ed5b41f74f 2586 /** PORT - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2587 typedef struct {
mbed_official 585:a1ed5b41f74f 2588 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2589 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 585:a1ed5b41f74f 2590 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 585:a1ed5b41f74f 2591 uint8_t RESERVED_0[24];
mbed_official 585:a1ed5b41f74f 2592 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 585:a1ed5b41f74f 2593 } PORT_Type;
mbed_official 585:a1ed5b41f74f 2594
mbed_official 585:a1ed5b41f74f 2595 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2596 -- PORT Register Masks
mbed_official 585:a1ed5b41f74f 2597 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2598
mbed_official 585:a1ed5b41f74f 2599 /**
mbed_official 585:a1ed5b41f74f 2600 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 585:a1ed5b41f74f 2601 * @{
mbed_official 585:a1ed5b41f74f 2602 */
mbed_official 585:a1ed5b41f74f 2603
mbed_official 585:a1ed5b41f74f 2604 /* PCR Bit Fields */
mbed_official 585:a1ed5b41f74f 2605 #define PORT_PCR_PS_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2606 #define PORT_PCR_PS_SHIFT 0
mbed_official 585:a1ed5b41f74f 2607 #define PORT_PCR_PE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2608 #define PORT_PCR_PE_SHIFT 1
mbed_official 585:a1ed5b41f74f 2609 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2610 #define PORT_PCR_SRE_SHIFT 2
mbed_official 585:a1ed5b41f74f 2611 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2612 #define PORT_PCR_PFE_SHIFT 4
mbed_official 585:a1ed5b41f74f 2613 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 2614 #define PORT_PCR_DSE_SHIFT 6
mbed_official 585:a1ed5b41f74f 2615 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 585:a1ed5b41f74f 2616 #define PORT_PCR_MUX_SHIFT 8
mbed_official 585:a1ed5b41f74f 2617 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 585:a1ed5b41f74f 2618 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 585:a1ed5b41f74f 2619 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 585:a1ed5b41f74f 2620 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 585:a1ed5b41f74f 2621 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 2622 #define PORT_PCR_ISF_SHIFT 24
mbed_official 585:a1ed5b41f74f 2623 /* GPCLR Bit Fields */
mbed_official 585:a1ed5b41f74f 2624 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 2625 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 585:a1ed5b41f74f 2626 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 585:a1ed5b41f74f 2627 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 585:a1ed5b41f74f 2628 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 585:a1ed5b41f74f 2629 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 585:a1ed5b41f74f 2630 /* GPCHR Bit Fields */
mbed_official 585:a1ed5b41f74f 2631 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 2632 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 585:a1ed5b41f74f 2633 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 585:a1ed5b41f74f 2634 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 585:a1ed5b41f74f 2635 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 585:a1ed5b41f74f 2636 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 585:a1ed5b41f74f 2637 /* ISFR Bit Fields */
mbed_official 585:a1ed5b41f74f 2638 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2639 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 585:a1ed5b41f74f 2640 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 585:a1ed5b41f74f 2641
mbed_official 585:a1ed5b41f74f 2642 /**
mbed_official 585:a1ed5b41f74f 2643 * @}
mbed_official 585:a1ed5b41f74f 2644 */ /* end of group PORT_Register_Masks */
mbed_official 585:a1ed5b41f74f 2645
mbed_official 585:a1ed5b41f74f 2646
mbed_official 585:a1ed5b41f74f 2647 /* PORT - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2648 /** Peripheral PORTA base address */
mbed_official 585:a1ed5b41f74f 2649 #define PORTA_BASE (0x40049000u)
mbed_official 585:a1ed5b41f74f 2650 /** Peripheral PORTA base pointer */
mbed_official 585:a1ed5b41f74f 2651 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 585:a1ed5b41f74f 2652 /** Peripheral PORTB base address */
mbed_official 585:a1ed5b41f74f 2653 #define PORTB_BASE (0x4004A000u)
mbed_official 585:a1ed5b41f74f 2654 /** Peripheral PORTB base pointer */
mbed_official 585:a1ed5b41f74f 2655 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 585:a1ed5b41f74f 2656 /** Peripheral PORTC base address */
mbed_official 585:a1ed5b41f74f 2657 #define PORTC_BASE (0x4004B000u)
mbed_official 585:a1ed5b41f74f 2658 /** Peripheral PORTC base pointer */
mbed_official 585:a1ed5b41f74f 2659 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 585:a1ed5b41f74f 2660 /** Peripheral PORTD base address */
mbed_official 585:a1ed5b41f74f 2661 #define PORTD_BASE (0x4004C000u)
mbed_official 585:a1ed5b41f74f 2662 /** Peripheral PORTD base pointer */
mbed_official 585:a1ed5b41f74f 2663 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 585:a1ed5b41f74f 2664 /** Peripheral PORTE base address */
mbed_official 585:a1ed5b41f74f 2665 #define PORTE_BASE (0x4004D000u)
mbed_official 585:a1ed5b41f74f 2666 /** Peripheral PORTE base pointer */
mbed_official 585:a1ed5b41f74f 2667 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 585:a1ed5b41f74f 2668 /** Array initializer of PORT peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2669 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
mbed_official 585:a1ed5b41f74f 2670
mbed_official 585:a1ed5b41f74f 2671 /**
mbed_official 585:a1ed5b41f74f 2672 * @}
mbed_official 585:a1ed5b41f74f 2673 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2674
mbed_official 585:a1ed5b41f74f 2675
mbed_official 585:a1ed5b41f74f 2676 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2677 -- RCM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2678 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2679
mbed_official 585:a1ed5b41f74f 2680 /**
mbed_official 585:a1ed5b41f74f 2681 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2682 * @{
mbed_official 585:a1ed5b41f74f 2683 */
mbed_official 585:a1ed5b41f74f 2684
mbed_official 585:a1ed5b41f74f 2685 /** RCM - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2686 typedef struct {
mbed_official 585:a1ed5b41f74f 2687 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2688 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 2689 uint8_t RESERVED_0[2];
mbed_official 585:a1ed5b41f74f 2690 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 2691 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 2692 } RCM_Type;
mbed_official 585:a1ed5b41f74f 2693
mbed_official 585:a1ed5b41f74f 2694 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2695 -- RCM Register Masks
mbed_official 585:a1ed5b41f74f 2696 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2697
mbed_official 585:a1ed5b41f74f 2698 /**
mbed_official 585:a1ed5b41f74f 2699 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 585:a1ed5b41f74f 2700 * @{
mbed_official 585:a1ed5b41f74f 2701 */
mbed_official 585:a1ed5b41f74f 2702
mbed_official 585:a1ed5b41f74f 2703 /* SRS0 Bit Fields */
mbed_official 585:a1ed5b41f74f 2704 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2705 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 585:a1ed5b41f74f 2706 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2707 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 585:a1ed5b41f74f 2708 #define RCM_SRS0_LOC_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2709 #define RCM_SRS0_LOC_SHIFT 2
mbed_official 585:a1ed5b41f74f 2710 #define RCM_SRS0_LOL_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2711 #define RCM_SRS0_LOL_SHIFT 3
mbed_official 585:a1ed5b41f74f 2712 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2713 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 585:a1ed5b41f74f 2714 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 2715 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 585:a1ed5b41f74f 2716 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 585:a1ed5b41f74f 2717 #define RCM_SRS0_POR_SHIFT 7
mbed_official 585:a1ed5b41f74f 2718 /* SRS1 Bit Fields */
mbed_official 585:a1ed5b41f74f 2719 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2720 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 585:a1ed5b41f74f 2721 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2722 #define RCM_SRS1_SW_SHIFT 2
mbed_official 585:a1ed5b41f74f 2723 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2724 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 585:a1ed5b41f74f 2725 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2726 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 585:a1ed5b41f74f 2727 /* RPFC Bit Fields */
mbed_official 585:a1ed5b41f74f 2728 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 585:a1ed5b41f74f 2729 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 585:a1ed5b41f74f 2730 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 585:a1ed5b41f74f 2731 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2732 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 585:a1ed5b41f74f 2733 /* RPFW Bit Fields */
mbed_official 585:a1ed5b41f74f 2734 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 2735 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 2736 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 585:a1ed5b41f74f 2737
mbed_official 585:a1ed5b41f74f 2738 /**
mbed_official 585:a1ed5b41f74f 2739 * @}
mbed_official 585:a1ed5b41f74f 2740 */ /* end of group RCM_Register_Masks */
mbed_official 585:a1ed5b41f74f 2741
mbed_official 585:a1ed5b41f74f 2742
mbed_official 585:a1ed5b41f74f 2743 /* RCM - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2744 /** Peripheral RCM base address */
mbed_official 585:a1ed5b41f74f 2745 #define RCM_BASE (0x4007F000u)
mbed_official 585:a1ed5b41f74f 2746 /** Peripheral RCM base pointer */
mbed_official 585:a1ed5b41f74f 2747 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 585:a1ed5b41f74f 2748 /** Array initializer of RCM peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2749 #define RCM_BASES { RCM }
mbed_official 585:a1ed5b41f74f 2750
mbed_official 585:a1ed5b41f74f 2751 /**
mbed_official 585:a1ed5b41f74f 2752 * @}
mbed_official 585:a1ed5b41f74f 2753 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2754
mbed_official 585:a1ed5b41f74f 2755
mbed_official 585:a1ed5b41f74f 2756 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2757 -- ROM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2758 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2759
mbed_official 585:a1ed5b41f74f 2760 /**
mbed_official 585:a1ed5b41f74f 2761 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2762 * @{
mbed_official 585:a1ed5b41f74f 2763 */
mbed_official 585:a1ed5b41f74f 2764
mbed_official 585:a1ed5b41f74f 2765 /** ROM - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2766 typedef struct {
mbed_official 585:a1ed5b41f74f 2767 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2768 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 2769 uint8_t RESERVED_0[4028];
mbed_official 585:a1ed5b41f74f 2770 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
mbed_official 585:a1ed5b41f74f 2771 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
mbed_official 585:a1ed5b41f74f 2772 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
mbed_official 585:a1ed5b41f74f 2773 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
mbed_official 585:a1ed5b41f74f 2774 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
mbed_official 585:a1ed5b41f74f 2775 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
mbed_official 585:a1ed5b41f74f 2776 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
mbed_official 585:a1ed5b41f74f 2777 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
mbed_official 585:a1ed5b41f74f 2778 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
mbed_official 585:a1ed5b41f74f 2779 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 2780 } ROM_Type;
mbed_official 585:a1ed5b41f74f 2781
mbed_official 585:a1ed5b41f74f 2782 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2783 -- ROM Register Masks
mbed_official 585:a1ed5b41f74f 2784 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2785
mbed_official 585:a1ed5b41f74f 2786 /**
mbed_official 585:a1ed5b41f74f 2787 * @addtogroup ROM_Register_Masks ROM Register Masks
mbed_official 585:a1ed5b41f74f 2788 * @{
mbed_official 585:a1ed5b41f74f 2789 */
mbed_official 585:a1ed5b41f74f 2790
mbed_official 585:a1ed5b41f74f 2791 /* ENTRY Bit Fields */
mbed_official 585:a1ed5b41f74f 2792 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2793 #define ROM_ENTRY_ENTRY_SHIFT 0
mbed_official 585:a1ed5b41f74f 2794 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
mbed_official 585:a1ed5b41f74f 2795 /* TABLEMARK Bit Fields */
mbed_official 585:a1ed5b41f74f 2796 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2797 #define ROM_TABLEMARK_MARK_SHIFT 0
mbed_official 585:a1ed5b41f74f 2798 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
mbed_official 585:a1ed5b41f74f 2799 /* SYSACCESS Bit Fields */
mbed_official 585:a1ed5b41f74f 2800 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2801 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
mbed_official 585:a1ed5b41f74f 2802 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
mbed_official 585:a1ed5b41f74f 2803 /* PERIPHID4 Bit Fields */
mbed_official 585:a1ed5b41f74f 2804 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2805 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2806 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2807 /* PERIPHID5 Bit Fields */
mbed_official 585:a1ed5b41f74f 2808 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2809 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2810 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2811 /* PERIPHID6 Bit Fields */
mbed_official 585:a1ed5b41f74f 2812 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2813 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2814 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2815 /* PERIPHID7 Bit Fields */
mbed_official 585:a1ed5b41f74f 2816 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2817 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2818 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2819 /* PERIPHID0 Bit Fields */
mbed_official 585:a1ed5b41f74f 2820 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2821 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2822 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2823 /* PERIPHID1 Bit Fields */
mbed_official 585:a1ed5b41f74f 2824 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2825 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2826 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2827 /* PERIPHID2 Bit Fields */
mbed_official 585:a1ed5b41f74f 2828 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2829 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2830 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2831 /* PERIPHID3 Bit Fields */
mbed_official 585:a1ed5b41f74f 2832 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2833 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2834 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
mbed_official 585:a1ed5b41f74f 2835 /* COMPID Bit Fields */
mbed_official 585:a1ed5b41f74f 2836 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2837 #define ROM_COMPID_COMPID_SHIFT 0
mbed_official 585:a1ed5b41f74f 2838 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
mbed_official 585:a1ed5b41f74f 2839
mbed_official 585:a1ed5b41f74f 2840 /**
mbed_official 585:a1ed5b41f74f 2841 * @}
mbed_official 585:a1ed5b41f74f 2842 */ /* end of group ROM_Register_Masks */
mbed_official 585:a1ed5b41f74f 2843
mbed_official 585:a1ed5b41f74f 2844
mbed_official 585:a1ed5b41f74f 2845 /* ROM - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2846 /** Peripheral ROM base address */
mbed_official 585:a1ed5b41f74f 2847 #define ROM_BASE (0xF0002000u)
mbed_official 585:a1ed5b41f74f 2848 /** Peripheral ROM base pointer */
mbed_official 585:a1ed5b41f74f 2849 #define ROM ((ROM_Type *)ROM_BASE)
mbed_official 585:a1ed5b41f74f 2850 /** Array initializer of ROM peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2851 #define ROM_BASES { ROM }
mbed_official 585:a1ed5b41f74f 2852
mbed_official 585:a1ed5b41f74f 2853 /**
mbed_official 585:a1ed5b41f74f 2854 * @}
mbed_official 585:a1ed5b41f74f 2855 */ /* end of group ROM_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2856
mbed_official 585:a1ed5b41f74f 2857
mbed_official 585:a1ed5b41f74f 2858 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2859 -- RTC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2860 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2861
mbed_official 585:a1ed5b41f74f 2862 /**
mbed_official 585:a1ed5b41f74f 2863 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2864 * @{
mbed_official 585:a1ed5b41f74f 2865 */
mbed_official 585:a1ed5b41f74f 2866
mbed_official 585:a1ed5b41f74f 2867 /** RTC - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2868 typedef struct {
mbed_official 585:a1ed5b41f74f 2869 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2870 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 2871 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 2872 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 2873 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 585:a1ed5b41f74f 2874 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 585:a1ed5b41f74f 2875 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 585:a1ed5b41f74f 2876 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 585:a1ed5b41f74f 2877 } RTC_Type;
mbed_official 585:a1ed5b41f74f 2878
mbed_official 585:a1ed5b41f74f 2879 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2880 -- RTC Register Masks
mbed_official 585:a1ed5b41f74f 2881 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2882
mbed_official 585:a1ed5b41f74f 2883 /**
mbed_official 585:a1ed5b41f74f 2884 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 585:a1ed5b41f74f 2885 * @{
mbed_official 585:a1ed5b41f74f 2886 */
mbed_official 585:a1ed5b41f74f 2887
mbed_official 585:a1ed5b41f74f 2888 /* TSR Bit Fields */
mbed_official 585:a1ed5b41f74f 2889 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2890 #define RTC_TSR_TSR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2891 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 585:a1ed5b41f74f 2892 /* TPR Bit Fields */
mbed_official 585:a1ed5b41f74f 2893 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 2894 #define RTC_TPR_TPR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2895 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 585:a1ed5b41f74f 2896 /* TAR Bit Fields */
mbed_official 585:a1ed5b41f74f 2897 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 2898 #define RTC_TAR_TAR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2899 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 585:a1ed5b41f74f 2900 /* TCR Bit Fields */
mbed_official 585:a1ed5b41f74f 2901 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 2902 #define RTC_TCR_TCR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2903 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 585:a1ed5b41f74f 2904 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 585:a1ed5b41f74f 2905 #define RTC_TCR_CIR_SHIFT 8
mbed_official 585:a1ed5b41f74f 2906 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 585:a1ed5b41f74f 2907 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 585:a1ed5b41f74f 2908 #define RTC_TCR_TCV_SHIFT 16
mbed_official 585:a1ed5b41f74f 2909 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 585:a1ed5b41f74f 2910 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 585:a1ed5b41f74f 2911 #define RTC_TCR_CIC_SHIFT 24
mbed_official 585:a1ed5b41f74f 2912 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 585:a1ed5b41f74f 2913 /* CR Bit Fields */
mbed_official 585:a1ed5b41f74f 2914 #define RTC_CR_SWR_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2915 #define RTC_CR_SWR_SHIFT 0
mbed_official 585:a1ed5b41f74f 2916 #define RTC_CR_WPE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2917 #define RTC_CR_WPE_SHIFT 1
mbed_official 585:a1ed5b41f74f 2918 #define RTC_CR_SUP_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2919 #define RTC_CR_SUP_SHIFT 2
mbed_official 585:a1ed5b41f74f 2920 #define RTC_CR_UM_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2921 #define RTC_CR_UM_SHIFT 3
mbed_official 585:a1ed5b41f74f 2922 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 585:a1ed5b41f74f 2923 #define RTC_CR_OSCE_SHIFT 8
mbed_official 585:a1ed5b41f74f 2924 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 585:a1ed5b41f74f 2925 #define RTC_CR_CLKO_SHIFT 9
mbed_official 585:a1ed5b41f74f 2926 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 585:a1ed5b41f74f 2927 #define RTC_CR_SC16P_SHIFT 10
mbed_official 585:a1ed5b41f74f 2928 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 585:a1ed5b41f74f 2929 #define RTC_CR_SC8P_SHIFT 11
mbed_official 585:a1ed5b41f74f 2930 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 585:a1ed5b41f74f 2931 #define RTC_CR_SC4P_SHIFT 12
mbed_official 585:a1ed5b41f74f 2932 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 585:a1ed5b41f74f 2933 #define RTC_CR_SC2P_SHIFT 13
mbed_official 585:a1ed5b41f74f 2934 /* SR Bit Fields */
mbed_official 585:a1ed5b41f74f 2935 #define RTC_SR_TIF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2936 #define RTC_SR_TIF_SHIFT 0
mbed_official 585:a1ed5b41f74f 2937 #define RTC_SR_TOF_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2938 #define RTC_SR_TOF_SHIFT 1
mbed_official 585:a1ed5b41f74f 2939 #define RTC_SR_TAF_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2940 #define RTC_SR_TAF_SHIFT 2
mbed_official 585:a1ed5b41f74f 2941 #define RTC_SR_TCE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2942 #define RTC_SR_TCE_SHIFT 4
mbed_official 585:a1ed5b41f74f 2943 /* LR Bit Fields */
mbed_official 585:a1ed5b41f74f 2944 #define RTC_LR_TCL_MASK 0x8u
mbed_official 585:a1ed5b41f74f 2945 #define RTC_LR_TCL_SHIFT 3
mbed_official 585:a1ed5b41f74f 2946 #define RTC_LR_CRL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2947 #define RTC_LR_CRL_SHIFT 4
mbed_official 585:a1ed5b41f74f 2948 #define RTC_LR_SRL_MASK 0x20u
mbed_official 585:a1ed5b41f74f 2949 #define RTC_LR_SRL_SHIFT 5
mbed_official 585:a1ed5b41f74f 2950 #define RTC_LR_LRL_MASK 0x40u
mbed_official 585:a1ed5b41f74f 2951 #define RTC_LR_LRL_SHIFT 6
mbed_official 585:a1ed5b41f74f 2952 /* IER Bit Fields */
mbed_official 585:a1ed5b41f74f 2953 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 2954 #define RTC_IER_TIIE_SHIFT 0
mbed_official 585:a1ed5b41f74f 2955 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 2956 #define RTC_IER_TOIE_SHIFT 1
mbed_official 585:a1ed5b41f74f 2957 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 2958 #define RTC_IER_TAIE_SHIFT 2
mbed_official 585:a1ed5b41f74f 2959 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 2960 #define RTC_IER_TSIE_SHIFT 4
mbed_official 585:a1ed5b41f74f 2961 #define RTC_IER_WPON_MASK 0x80u
mbed_official 585:a1ed5b41f74f 2962 #define RTC_IER_WPON_SHIFT 7
mbed_official 585:a1ed5b41f74f 2963
mbed_official 585:a1ed5b41f74f 2964 /**
mbed_official 585:a1ed5b41f74f 2965 * @}
mbed_official 585:a1ed5b41f74f 2966 */ /* end of group RTC_Register_Masks */
mbed_official 585:a1ed5b41f74f 2967
mbed_official 585:a1ed5b41f74f 2968
mbed_official 585:a1ed5b41f74f 2969 /* RTC - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 2970 /** Peripheral RTC base address */
mbed_official 585:a1ed5b41f74f 2971 #define RTC_BASE (0x4003D000u)
mbed_official 585:a1ed5b41f74f 2972 /** Peripheral RTC base pointer */
mbed_official 585:a1ed5b41f74f 2973 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 585:a1ed5b41f74f 2974 /** Array initializer of RTC peripheral base pointers */
mbed_official 585:a1ed5b41f74f 2975 #define RTC_BASES { RTC }
mbed_official 585:a1ed5b41f74f 2976
mbed_official 585:a1ed5b41f74f 2977 /**
mbed_official 585:a1ed5b41f74f 2978 * @}
mbed_official 585:a1ed5b41f74f 2979 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 2980
mbed_official 585:a1ed5b41f74f 2981
mbed_official 585:a1ed5b41f74f 2982 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 2983 -- SIM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2984 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 2985
mbed_official 585:a1ed5b41f74f 2986 /**
mbed_official 585:a1ed5b41f74f 2987 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 2988 * @{
mbed_official 585:a1ed5b41f74f 2989 */
mbed_official 585:a1ed5b41f74f 2990
mbed_official 585:a1ed5b41f74f 2991 /** SIM - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 2992 typedef struct {
mbed_official 585:a1ed5b41f74f 2993 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 2994 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 2995 uint8_t RESERVED_0[4092];
mbed_official 585:a1ed5b41f74f 2996 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 585:a1ed5b41f74f 2997 uint8_t RESERVED_1[4];
mbed_official 585:a1ed5b41f74f 2998 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 585:a1ed5b41f74f 2999 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 585:a1ed5b41f74f 3000 uint8_t RESERVED_2[4];
mbed_official 585:a1ed5b41f74f 3001 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 585:a1ed5b41f74f 3002 uint8_t RESERVED_3[8];
mbed_official 585:a1ed5b41f74f 3003 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 585:a1ed5b41f74f 3004 uint8_t RESERVED_4[12];
mbed_official 585:a1ed5b41f74f 3005 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 585:a1ed5b41f74f 3006 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 585:a1ed5b41f74f 3007 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 585:a1ed5b41f74f 3008 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 585:a1ed5b41f74f 3009 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 585:a1ed5b41f74f 3010 uint8_t RESERVED_5[4];
mbed_official 585:a1ed5b41f74f 3011 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 585:a1ed5b41f74f 3012 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 585:a1ed5b41f74f 3013 uint8_t RESERVED_6[4];
mbed_official 585:a1ed5b41f74f 3014 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 585:a1ed5b41f74f 3015 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 585:a1ed5b41f74f 3016 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 585:a1ed5b41f74f 3017 uint8_t RESERVED_7[156];
mbed_official 585:a1ed5b41f74f 3018 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
mbed_official 585:a1ed5b41f74f 3019 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
mbed_official 585:a1ed5b41f74f 3020 } SIM_Type;
mbed_official 585:a1ed5b41f74f 3021
mbed_official 585:a1ed5b41f74f 3022 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3023 -- SIM Register Masks
mbed_official 585:a1ed5b41f74f 3024 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3025
mbed_official 585:a1ed5b41f74f 3026 /**
mbed_official 585:a1ed5b41f74f 3027 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 585:a1ed5b41f74f 3028 * @{
mbed_official 585:a1ed5b41f74f 3029 */
mbed_official 585:a1ed5b41f74f 3030
mbed_official 585:a1ed5b41f74f 3031 /* SOPT1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3032 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 585:a1ed5b41f74f 3033 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 585:a1ed5b41f74f 3034 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 585:a1ed5b41f74f 3035 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mbed_official 585:a1ed5b41f74f 3036 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mbed_official 585:a1ed5b41f74f 3037 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mbed_official 585:a1ed5b41f74f 3038 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mbed_official 585:a1ed5b41f74f 3039 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 3040 #define SIM_SOPT1_USBREGEN_SHIFT 31
mbed_official 585:a1ed5b41f74f 3041 /* SOPT1CFG Bit Fields */
mbed_official 585:a1ed5b41f74f 3042 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 3043 #define SIM_SOPT1CFG_URWE_SHIFT 24
mbed_official 585:a1ed5b41f74f 3044 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 3045 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mbed_official 585:a1ed5b41f74f 3046 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mbed_official 585:a1ed5b41f74f 3047 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mbed_official 585:a1ed5b41f74f 3048 /* SOPT2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3049 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3050 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 585:a1ed5b41f74f 3051 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 585:a1ed5b41f74f 3052 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 585:a1ed5b41f74f 3053 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 585:a1ed5b41f74f 3054 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 3055 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
mbed_official 585:a1ed5b41f74f 3056 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mbed_official 585:a1ed5b41f74f 3057 #define SIM_SOPT2_USBSRC_SHIFT 18
mbed_official 585:a1ed5b41f74f 3058 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
mbed_official 585:a1ed5b41f74f 3059 #define SIM_SOPT2_TPMSRC_SHIFT 24
mbed_official 585:a1ed5b41f74f 3060 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
mbed_official 585:a1ed5b41f74f 3061 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
mbed_official 585:a1ed5b41f74f 3062 #define SIM_SOPT2_UART0SRC_SHIFT 26
mbed_official 585:a1ed5b41f74f 3063 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
mbed_official 585:a1ed5b41f74f 3064 /* SOPT4 Bit Fields */
mbed_official 585:a1ed5b41f74f 3065 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
mbed_official 585:a1ed5b41f74f 3066 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
mbed_official 585:a1ed5b41f74f 3067 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
mbed_official 585:a1ed5b41f74f 3068 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
mbed_official 585:a1ed5b41f74f 3069 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
mbed_official 585:a1ed5b41f74f 3070 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 3071 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
mbed_official 585:a1ed5b41f74f 3072 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 3073 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
mbed_official 585:a1ed5b41f74f 3074 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
mbed_official 585:a1ed5b41f74f 3075 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
mbed_official 585:a1ed5b41f74f 3076 /* SOPT5 Bit Fields */
mbed_official 585:a1ed5b41f74f 3077 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
mbed_official 585:a1ed5b41f74f 3078 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mbed_official 585:a1ed5b41f74f 3079 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
mbed_official 585:a1ed5b41f74f 3080 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3081 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mbed_official 585:a1ed5b41f74f 3082 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
mbed_official 585:a1ed5b41f74f 3083 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
mbed_official 585:a1ed5b41f74f 3084 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
mbed_official 585:a1ed5b41f74f 3085 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3086 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
mbed_official 585:a1ed5b41f74f 3087 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 3088 #define SIM_SOPT5_UART0ODE_SHIFT 16
mbed_official 585:a1ed5b41f74f 3089 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
mbed_official 585:a1ed5b41f74f 3090 #define SIM_SOPT5_UART1ODE_SHIFT 17
mbed_official 585:a1ed5b41f74f 3091 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
mbed_official 585:a1ed5b41f74f 3092 #define SIM_SOPT5_UART2ODE_SHIFT 18
mbed_official 585:a1ed5b41f74f 3093 /* SOPT7 Bit Fields */
mbed_official 585:a1ed5b41f74f 3094 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 585:a1ed5b41f74f 3095 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 585:a1ed5b41f74f 3096 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 585:a1ed5b41f74f 3097 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3098 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 585:a1ed5b41f74f 3099 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3100 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 3101 /* SDID Bit Fields */
mbed_official 585:a1ed5b41f74f 3102 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 585:a1ed5b41f74f 3103 #define SIM_SDID_PINID_SHIFT 0
mbed_official 585:a1ed5b41f74f 3104 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 585:a1ed5b41f74f 3105 #define SIM_SDID_DIEID_MASK 0xF80u
mbed_official 585:a1ed5b41f74f 3106 #define SIM_SDID_DIEID_SHIFT 7
mbed_official 585:a1ed5b41f74f 3107 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
mbed_official 585:a1ed5b41f74f 3108 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 585:a1ed5b41f74f 3109 #define SIM_SDID_REVID_SHIFT 12
mbed_official 585:a1ed5b41f74f 3110 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 585:a1ed5b41f74f 3111 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
mbed_official 585:a1ed5b41f74f 3112 #define SIM_SDID_SRAMSIZE_SHIFT 16
mbed_official 585:a1ed5b41f74f 3113 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
mbed_official 585:a1ed5b41f74f 3114 #define SIM_SDID_SERIESID_MASK 0xF00000u
mbed_official 585:a1ed5b41f74f 3115 #define SIM_SDID_SERIESID_SHIFT 20
mbed_official 585:a1ed5b41f74f 3116 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mbed_official 585:a1ed5b41f74f 3117 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mbed_official 585:a1ed5b41f74f 3118 #define SIM_SDID_SUBFAMID_SHIFT 24
mbed_official 585:a1ed5b41f74f 3119 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mbed_official 585:a1ed5b41f74f 3120 #define SIM_SDID_FAMID_MASK 0xF0000000u
mbed_official 585:a1ed5b41f74f 3121 #define SIM_SDID_FAMID_SHIFT 28
mbed_official 585:a1ed5b41f74f 3122 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 585:a1ed5b41f74f 3123 /* SCGC4 Bit Fields */
mbed_official 585:a1ed5b41f74f 3124 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3125 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 585:a1ed5b41f74f 3126 #define SIM_SCGC4_I2C1_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3127 #define SIM_SCGC4_I2C1_SHIFT 7
mbed_official 585:a1ed5b41f74f 3128 #define SIM_SCGC4_UART0_MASK 0x400u
mbed_official 585:a1ed5b41f74f 3129 #define SIM_SCGC4_UART0_SHIFT 10
mbed_official 585:a1ed5b41f74f 3130 #define SIM_SCGC4_UART1_MASK 0x800u
mbed_official 585:a1ed5b41f74f 3131 #define SIM_SCGC4_UART1_SHIFT 11
mbed_official 585:a1ed5b41f74f 3132 #define SIM_SCGC4_UART2_MASK 0x1000u
mbed_official 585:a1ed5b41f74f 3133 #define SIM_SCGC4_UART2_SHIFT 12
mbed_official 585:a1ed5b41f74f 3134 #define SIM_SCGC4_USBOTG_MASK 0x40000u
mbed_official 585:a1ed5b41f74f 3135 #define SIM_SCGC4_USBOTG_SHIFT 18
mbed_official 585:a1ed5b41f74f 3136 #define SIM_SCGC4_CMP_MASK 0x80000u
mbed_official 585:a1ed5b41f74f 3137 #define SIM_SCGC4_CMP_SHIFT 19
mbed_official 585:a1ed5b41f74f 3138 #define SIM_SCGC4_SPI0_MASK 0x400000u
mbed_official 585:a1ed5b41f74f 3139 #define SIM_SCGC4_SPI0_SHIFT 22
mbed_official 585:a1ed5b41f74f 3140 #define SIM_SCGC4_SPI1_MASK 0x800000u
mbed_official 585:a1ed5b41f74f 3141 #define SIM_SCGC4_SPI1_SHIFT 23
mbed_official 585:a1ed5b41f74f 3142 /* SCGC5 Bit Fields */
mbed_official 585:a1ed5b41f74f 3143 #define SIM_SCGC5_LPTMR_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3144 #define SIM_SCGC5_LPTMR_SHIFT 0
mbed_official 585:a1ed5b41f74f 3145 #define SIM_SCGC5_TSI_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3146 #define SIM_SCGC5_TSI_SHIFT 5
mbed_official 585:a1ed5b41f74f 3147 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 585:a1ed5b41f74f 3148 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 585:a1ed5b41f74f 3149 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 585:a1ed5b41f74f 3150 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 585:a1ed5b41f74f 3151 #define SIM_SCGC5_PORTC_MASK 0x800u
mbed_official 585:a1ed5b41f74f 3152 #define SIM_SCGC5_PORTC_SHIFT 11
mbed_official 585:a1ed5b41f74f 3153 #define SIM_SCGC5_PORTD_MASK 0x1000u
mbed_official 585:a1ed5b41f74f 3154 #define SIM_SCGC5_PORTD_SHIFT 12
mbed_official 585:a1ed5b41f74f 3155 #define SIM_SCGC5_PORTE_MASK 0x2000u
mbed_official 585:a1ed5b41f74f 3156 #define SIM_SCGC5_PORTE_SHIFT 13
mbed_official 585:a1ed5b41f74f 3157 /* SCGC6 Bit Fields */
mbed_official 585:a1ed5b41f74f 3158 #define SIM_SCGC6_FTF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3159 #define SIM_SCGC6_FTF_SHIFT 0
mbed_official 585:a1ed5b41f74f 3160 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3161 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 585:a1ed5b41f74f 3162 #define SIM_SCGC6_I2S_MASK 0x8000u
mbed_official 585:a1ed5b41f74f 3163 #define SIM_SCGC6_I2S_SHIFT 15
mbed_official 585:a1ed5b41f74f 3164 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 585:a1ed5b41f74f 3165 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 585:a1ed5b41f74f 3166 #define SIM_SCGC6_TPM0_MASK 0x1000000u
mbed_official 585:a1ed5b41f74f 3167 #define SIM_SCGC6_TPM0_SHIFT 24
mbed_official 585:a1ed5b41f74f 3168 #define SIM_SCGC6_TPM1_MASK 0x2000000u
mbed_official 585:a1ed5b41f74f 3169 #define SIM_SCGC6_TPM1_SHIFT 25
mbed_official 585:a1ed5b41f74f 3170 #define SIM_SCGC6_TPM2_MASK 0x4000000u
mbed_official 585:a1ed5b41f74f 3171 #define SIM_SCGC6_TPM2_SHIFT 26
mbed_official 585:a1ed5b41f74f 3172 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 585:a1ed5b41f74f 3173 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 585:a1ed5b41f74f 3174 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 585:a1ed5b41f74f 3175 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 585:a1ed5b41f74f 3176 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 3177 #define SIM_SCGC6_DAC0_SHIFT 31
mbed_official 585:a1ed5b41f74f 3178 /* SCGC7 Bit Fields */
mbed_official 585:a1ed5b41f74f 3179 #define SIM_SCGC7_DMA_MASK 0x100u
mbed_official 585:a1ed5b41f74f 3180 #define SIM_SCGC7_DMA_SHIFT 8
mbed_official 585:a1ed5b41f74f 3181 /* CLKDIV1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3182 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
mbed_official 585:a1ed5b41f74f 3183 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 585:a1ed5b41f74f 3184 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 585:a1ed5b41f74f 3185 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 585:a1ed5b41f74f 3186 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 585:a1ed5b41f74f 3187 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 585:a1ed5b41f74f 3188 /* FCFG1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3189 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3190 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 585:a1ed5b41f74f 3191 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3192 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3193 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 585:a1ed5b41f74f 3194 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 585:a1ed5b41f74f 3195 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 585:a1ed5b41f74f 3196 /* FCFG2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3197 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mbed_official 585:a1ed5b41f74f 3198 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mbed_official 585:a1ed5b41f74f 3199 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mbed_official 585:a1ed5b41f74f 3200 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 585:a1ed5b41f74f 3201 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 585:a1ed5b41f74f 3202 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 585:a1ed5b41f74f 3203 /* UIDMH Bit Fields */
mbed_official 585:a1ed5b41f74f 3204 #define SIM_UIDMH_UID_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 3205 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 585:a1ed5b41f74f 3206 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 585:a1ed5b41f74f 3207 /* UIDML Bit Fields */
mbed_official 585:a1ed5b41f74f 3208 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 3209 #define SIM_UIDML_UID_SHIFT 0
mbed_official 585:a1ed5b41f74f 3210 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 585:a1ed5b41f74f 3211 /* UIDL Bit Fields */
mbed_official 585:a1ed5b41f74f 3212 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 585:a1ed5b41f74f 3213 #define SIM_UIDL_UID_SHIFT 0
mbed_official 585:a1ed5b41f74f 3214 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 585:a1ed5b41f74f 3215 /* COPC Bit Fields */
mbed_official 585:a1ed5b41f74f 3216 #define SIM_COPC_COPW_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3217 #define SIM_COPC_COPW_SHIFT 0
mbed_official 585:a1ed5b41f74f 3218 #define SIM_COPC_COPCLKS_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3219 #define SIM_COPC_COPCLKS_SHIFT 1
mbed_official 585:a1ed5b41f74f 3220 #define SIM_COPC_COPT_MASK 0xCu
mbed_official 585:a1ed5b41f74f 3221 #define SIM_COPC_COPT_SHIFT 2
mbed_official 585:a1ed5b41f74f 3222 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
mbed_official 585:a1ed5b41f74f 3223 /* SRVCOP Bit Fields */
mbed_official 585:a1ed5b41f74f 3224 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3225 #define SIM_SRVCOP_SRVCOP_SHIFT 0
mbed_official 585:a1ed5b41f74f 3226 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
mbed_official 585:a1ed5b41f74f 3227
mbed_official 585:a1ed5b41f74f 3228 /**
mbed_official 585:a1ed5b41f74f 3229 * @}
mbed_official 585:a1ed5b41f74f 3230 */ /* end of group SIM_Register_Masks */
mbed_official 585:a1ed5b41f74f 3231
mbed_official 585:a1ed5b41f74f 3232
mbed_official 585:a1ed5b41f74f 3233 /* SIM - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 3234 /** Peripheral SIM base address */
mbed_official 585:a1ed5b41f74f 3235 #define SIM_BASE (0x40047000u)
mbed_official 585:a1ed5b41f74f 3236 /** Peripheral SIM base pointer */
mbed_official 585:a1ed5b41f74f 3237 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 585:a1ed5b41f74f 3238 /** Array initializer of SIM peripheral base pointers */
mbed_official 585:a1ed5b41f74f 3239 #define SIM_BASES { SIM }
mbed_official 585:a1ed5b41f74f 3240
mbed_official 585:a1ed5b41f74f 3241 /**
mbed_official 585:a1ed5b41f74f 3242 * @}
mbed_official 585:a1ed5b41f74f 3243 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 3244
mbed_official 585:a1ed5b41f74f 3245
mbed_official 585:a1ed5b41f74f 3246 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3247 -- SMC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3248 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3249
mbed_official 585:a1ed5b41f74f 3250 /**
mbed_official 585:a1ed5b41f74f 3251 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3252 * @{
mbed_official 585:a1ed5b41f74f 3253 */
mbed_official 585:a1ed5b41f74f 3254
mbed_official 585:a1ed5b41f74f 3255 /** SMC - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 3256 typedef struct {
mbed_official 585:a1ed5b41f74f 3257 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 3258 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 3259 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 3260 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 3261 } SMC_Type;
mbed_official 585:a1ed5b41f74f 3262
mbed_official 585:a1ed5b41f74f 3263 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3264 -- SMC Register Masks
mbed_official 585:a1ed5b41f74f 3265 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3266
mbed_official 585:a1ed5b41f74f 3267 /**
mbed_official 585:a1ed5b41f74f 3268 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 585:a1ed5b41f74f 3269 * @{
mbed_official 585:a1ed5b41f74f 3270 */
mbed_official 585:a1ed5b41f74f 3271
mbed_official 585:a1ed5b41f74f 3272 /* PMPROT Bit Fields */
mbed_official 585:a1ed5b41f74f 3273 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3274 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 585:a1ed5b41f74f 3275 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3276 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 585:a1ed5b41f74f 3277 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3278 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 585:a1ed5b41f74f 3279 /* PMCTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 3280 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 585:a1ed5b41f74f 3281 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 585:a1ed5b41f74f 3282 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 585:a1ed5b41f74f 3283 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3284 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 585:a1ed5b41f74f 3285 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 585:a1ed5b41f74f 3286 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 585:a1ed5b41f74f 3287 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 585:a1ed5b41f74f 3288 /* STOPCTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 3289 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
mbed_official 585:a1ed5b41f74f 3290 #define SMC_STOPCTRL_VLLSM_SHIFT 0
mbed_official 585:a1ed5b41f74f 3291 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
mbed_official 585:a1ed5b41f74f 3292 #define SMC_STOPCTRL_PORPO_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3293 #define SMC_STOPCTRL_PORPO_SHIFT 5
mbed_official 585:a1ed5b41f74f 3294 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 3295 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
mbed_official 585:a1ed5b41f74f 3296 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
mbed_official 585:a1ed5b41f74f 3297 /* PMSTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 3298 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
mbed_official 585:a1ed5b41f74f 3299 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 585:a1ed5b41f74f 3300 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 585:a1ed5b41f74f 3301
mbed_official 585:a1ed5b41f74f 3302 /**
mbed_official 585:a1ed5b41f74f 3303 * @}
mbed_official 585:a1ed5b41f74f 3304 */ /* end of group SMC_Register_Masks */
mbed_official 585:a1ed5b41f74f 3305
mbed_official 585:a1ed5b41f74f 3306
mbed_official 585:a1ed5b41f74f 3307 /* SMC - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 3308 /** Peripheral SMC base address */
mbed_official 585:a1ed5b41f74f 3309 #define SMC_BASE (0x4007E000u)
mbed_official 585:a1ed5b41f74f 3310 /** Peripheral SMC base pointer */
mbed_official 585:a1ed5b41f74f 3311 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 585:a1ed5b41f74f 3312 /** Array initializer of SMC peripheral base pointers */
mbed_official 585:a1ed5b41f74f 3313 #define SMC_BASES { SMC }
mbed_official 585:a1ed5b41f74f 3314
mbed_official 585:a1ed5b41f74f 3315 /**
mbed_official 585:a1ed5b41f74f 3316 * @}
mbed_official 585:a1ed5b41f74f 3317 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 3318
mbed_official 585:a1ed5b41f74f 3319
mbed_official 585:a1ed5b41f74f 3320 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3321 -- SPI Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3322 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3323
mbed_official 585:a1ed5b41f74f 3324 /**
mbed_official 585:a1ed5b41f74f 3325 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3326 * @{
mbed_official 585:a1ed5b41f74f 3327 */
mbed_official 585:a1ed5b41f74f 3328
mbed_official 585:a1ed5b41f74f 3329 /** SPI - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 3330 typedef struct {
mbed_official 585:a1ed5b41f74f 3331 __I uint8_t S; /**< SPI status register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 3332 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 3333 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 3334 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 3335 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 3336 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 3337 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 3338 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
mbed_official 585:a1ed5b41f74f 3339 uint8_t RESERVED_0[2];
mbed_official 585:a1ed5b41f74f 3340 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
mbed_official 585:a1ed5b41f74f 3341 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
mbed_official 585:a1ed5b41f74f 3342 } SPI_Type;
mbed_official 585:a1ed5b41f74f 3343
mbed_official 585:a1ed5b41f74f 3344 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3345 -- SPI Register Masks
mbed_official 585:a1ed5b41f74f 3346 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3347
mbed_official 585:a1ed5b41f74f 3348 /**
mbed_official 585:a1ed5b41f74f 3349 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 585:a1ed5b41f74f 3350 * @{
mbed_official 585:a1ed5b41f74f 3351 */
mbed_official 585:a1ed5b41f74f 3352
mbed_official 585:a1ed5b41f74f 3353 /* S Bit Fields */
mbed_official 585:a1ed5b41f74f 3354 #define SPI_S_RFIFOEF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3355 #define SPI_S_RFIFOEF_SHIFT 0
mbed_official 585:a1ed5b41f74f 3356 #define SPI_S_TXFULLF_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3357 #define SPI_S_TXFULLF_SHIFT 1
mbed_official 585:a1ed5b41f74f 3358 #define SPI_S_TNEAREF_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3359 #define SPI_S_TNEAREF_SHIFT 2
mbed_official 585:a1ed5b41f74f 3360 #define SPI_S_RNFULLF_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3361 #define SPI_S_RNFULLF_SHIFT 3
mbed_official 585:a1ed5b41f74f 3362 #define SPI_S_MODF_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3363 #define SPI_S_MODF_SHIFT 4
mbed_official 585:a1ed5b41f74f 3364 #define SPI_S_SPTEF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3365 #define SPI_S_SPTEF_SHIFT 5
mbed_official 585:a1ed5b41f74f 3366 #define SPI_S_SPMF_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3367 #define SPI_S_SPMF_SHIFT 6
mbed_official 585:a1ed5b41f74f 3368 #define SPI_S_SPRF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3369 #define SPI_S_SPRF_SHIFT 7
mbed_official 585:a1ed5b41f74f 3370 /* BR Bit Fields */
mbed_official 585:a1ed5b41f74f 3371 #define SPI_BR_SPR_MASK 0xFu
mbed_official 585:a1ed5b41f74f 3372 #define SPI_BR_SPR_SHIFT 0
mbed_official 585:a1ed5b41f74f 3373 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
mbed_official 585:a1ed5b41f74f 3374 #define SPI_BR_SPPR_MASK 0x70u
mbed_official 585:a1ed5b41f74f 3375 #define SPI_BR_SPPR_SHIFT 4
mbed_official 585:a1ed5b41f74f 3376 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
mbed_official 585:a1ed5b41f74f 3377 /* C2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3378 #define SPI_C2_SPC0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3379 #define SPI_C2_SPC0_SHIFT 0
mbed_official 585:a1ed5b41f74f 3380 #define SPI_C2_SPISWAI_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3381 #define SPI_C2_SPISWAI_SHIFT 1
mbed_official 585:a1ed5b41f74f 3382 #define SPI_C2_RXDMAE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3383 #define SPI_C2_RXDMAE_SHIFT 2
mbed_official 585:a1ed5b41f74f 3384 #define SPI_C2_BIDIROE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3385 #define SPI_C2_BIDIROE_SHIFT 3
mbed_official 585:a1ed5b41f74f 3386 #define SPI_C2_MODFEN_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3387 #define SPI_C2_MODFEN_SHIFT 4
mbed_official 585:a1ed5b41f74f 3388 #define SPI_C2_TXDMAE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3389 #define SPI_C2_TXDMAE_SHIFT 5
mbed_official 585:a1ed5b41f74f 3390 #define SPI_C2_SPIMODE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3391 #define SPI_C2_SPIMODE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3392 #define SPI_C2_SPMIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3393 #define SPI_C2_SPMIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3394 /* C1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3395 #define SPI_C1_LSBFE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3396 #define SPI_C1_LSBFE_SHIFT 0
mbed_official 585:a1ed5b41f74f 3397 #define SPI_C1_SSOE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3398 #define SPI_C1_SSOE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3399 #define SPI_C1_CPHA_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3400 #define SPI_C1_CPHA_SHIFT 2
mbed_official 585:a1ed5b41f74f 3401 #define SPI_C1_CPOL_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3402 #define SPI_C1_CPOL_SHIFT 3
mbed_official 585:a1ed5b41f74f 3403 #define SPI_C1_MSTR_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3404 #define SPI_C1_MSTR_SHIFT 4
mbed_official 585:a1ed5b41f74f 3405 #define SPI_C1_SPTIE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3406 #define SPI_C1_SPTIE_SHIFT 5
mbed_official 585:a1ed5b41f74f 3407 #define SPI_C1_SPE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3408 #define SPI_C1_SPE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3409 #define SPI_C1_SPIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3410 #define SPI_C1_SPIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3411 /* ML Bit Fields */
mbed_official 585:a1ed5b41f74f 3412 #define SPI_ML_Bits_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3413 #define SPI_ML_Bits_SHIFT 0
mbed_official 585:a1ed5b41f74f 3414 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
mbed_official 585:a1ed5b41f74f 3415 /* MH Bit Fields */
mbed_official 585:a1ed5b41f74f 3416 #define SPI_MH_Bits_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3417 #define SPI_MH_Bits_SHIFT 0
mbed_official 585:a1ed5b41f74f 3418 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
mbed_official 585:a1ed5b41f74f 3419 /* DL Bit Fields */
mbed_official 585:a1ed5b41f74f 3420 #define SPI_DL_Bits_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3421 #define SPI_DL_Bits_SHIFT 0
mbed_official 585:a1ed5b41f74f 3422 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
mbed_official 585:a1ed5b41f74f 3423 /* DH Bit Fields */
mbed_official 585:a1ed5b41f74f 3424 #define SPI_DH_Bits_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3425 #define SPI_DH_Bits_SHIFT 0
mbed_official 585:a1ed5b41f74f 3426 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
mbed_official 585:a1ed5b41f74f 3427 /* CI Bit Fields */
mbed_official 585:a1ed5b41f74f 3428 #define SPI_CI_SPRFCI_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3429 #define SPI_CI_SPRFCI_SHIFT 0
mbed_official 585:a1ed5b41f74f 3430 #define SPI_CI_SPTEFCI_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3431 #define SPI_CI_SPTEFCI_SHIFT 1
mbed_official 585:a1ed5b41f74f 3432 #define SPI_CI_RNFULLFCI_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3433 #define SPI_CI_RNFULLFCI_SHIFT 2
mbed_official 585:a1ed5b41f74f 3434 #define SPI_CI_TNEAREFCI_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3435 #define SPI_CI_TNEAREFCI_SHIFT 3
mbed_official 585:a1ed5b41f74f 3436 #define SPI_CI_RXFOF_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3437 #define SPI_CI_RXFOF_SHIFT 4
mbed_official 585:a1ed5b41f74f 3438 #define SPI_CI_TXFOF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3439 #define SPI_CI_TXFOF_SHIFT 5
mbed_official 585:a1ed5b41f74f 3440 #define SPI_CI_RXFERR_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3441 #define SPI_CI_RXFERR_SHIFT 6
mbed_official 585:a1ed5b41f74f 3442 #define SPI_CI_TXFERR_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3443 #define SPI_CI_TXFERR_SHIFT 7
mbed_official 585:a1ed5b41f74f 3444 /* C3 Bit Fields */
mbed_official 585:a1ed5b41f74f 3445 #define SPI_C3_FIFOMODE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3446 #define SPI_C3_FIFOMODE_SHIFT 0
mbed_official 585:a1ed5b41f74f 3447 #define SPI_C3_RNFULLIEN_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3448 #define SPI_C3_RNFULLIEN_SHIFT 1
mbed_official 585:a1ed5b41f74f 3449 #define SPI_C3_TNEARIEN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3450 #define SPI_C3_TNEARIEN_SHIFT 2
mbed_official 585:a1ed5b41f74f 3451 #define SPI_C3_INTCLR_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3452 #define SPI_C3_INTCLR_SHIFT 3
mbed_official 585:a1ed5b41f74f 3453 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3454 #define SPI_C3_RNFULLF_MARK_SHIFT 4
mbed_official 585:a1ed5b41f74f 3455 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3456 #define SPI_C3_TNEAREF_MARK_SHIFT 5
mbed_official 585:a1ed5b41f74f 3457
mbed_official 585:a1ed5b41f74f 3458 /**
mbed_official 585:a1ed5b41f74f 3459 * @}
mbed_official 585:a1ed5b41f74f 3460 */ /* end of group SPI_Register_Masks */
mbed_official 585:a1ed5b41f74f 3461
mbed_official 585:a1ed5b41f74f 3462
mbed_official 585:a1ed5b41f74f 3463 /* SPI - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 3464 /** Peripheral SPI0 base address */
mbed_official 585:a1ed5b41f74f 3465 #define SPI0_BASE (0x40076000u)
mbed_official 585:a1ed5b41f74f 3466 /** Peripheral SPI0 base pointer */
mbed_official 585:a1ed5b41f74f 3467 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 585:a1ed5b41f74f 3468 /** Peripheral SPI1 base address */
mbed_official 585:a1ed5b41f74f 3469 #define SPI1_BASE (0x40077000u)
mbed_official 585:a1ed5b41f74f 3470 /** Peripheral SPI1 base pointer */
mbed_official 585:a1ed5b41f74f 3471 #define SPI1 ((SPI_Type *)SPI1_BASE)
mbed_official 585:a1ed5b41f74f 3472 /** Array initializer of SPI peripheral base pointers */
mbed_official 585:a1ed5b41f74f 3473 #define SPI_BASES { SPI0, SPI1 }
mbed_official 585:a1ed5b41f74f 3474
mbed_official 585:a1ed5b41f74f 3475 /**
mbed_official 585:a1ed5b41f74f 3476 * @}
mbed_official 585:a1ed5b41f74f 3477 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 3478
mbed_official 585:a1ed5b41f74f 3479
mbed_official 585:a1ed5b41f74f 3480 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3481 -- TPM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3482 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3483
mbed_official 585:a1ed5b41f74f 3484 /**
mbed_official 585:a1ed5b41f74f 3485 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3486 * @{
mbed_official 585:a1ed5b41f74f 3487 */
mbed_official 585:a1ed5b41f74f 3488
mbed_official 585:a1ed5b41f74f 3489 /** TPM - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 3490 typedef struct {
mbed_official 585:a1ed5b41f74f 3491 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 3492 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 3493 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 3494 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 585:a1ed5b41f74f 3495 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
mbed_official 585:a1ed5b41f74f 3496 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 585:a1ed5b41f74f 3497 } CONTROLS[6];
mbed_official 585:a1ed5b41f74f 3498 uint8_t RESERVED_0[20];
mbed_official 585:a1ed5b41f74f 3499 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
mbed_official 585:a1ed5b41f74f 3500 uint8_t RESERVED_1[48];
mbed_official 585:a1ed5b41f74f 3501 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 585:a1ed5b41f74f 3502 } TPM_Type;
mbed_official 585:a1ed5b41f74f 3503
mbed_official 585:a1ed5b41f74f 3504 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3505 -- TPM Register Masks
mbed_official 585:a1ed5b41f74f 3506 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3507
mbed_official 585:a1ed5b41f74f 3508 /**
mbed_official 585:a1ed5b41f74f 3509 * @addtogroup TPM_Register_Masks TPM Register Masks
mbed_official 585:a1ed5b41f74f 3510 * @{
mbed_official 585:a1ed5b41f74f 3511 */
mbed_official 585:a1ed5b41f74f 3512
mbed_official 585:a1ed5b41f74f 3513 /* SC Bit Fields */
mbed_official 585:a1ed5b41f74f 3514 #define TPM_SC_PS_MASK 0x7u
mbed_official 585:a1ed5b41f74f 3515 #define TPM_SC_PS_SHIFT 0
mbed_official 585:a1ed5b41f74f 3516 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
mbed_official 585:a1ed5b41f74f 3517 #define TPM_SC_CMOD_MASK 0x18u
mbed_official 585:a1ed5b41f74f 3518 #define TPM_SC_CMOD_SHIFT 3
mbed_official 585:a1ed5b41f74f 3519 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
mbed_official 585:a1ed5b41f74f 3520 #define TPM_SC_CPWMS_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3521 #define TPM_SC_CPWMS_SHIFT 5
mbed_official 585:a1ed5b41f74f 3522 #define TPM_SC_TOIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3523 #define TPM_SC_TOIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3524 #define TPM_SC_TOF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3525 #define TPM_SC_TOF_SHIFT 7
mbed_official 585:a1ed5b41f74f 3526 #define TPM_SC_DMA_MASK 0x100u
mbed_official 585:a1ed5b41f74f 3527 #define TPM_SC_DMA_SHIFT 8
mbed_official 585:a1ed5b41f74f 3528 /* CNT Bit Fields */
mbed_official 585:a1ed5b41f74f 3529 #define TPM_CNT_COUNT_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 3530 #define TPM_CNT_COUNT_SHIFT 0
mbed_official 585:a1ed5b41f74f 3531 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
mbed_official 585:a1ed5b41f74f 3532 /* MOD Bit Fields */
mbed_official 585:a1ed5b41f74f 3533 #define TPM_MOD_MOD_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 3534 #define TPM_MOD_MOD_SHIFT 0
mbed_official 585:a1ed5b41f74f 3535 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
mbed_official 585:a1ed5b41f74f 3536 /* CnSC Bit Fields */
mbed_official 585:a1ed5b41f74f 3537 #define TPM_CnSC_DMA_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3538 #define TPM_CnSC_DMA_SHIFT 0
mbed_official 585:a1ed5b41f74f 3539 #define TPM_CnSC_ELSA_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3540 #define TPM_CnSC_ELSA_SHIFT 2
mbed_official 585:a1ed5b41f74f 3541 #define TPM_CnSC_ELSB_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3542 #define TPM_CnSC_ELSB_SHIFT 3
mbed_official 585:a1ed5b41f74f 3543 #define TPM_CnSC_MSA_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3544 #define TPM_CnSC_MSA_SHIFT 4
mbed_official 585:a1ed5b41f74f 3545 #define TPM_CnSC_MSB_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3546 #define TPM_CnSC_MSB_SHIFT 5
mbed_official 585:a1ed5b41f74f 3547 #define TPM_CnSC_CHIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3548 #define TPM_CnSC_CHIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3549 #define TPM_CnSC_CHF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3550 #define TPM_CnSC_CHF_SHIFT 7
mbed_official 585:a1ed5b41f74f 3551 /* CnV Bit Fields */
mbed_official 585:a1ed5b41f74f 3552 #define TPM_CnV_VAL_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 3553 #define TPM_CnV_VAL_SHIFT 0
mbed_official 585:a1ed5b41f74f 3554 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
mbed_official 585:a1ed5b41f74f 3555 /* STATUS Bit Fields */
mbed_official 585:a1ed5b41f74f 3556 #define TPM_STATUS_CH0F_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3557 #define TPM_STATUS_CH0F_SHIFT 0
mbed_official 585:a1ed5b41f74f 3558 #define TPM_STATUS_CH1F_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3559 #define TPM_STATUS_CH1F_SHIFT 1
mbed_official 585:a1ed5b41f74f 3560 #define TPM_STATUS_CH2F_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3561 #define TPM_STATUS_CH2F_SHIFT 2
mbed_official 585:a1ed5b41f74f 3562 #define TPM_STATUS_CH3F_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3563 #define TPM_STATUS_CH3F_SHIFT 3
mbed_official 585:a1ed5b41f74f 3564 #define TPM_STATUS_CH4F_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3565 #define TPM_STATUS_CH4F_SHIFT 4
mbed_official 585:a1ed5b41f74f 3566 #define TPM_STATUS_CH5F_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3567 #define TPM_STATUS_CH5F_SHIFT 5
mbed_official 585:a1ed5b41f74f 3568 #define TPM_STATUS_TOF_MASK 0x100u
mbed_official 585:a1ed5b41f74f 3569 #define TPM_STATUS_TOF_SHIFT 8
mbed_official 585:a1ed5b41f74f 3570 /* CONF Bit Fields */
mbed_official 585:a1ed5b41f74f 3571 #define TPM_CONF_DOZEEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3572 #define TPM_CONF_DOZEEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 3573 #define TPM_CONF_DBGMODE_MASK 0xC0u
mbed_official 585:a1ed5b41f74f 3574 #define TPM_CONF_DBGMODE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3575 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
mbed_official 585:a1ed5b41f74f 3576 #define TPM_CONF_GTBEEN_MASK 0x200u
mbed_official 585:a1ed5b41f74f 3577 #define TPM_CONF_GTBEEN_SHIFT 9
mbed_official 585:a1ed5b41f74f 3578 #define TPM_CONF_CSOT_MASK 0x10000u
mbed_official 585:a1ed5b41f74f 3579 #define TPM_CONF_CSOT_SHIFT 16
mbed_official 585:a1ed5b41f74f 3580 #define TPM_CONF_CSOO_MASK 0x20000u
mbed_official 585:a1ed5b41f74f 3581 #define TPM_CONF_CSOO_SHIFT 17
mbed_official 585:a1ed5b41f74f 3582 #define TPM_CONF_CROT_MASK 0x40000u
mbed_official 585:a1ed5b41f74f 3583 #define TPM_CONF_CROT_SHIFT 18
mbed_official 585:a1ed5b41f74f 3584 #define TPM_CONF_TRGSEL_MASK 0xF000000u
mbed_official 585:a1ed5b41f74f 3585 #define TPM_CONF_TRGSEL_SHIFT 24
mbed_official 585:a1ed5b41f74f 3586 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
mbed_official 585:a1ed5b41f74f 3587
mbed_official 585:a1ed5b41f74f 3588 /**
mbed_official 585:a1ed5b41f74f 3589 * @}
mbed_official 585:a1ed5b41f74f 3590 */ /* end of group TPM_Register_Masks */
mbed_official 585:a1ed5b41f74f 3591
mbed_official 585:a1ed5b41f74f 3592
mbed_official 585:a1ed5b41f74f 3593 /* TPM - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 3594 /** Peripheral TPM0 base address */
mbed_official 585:a1ed5b41f74f 3595 #define TPM0_BASE (0x40038000u)
mbed_official 585:a1ed5b41f74f 3596 /** Peripheral TPM0 base pointer */
mbed_official 585:a1ed5b41f74f 3597 #define TPM0 ((TPM_Type *)TPM0_BASE)
mbed_official 585:a1ed5b41f74f 3598 /** Peripheral TPM1 base address */
mbed_official 585:a1ed5b41f74f 3599 #define TPM1_BASE (0x40039000u)
mbed_official 585:a1ed5b41f74f 3600 /** Peripheral TPM1 base pointer */
mbed_official 585:a1ed5b41f74f 3601 #define TPM1 ((TPM_Type *)TPM1_BASE)
mbed_official 585:a1ed5b41f74f 3602 /** Peripheral TPM2 base address */
mbed_official 585:a1ed5b41f74f 3603 #define TPM2_BASE (0x4003A000u)
mbed_official 585:a1ed5b41f74f 3604 /** Peripheral TPM2 base pointer */
mbed_official 585:a1ed5b41f74f 3605 #define TPM2 ((TPM_Type *)TPM2_BASE)
mbed_official 585:a1ed5b41f74f 3606 /** Array initializer of TPM peripheral base pointers */
mbed_official 585:a1ed5b41f74f 3607 #define TPM_BASES { TPM0, TPM1, TPM2 }
mbed_official 585:a1ed5b41f74f 3608
mbed_official 585:a1ed5b41f74f 3609 /**
mbed_official 585:a1ed5b41f74f 3610 * @}
mbed_official 585:a1ed5b41f74f 3611 */ /* end of group TPM_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 3612
mbed_official 585:a1ed5b41f74f 3613
mbed_official 585:a1ed5b41f74f 3614 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3615 -- TSI Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3616 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3617
mbed_official 585:a1ed5b41f74f 3618 /**
mbed_official 585:a1ed5b41f74f 3619 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3620 * @{
mbed_official 585:a1ed5b41f74f 3621 */
mbed_official 585:a1ed5b41f74f 3622
mbed_official 585:a1ed5b41f74f 3623 /** TSI - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 3624 typedef struct {
mbed_official 585:a1ed5b41f74f 3625 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 3626 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 3627 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 3628 } TSI_Type;
mbed_official 585:a1ed5b41f74f 3629
mbed_official 585:a1ed5b41f74f 3630 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3631 -- TSI Register Masks
mbed_official 585:a1ed5b41f74f 3632 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3633
mbed_official 585:a1ed5b41f74f 3634 /**
mbed_official 585:a1ed5b41f74f 3635 * @addtogroup TSI_Register_Masks TSI Register Masks
mbed_official 585:a1ed5b41f74f 3636 * @{
mbed_official 585:a1ed5b41f74f 3637 */
mbed_official 585:a1ed5b41f74f 3638
mbed_official 585:a1ed5b41f74f 3639 /* GENCS Bit Fields */
mbed_official 585:a1ed5b41f74f 3640 #define TSI_GENCS_CURSW_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3641 #define TSI_GENCS_CURSW_SHIFT 1
mbed_official 585:a1ed5b41f74f 3642 #define TSI_GENCS_EOSF_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3643 #define TSI_GENCS_EOSF_SHIFT 2
mbed_official 585:a1ed5b41f74f 3644 #define TSI_GENCS_SCNIP_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3645 #define TSI_GENCS_SCNIP_SHIFT 3
mbed_official 585:a1ed5b41f74f 3646 #define TSI_GENCS_STM_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3647 #define TSI_GENCS_STM_SHIFT 4
mbed_official 585:a1ed5b41f74f 3648 #define TSI_GENCS_STPE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3649 #define TSI_GENCS_STPE_SHIFT 5
mbed_official 585:a1ed5b41f74f 3650 #define TSI_GENCS_TSIIEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3651 #define TSI_GENCS_TSIIEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 3652 #define TSI_GENCS_TSIEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3653 #define TSI_GENCS_TSIEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 3654 #define TSI_GENCS_NSCN_MASK 0x1F00u
mbed_official 585:a1ed5b41f74f 3655 #define TSI_GENCS_NSCN_SHIFT 8
mbed_official 585:a1ed5b41f74f 3656 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
mbed_official 585:a1ed5b41f74f 3657 #define TSI_GENCS_PS_MASK 0xE000u
mbed_official 585:a1ed5b41f74f 3658 #define TSI_GENCS_PS_SHIFT 13
mbed_official 585:a1ed5b41f74f 3659 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
mbed_official 585:a1ed5b41f74f 3660 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
mbed_official 585:a1ed5b41f74f 3661 #define TSI_GENCS_EXTCHRG_SHIFT 16
mbed_official 585:a1ed5b41f74f 3662 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
mbed_official 585:a1ed5b41f74f 3663 #define TSI_GENCS_DVOLT_MASK 0x180000u
mbed_official 585:a1ed5b41f74f 3664 #define TSI_GENCS_DVOLT_SHIFT 19
mbed_official 585:a1ed5b41f74f 3665 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
mbed_official 585:a1ed5b41f74f 3666 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
mbed_official 585:a1ed5b41f74f 3667 #define TSI_GENCS_REFCHRG_SHIFT 21
mbed_official 585:a1ed5b41f74f 3668 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
mbed_official 585:a1ed5b41f74f 3669 #define TSI_GENCS_MODE_MASK 0xF000000u
mbed_official 585:a1ed5b41f74f 3670 #define TSI_GENCS_MODE_SHIFT 24
mbed_official 585:a1ed5b41f74f 3671 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
mbed_official 585:a1ed5b41f74f 3672 #define TSI_GENCS_ESOR_MASK 0x10000000u
mbed_official 585:a1ed5b41f74f 3673 #define TSI_GENCS_ESOR_SHIFT 28
mbed_official 585:a1ed5b41f74f 3674 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
mbed_official 585:a1ed5b41f74f 3675 #define TSI_GENCS_OUTRGF_SHIFT 31
mbed_official 585:a1ed5b41f74f 3676 /* DATA Bit Fields */
mbed_official 585:a1ed5b41f74f 3677 #define TSI_DATA_TSICNT_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 3678 #define TSI_DATA_TSICNT_SHIFT 0
mbed_official 585:a1ed5b41f74f 3679 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
mbed_official 585:a1ed5b41f74f 3680 #define TSI_DATA_SWTS_MASK 0x400000u
mbed_official 585:a1ed5b41f74f 3681 #define TSI_DATA_SWTS_SHIFT 22
mbed_official 585:a1ed5b41f74f 3682 #define TSI_DATA_DMAEN_MASK 0x800000u
mbed_official 585:a1ed5b41f74f 3683 #define TSI_DATA_DMAEN_SHIFT 23
mbed_official 585:a1ed5b41f74f 3684 #define TSI_DATA_TSICH_MASK 0xF0000000u
mbed_official 585:a1ed5b41f74f 3685 #define TSI_DATA_TSICH_SHIFT 28
mbed_official 585:a1ed5b41f74f 3686 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
mbed_official 585:a1ed5b41f74f 3687 /* TSHD Bit Fields */
mbed_official 585:a1ed5b41f74f 3688 #define TSI_TSHD_THRESL_MASK 0xFFFFu
mbed_official 585:a1ed5b41f74f 3689 #define TSI_TSHD_THRESL_SHIFT 0
mbed_official 585:a1ed5b41f74f 3690 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
mbed_official 585:a1ed5b41f74f 3691 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
mbed_official 585:a1ed5b41f74f 3692 #define TSI_TSHD_THRESH_SHIFT 16
mbed_official 585:a1ed5b41f74f 3693 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
mbed_official 585:a1ed5b41f74f 3694
mbed_official 585:a1ed5b41f74f 3695 /**
mbed_official 585:a1ed5b41f74f 3696 * @}
mbed_official 585:a1ed5b41f74f 3697 */ /* end of group TSI_Register_Masks */
mbed_official 585:a1ed5b41f74f 3698
mbed_official 585:a1ed5b41f74f 3699
mbed_official 585:a1ed5b41f74f 3700 /* TSI - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 3701 /** Peripheral TSI0 base address */
mbed_official 585:a1ed5b41f74f 3702 #define TSI0_BASE (0x40045000u)
mbed_official 585:a1ed5b41f74f 3703 /** Peripheral TSI0 base pointer */
mbed_official 585:a1ed5b41f74f 3704 #define TSI0 ((TSI_Type *)TSI0_BASE)
mbed_official 585:a1ed5b41f74f 3705 /** Array initializer of TSI peripheral base pointers */
mbed_official 585:a1ed5b41f74f 3706 #define TSI_BASES { TSI0 }
mbed_official 585:a1ed5b41f74f 3707
mbed_official 585:a1ed5b41f74f 3708 /**
mbed_official 585:a1ed5b41f74f 3709 * @}
mbed_official 585:a1ed5b41f74f 3710 */ /* end of group TSI_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 3711
mbed_official 585:a1ed5b41f74f 3712
mbed_official 585:a1ed5b41f74f 3713 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3714 -- UART Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3715 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3716
mbed_official 585:a1ed5b41f74f 3717 /**
mbed_official 585:a1ed5b41f74f 3718 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3719 * @{
mbed_official 585:a1ed5b41f74f 3720 */
mbed_official 585:a1ed5b41f74f 3721
mbed_official 585:a1ed5b41f74f 3722 /** UART - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 3723 typedef struct {
mbed_official 585:a1ed5b41f74f 3724 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 3725 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 3726 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 3727 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 3728 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 3729 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 3730 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 3731 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 585:a1ed5b41f74f 3732 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 3733 } UART_Type;
mbed_official 585:a1ed5b41f74f 3734
mbed_official 585:a1ed5b41f74f 3735 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3736 -- UART Register Masks
mbed_official 585:a1ed5b41f74f 3737 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3738
mbed_official 585:a1ed5b41f74f 3739 /**
mbed_official 585:a1ed5b41f74f 3740 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 585:a1ed5b41f74f 3741 * @{
mbed_official 585:a1ed5b41f74f 3742 */
mbed_official 585:a1ed5b41f74f 3743
mbed_official 585:a1ed5b41f74f 3744 /* BDH Bit Fields */
mbed_official 585:a1ed5b41f74f 3745 #define UART_BDH_SBR_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 3746 #define UART_BDH_SBR_SHIFT 0
mbed_official 585:a1ed5b41f74f 3747 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mbed_official 585:a1ed5b41f74f 3748 #define UART_BDH_SBNS_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3749 #define UART_BDH_SBNS_SHIFT 5
mbed_official 585:a1ed5b41f74f 3750 #define UART_BDH_RXEDGIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3751 #define UART_BDH_RXEDGIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3752 #define UART_BDH_LBKDIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3753 #define UART_BDH_LBKDIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3754 /* BDL Bit Fields */
mbed_official 585:a1ed5b41f74f 3755 #define UART_BDL_SBR_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3756 #define UART_BDL_SBR_SHIFT 0
mbed_official 585:a1ed5b41f74f 3757 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mbed_official 585:a1ed5b41f74f 3758 /* C1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3759 #define UART_C1_PT_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3760 #define UART_C1_PT_SHIFT 0
mbed_official 585:a1ed5b41f74f 3761 #define UART_C1_PE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3762 #define UART_C1_PE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3763 #define UART_C1_ILT_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3764 #define UART_C1_ILT_SHIFT 2
mbed_official 585:a1ed5b41f74f 3765 #define UART_C1_WAKE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3766 #define UART_C1_WAKE_SHIFT 3
mbed_official 585:a1ed5b41f74f 3767 #define UART_C1_M_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3768 #define UART_C1_M_SHIFT 4
mbed_official 585:a1ed5b41f74f 3769 #define UART_C1_RSRC_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3770 #define UART_C1_RSRC_SHIFT 5
mbed_official 585:a1ed5b41f74f 3771 #define UART_C1_UARTSWAI_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3772 #define UART_C1_UARTSWAI_SHIFT 6
mbed_official 585:a1ed5b41f74f 3773 #define UART_C1_LOOPS_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3774 #define UART_C1_LOOPS_SHIFT 7
mbed_official 585:a1ed5b41f74f 3775 /* C2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3776 #define UART_C2_SBK_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3777 #define UART_C2_SBK_SHIFT 0
mbed_official 585:a1ed5b41f74f 3778 #define UART_C2_RWU_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3779 #define UART_C2_RWU_SHIFT 1
mbed_official 585:a1ed5b41f74f 3780 #define UART_C2_RE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3781 #define UART_C2_RE_SHIFT 2
mbed_official 585:a1ed5b41f74f 3782 #define UART_C2_TE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3783 #define UART_C2_TE_SHIFT 3
mbed_official 585:a1ed5b41f74f 3784 #define UART_C2_ILIE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3785 #define UART_C2_ILIE_SHIFT 4
mbed_official 585:a1ed5b41f74f 3786 #define UART_C2_RIE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3787 #define UART_C2_RIE_SHIFT 5
mbed_official 585:a1ed5b41f74f 3788 #define UART_C2_TCIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3789 #define UART_C2_TCIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3790 #define UART_C2_TIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3791 #define UART_C2_TIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3792 /* S1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3793 #define UART_S1_PF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3794 #define UART_S1_PF_SHIFT 0
mbed_official 585:a1ed5b41f74f 3795 #define UART_S1_FE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3796 #define UART_S1_FE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3797 #define UART_S1_NF_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3798 #define UART_S1_NF_SHIFT 2
mbed_official 585:a1ed5b41f74f 3799 #define UART_S1_OR_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3800 #define UART_S1_OR_SHIFT 3
mbed_official 585:a1ed5b41f74f 3801 #define UART_S1_IDLE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3802 #define UART_S1_IDLE_SHIFT 4
mbed_official 585:a1ed5b41f74f 3803 #define UART_S1_RDRF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3804 #define UART_S1_RDRF_SHIFT 5
mbed_official 585:a1ed5b41f74f 3805 #define UART_S1_TC_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3806 #define UART_S1_TC_SHIFT 6
mbed_official 585:a1ed5b41f74f 3807 #define UART_S1_TDRE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3808 #define UART_S1_TDRE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3809 /* S2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3810 #define UART_S2_RAF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3811 #define UART_S2_RAF_SHIFT 0
mbed_official 585:a1ed5b41f74f 3812 #define UART_S2_LBKDE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3813 #define UART_S2_LBKDE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3814 #define UART_S2_BRK13_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3815 #define UART_S2_BRK13_SHIFT 2
mbed_official 585:a1ed5b41f74f 3816 #define UART_S2_RWUID_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3817 #define UART_S2_RWUID_SHIFT 3
mbed_official 585:a1ed5b41f74f 3818 #define UART_S2_RXINV_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3819 #define UART_S2_RXINV_SHIFT 4
mbed_official 585:a1ed5b41f74f 3820 #define UART_S2_RXEDGIF_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3821 #define UART_S2_RXEDGIF_SHIFT 6
mbed_official 585:a1ed5b41f74f 3822 #define UART_S2_LBKDIF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3823 #define UART_S2_LBKDIF_SHIFT 7
mbed_official 585:a1ed5b41f74f 3824 /* C3 Bit Fields */
mbed_official 585:a1ed5b41f74f 3825 #define UART_C3_PEIE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3826 #define UART_C3_PEIE_SHIFT 0
mbed_official 585:a1ed5b41f74f 3827 #define UART_C3_FEIE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3828 #define UART_C3_FEIE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3829 #define UART_C3_NEIE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3830 #define UART_C3_NEIE_SHIFT 2
mbed_official 585:a1ed5b41f74f 3831 #define UART_C3_ORIE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3832 #define UART_C3_ORIE_SHIFT 3
mbed_official 585:a1ed5b41f74f 3833 #define UART_C3_TXINV_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3834 #define UART_C3_TXINV_SHIFT 4
mbed_official 585:a1ed5b41f74f 3835 #define UART_C3_TXDIR_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3836 #define UART_C3_TXDIR_SHIFT 5
mbed_official 585:a1ed5b41f74f 3837 #define UART_C3_T8_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3838 #define UART_C3_T8_SHIFT 6
mbed_official 585:a1ed5b41f74f 3839 #define UART_C3_R8_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3840 #define UART_C3_R8_SHIFT 7
mbed_official 585:a1ed5b41f74f 3841 /* D Bit Fields */
mbed_official 585:a1ed5b41f74f 3842 #define UART_D_R0T0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3843 #define UART_D_R0T0_SHIFT 0
mbed_official 585:a1ed5b41f74f 3844 #define UART_D_R1T1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3845 #define UART_D_R1T1_SHIFT 1
mbed_official 585:a1ed5b41f74f 3846 #define UART_D_R2T2_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3847 #define UART_D_R2T2_SHIFT 2
mbed_official 585:a1ed5b41f74f 3848 #define UART_D_R3T3_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3849 #define UART_D_R3T3_SHIFT 3
mbed_official 585:a1ed5b41f74f 3850 #define UART_D_R4T4_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3851 #define UART_D_R4T4_SHIFT 4
mbed_official 585:a1ed5b41f74f 3852 #define UART_D_R5T5_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3853 #define UART_D_R5T5_SHIFT 5
mbed_official 585:a1ed5b41f74f 3854 #define UART_D_R6T6_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3855 #define UART_D_R6T6_SHIFT 6
mbed_official 585:a1ed5b41f74f 3856 #define UART_D_R7T7_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3857 #define UART_D_R7T7_SHIFT 7
mbed_official 585:a1ed5b41f74f 3858 /* C4 Bit Fields */
mbed_official 585:a1ed5b41f74f 3859 #define UART_C4_RDMAS_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3860 #define UART_C4_RDMAS_SHIFT 5
mbed_official 585:a1ed5b41f74f 3861 #define UART_C4_TDMAS_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3862 #define UART_C4_TDMAS_SHIFT 7
mbed_official 585:a1ed5b41f74f 3863
mbed_official 585:a1ed5b41f74f 3864 /**
mbed_official 585:a1ed5b41f74f 3865 * @}
mbed_official 585:a1ed5b41f74f 3866 */ /* end of group UART_Register_Masks */
mbed_official 585:a1ed5b41f74f 3867
mbed_official 585:a1ed5b41f74f 3868
mbed_official 585:a1ed5b41f74f 3869 /* UART - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 3870 /** Peripheral UART1 base address */
mbed_official 585:a1ed5b41f74f 3871 #define UART1_BASE (0x4006B000u)
mbed_official 585:a1ed5b41f74f 3872 /** Peripheral UART1 base pointer */
mbed_official 585:a1ed5b41f74f 3873 #define UART1 ((UART_Type *)UART1_BASE)
mbed_official 585:a1ed5b41f74f 3874 /** Peripheral UART2 base address */
mbed_official 585:a1ed5b41f74f 3875 #define UART2_BASE (0x4006C000u)
mbed_official 585:a1ed5b41f74f 3876 /** Peripheral UART2 base pointer */
mbed_official 585:a1ed5b41f74f 3877 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 585:a1ed5b41f74f 3878 /** Array initializer of UART peripheral base pointers */
mbed_official 585:a1ed5b41f74f 3879 #define UART_BASES { UART1, UART2 }
mbed_official 585:a1ed5b41f74f 3880
mbed_official 585:a1ed5b41f74f 3881 /**
mbed_official 585:a1ed5b41f74f 3882 * @}
mbed_official 585:a1ed5b41f74f 3883 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 3884
mbed_official 585:a1ed5b41f74f 3885
mbed_official 585:a1ed5b41f74f 3886 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3887 -- UART0 Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3888 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3889
mbed_official 585:a1ed5b41f74f 3890 /**
mbed_official 585:a1ed5b41f74f 3891 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 3892 * @{
mbed_official 585:a1ed5b41f74f 3893 */
mbed_official 585:a1ed5b41f74f 3894
mbed_official 585:a1ed5b41f74f 3895 /** UART0 - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 3896 typedef struct {
mbed_official 585:a1ed5b41f74f 3897 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 3898 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
mbed_official 585:a1ed5b41f74f 3899 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 585:a1ed5b41f74f 3900 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 585:a1ed5b41f74f 3901 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 3902 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 585:a1ed5b41f74f 3903 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 585:a1ed5b41f74f 3904 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 585:a1ed5b41f74f 3905 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 3906 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 585:a1ed5b41f74f 3907 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 585:a1ed5b41f74f 3908 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 585:a1ed5b41f74f 3909 } UART0_Type;
mbed_official 585:a1ed5b41f74f 3910
mbed_official 585:a1ed5b41f74f 3911 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 3912 -- UART0 Register Masks
mbed_official 585:a1ed5b41f74f 3913 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 3914
mbed_official 585:a1ed5b41f74f 3915 /**
mbed_official 585:a1ed5b41f74f 3916 * @addtogroup UART0_Register_Masks UART0 Register Masks
mbed_official 585:a1ed5b41f74f 3917 * @{
mbed_official 585:a1ed5b41f74f 3918 */
mbed_official 585:a1ed5b41f74f 3919
mbed_official 585:a1ed5b41f74f 3920 /* BDH Bit Fields */
mbed_official 585:a1ed5b41f74f 3921 #define UART0_BDH_SBR_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 3922 #define UART0_BDH_SBR_SHIFT 0
mbed_official 585:a1ed5b41f74f 3923 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
mbed_official 585:a1ed5b41f74f 3924 #define UART0_BDH_SBNS_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3925 #define UART0_BDH_SBNS_SHIFT 5
mbed_official 585:a1ed5b41f74f 3926 #define UART0_BDH_RXEDGIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3927 #define UART0_BDH_RXEDGIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3928 #define UART0_BDH_LBKDIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3929 #define UART0_BDH_LBKDIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3930 /* BDL Bit Fields */
mbed_official 585:a1ed5b41f74f 3931 #define UART0_BDL_SBR_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 3932 #define UART0_BDL_SBR_SHIFT 0
mbed_official 585:a1ed5b41f74f 3933 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
mbed_official 585:a1ed5b41f74f 3934 /* C1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3935 #define UART0_C1_PT_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3936 #define UART0_C1_PT_SHIFT 0
mbed_official 585:a1ed5b41f74f 3937 #define UART0_C1_PE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3938 #define UART0_C1_PE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3939 #define UART0_C1_ILT_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3940 #define UART0_C1_ILT_SHIFT 2
mbed_official 585:a1ed5b41f74f 3941 #define UART0_C1_WAKE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3942 #define UART0_C1_WAKE_SHIFT 3
mbed_official 585:a1ed5b41f74f 3943 #define UART0_C1_M_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3944 #define UART0_C1_M_SHIFT 4
mbed_official 585:a1ed5b41f74f 3945 #define UART0_C1_RSRC_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3946 #define UART0_C1_RSRC_SHIFT 5
mbed_official 585:a1ed5b41f74f 3947 #define UART0_C1_DOZEEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3948 #define UART0_C1_DOZEEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 3949 #define UART0_C1_LOOPS_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3950 #define UART0_C1_LOOPS_SHIFT 7
mbed_official 585:a1ed5b41f74f 3951 /* C2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3952 #define UART0_C2_SBK_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3953 #define UART0_C2_SBK_SHIFT 0
mbed_official 585:a1ed5b41f74f 3954 #define UART0_C2_RWU_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3955 #define UART0_C2_RWU_SHIFT 1
mbed_official 585:a1ed5b41f74f 3956 #define UART0_C2_RE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3957 #define UART0_C2_RE_SHIFT 2
mbed_official 585:a1ed5b41f74f 3958 #define UART0_C2_TE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3959 #define UART0_C2_TE_SHIFT 3
mbed_official 585:a1ed5b41f74f 3960 #define UART0_C2_ILIE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3961 #define UART0_C2_ILIE_SHIFT 4
mbed_official 585:a1ed5b41f74f 3962 #define UART0_C2_RIE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3963 #define UART0_C2_RIE_SHIFT 5
mbed_official 585:a1ed5b41f74f 3964 #define UART0_C2_TCIE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3965 #define UART0_C2_TCIE_SHIFT 6
mbed_official 585:a1ed5b41f74f 3966 #define UART0_C2_TIE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3967 #define UART0_C2_TIE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3968 /* S1 Bit Fields */
mbed_official 585:a1ed5b41f74f 3969 #define UART0_S1_PF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3970 #define UART0_S1_PF_SHIFT 0
mbed_official 585:a1ed5b41f74f 3971 #define UART0_S1_FE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3972 #define UART0_S1_FE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3973 #define UART0_S1_NF_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3974 #define UART0_S1_NF_SHIFT 2
mbed_official 585:a1ed5b41f74f 3975 #define UART0_S1_OR_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3976 #define UART0_S1_OR_SHIFT 3
mbed_official 585:a1ed5b41f74f 3977 #define UART0_S1_IDLE_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3978 #define UART0_S1_IDLE_SHIFT 4
mbed_official 585:a1ed5b41f74f 3979 #define UART0_S1_RDRF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3980 #define UART0_S1_RDRF_SHIFT 5
mbed_official 585:a1ed5b41f74f 3981 #define UART0_S1_TC_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3982 #define UART0_S1_TC_SHIFT 6
mbed_official 585:a1ed5b41f74f 3983 #define UART0_S1_TDRE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 3984 #define UART0_S1_TDRE_SHIFT 7
mbed_official 585:a1ed5b41f74f 3985 /* S2 Bit Fields */
mbed_official 585:a1ed5b41f74f 3986 #define UART0_S2_RAF_MASK 0x1u
mbed_official 585:a1ed5b41f74f 3987 #define UART0_S2_RAF_SHIFT 0
mbed_official 585:a1ed5b41f74f 3988 #define UART0_S2_LBKDE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 3989 #define UART0_S2_LBKDE_SHIFT 1
mbed_official 585:a1ed5b41f74f 3990 #define UART0_S2_BRK13_MASK 0x4u
mbed_official 585:a1ed5b41f74f 3991 #define UART0_S2_BRK13_SHIFT 2
mbed_official 585:a1ed5b41f74f 3992 #define UART0_S2_RWUID_MASK 0x8u
mbed_official 585:a1ed5b41f74f 3993 #define UART0_S2_RWUID_SHIFT 3
mbed_official 585:a1ed5b41f74f 3994 #define UART0_S2_RXINV_MASK 0x10u
mbed_official 585:a1ed5b41f74f 3995 #define UART0_S2_RXINV_SHIFT 4
mbed_official 585:a1ed5b41f74f 3996 #define UART0_S2_MSBF_MASK 0x20u
mbed_official 585:a1ed5b41f74f 3997 #define UART0_S2_MSBF_SHIFT 5
mbed_official 585:a1ed5b41f74f 3998 #define UART0_S2_RXEDGIF_MASK 0x40u
mbed_official 585:a1ed5b41f74f 3999 #define UART0_S2_RXEDGIF_SHIFT 6
mbed_official 585:a1ed5b41f74f 4000 #define UART0_S2_LBKDIF_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4001 #define UART0_S2_LBKDIF_SHIFT 7
mbed_official 585:a1ed5b41f74f 4002 /* C3 Bit Fields */
mbed_official 585:a1ed5b41f74f 4003 #define UART0_C3_PEIE_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4004 #define UART0_C3_PEIE_SHIFT 0
mbed_official 585:a1ed5b41f74f 4005 #define UART0_C3_FEIE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4006 #define UART0_C3_FEIE_SHIFT 1
mbed_official 585:a1ed5b41f74f 4007 #define UART0_C3_NEIE_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4008 #define UART0_C3_NEIE_SHIFT 2
mbed_official 585:a1ed5b41f74f 4009 #define UART0_C3_ORIE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4010 #define UART0_C3_ORIE_SHIFT 3
mbed_official 585:a1ed5b41f74f 4011 #define UART0_C3_TXINV_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4012 #define UART0_C3_TXINV_SHIFT 4
mbed_official 585:a1ed5b41f74f 4013 #define UART0_C3_TXDIR_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4014 #define UART0_C3_TXDIR_SHIFT 5
mbed_official 585:a1ed5b41f74f 4015 #define UART0_C3_R9T8_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4016 #define UART0_C3_R9T8_SHIFT 6
mbed_official 585:a1ed5b41f74f 4017 #define UART0_C3_R8T9_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4018 #define UART0_C3_R8T9_SHIFT 7
mbed_official 585:a1ed5b41f74f 4019 /* D Bit Fields */
mbed_official 585:a1ed5b41f74f 4020 #define UART0_D_R0T0_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4021 #define UART0_D_R0T0_SHIFT 0
mbed_official 585:a1ed5b41f74f 4022 #define UART0_D_R1T1_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4023 #define UART0_D_R1T1_SHIFT 1
mbed_official 585:a1ed5b41f74f 4024 #define UART0_D_R2T2_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4025 #define UART0_D_R2T2_SHIFT 2
mbed_official 585:a1ed5b41f74f 4026 #define UART0_D_R3T3_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4027 #define UART0_D_R3T3_SHIFT 3
mbed_official 585:a1ed5b41f74f 4028 #define UART0_D_R4T4_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4029 #define UART0_D_R4T4_SHIFT 4
mbed_official 585:a1ed5b41f74f 4030 #define UART0_D_R5T5_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4031 #define UART0_D_R5T5_SHIFT 5
mbed_official 585:a1ed5b41f74f 4032 #define UART0_D_R6T6_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4033 #define UART0_D_R6T6_SHIFT 6
mbed_official 585:a1ed5b41f74f 4034 #define UART0_D_R7T7_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4035 #define UART0_D_R7T7_SHIFT 7
mbed_official 585:a1ed5b41f74f 4036 /* MA1 Bit Fields */
mbed_official 585:a1ed5b41f74f 4037 #define UART0_MA1_MA_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4038 #define UART0_MA1_MA_SHIFT 0
mbed_official 585:a1ed5b41f74f 4039 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
mbed_official 585:a1ed5b41f74f 4040 /* MA2 Bit Fields */
mbed_official 585:a1ed5b41f74f 4041 #define UART0_MA2_MA_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4042 #define UART0_MA2_MA_SHIFT 0
mbed_official 585:a1ed5b41f74f 4043 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
mbed_official 585:a1ed5b41f74f 4044 /* C4 Bit Fields */
mbed_official 585:a1ed5b41f74f 4045 #define UART0_C4_OSR_MASK 0x1Fu
mbed_official 585:a1ed5b41f74f 4046 #define UART0_C4_OSR_SHIFT 0
mbed_official 585:a1ed5b41f74f 4047 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
mbed_official 585:a1ed5b41f74f 4048 #define UART0_C4_M10_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4049 #define UART0_C4_M10_SHIFT 5
mbed_official 585:a1ed5b41f74f 4050 #define UART0_C4_MAEN2_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4051 #define UART0_C4_MAEN2_SHIFT 6
mbed_official 585:a1ed5b41f74f 4052 #define UART0_C4_MAEN1_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4053 #define UART0_C4_MAEN1_SHIFT 7
mbed_official 585:a1ed5b41f74f 4054 /* C5 Bit Fields */
mbed_official 585:a1ed5b41f74f 4055 #define UART0_C5_RESYNCDIS_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4056 #define UART0_C5_RESYNCDIS_SHIFT 0
mbed_official 585:a1ed5b41f74f 4057 #define UART0_C5_BOTHEDGE_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4058 #define UART0_C5_BOTHEDGE_SHIFT 1
mbed_official 585:a1ed5b41f74f 4059 #define UART0_C5_RDMAE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4060 #define UART0_C5_RDMAE_SHIFT 5
mbed_official 585:a1ed5b41f74f 4061 #define UART0_C5_TDMAE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4062 #define UART0_C5_TDMAE_SHIFT 7
mbed_official 585:a1ed5b41f74f 4063
mbed_official 585:a1ed5b41f74f 4064 /**
mbed_official 585:a1ed5b41f74f 4065 * @}
mbed_official 585:a1ed5b41f74f 4066 */ /* end of group UART0_Register_Masks */
mbed_official 585:a1ed5b41f74f 4067
mbed_official 585:a1ed5b41f74f 4068
mbed_official 585:a1ed5b41f74f 4069 /* UART0 - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 4070 /** Peripheral UART0 base address */
mbed_official 585:a1ed5b41f74f 4071 #define UART0_BASE (0x4006A000u)
mbed_official 585:a1ed5b41f74f 4072 /** Peripheral UART0 base pointer */
mbed_official 585:a1ed5b41f74f 4073 #define UART0 ((UART0_Type *)UART0_BASE)
mbed_official 585:a1ed5b41f74f 4074 /** Array initializer of UART0 peripheral base pointers */
mbed_official 585:a1ed5b41f74f 4075 #define UART0_BASES { UART0 }
mbed_official 585:a1ed5b41f74f 4076
mbed_official 585:a1ed5b41f74f 4077 /**
mbed_official 585:a1ed5b41f74f 4078 * @}
mbed_official 585:a1ed5b41f74f 4079 */ /* end of group UART0_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 4080
mbed_official 585:a1ed5b41f74f 4081
mbed_official 585:a1ed5b41f74f 4082 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 4083 -- USB Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 4084 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 4085
mbed_official 585:a1ed5b41f74f 4086 /**
mbed_official 585:a1ed5b41f74f 4087 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 585:a1ed5b41f74f 4088 * @{
mbed_official 585:a1ed5b41f74f 4089 */
mbed_official 585:a1ed5b41f74f 4090
mbed_official 585:a1ed5b41f74f 4091 /** USB - Register Layout Typedef */
mbed_official 585:a1ed5b41f74f 4092 typedef struct {
mbed_official 585:a1ed5b41f74f 4093 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mbed_official 585:a1ed5b41f74f 4094 uint8_t RESERVED_0[3];
mbed_official 585:a1ed5b41f74f 4095 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mbed_official 585:a1ed5b41f74f 4096 uint8_t RESERVED_1[3];
mbed_official 585:a1ed5b41f74f 4097 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mbed_official 585:a1ed5b41f74f 4098 uint8_t RESERVED_2[3];
mbed_official 585:a1ed5b41f74f 4099 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mbed_official 585:a1ed5b41f74f 4100 uint8_t RESERVED_3[3];
mbed_official 585:a1ed5b41f74f 4101 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
mbed_official 585:a1ed5b41f74f 4102 uint8_t RESERVED_4[3];
mbed_official 585:a1ed5b41f74f 4103 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
mbed_official 585:a1ed5b41f74f 4104 uint8_t RESERVED_5[3];
mbed_official 585:a1ed5b41f74f 4105 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
mbed_official 585:a1ed5b41f74f 4106 uint8_t RESERVED_6[3];
mbed_official 585:a1ed5b41f74f 4107 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mbed_official 585:a1ed5b41f74f 4108 uint8_t RESERVED_7[99];
mbed_official 585:a1ed5b41f74f 4109 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mbed_official 585:a1ed5b41f74f 4110 uint8_t RESERVED_8[3];
mbed_official 585:a1ed5b41f74f 4111 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mbed_official 585:a1ed5b41f74f 4112 uint8_t RESERVED_9[3];
mbed_official 585:a1ed5b41f74f 4113 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mbed_official 585:a1ed5b41f74f 4114 uint8_t RESERVED_10[3];
mbed_official 585:a1ed5b41f74f 4115 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mbed_official 585:a1ed5b41f74f 4116 uint8_t RESERVED_11[3];
mbed_official 585:a1ed5b41f74f 4117 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mbed_official 585:a1ed5b41f74f 4118 uint8_t RESERVED_12[3];
mbed_official 585:a1ed5b41f74f 4119 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mbed_official 585:a1ed5b41f74f 4120 uint8_t RESERVED_13[3];
mbed_official 585:a1ed5b41f74f 4121 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mbed_official 585:a1ed5b41f74f 4122 uint8_t RESERVED_14[3];
mbed_official 585:a1ed5b41f74f 4123 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
mbed_official 585:a1ed5b41f74f 4124 uint8_t RESERVED_15[3];
mbed_official 585:a1ed5b41f74f 4125 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
mbed_official 585:a1ed5b41f74f 4126 uint8_t RESERVED_16[3];
mbed_official 585:a1ed5b41f74f 4127 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
mbed_official 585:a1ed5b41f74f 4128 uint8_t RESERVED_17[3];
mbed_official 585:a1ed5b41f74f 4129 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
mbed_official 585:a1ed5b41f74f 4130 uint8_t RESERVED_18[3];
mbed_official 585:a1ed5b41f74f 4131 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
mbed_official 585:a1ed5b41f74f 4132 uint8_t RESERVED_19[3];
mbed_official 585:a1ed5b41f74f 4133 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 585:a1ed5b41f74f 4134 uint8_t RESERVED_20[3];
mbed_official 585:a1ed5b41f74f 4135 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 585:a1ed5b41f74f 4136 uint8_t RESERVED_21[11];
mbed_official 585:a1ed5b41f74f 4137 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 4138 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mbed_official 585:a1ed5b41f74f 4139 uint8_t RESERVED_0[3];
mbed_official 585:a1ed5b41f74f 4140 } ENDPOINT[16];
mbed_official 585:a1ed5b41f74f 4141 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mbed_official 585:a1ed5b41f74f 4142 uint8_t RESERVED_22[3];
mbed_official 585:a1ed5b41f74f 4143 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mbed_official 585:a1ed5b41f74f 4144 uint8_t RESERVED_23[3];
mbed_official 585:a1ed5b41f74f 4145 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mbed_official 585:a1ed5b41f74f 4146 uint8_t RESERVED_24[3];
mbed_official 585:a1ed5b41f74f 4147 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
mbed_official 585:a1ed5b41f74f 4148 uint8_t RESERVED_25[7];
mbed_official 585:a1ed5b41f74f 4149 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 585:a1ed5b41f74f 4150 } USB_Type;
mbed_official 585:a1ed5b41f74f 4151
mbed_official 585:a1ed5b41f74f 4152 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 4153 -- USB Register Masks
mbed_official 585:a1ed5b41f74f 4154 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 4155
mbed_official 585:a1ed5b41f74f 4156 /**
mbed_official 585:a1ed5b41f74f 4157 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 585:a1ed5b41f74f 4158 * @{
mbed_official 585:a1ed5b41f74f 4159 */
mbed_official 585:a1ed5b41f74f 4160
mbed_official 585:a1ed5b41f74f 4161 /* PERID Bit Fields */
mbed_official 585:a1ed5b41f74f 4162 #define USB_PERID_ID_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 4163 #define USB_PERID_ID_SHIFT 0
mbed_official 585:a1ed5b41f74f 4164 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mbed_official 585:a1ed5b41f74f 4165 /* IDCOMP Bit Fields */
mbed_official 585:a1ed5b41f74f 4166 #define USB_IDCOMP_NID_MASK 0x3Fu
mbed_official 585:a1ed5b41f74f 4167 #define USB_IDCOMP_NID_SHIFT 0
mbed_official 585:a1ed5b41f74f 4168 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mbed_official 585:a1ed5b41f74f 4169 /* REV Bit Fields */
mbed_official 585:a1ed5b41f74f 4170 #define USB_REV_REV_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4171 #define USB_REV_REV_SHIFT 0
mbed_official 585:a1ed5b41f74f 4172 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mbed_official 585:a1ed5b41f74f 4173 /* ADDINFO Bit Fields */
mbed_official 585:a1ed5b41f74f 4174 #define USB_ADDINFO_IEHOST_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4175 #define USB_ADDINFO_IEHOST_SHIFT 0
mbed_official 585:a1ed5b41f74f 4176 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
mbed_official 585:a1ed5b41f74f 4177 #define USB_ADDINFO_IRQNUM_SHIFT 3
mbed_official 585:a1ed5b41f74f 4178 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
mbed_official 585:a1ed5b41f74f 4179 /* OTGISTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 4180 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4181 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
mbed_official 585:a1ed5b41f74f 4182 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4183 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
mbed_official 585:a1ed5b41f74f 4184 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4185 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
mbed_official 585:a1ed5b41f74f 4186 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4187 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
mbed_official 585:a1ed5b41f74f 4188 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4189 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
mbed_official 585:a1ed5b41f74f 4190 #define USB_OTGISTAT_IDCHG_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4191 #define USB_OTGISTAT_IDCHG_SHIFT 7
mbed_official 585:a1ed5b41f74f 4192 /* OTGICR Bit Fields */
mbed_official 585:a1ed5b41f74f 4193 #define USB_OTGICR_AVBUSEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4194 #define USB_OTGICR_AVBUSEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 4195 #define USB_OTGICR_BSESSEN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4196 #define USB_OTGICR_BSESSEN_SHIFT 2
mbed_official 585:a1ed5b41f74f 4197 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4198 #define USB_OTGICR_SESSVLDEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 4199 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4200 #define USB_OTGICR_LINESTATEEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 4201 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4202 #define USB_OTGICR_ONEMSECEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 4203 #define USB_OTGICR_IDEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4204 #define USB_OTGICR_IDEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 4205 /* OTGSTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 4206 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4207 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
mbed_official 585:a1ed5b41f74f 4208 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4209 #define USB_OTGSTAT_BSESSEND_SHIFT 2
mbed_official 585:a1ed5b41f74f 4210 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4211 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
mbed_official 585:a1ed5b41f74f 4212 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4213 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
mbed_official 585:a1ed5b41f74f 4214 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4215 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 4216 #define USB_OTGSTAT_ID_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4217 #define USB_OTGSTAT_ID_SHIFT 7
mbed_official 585:a1ed5b41f74f 4218 /* OTGCTL Bit Fields */
mbed_official 585:a1ed5b41f74f 4219 #define USB_OTGCTL_OTGEN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4220 #define USB_OTGCTL_OTGEN_SHIFT 2
mbed_official 585:a1ed5b41f74f 4221 #define USB_OTGCTL_DMLOW_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4222 #define USB_OTGCTL_DMLOW_SHIFT 4
mbed_official 585:a1ed5b41f74f 4223 #define USB_OTGCTL_DPLOW_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4224 #define USB_OTGCTL_DPLOW_SHIFT 5
mbed_official 585:a1ed5b41f74f 4225 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4226 #define USB_OTGCTL_DPHIGH_SHIFT 7
mbed_official 585:a1ed5b41f74f 4227 /* ISTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 4228 #define USB_ISTAT_USBRST_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4229 #define USB_ISTAT_USBRST_SHIFT 0
mbed_official 585:a1ed5b41f74f 4230 #define USB_ISTAT_ERROR_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4231 #define USB_ISTAT_ERROR_SHIFT 1
mbed_official 585:a1ed5b41f74f 4232 #define USB_ISTAT_SOFTOK_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4233 #define USB_ISTAT_SOFTOK_SHIFT 2
mbed_official 585:a1ed5b41f74f 4234 #define USB_ISTAT_TOKDNE_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4235 #define USB_ISTAT_TOKDNE_SHIFT 3
mbed_official 585:a1ed5b41f74f 4236 #define USB_ISTAT_SLEEP_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4237 #define USB_ISTAT_SLEEP_SHIFT 4
mbed_official 585:a1ed5b41f74f 4238 #define USB_ISTAT_RESUME_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4239 #define USB_ISTAT_RESUME_SHIFT 5
mbed_official 585:a1ed5b41f74f 4240 #define USB_ISTAT_ATTACH_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4241 #define USB_ISTAT_ATTACH_SHIFT 6
mbed_official 585:a1ed5b41f74f 4242 #define USB_ISTAT_STALL_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4243 #define USB_ISTAT_STALL_SHIFT 7
mbed_official 585:a1ed5b41f74f 4244 /* INTEN Bit Fields */
mbed_official 585:a1ed5b41f74f 4245 #define USB_INTEN_USBRSTEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4246 #define USB_INTEN_USBRSTEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 4247 #define USB_INTEN_ERROREN_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4248 #define USB_INTEN_ERROREN_SHIFT 1
mbed_official 585:a1ed5b41f74f 4249 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4250 #define USB_INTEN_SOFTOKEN_SHIFT 2
mbed_official 585:a1ed5b41f74f 4251 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4252 #define USB_INTEN_TOKDNEEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 4253 #define USB_INTEN_SLEEPEN_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4254 #define USB_INTEN_SLEEPEN_SHIFT 4
mbed_official 585:a1ed5b41f74f 4255 #define USB_INTEN_RESUMEEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4256 #define USB_INTEN_RESUMEEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 4257 #define USB_INTEN_ATTACHEN_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4258 #define USB_INTEN_ATTACHEN_SHIFT 6
mbed_official 585:a1ed5b41f74f 4259 #define USB_INTEN_STALLEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4260 #define USB_INTEN_STALLEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 4261 /* ERRSTAT Bit Fields */
mbed_official 585:a1ed5b41f74f 4262 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4263 #define USB_ERRSTAT_PIDERR_SHIFT 0
mbed_official 585:a1ed5b41f74f 4264 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4265 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
mbed_official 585:a1ed5b41f74f 4266 #define USB_ERRSTAT_CRC16_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4267 #define USB_ERRSTAT_CRC16_SHIFT 2
mbed_official 585:a1ed5b41f74f 4268 #define USB_ERRSTAT_DFN8_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4269 #define USB_ERRSTAT_DFN8_SHIFT 3
mbed_official 585:a1ed5b41f74f 4270 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4271 #define USB_ERRSTAT_BTOERR_SHIFT 4
mbed_official 585:a1ed5b41f74f 4272 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4273 #define USB_ERRSTAT_DMAERR_SHIFT 5
mbed_official 585:a1ed5b41f74f 4274 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4275 #define USB_ERRSTAT_BTSERR_SHIFT 7
mbed_official 585:a1ed5b41f74f 4276 /* ERREN Bit Fields */
mbed_official 585:a1ed5b41f74f 4277 #define USB_ERREN_PIDERREN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4278 #define USB_ERREN_PIDERREN_SHIFT 0
mbed_official 585:a1ed5b41f74f 4279 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4280 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mbed_official 585:a1ed5b41f74f 4281 #define USB_ERREN_CRC16EN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4282 #define USB_ERREN_CRC16EN_SHIFT 2
mbed_official 585:a1ed5b41f74f 4283 #define USB_ERREN_DFN8EN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4284 #define USB_ERREN_DFN8EN_SHIFT 3
mbed_official 585:a1ed5b41f74f 4285 #define USB_ERREN_BTOERREN_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4286 #define USB_ERREN_BTOERREN_SHIFT 4
mbed_official 585:a1ed5b41f74f 4287 #define USB_ERREN_DMAERREN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4288 #define USB_ERREN_DMAERREN_SHIFT 5
mbed_official 585:a1ed5b41f74f 4289 #define USB_ERREN_BTSERREN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4290 #define USB_ERREN_BTSERREN_SHIFT 7
mbed_official 585:a1ed5b41f74f 4291 /* STAT Bit Fields */
mbed_official 585:a1ed5b41f74f 4292 #define USB_STAT_ODD_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4293 #define USB_STAT_ODD_SHIFT 2
mbed_official 585:a1ed5b41f74f 4294 #define USB_STAT_TX_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4295 #define USB_STAT_TX_SHIFT 3
mbed_official 585:a1ed5b41f74f 4296 #define USB_STAT_ENDP_MASK 0xF0u
mbed_official 585:a1ed5b41f74f 4297 #define USB_STAT_ENDP_SHIFT 4
mbed_official 585:a1ed5b41f74f 4298 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mbed_official 585:a1ed5b41f74f 4299 /* CTL Bit Fields */
mbed_official 585:a1ed5b41f74f 4300 #define USB_CTL_USBENSOFEN_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4301 #define USB_CTL_USBENSOFEN_SHIFT 0
mbed_official 585:a1ed5b41f74f 4302 #define USB_CTL_ODDRST_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4303 #define USB_CTL_ODDRST_SHIFT 1
mbed_official 585:a1ed5b41f74f 4304 #define USB_CTL_RESUME_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4305 #define USB_CTL_RESUME_SHIFT 2
mbed_official 585:a1ed5b41f74f 4306 #define USB_CTL_HOSTMODEEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4307 #define USB_CTL_HOSTMODEEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 4308 #define USB_CTL_RESET_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4309 #define USB_CTL_RESET_SHIFT 4
mbed_official 585:a1ed5b41f74f 4310 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4311 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mbed_official 585:a1ed5b41f74f 4312 #define USB_CTL_SE0_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4313 #define USB_CTL_SE0_SHIFT 6
mbed_official 585:a1ed5b41f74f 4314 #define USB_CTL_JSTATE_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4315 #define USB_CTL_JSTATE_SHIFT 7
mbed_official 585:a1ed5b41f74f 4316 /* ADDR Bit Fields */
mbed_official 585:a1ed5b41f74f 4317 #define USB_ADDR_ADDR_MASK 0x7Fu
mbed_official 585:a1ed5b41f74f 4318 #define USB_ADDR_ADDR_SHIFT 0
mbed_official 585:a1ed5b41f74f 4319 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mbed_official 585:a1ed5b41f74f 4320 #define USB_ADDR_LSEN_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4321 #define USB_ADDR_LSEN_SHIFT 7
mbed_official 585:a1ed5b41f74f 4322 /* BDTPAGE1 Bit Fields */
mbed_official 585:a1ed5b41f74f 4323 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mbed_official 585:a1ed5b41f74f 4324 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mbed_official 585:a1ed5b41f74f 4325 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mbed_official 585:a1ed5b41f74f 4326 /* FRMNUML Bit Fields */
mbed_official 585:a1ed5b41f74f 4327 #define USB_FRMNUML_FRM_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4328 #define USB_FRMNUML_FRM_SHIFT 0
mbed_official 585:a1ed5b41f74f 4329 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mbed_official 585:a1ed5b41f74f 4330 /* FRMNUMH Bit Fields */
mbed_official 585:a1ed5b41f74f 4331 #define USB_FRMNUMH_FRM_MASK 0x7u
mbed_official 585:a1ed5b41f74f 4332 #define USB_FRMNUMH_FRM_SHIFT 0
mbed_official 585:a1ed5b41f74f 4333 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mbed_official 585:a1ed5b41f74f 4334 /* TOKEN Bit Fields */
mbed_official 585:a1ed5b41f74f 4335 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
mbed_official 585:a1ed5b41f74f 4336 #define USB_TOKEN_TOKENENDPT_SHIFT 0
mbed_official 585:a1ed5b41f74f 4337 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
mbed_official 585:a1ed5b41f74f 4338 #define USB_TOKEN_TOKENPID_MASK 0xF0u
mbed_official 585:a1ed5b41f74f 4339 #define USB_TOKEN_TOKENPID_SHIFT 4
mbed_official 585:a1ed5b41f74f 4340 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
mbed_official 585:a1ed5b41f74f 4341 /* SOFTHLD Bit Fields */
mbed_official 585:a1ed5b41f74f 4342 #define USB_SOFTHLD_CNT_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4343 #define USB_SOFTHLD_CNT_SHIFT 0
mbed_official 585:a1ed5b41f74f 4344 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
mbed_official 585:a1ed5b41f74f 4345 /* BDTPAGE2 Bit Fields */
mbed_official 585:a1ed5b41f74f 4346 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4347 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mbed_official 585:a1ed5b41f74f 4348 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mbed_official 585:a1ed5b41f74f 4349 /* BDTPAGE3 Bit Fields */
mbed_official 585:a1ed5b41f74f 4350 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4351 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mbed_official 585:a1ed5b41f74f 4352 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mbed_official 585:a1ed5b41f74f 4353 /* ENDPT Bit Fields */
mbed_official 585:a1ed5b41f74f 4354 #define USB_ENDPT_EPHSHK_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4355 #define USB_ENDPT_EPHSHK_SHIFT 0
mbed_official 585:a1ed5b41f74f 4356 #define USB_ENDPT_EPSTALL_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4357 #define USB_ENDPT_EPSTALL_SHIFT 1
mbed_official 585:a1ed5b41f74f 4358 #define USB_ENDPT_EPTXEN_MASK 0x4u
mbed_official 585:a1ed5b41f74f 4359 #define USB_ENDPT_EPTXEN_SHIFT 2
mbed_official 585:a1ed5b41f74f 4360 #define USB_ENDPT_EPRXEN_MASK 0x8u
mbed_official 585:a1ed5b41f74f 4361 #define USB_ENDPT_EPRXEN_SHIFT 3
mbed_official 585:a1ed5b41f74f 4362 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4363 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mbed_official 585:a1ed5b41f74f 4364 #define USB_ENDPT_RETRYDIS_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4365 #define USB_ENDPT_RETRYDIS_SHIFT 6
mbed_official 585:a1ed5b41f74f 4366 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4367 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
mbed_official 585:a1ed5b41f74f 4368 /* USBCTRL Bit Fields */
mbed_official 585:a1ed5b41f74f 4369 #define USB_USBCTRL_PDE_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4370 #define USB_USBCTRL_PDE_SHIFT 6
mbed_official 585:a1ed5b41f74f 4371 #define USB_USBCTRL_SUSP_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4372 #define USB_USBCTRL_SUSP_SHIFT 7
mbed_official 585:a1ed5b41f74f 4373 /* OBSERVE Bit Fields */
mbed_official 585:a1ed5b41f74f 4374 #define USB_OBSERVE_DMPD_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4375 #define USB_OBSERVE_DMPD_SHIFT 4
mbed_official 585:a1ed5b41f74f 4376 #define USB_OBSERVE_DPPD_MASK 0x40u
mbed_official 585:a1ed5b41f74f 4377 #define USB_OBSERVE_DPPD_SHIFT 6
mbed_official 585:a1ed5b41f74f 4378 #define USB_OBSERVE_DPPU_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4379 #define USB_OBSERVE_DPPU_SHIFT 7
mbed_official 585:a1ed5b41f74f 4380 /* CONTROL Bit Fields */
mbed_official 585:a1ed5b41f74f 4381 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mbed_official 585:a1ed5b41f74f 4382 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mbed_official 585:a1ed5b41f74f 4383 /* USBTRC0 Bit Fields */
mbed_official 585:a1ed5b41f74f 4384 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mbed_official 585:a1ed5b41f74f 4385 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mbed_official 585:a1ed5b41f74f 4386 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mbed_official 585:a1ed5b41f74f 4387 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mbed_official 585:a1ed5b41f74f 4388 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mbed_official 585:a1ed5b41f74f 4389 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mbed_official 585:a1ed5b41f74f 4390 #define USB_USBTRC0_USBRESET_MASK 0x80u
mbed_official 585:a1ed5b41f74f 4391 #define USB_USBTRC0_USBRESET_SHIFT 7
mbed_official 585:a1ed5b41f74f 4392 /* USBFRMADJUST Bit Fields */
mbed_official 585:a1ed5b41f74f 4393 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mbed_official 585:a1ed5b41f74f 4394 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mbed_official 585:a1ed5b41f74f 4395 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mbed_official 585:a1ed5b41f74f 4396
mbed_official 585:a1ed5b41f74f 4397 /**
mbed_official 585:a1ed5b41f74f 4398 * @}
mbed_official 585:a1ed5b41f74f 4399 */ /* end of group USB_Register_Masks */
mbed_official 585:a1ed5b41f74f 4400
mbed_official 585:a1ed5b41f74f 4401
mbed_official 585:a1ed5b41f74f 4402 /* USB - Peripheral instance base addresses */
mbed_official 585:a1ed5b41f74f 4403 /** Peripheral USB0 base address */
mbed_official 585:a1ed5b41f74f 4404 #define USB0_BASE (0x40072000u)
mbed_official 585:a1ed5b41f74f 4405 /** Peripheral USB0 base pointer */
mbed_official 585:a1ed5b41f74f 4406 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 585:a1ed5b41f74f 4407 /** Array initializer of USB peripheral base pointers */
mbed_official 585:a1ed5b41f74f 4408 #define USB_BASES { USB0 }
mbed_official 585:a1ed5b41f74f 4409
mbed_official 585:a1ed5b41f74f 4410 /**
mbed_official 585:a1ed5b41f74f 4411 * @}
mbed_official 585:a1ed5b41f74f 4412 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 585:a1ed5b41f74f 4413
mbed_official 585:a1ed5b41f74f 4414
mbed_official 585:a1ed5b41f74f 4415 /*
mbed_official 585:a1ed5b41f74f 4416 ** End of section using anonymous unions
mbed_official 585:a1ed5b41f74f 4417 */
mbed_official 585:a1ed5b41f74f 4418
mbed_official 585:a1ed5b41f74f 4419 #if defined(__ARMCC_VERSION)
mbed_official 585:a1ed5b41f74f 4420 #pragma pop
mbed_official 585:a1ed5b41f74f 4421 #elif defined(__CWCC__)
mbed_official 585:a1ed5b41f74f 4422 #pragma pop
mbed_official 585:a1ed5b41f74f 4423 #elif defined(__GNUC__)
mbed_official 585:a1ed5b41f74f 4424 /* leave anonymous unions enabled */
mbed_official 585:a1ed5b41f74f 4425 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 585:a1ed5b41f74f 4426 #pragma language=default
mbed_official 585:a1ed5b41f74f 4427 #else
mbed_official 585:a1ed5b41f74f 4428 #error Not supported compiler type
mbed_official 585:a1ed5b41f74f 4429 #endif
mbed_official 585:a1ed5b41f74f 4430
mbed_official 585:a1ed5b41f74f 4431 /**
mbed_official 585:a1ed5b41f74f 4432 * @}
mbed_official 585:a1ed5b41f74f 4433 */ /* end of group Peripheral_access_layer */
mbed_official 585:a1ed5b41f74f 4434
mbed_official 585:a1ed5b41f74f 4435
mbed_official 585:a1ed5b41f74f 4436 /* ----------------------------------------------------------------------------
mbed_official 585:a1ed5b41f74f 4437 -- Backward Compatibility
mbed_official 585:a1ed5b41f74f 4438 ---------------------------------------------------------------------------- */
mbed_official 585:a1ed5b41f74f 4439
mbed_official 585:a1ed5b41f74f 4440 /**
mbed_official 585:a1ed5b41f74f 4441 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 585:a1ed5b41f74f 4442 * @{
mbed_official 585:a1ed5b41f74f 4443 */
mbed_official 585:a1ed5b41f74f 4444
mbed_official 585:a1ed5b41f74f 4445 /* No backward compatibility issues. */
mbed_official 585:a1ed5b41f74f 4446
mbed_official 585:a1ed5b41f74f 4447 /**
mbed_official 585:a1ed5b41f74f 4448 * @}
mbed_official 585:a1ed5b41f74f 4449 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 585:a1ed5b41f74f 4450
mbed_official 585:a1ed5b41f74f 4451
mbed_official 585:a1ed5b41f74f 4452 #endif /* #if !defined(MKL26Z4_H_) */
mbed_official 585:a1ed5b41f74f 4453
mbed_official 585:a1ed5b41f74f 4454 /* MKL26Z4.h, eof. */